Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-18 Thread Peter Hurley
On 08/15/2014 04:28 PM, Tony Lindgren wrote:
 * Sebastian Andrzej Siewior bige...@linutronix.de [140815 12:16]:
 On 08/15/2014 08:17 PM, Lennart Sorensen wrote:

 Are you saying that with the new driver you have to respond to the RX
 irq faster than before to avoid overflows?  It is not quite clear.

 Yes. The irq fires 46 bytes giving you 16 bytes buffer before overflow
 vs 63 bytes buffer the old one had.

 I do think 4 interrupts to handle 4 bytes of date does seem a
 tad inefficient, so dropping to 854 looks a lot nicer.  Was the omap
 driver not using the fifo trigger levels at all?

 It configured the trigger levels to 1 for RX and 16 for TX.
 
 Hmm that weird RX trigger level is a workaround for lost characters.
 
 See commit 0ba5f66836 (tty: serial: OMAP: use a 1-byte RX FIFO
 threshold in PIO mode :)

That commit looks like it should have been specific to the silicon
exhibiting the rx timeout bug.

Regards,
Peter Hurley

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Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-18 Thread Felipe Balbi
On Mon, Aug 18, 2014 at 11:15:17AM -0400, Peter Hurley wrote:
 On 08/15/2014 04:28 PM, Tony Lindgren wrote:
  * Sebastian Andrzej Siewior bige...@linutronix.de [140815 12:16]:
  On 08/15/2014 08:17 PM, Lennart Sorensen wrote:
 
  Are you saying that with the new driver you have to respond to the RX
  irq faster than before to avoid overflows?  It is not quite clear.
 
  Yes. The irq fires 46 bytes giving you 16 bytes buffer before overflow
  vs 63 bytes buffer the old one had.
 
  I do think 4 interrupts to handle 4 bytes of date does seem a
  tad inefficient, so dropping to 854 looks a lot nicer.  Was the omap
  driver not using the fifo trigger levels at all?
 
  It configured the trigger levels to 1 for RX and 16 for TX.
  
  Hmm that weird RX trigger level is a workaround for lost characters.
  
  See commit 0ba5f66836 (tty: serial: OMAP: use a 1-byte RX FIFO
  threshold in PIO mode :)
 
 That commit looks like it should have been specific to the silicon
 exhibiting the rx timeout bug.

yeah, I'll agree with that.

-- 
balbi


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Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-17 Thread Sebastian Andrzej Siewior
* Tony Lindgren | 2014-08-15 13:28:27 [-0700]:

 It configured the trigger levels to 1 for RX and 16 for TX.

Hmm that weird RX trigger level is a workaround for lost characters.

See commit 0ba5f66836 (tty: serial: OMAP: use a 1-byte RX FIFO
threshold in PIO mode :)

There's paste test in that commit, I wonder if the 8250 drivers
can deal with it any better?

I recall that I used it as a console and didn't see any missing chars.
I will try test but I am traveling this week…

Regards,

Tony

Sebastian
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Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-15 Thread Lennart Sorensen
On Fri, Aug 15, 2014 at 07:42:28PM +0200, Sebastian Andrzej Siewior wrote:
 This is my complete queue fo the omap serial driver based on the 8250 core
 code. I played with it on beagle bone, am335x-evm and dra7xx including DMA.
 The uncertain remain the runtime-pm pieces.
 I hacked a small serial testing application which sent 10x 4KiB of data in
 raw mode. The number of interrupts in comparison:
 
 serial-omap | 8250 omap | 8250 omap + dma |

 TX |   2558 |   641 | 0 +  30 |
 RX |  40960 |   854 | 1 + 853 |
 
 So the 8250 version uses less interrupts for the same amount of data.
 The consequence is that in TX mode there should be short periods where
 no data is sent (before the CPU gets to re-fill the FIFO). On RX we have
 a smaller time frame where we have to start to purge the FIFO before it
 overflows.

Are you saying that with the new driver you have to respond to the RX
irq faster than before to avoid overflows?  It is not quite clear.

I do think 4 interrupts to handle 4 bytes of date does seem a
tad inefficient, so dropping to 854 looks a lot nicer.  Was the omap
driver not using the fifo trigger levels at all?

-- 
Len Sorensen
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Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-15 Thread Sebastian Andrzej Siewior
On 08/15/2014 08:17 PM, Lennart Sorensen wrote:

 Are you saying that with the new driver you have to respond to the RX
 irq faster than before to avoid overflows?  It is not quite clear.

Yes. The irq fires 46 bytes giving you 16 bytes buffer before overflow
vs 63 bytes buffer the old one had.

 I do think 4 interrupts to handle 4 bytes of date does seem a
 tad inefficient, so dropping to 854 looks a lot nicer.  Was the omap
 driver not using the fifo trigger levels at all?

It configured the trigger levels to 1 for RX and 16 for TX.

Sebastian
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Re: [PATCH v7] 8250-core based serial driver for OMAP + DMA

2014-08-15 Thread Tony Lindgren
* Sebastian Andrzej Siewior bige...@linutronix.de [140815 12:16]:
 On 08/15/2014 08:17 PM, Lennart Sorensen wrote:
 
  Are you saying that with the new driver you have to respond to the RX
  irq faster than before to avoid overflows?  It is not quite clear.
 
 Yes. The irq fires 46 bytes giving you 16 bytes buffer before overflow
 vs 63 bytes buffer the old one had.
 
  I do think 4 interrupts to handle 4 bytes of date does seem a
  tad inefficient, so dropping to 854 looks a lot nicer.  Was the omap
  driver not using the fifo trigger levels at all?
 
 It configured the trigger levels to 1 for RX and 16 for TX.

Hmm that weird RX trigger level is a workaround for lost characters.

See commit 0ba5f66836 (tty: serial: OMAP: use a 1-byte RX FIFO
threshold in PIO mode :)

There's paste test in that commit, I wonder if the 8250 drivers
can deal with it any better?

Regards,

Tony
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