Re: Routable IRQs
Hi, Thomas Gleixner writes: > Felipe, > > On Wed, 30 Dec 2015, Felipe Balbi wrote: >> Thomas Gleixner writes: >> > - Is there a "mapping" block between PRUSS and the host interrupt >> > controller >> >or is this "mapping" block part of PRUSS? >> >> The description in TRM is a bit "poor", but from what I can gather, the >> mapping is done on an interrupt controller inside the PRUSS. However, >> Linux is the one who's got the driver for that INTC (well, Linux will be >> the one with the soft ethernet/uart/whatever IP to talk to). All of its >> (INTC's) registers are memory mapped to the ARM side. > > Ok. And the INTC registers include the "mapping" configuration, right? right. A bunch of 32 bit registers each with several 4 bit fields (one for each of the 64 events) where we write the physical IRQ number. >> > - We all know how well shared interrupts work. Is there a point of >> > supporting >> >64 interrupts when you only have 10 irq lines available? >> >> I'm looking at these 64 events more like MSI kind of events. It's just > > Well, that's fine to look at them this way, but they will end up > shared no matter what. sure :-) >> that the events themselves can be routed to any of the 10 available HW >> IRQ lines. >> >> > - I assume that the PRUSS interrupt mapping is more or less a question of >> > the >> >firmware implementation. So you either have a fixed association in the >> >firmware which is reflected in the DT description of the IP block or you >> >need an interface to tell the PRUSS firmware which event it should map >> > to >> >which irq line. Is there actually a value in doing the latter? >> >> right, I'd say the mapping is pretty static. Unless Suman has some extra >> information which I don't. I guess the question was really to see if >> there was an easy way for doing this so we don't have to mess with DTS >> for every other FW and their neighbor. > > Well, you will need information about every other firmware simply because you > need to know which events the firmware is actually using and what the purpose > of the particular event is. > > Assume you have a simple uart with 3 events (RX, TX, status). So how will the > firmware tell you which event is which? You have a few options: > > 1) DT + fixed mapping scheme: > > Describe the PRUSS event number in DT and have a fixed mapping scheme like > the one you mentioned evt0 -> irq0 . > > 2) DT + DT mapping scheme > > Describe the PRUSS event number in DT and describe the mapping scheme in > DT as well > > 3) DT + dynamic mapping scheme > > Describe the PRUSS event number in DT and let your interrupt controller > associate the irq number dynamically. That's kind of similar to MSI with > the exception that it needs to support shared interrupts. > > 4) Fully dynamic association > > Have a query interface to the firmware which tells you which event it uses > for which particular purpose (RX, TX ...) and then establish a dynamic > mapping to one of the interrupts. > > Not sure which level of complexity you want :) I guess only 1, 2 are anything worth considering, most likely. 4 would just be too much headache :-p 3 might be doable too, though a bit more complex. Suman (who has been working on this for much longer than I have) might have some extra info to add, but he's on vacations for now. Hopefully, he'll add to this thread once he's back. cheers -- balbi signature.asc Description: PGP signature
Re: Routable IRQs
Felipe, On Wed, 30 Dec 2015, Felipe Balbi wrote: > Thomas Gleixner writes: > > - Is there a "mapping" block between PRUSS and the host interrupt > > controller > >or is this "mapping" block part of PRUSS? > > The description in TRM is a bit "poor", but from what I can gather, the > mapping is done on an interrupt controller inside the PRUSS. However, > Linux is the one who's got the driver for that INTC (well, Linux will be > the one with the soft ethernet/uart/whatever IP to talk to). All of its > (INTC's) registers are memory mapped to the ARM side. Ok. And the INTC registers include the "mapping" configuration, right? > > - We all know how well shared interrupts work. Is there a point of > > supporting > >64 interrupts when you only have 10 irq lines available? > > I'm looking at these 64 events more like MSI kind of events. It's just Well, that's fine to look at them this way, but they will end up shared no matter what. > that the events themselves can be routed to any of the 10 available HW > IRQ lines. > > > - I assume that the PRUSS interrupt mapping is more or less a question of > > the > >firmware implementation. So you either have a fixed association in the > >firmware which is reflected in the DT description of the IP block or you > >need an interface to tell the PRUSS firmware which event it should map to > >which irq line. Is there actually a value in doing the latter? > > right, I'd say the mapping is pretty static. Unless Suman has some extra > information which I don't. I guess the question was really to see if > there was an easy way for doing this so we don't have to mess with DTS > for every other FW and their neighbor. Well, you will need information about every other firmware simply because you need to know which events the firmware is actually using and what the purpose of the particular event is. Assume you have a simple uart with 3 events (RX, TX, status). So how will the firmware tell you which event is which? You have a few options: 1) DT + fixed mapping scheme: Describe the PRUSS event number in DT and have a fixed mapping scheme like the one you mentioned evt0 -> irq0 . 2) DT + DT mapping scheme Describe the PRUSS event number in DT and describe the mapping scheme in DT as well 3) DT + dynamic mapping scheme Describe the PRUSS event number in DT and let your interrupt controller associate the irq number dynamically. That's kind of similar to MSI with the exception that it needs to support shared interrupts. 4) Fully dynamic association Have a query interface to the firmware which tells you which event it uses for which particular purpose (RX, TX ...) and then establish a dynamic mapping to one of the interrupts. Not sure which level of complexity you want :) Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Routable IRQs
Hi Thomas, Thomas Gleixner writes: > On Tue, 29 Dec 2015, Felipe Balbi wrote: >> Anyway, the interesting part is that PRUSS has 64 events (on current >> incarnations at least) and PRUSS has 10 physical IRQ lines to the ARM >> land. Each of these 64 events can be routed to any of these 10 IRQ >> lines. This might not be very useful on UP (AM335x & AM437x) other than >> the fact that soft-IP drivers running on Linux would need to guarantee >> they are the ones who should handle the IRQ. However, on SMP (AM57xx) we >> could have real tangible benefits by means of IRQ affinity, etc. >> >> So, the question is, what is there in IRQ subsystem today for routable >> IRQ support ? >> >> If a Diagram helps here's a simple one. Note that I'm not showing >> details on the PRUSS side, but that side can also map events pretty much >> any way it wants. >> >> .. .. >> | HOST CPU | | PRUSS| >> || || >> || || >> | irq0 |<-.--|evt0| >> || | || >> | irq1 | | .---|evt1| >> || | | || >> | irq2 | '--|evt2| >> || | || >> | irq3 | | || >> || | || >> | irq4 | | | . | >> || | || >> | irq5 | | | . | >> || | || >> | irq6 | | | . | >> || | || >> | irq7 |<' || >> || || >> | irq8 | || >> || || >> | irq9 |<|evtN| >> '' '' >> >> Given this setup, what I want to do, is let soft-IP drivers running on >> linux rely on standard *request_*irq() calls and DTS descrition. But I'm >> still considering how/if we should describe the routing itself or just >> go round-robin (i.o.w. irq0 -> evt0, irq1 -> evt1, ..., irq9 -> evt9, >> irq0 -> evt10, ...). >> >> Thoughts ? > > I have a few questions: > > - Is there a "mapping" block between PRUSS and the host interrupt controller >or is this "mapping" block part of PRUSS? The description in TRM is a bit "poor", but from what I can gather, the mapping is done on an interrupt controller inside the PRUSS. However, Linux is the one who's got the driver for that INTC (well, Linux will be the one with the soft ethernet/uart/whatever IP to talk to). All of its (INTC's) registers are memory mapped to the ARM side. > - We all know how well shared interrupts work. Is there a point of supporting >64 interrupts when you only have 10 irq lines available? I'm looking at these 64 events more like MSI kind of events. It's just that the events themselves can be routed to any of the 10 available HW IRQ lines. > - I assume that the PRUSS interrupt mapping is more or less a question of the >firmware implementation. So you either have a fixed association in the >firmware which is reflected in the DT description of the IP block or you >need an interface to tell the PRUSS firmware which event it should map to >which irq line. Is there actually a value in doing the latter? right, I'd say the mapping is pretty static. Unless Suman has some extra information which I don't. I guess the question was really to see if there was an easy way for doing this so we don't have to mess with DTS for every other FW and their neighbor. Chances are (or at least I'm speculating) in most cases we won't use more than 10 events anyway (Suman ?) so we might not run into any troubles. -- balbi signature.asc Description: PGP signature
Re: Routable IRQs
Felipe, On Tue, 29 Dec 2015, Felipe Balbi wrote: > Anyway, the interesting part is that PRUSS has 64 events (on current > incarnations at least) and PRUSS has 10 physical IRQ lines to the ARM > land. Each of these 64 events can be routed to any of these 10 IRQ > lines. This might not be very useful on UP (AM335x & AM437x) other than > the fact that soft-IP drivers running on Linux would need to guarantee > they are the ones who should handle the IRQ. However, on SMP (AM57xx) we > could have real tangible benefits by means of IRQ affinity, etc. > > So, the question is, what is there in IRQ subsystem today for routable > IRQ support ? > > If a Diagram helps here's a simple one. Note that I'm not showing > details on the PRUSS side, but that side can also map events pretty much > any way it wants. > > .. .. > | HOST CPU | | PRUSS| > || || > || || > | irq0 |<-.--|evt0| > || | || > | irq1 | | .---|evt1| > || | | || > | irq2 | '--|evt2| > || | || > | irq3 | | || > || | || > | irq4 | | | . | > || | || > | irq5 | | | . | > || | || > | irq6 | | | . | > || | || > | irq7 |<' || > || || > | irq8 | || > || || > | irq9 |<|evtN| > '' '' > > Given this setup, what I want to do, is let soft-IP drivers running on > linux rely on standard *request_*irq() calls and DTS descrition. But I'm > still considering how/if we should describe the routing itself or just > go round-robin (i.o.w. irq0 -> evt0, irq1 -> evt1, ..., irq9 -> evt9, > irq0 -> evt10, ...). > > Thoughts ? I have a few questions: - Is there a "mapping" block between PRUSS and the host interrupt controller or is this "mapping" block part of PRUSS? - We all know how well shared interrupts work. Is there a point of supporting 64 interrupts when you only have 10 irq lines available? - I assume that the PRUSS interrupt mapping is more or less a question of the firmware implementation. So you either have a fixed association in the firmware which is reflected in the DT description of the IP block or you need an interface to tell the PRUSS firmware which event it should map to which irq line. Is there actually a value in doing the latter? Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Routable IRQs
Hi Thomas & Jason, I'm dealing with an interesting situation which I'm wondering if Linux already support for. Basically, in some TI SoCs we have what's referred to as Programmable Real-Time Unit SubSystem (PRUSS). That's essentially a really simple, low latency, single cycle architecture which is pretty darn good for bit banging peripherals (ETH, SPI, I2C, UART, etc). It's very predicatable because every instruction takes 5ns and interrupts don't cause exceptions, they just get registered. Anyway, the interesting part is that PRUSS has 64 events (on current incarnations at least) and PRUSS has 10 physical IRQ lines to the ARM land. Each of these 64 events can be routed to any of these 10 IRQ lines. This might not be very useful on UP (AM335x & AM437x) other than the fact that soft-IP drivers running on Linux would need to guarantee they are the ones who should handle the IRQ. However, on SMP (AM57xx) we could have real tangible benefits by means of IRQ affinity, etc. So, the question is, what is there in IRQ subsystem today for routable IRQ support ? If a Diagram helps here's a simple one. Note that I'm not showing details on the PRUSS side, but that side can also map events pretty much any way it wants. .. .. | HOST CPU | | PRUSS| || || || || | irq0 |<-.--|evt0| || | || | irq1 | | .---|evt1| || | | || | irq2 | '--|evt2| || | || | irq3 | | || || | || | irq4 | | | . | || | || | irq5 | | | . | || | || | irq6 | | | . | || | || | irq7 |<' || || || | irq8 | || || || | irq9 |<|evtN| '' '' Given this setup, what I want to do, is let soft-IP drivers running on linux rely on standard *request_*irq() calls and DTS descrition. But I'm still considering how/if we should describe the routing itself or just go round-robin (i.o.w. irq0 -> evt0, irq1 -> evt1, ..., irq9 -> evt9, irq0 -> evt10, ...). Thoughts ? -- balbi signature.asc Description: PGP signature
[PATCH v6 5/7] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Acked-by: Tony Lindgren
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b..1e0d212 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
- arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
--
2.1.4
--
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[PATCH v5 5/7] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b..1e0d212 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
- arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
--
2.1.4
--
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the body of a message to majord...@vger.kernel.org
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[PATCH v4 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
- arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
--
2.1.4
--
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the body of a message to majord...@vger.kernel.org
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[PATCH v3 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
- arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
--
2.1.4
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 11/21] DT: arm,gic: kill arm,routable-irqs
Nobody will regret it.
Signed-off-by: Marc Zyngier
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -52,11 +52,6 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
-- arm,routable-irqs : Total number of gic irq inputs which are not directly
- connected from the peripherals, but are routed dynamically
- by a crossbar/multiplexer preceding the GIC. The GIC irq
- input line is assigned dynamically when the corresponding
- peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -64,7 +59,6 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
- arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
--
2.1.4
--
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[PATCH V4 1/2] arm: dts: dra7: add routable-irqs property for gic node
From: R Sricharan There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..1cf4ee1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/2] arm: dts: dra7: add routable-irqs property for gic node
From: R Sricharan There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..1cf4ee1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/2] ARM: dts: DRA7: Add routable-irqs property for gic node
From: R Sricharan There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Tested-by: Darren Etheridge Tested-by: Roger Quadros --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..1cf4ee1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: DRA7: Add routable-irqs property for gic node
From: R Sricharan There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Tested-by: Darren Etheridge Tested-by: Roger Quadros --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c29945e..1cf4ee1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -45,6 +45,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V6 1/2] arm: dts: dra7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Tested-by: Darren Etheridge Tested-by: Roger Quadros --- [V6] Reordered patch 3 from V5 to patch 1 arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 149b550..52df16a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 3/3] arm: dts: dra7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon --- [V5] Rebased and corrected routable irqs from 160 to 192 arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 52e4bd0..cec826f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND Patch 9/9] ARM: DTS: DRA7: Add routable-irqs property for gic node
From: Sricharan R There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar Signed-off-by: Mugunthan V N --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2bd3a9a..824e316 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <160>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V5 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
Reviewed-by: Thomas Gleixner
Acked-by: Santosh Shilimkar
Acked-by: Linus Walleij
---
Documentation/devicetree/bindings/arm/gic.txt |6 ++
drivers/irqchip/irq-gic.c | 82 ++---
include/linux/irqchip/arm-gic.h |7 ++-
3 files changed, 84 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
+ arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9031171..5cfb602 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -824,16 +824,25 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ gic_routable_irq_domain_ops->map(d, irq, hw);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int
*out_type)
{
+ unsigned long ret = 0;
+
if (d->of_node != controller)
return -EINVAL;
if (intsize < 3)
@@ -843,11 +852,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
- *out_hwirq += 16;
+ if (!intspec[0]) {
+ ret = gic_routable_irq_domain_ops->xlate(d, controller,
+intspec,
+intsize,
+out_hwirq,
+out_type);
+
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ }
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
- return 0;
+
+ return ret;
}
#ifdef CONFIG_SMP
@@ -871,9 +889,41 @@ static struct notifier_block gic_cpu_notifier = {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+ .unmap = gic_irq_domain_unmap,
.xlate = gic_irq_domain_xlate,
};
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ return 0;
+}
+
+static void gic_routable_irq_domain_unmap(struct irq_domain *d,
+ unsigned int irq)
+{
+}
+
+static int gic_routable_irq_domain_xlate(struct irq_domain *d,
+ struct device_node *contr
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Hi Mark, Sorry for delayed response. I was away for some time. On Friday 15 November 2013 04:53 PM, Mark Rutland wrote: > On Thu, Nov 14, 2013 at 04:46:36PM +, Sricharan R wrote: >> Hi Mark, >> >> On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote: >>> On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote: >>>> In some socs the gic can be preceded by a crossbar IP which >>>> routes the peripheral interrupts to the gic inputs. The peripheral >>>> interrupts are associated with a fixed crossbar input line and the >>>> crossbar routes that to one of the free gic input line. >>>> >>>> The DT entries for peripherals provides the fixed crossbar input line >>>> as its interrupt number and the mapping code should associate this with >>>> a free gic input line. This patch adds the support inside the gic irqchip >>>> to handle such routable irqs. The routable irqs are registered in a linear >>>> domain. The registered routable domain's callback should be implemented >>>> to get a free irq and to configure the IP to route it. >>>> >>>> Cc: Thomas Gleixner >>>> Cc: Linus Walleij >>>> Cc: Santosh Shilimkar >>>> Cc: Russell King >>>> Cc: Tony Lindgren >>>> Cc: Rajendra Nayak >>>> Cc: Marc Zyngier >>>> Cc: Grant Likely >>>> Cc: Rob Herring >>>> Signed-off-by: Sricharan R >>>> Acked-by: Santosh Shilimkar >>>> --- >>>> [V2] Added default routable-irqs functions to avoid >>>> unnecessary if checks as per Thomas Gleixner comments >>>> and renamed routable-irq binding as per >>>> Kumar Gala comments. >>>> >>>> [V3] Addressed unnecessary warn-on and updated default >>>> xlate function as per Thomas Gleixner comments >>>> >>>> Documentation/devicetree/bindings/arm/gic.txt |6 ++ >>>> drivers/irqchip/irq-gic.c | 81 >>>> ++--- >>>> include/linux/irqchip/arm-gic.h |7 ++- >>>> 3 files changed, 83 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/gic.txt >>>> b/Documentation/devicetree/bindings/arm/gic.txt >>>> index 3dfb0c0..5357745 100644 >>>> --- a/Documentation/devicetree/bindings/arm/gic.txt >>>> +++ b/Documentation/devicetree/bindings/arm/gic.txt >>>> @@ -49,6 +49,11 @@ Optional >>>>regions, used when the GIC doesn't have banked registers. The offset is >>>>cpu-offset * cpu-nr. >>>> >>>> +- arm,routable-irqs : Total number of gic irq inputs which are not >>>> directly >>>> +connected from the peripherals, but are routed dynamically >>>> +by a crossbar/multiplexer preceding the GIC. The GIC irq >>>> +input line is assigned dynamically when the corresponding >>>> +peripheral's crossbar line is mapped. >>> I'm not keen on the design of the arm,routable-irqs property. The set of >>> IRQs which the crossbar IP can use is a property of which IRQ lines it >>> has routed to the GIC. I don't see why that should be considered a >>> property of the GIC; it's a property of the crossbar IP's attachment to >>> the GIC. >>> >>> Given we already have a mechanism for describing the attachment (i.e. >>> the interrupts property) where the property appears on the node for the >>> device generating/propagating the interrupt, I don't see why we should >>> do differently here. >> We did try using interrupts=<> property for all peripherals and >> mapping them as crossbar's parent. But that approach of representing >> crossbar as a interrupt parent was not accepted, since the crossbar >> was just routing the interrupts from peripherals to GIC and nothing more. >> Also mapping all the interrupts using interrupt-map like property by a >> fixed way >> in DTS itself was considered hacky > I'm not suggesting you should interrupt-map. I agree that that > interrupt-map is not suitable for a dynamically configurable device like > the crossbar. > > When you say that the crossbar is just routing the interrupts, at what > level is it doing so? Does it accept a logical interrupt and output > another logical interrupt, or does it just connect the two lines >
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Friday 15 November 2013 06:23 AM, Mark Rutland wrote: > On Thu, Nov 14, 2013 at 04:46:36PM +, Sricharan R wrote: >> Hi Mark, >> >> On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote: >>> On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote: >>>> In some socs the gic can be preceded by a crossbar IP which >>>> routes the peripheral interrupts to the gic inputs. The peripheral >>>> interrupts are associated with a fixed crossbar input line and the >>>> crossbar routes that to one of the free gic input line. >>>> >>>> The DT entries for peripherals provides the fixed crossbar input line >>>> as its interrupt number and the mapping code should associate this with >>>> a free gic input line. This patch adds the support inside the gic irqchip >>>> to handle such routable irqs. The routable irqs are registered in a linear >>>> domain. The registered routable domain's callback should be implemented >>>> to get a free irq and to configure the IP to route it. >>>> >>>> Cc: Thomas Gleixner >>>> Cc: Linus Walleij >>>> Cc: Santosh Shilimkar >>>> Cc: Russell King >>>> Cc: Tony Lindgren >>>> Cc: Rajendra Nayak >>>> Cc: Marc Zyngier >>>> Cc: Grant Likely >>>> Cc: Rob Herring >>>> Signed-off-by: Sricharan R >>>> Acked-by: Santosh Shilimkar >>>> --- >>>> [V2] Added default routable-irqs functions to avoid >>>> unnecessary if checks as per Thomas Gleixner comments >>>> and renamed routable-irq binding as per >>>> Kumar Gala comments. >>>> >>>> [V3] Addressed unnecessary warn-on and updated default >>>> xlate function as per Thomas Gleixner comments >>>> >>>> Documentation/devicetree/bindings/arm/gic.txt |6 ++ >>>> drivers/irqchip/irq-gic.c | 81 >>>> ++--- >>>> include/linux/irqchip/arm-gic.h |7 ++- >>>> 3 files changed, 83 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/arm/gic.txt >>>> b/Documentation/devicetree/bindings/arm/gic.txt >>>> index 3dfb0c0..5357745 100644 >>>> --- a/Documentation/devicetree/bindings/arm/gic.txt >>>> +++ b/Documentation/devicetree/bindings/arm/gic.txt >>>> @@ -49,6 +49,11 @@ Optional >>>>regions, used when the GIC doesn't have banked registers. The offset is >>>>cpu-offset * cpu-nr. >>>> >>>> +- arm,routable-irqs : Total number of gic irq inputs which are not >>>> directly >>>> +connected from the peripherals, but are routed dynamically >>>> +by a crossbar/multiplexer preceding the GIC. The GIC irq >>>> +input line is assigned dynamically when the corresponding >>>> +peripheral's crossbar line is mapped. >>> I'm not keen on the design of the arm,routable-irqs property. The set of >>> IRQs which the crossbar IP can use is a property of which IRQ lines it >>> has routed to the GIC. I don't see why that should be considered a >>> property of the GIC; it's a property of the crossbar IP's attachment to >>> the GIC. >>> >>> Given we already have a mechanism for describing the attachment (i.e. >>> the interrupts property) where the property appears on the node for the >>> device generating/propagating the interrupt, I don't see why we should >>> do differently here. >> We did try using interrupts=<> property for all peripherals and >> mapping them as crossbar's parent. But that approach of representing >> crossbar as a interrupt parent was not accepted, since the crossbar >> was just routing the interrupts from peripherals to GIC and nothing more. >> Also mapping all the interrupts using interrupt-map like property by a >> fixed way >> in DTS itself was considered hacky > > I'm not suggesting you should interrupt-map. I agree that that > interrupt-map is not suitable for a dynamically configurable device like > the crossbar. > > When you say that the crossbar is just routing the interrupts, at what > level is it doing so? Does it accept a logical interrupt and output > another logical interrupt, or does it just connect the two lines > electrically? > Its just makes electrical connection between input and output line and thats it. Regards, Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Thu, Nov 14, 2013 at 04:46:36PM +, Sricharan R wrote: > Hi Mark, > > On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote: > > On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote: > >> In some socs the gic can be preceded by a crossbar IP which > >> routes the peripheral interrupts to the gic inputs. The peripheral > >> interrupts are associated with a fixed crossbar input line and the > >> crossbar routes that to one of the free gic input line. > >> > >> The DT entries for peripherals provides the fixed crossbar input line > >> as its interrupt number and the mapping code should associate this with > >> a free gic input line. This patch adds the support inside the gic irqchip > >> to handle such routable irqs. The routable irqs are registered in a linear > >> domain. The registered routable domain's callback should be implemented > >> to get a free irq and to configure the IP to route it. > >> > >> Cc: Thomas Gleixner > >> Cc: Linus Walleij > >> Cc: Santosh Shilimkar > >> Cc: Russell King > >> Cc: Tony Lindgren > >> Cc: Rajendra Nayak > >> Cc: Marc Zyngier > >> Cc: Grant Likely > >> Cc: Rob Herring > >> Signed-off-by: Sricharan R > >> Acked-by: Santosh Shilimkar > >> --- > >> [V2] Added default routable-irqs functions to avoid > >> unnecessary if checks as per Thomas Gleixner comments > >> and renamed routable-irq binding as per > >> Kumar Gala comments. > >> > >> [V3] Addressed unnecessary warn-on and updated default > >> xlate function as per Thomas Gleixner comments > >> > >> Documentation/devicetree/bindings/arm/gic.txt |6 ++ > >> drivers/irqchip/irq-gic.c | 81 > >> ++--- > >> include/linux/irqchip/arm-gic.h |7 ++- > >> 3 files changed, 83 insertions(+), 11 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/gic.txt > >> b/Documentation/devicetree/bindings/arm/gic.txt > >> index 3dfb0c0..5357745 100644 > >> --- a/Documentation/devicetree/bindings/arm/gic.txt > >> +++ b/Documentation/devicetree/bindings/arm/gic.txt > >> @@ -49,6 +49,11 @@ Optional > >>regions, used when the GIC doesn't have banked registers. The offset is > >>cpu-offset * cpu-nr. > >> > >> +- arm,routable-irqs : Total number of gic irq inputs which are not > >> directly > >> +connected from the peripherals, but are routed dynamically > >> +by a crossbar/multiplexer preceding the GIC. The GIC irq > >> +input line is assigned dynamically when the corresponding > >> +peripheral's crossbar line is mapped. > > I'm not keen on the design of the arm,routable-irqs property. The set of > > IRQs which the crossbar IP can use is a property of which IRQ lines it > > has routed to the GIC. I don't see why that should be considered a > > property of the GIC; it's a property of the crossbar IP's attachment to > > the GIC. > > > > Given we already have a mechanism for describing the attachment (i.e. > > the interrupts property) where the property appears on the node for the > > device generating/propagating the interrupt, I don't see why we should > > do differently here. > We did try using interrupts=<> property for all peripherals and > mapping them as crossbar's parent. But that approach of representing > crossbar as a interrupt parent was not accepted, since the crossbar > was just routing the interrupts from peripherals to GIC and nothing more. > Also mapping all the interrupts using interrupt-map like property by a > fixed way > in DTS itself was considered hacky I'm not suggesting you should interrupt-map. I agree that that interrupt-map is not suitable for a dynamically configurable device like the crossbar. When you say that the crossbar is just routing the interrupts, at what level is it doing so? Does it accept a logical interrupt and output another logical interrupt, or does it just connect the two lines electrically? We don't necessarily have to use the interrupts property, but I still think that the set of GIC input IRQ lines that the crossbar is wired to should be described on the crossbar node. > > Listing 160 interrupts in the crossbar node is clearly something we > > don't want to have to do. If we had a property that we could use to > > define a range (or multiple
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Hi Mark, On Thursday 14 November 2013 07:31 PM, Mark Rutland wrote: > On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote: >> In some socs the gic can be preceded by a crossbar IP which >> routes the peripheral interrupts to the gic inputs. The peripheral >> interrupts are associated with a fixed crossbar input line and the >> crossbar routes that to one of the free gic input line. >> >> The DT entries for peripherals provides the fixed crossbar input line >> as its interrupt number and the mapping code should associate this with >> a free gic input line. This patch adds the support inside the gic irqchip >> to handle such routable irqs. The routable irqs are registered in a linear >> domain. The registered routable domain's callback should be implemented >> to get a free irq and to configure the IP to route it. >> >> Cc: Thomas Gleixner >> Cc: Linus Walleij >> Cc: Santosh Shilimkar >> Cc: Russell King >> Cc: Tony Lindgren >> Cc: Rajendra Nayak >> Cc: Marc Zyngier >> Cc: Grant Likely >> Cc: Rob Herring >> Signed-off-by: Sricharan R >> Acked-by: Santosh Shilimkar >> --- >> [V2] Added default routable-irqs functions to avoid >> unnecessary if checks as per Thomas Gleixner comments >> and renamed routable-irq binding as per >> Kumar Gala comments. >> >> [V3] Addressed unnecessary warn-on and updated default >> xlate function as per Thomas Gleixner comments >> >> Documentation/devicetree/bindings/arm/gic.txt |6 ++ >> drivers/irqchip/irq-gic.c | 81 >> ++--- >> include/linux/irqchip/arm-gic.h |7 ++- >> 3 files changed, 83 insertions(+), 11 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/gic.txt >> b/Documentation/devicetree/bindings/arm/gic.txt >> index 3dfb0c0..5357745 100644 >> --- a/Documentation/devicetree/bindings/arm/gic.txt >> +++ b/Documentation/devicetree/bindings/arm/gic.txt >> @@ -49,6 +49,11 @@ Optional >>regions, used when the GIC doesn't have banked registers. The offset is >>cpu-offset * cpu-nr. >> >> +- arm,routable-irqs : Total number of gic irq inputs which are not directly >> + connected from the peripherals, but are routed dynamically >> + by a crossbar/multiplexer preceding the GIC. The GIC irq >> + input line is assigned dynamically when the corresponding >> + peripheral's crossbar line is mapped. > I'm not keen on the design of the arm,routable-irqs property. The set of > IRQs which the crossbar IP can use is a property of which IRQ lines it > has routed to the GIC. I don't see why that should be considered a > property of the GIC; it's a property of the crossbar IP's attachment to > the GIC. > > Given we already have a mechanism for describing the attachment (i.e. > the interrupts property) where the property appears on the node for the > device generating/propagating the interrupt, I don't see why we should > do differently here. We did try using interrupts=<> property for all peripherals and mapping them as crossbar's parent. But that approach of representing crossbar as a interrupt parent was not accepted, since the crossbar was just routing the interrupts from peripherals to GIC and nothing more. Also mapping all the interrupts using interrupt-map like property by a fixed way in DTS itself was considered hacky > Listing 160 interrupts in the crossbar node is clearly something we > don't want to have to do. If we had a property that we could use to > define a range (or multiple ranges) of interrupts, then the crossbar > driver could go and request those ranges from its interrupt-parent (the > GIC) and the GIC driver could reserve/allocate the irqdomain at that > time. Again, this kind of approach of crossbar requesting irqs from GIC was tried earlier and it did not go anywhere. Subsequently after lot of discussions this design was considered the best one. http://www.spinics.net/lists/linux-omap/msg97085.html > This feels like a point-hack, counter in style to the vast majority of > provider/consumer bindings. It only allows for one multiplexer before > the GIC. What if we had multiple multiplexers feeding into the GIC? > Describing the attachment on the multiplexer allows that to be handled, > describing that on the GIC does not. This is case where the interrupts to GIC is not coming from full irqchip, but just a router and support added in the GIC helps to handle such cases. In the case of more than one multiplexer, the crossbar driver should real
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Thu, Nov 14, 2013 at 12:18:47PM +, Sricharan R wrote: > In some socs the gic can be preceded by a crossbar IP which > routes the peripheral interrupts to the gic inputs. The peripheral > interrupts are associated with a fixed crossbar input line and the > crossbar routes that to one of the free gic input line. > > The DT entries for peripherals provides the fixed crossbar input line > as its interrupt number and the mapping code should associate this with > a free gic input line. This patch adds the support inside the gic irqchip > to handle such routable irqs. The routable irqs are registered in a linear > domain. The registered routable domain's callback should be implemented > to get a free irq and to configure the IP to route it. > > Cc: Thomas Gleixner > Cc: Linus Walleij > Cc: Santosh Shilimkar > Cc: Russell King > Cc: Tony Lindgren > Cc: Rajendra Nayak > Cc: Marc Zyngier > Cc: Grant Likely > Cc: Rob Herring > Signed-off-by: Sricharan R > Acked-by: Santosh Shilimkar > --- > [V2] Added default routable-irqs functions to avoid > unnecessary if checks as per Thomas Gleixner comments > and renamed routable-irq binding as per > Kumar Gala comments. > > [V3] Addressed unnecessary warn-on and updated default > xlate function as per Thomas Gleixner comments > > Documentation/devicetree/bindings/arm/gic.txt |6 ++ > drivers/irqchip/irq-gic.c | 81 > ++--- > include/linux/irqchip/arm-gic.h |7 ++- > 3 files changed, 83 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/gic.txt > b/Documentation/devicetree/bindings/arm/gic.txt > index 3dfb0c0..5357745 100644 > --- a/Documentation/devicetree/bindings/arm/gic.txt > +++ b/Documentation/devicetree/bindings/arm/gic.txt > @@ -49,6 +49,11 @@ Optional >regions, used when the GIC doesn't have banked registers. The offset is >cpu-offset * cpu-nr. > > +- arm,routable-irqs : Total number of gic irq inputs which are not directly > + connected from the peripherals, but are routed dynamically > + by a crossbar/multiplexer preceding the GIC. The GIC irq > + input line is assigned dynamically when the corresponding > + peripheral's crossbar line is mapped. I'm not keen on the design of the arm,routable-irqs property. The set of IRQs which the crossbar IP can use is a property of which IRQ lines it has routed to the GIC. I don't see why that should be considered a property of the GIC; it's a property of the crossbar IP's attachment to the GIC. Given we already have a mechanism for describing the attachment (i.e. the interrupts property) where the property appears on the node for the device generating/propagating the interrupt, I don't see why we should do differently here. Listing 160 interrupts in the crossbar node is clearly something we don't want to have to do. If we had a property that we could use to define a range (or multiple ranges) of interrupts, then the crossbar driver could go and request those ranges from its interrupt-parent (the GIC) and the GIC driver could reserve/allocate the irqdomain at that time. This feels like a point-hack, counter in style to the vast majority of provider/consumer bindings. It only allows for one multiplexer before the GIC. What if we had multiple multiplexers feeding into the GIC? Describing the attachment on the multiplexer allows that to be handled, describing that on the GIC does not. Describing the attachement on the multiplexer would also prevent the duplication of information (i.e. the max-irqs property in the crossbar binding). Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Thursday 14 November 2013 06:03 PM, Thomas Gleixner wrote: > On Thu, 14 Nov 2013, Sricharan R wrote: >> [V3] Addressed unnecessary warn-on and updated default >> xlate function as per Thomas Gleixner comments > Reviewed-by: Thomas Gleixner Thanks Thomas.. Regards, Sricharan -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Thu, 14 Nov 2013, Sricharan R wrote: > [V3] Addressed unnecessary warn-on and updated default > xlate function as per Thomas Gleixner comments Reviewed-by: Thomas Gleixner -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 3/3] ARM: DTS: DRA7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R Acked-by: Santosh Shilimkar --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8b93b7a..fd58a09 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -67,6 +67,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <160>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 1/4] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
Acked-by: Santosh Shilimkar
---
[V2] Added default routable-irqs functions to avoid
unnecessary if checks as per Thomas Gleixner comments
and renamed routable-irq binding as per
Kumar Gala comments.
[V3] Addressed unnecessary warn-on and updated default
xlate function as per Thomas Gleixner comments
Documentation/devicetree/bindings/arm/gic.txt |6 ++
drivers/irqchip/irq-gic.c | 81 ++---
include/linux/irqchip/arm-gic.h |7 ++-
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
+ arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9031171..b7b39a7 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -824,16 +824,25 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ gic_routable_irq_domain_ops->map(d, irq, hw);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int
*out_type)
{
+ unsigned long ret = 0;
+
if (d->of_node != controller)
return -EINVAL;
if (intsize < 3)
@@ -843,11 +852,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
- *out_hwirq += 16;
+ if (!intspec[0]) {
+ ret = gic_routable_irq_domain_ops->xlate(d, controller,
+intspec,
+intsize,
+out_hwirq,
+out_type);
+
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ }
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
- return 0;
+
+ return ret;
}
#ifdef CONFIG_SMP
@@ -871,9 +889,41 @@ static struct notifier_block gic_cpu_notifier = {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+ .unmap = gic_irq_domain_unmap,
.xlate = gic_irq_domain_xlate,
};
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ return
Re: [PATCH V3 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Hi, On Wednesday 13 November 2013 08:54 PM, Santosh Shilimkar wrote: > On Tuesday 05 November 2013 08:14 AM, Sricharan R wrote: >> In some socs the gic can be preceded by a crossbar IP which >> routes the peripheral interrupts to the gic inputs. The peripheral >> interrupts are associated with a fixed crossbar input line and the >> crossbar routes that to one of the free gic input line. >> >> The DT entries for peripherals provides the fixed crossbar input line >> as its interrupt number and the mapping code should associate this with >> a free gic input line. This patch adds the support inside the gic irqchip >> to handle such routable irqs. The routable irqs are registered in a linear >> domain. The registered routable domain's callback should be implemented >> to get a free irq and to configure the IP to route it. >> >> Cc: Thomas Gleixner >> Cc: Linus Walleij >> Cc: Santosh Shilimkar >> Cc: Russell King >> Cc: Tony Lindgren >> Cc: Rajendra Nayak >> Cc: Marc Zyngier >> Cc: Grant Likely >> Cc: Rob Herring >> Signed-off-by: Sricharan R >> --- > Acked-by: Santosh Shilimkar Thanks Santosh. Will repost all with the minor changes suggested. Regards, Sricharan -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3 5/7] ARM: DTS: DRA7: Add routable-irqs property for gic node
On Tuesday 05 November 2013 08:14 AM, Sricharan R wrote: > There is a IRQ crossbar device in the soc, which maps the > irq requests from the peripherals to the mpu interrupt > controller's inputs. The gic provides the support for such > IPs in the form of routable-irqs. So adding the property > here to gic node. > > Cc: Benoit Cousson > Cc: Santosh Shilimkar > Cc: Rajendra Nayak > Cc: Tony Lindgren > Signed-off-by: Sricharan R > --- Acked-by: Santosh Shilimkar -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V3 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Tuesday 05 November 2013 08:14 AM, Sricharan R wrote: > In some socs the gic can be preceded by a crossbar IP which > routes the peripheral interrupts to the gic inputs. The peripheral > interrupts are associated with a fixed crossbar input line and the > crossbar routes that to one of the free gic input line. > > The DT entries for peripherals provides the fixed crossbar input line > as its interrupt number and the mapping code should associate this with > a free gic input line. This patch adds the support inside the gic irqchip > to handle such routable irqs. The routable irqs are registered in a linear > domain. The registered routable domain's callback should be implemented > to get a free irq and to configure the IP to route it. > > Cc: Thomas Gleixner > Cc: Linus Walleij > Cc: Santosh Shilimkar > Cc: Russell King > Cc: Tony Lindgren > Cc: Rajendra Nayak > Cc: Marc Zyngier > Cc: Grant Likely > Cc: Rob Herring > Signed-off-by: Sricharan R > --- Acked-by: Santosh Shilimkar -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V3 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
---
[V2] Added default routable-irqs functions to avoid
unnecessary if checks as per Thomas Gleixner comments
and renamed routable-irq binding as per
Kumar Gala comments.
[V3] Addressed unnecessary warn-on and updated default
xlate function as per Thomas Gleixner comments
Documentation/devicetree/bindings/arm/gic.txt |6 ++
drivers/irqchip/irq-gic.c | 81 ++---
include/linux/irqchip/arm-gic.h |8 ++-
3 files changed, 84 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
+ arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d0e9480..07be228 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -681,16 +681,25 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ gic_routable_irq_domain_ops->map(d, irq, hw);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int
*out_type)
{
+ unsigned long ret = 0;
+
if (d->of_node != controller)
return -EINVAL;
if (intsize < 3)
@@ -700,11 +709,20 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
- *out_hwirq += 16;
+ if (!intspec[0]) {
+ ret = gic_routable_irq_domain_ops->xlate(d, controller,
+intspec,
+intsize,
+out_hwirq,
+out_type);
+
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ }
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
- return 0;
+
+ return ret;
}
#ifdef CONFIG_SMP
@@ -728,9 +746,41 @@ static struct notifier_block gic_cpu_notifier = {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+ .unmap = gic_irq_domain_unmap,
.xlate = gic_irq_domain_xlate,
};
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ return
[PATCH V3 5/7] ARM: DTS: DRA7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8b93b7a..fd58a09 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -67,6 +67,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <160>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Oct 30, 2013, at 9:57 AM, Sricharan R wrote:
> In some socs the gic can be preceded by a crossbar IP which
> routes the peripheral interrupts to the gic inputs. The peripheral
> interrupts are associated with a fixed crossbar input line and the
> crossbar routes that to one of the free gic input line.
>
> The DT entries for peripherals provides the fixed crossbar input line
> as its interrupt number and the mapping code should associate this with
> a free gic input line. This patch adds the support inside the gic irqchip
> to handle such routable irqs. The routable irqs are registered in a linear
> domain. The registered routable domain's callback should be implemented
> to get a free irq and to configure the IP to route it.
>
> Cc: Thomas Gleixner
> Cc: Linus Walleij
> Cc: Santosh Shilimkar
> Cc: Russell King
> Cc: Tony Lindgren
> Cc: Rajendra Nayak
> Cc: Marc Zyngier
> Cc: Grant Likely
> Cc: Rob Herring
> Signed-off-by: Sricharan R
> ---
> [V2] Added default routable-irqs functions to avoid
> unnessecary if checks as per Thomas Gleixner comments
> and renamed routable-irq binding as per
> Kumar Gala comments.
>
> Documentation/devicetree/bindings/arm/gic.txt |6 ++
> drivers/irqchip/irq-gic.c | 83 ++---
> include/linux/irqchip/arm-gic.h |8 ++-
> 3 files changed, 87 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt
> b/Documentation/devicetree/bindings/arm/gic.txt
> index 3dfb0c0..5357745 100644
> --- a/Documentation/devicetree/bindings/arm/gic.txt
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -49,6 +49,11 @@ Optional
> regions, used when the GIC doesn't have banked registers. The offset is
> cpu-offset * cpu-nr.
>
> +- arm,routable-irqs : Total number of gic irq inputs which are not directly
> + connected from the peripherals, but are routed dynamically
> + by a crossbar/multiplexer preceding the GIC. The GIC irq
> + input line is assigned dynamically when the corresponding
> + peripheral's crossbar line is mapped.
> Example:
>
> intc: interrupt-controller@fff11000 {
> @@ -56,6 +61,7 @@ Example:
> #interrupt-cells = <3>;
> #address-cells = <1>;
> interrupt-controller;
> + arm,routable-irqs = <160>;
> reg = <0xfff11000 0x1000>,
> <0xfff10100 0x100>;
> };
DT Binding portion:
Acked-by: Kumar Gala
- k
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RE: [PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Hi Thomas,
Sorry for top posting. My mailer is not allowing me any formatting.
I agree with both of your comments below.
I will post V3 for this.
Regards,
Sricharan
From: Thomas Gleixner [t...@linutronix.de]
Sent: Wednesday, October 30, 2013 8:45 PM
To: R, Sricharan
Cc: linux-ker...@vger.kernel.org; devicet...@vger.kernel.org;
linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
linux-omap@vger.kernel.org; linus.wall...@linaro.org; li...@arm.linux.org.uk;
t...@atomide.com; Nayak, Rajendra; marc.zyng...@arm.com;
grant.lik...@linaro.org; mark.rutl...@arm.com; robherri...@gmail.com;
Shilimkar, Santosh; Rob Herring
Subject: Re: [PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable
irqs
On Wed, 30 Oct 2013, Sricharan R wrote:
> @@ -700,11 +709,22 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> *out_hwirq = intspec[1] + 16;
>
> /* For SPIs, we need to add 16 more to get the GIC irq ID number */
> - if (!intspec[0])
> + if (!intspec[0]) {
> *out_hwirq += 16;
Minor nit. This should be in the default implementation. The crossbar
implementation will fill out_hwirq in its own way and is not
interested in the +16 operation at all.
> + ret = gic_routable_irq_domain_ops->xlate(d, controller,
> + intspec,
> + intsize,
> + out_hwirq,
> + out_type);
> +
> + gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
> + hwirq_base, &gic_irq_domain_ops, gic);
> + } else {
> + if (WARN_ON(!gic_routable_irq_domain_ops))
> + return;
This warning is pointless, because you have default ops now.
> +
> + gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
> + &gic_irq_domain_ops,
> + gic);
> }
Thanks,
tglx--
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Re: [PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Wed, 30 Oct 2013, Sricharan R wrote:
> @@ -700,11 +709,22 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> *out_hwirq = intspec[1] + 16;
>
> /* For SPIs, we need to add 16 more to get the GIC irq ID number */
> - if (!intspec[0])
> + if (!intspec[0]) {
> *out_hwirq += 16;
Minor nit. This should be in the default implementation. The crossbar
implementation will fill out_hwirq in its own way and is not
interested in the +16 operation at all.
> + ret = gic_routable_irq_domain_ops->xlate(d, controller,
> + intspec,
> + intsize,
> + out_hwirq,
> + out_type);
> +
> + gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
> + hwirq_base, &gic_irq_domain_ops, gic);
> + } else {
> + if (WARN_ON(!gic_routable_irq_domain_ops))
> + return;
This warning is pointless, because you have default ops now.
> +
> + gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
> + &gic_irq_domain_ops,
> + gic);
> }
Thanks,
tglx
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[PATCH V2 1/7] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
---
[V2] Added default routable-irqs functions to avoid
unnessecary if checks as per Thomas Gleixner comments
and renamed routable-irq binding as per
Kumar Gala comments.
Documentation/devicetree/bindings/arm/gic.txt |6 ++
drivers/irqchip/irq-gic.c | 83 ++---
include/linux/irqchip/arm-gic.h |8 ++-
3 files changed, 87 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..5357745 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
@@ -56,6 +61,7 @@ Example:
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
+ arm,routable-irqs = <160>;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d0e9480..978be2e 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -681,16 +681,25 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ gic_routable_irq_domain_ops->map(d, irq, hw);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ gic_routable_irq_domain_ops->unmap(d, irq);
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
unsigned long *out_hwirq, unsigned int
*out_type)
{
+ unsigned long ret = 0;
+
if (d->of_node != controller)
return -EINVAL;
if (intsize < 3)
@@ -700,11 +709,22 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
+ if (!intspec[0]) {
*out_hwirq += 16;
+ ret = gic_routable_irq_domain_ops->xlate(d, controller,
+intspec,
+intsize,
+out_hwirq,
+out_type);
+
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ }
+
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
- return 0;
+
+ return ret;
}
#ifdef CONFIG_SMP
@@ -728,9 +748,40 @@ static struct notifier_block gic_cpu_notifier = {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+ .unmap = gic_irq_domain_unmap,
.xlate = gic_irq_domain_xlate,
};
+/* Default functions for routable irq domain */
+static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ return 0;
+}
+
+static void gic_routable_irq_domain_unmap(struct irq_domain *d,
+ unsigned int irq)
[PATCH V2 5/7] ARM: DTS: DRA7: Add routable-irqs property for gic node
There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R --- arch/arm/boot/dts/dra7.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index afb89f1..6a5404f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -59,6 +59,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <160>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Thursday 24 October 2013 03:08 PM, Kumar Gala wrote: > On Sep 30, 2013, at 8:59 AM, Sricharan R wrote: > >> In some socs the gic can be preceded by a crossbar IP which >> routes the peripheral interrupts to the gic inputs. The peripheral >> interrupts are associated with a fixed crossbar input line and the >> crossbar routes that to one of the free gic input line. >> >> The DT entries for peripherals provides the fixed crossbar input line >> as its interrupt number and the mapping code should associate this with >> a free gic input line. This patch adds the support inside the gic irqchip >> to handle such routable irqs. The routable irqs are registered in a linear >> domain. The registered routable domain's callback should be implemented >> to get a free irq and to configure the IP to route it. >> >> Cc: Thomas Gleixner >> Cc: Linus Walleij >> Cc: Santosh Shilimkar >> Cc: Russell King >> Cc: Tony Lindgren >> Cc: Rajendra Nayak >> Cc: Marc Zyngier >> Cc: Grant Likely >> Cc: Rob Herring >> Signed-off-by: Sricharan R >> --- >> Documentation/devicetree/bindings/arm/gic.txt |5 +++ >> arch/arm/boot/dts/dra7.dtsi |1 + >> drivers/irqchip/irq-gic.c | 57 >> + >> include/linux/irqchip/arm-gic.h |8 +++- >> 4 files changed, 61 insertions(+), 10 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/gic.txt >> b/Documentation/devicetree/bindings/arm/gic.txt >> index 3dfb0c0..2d8c680 100644 >> --- a/Documentation/devicetree/bindings/arm/gic.txt >> +++ b/Documentation/devicetree/bindings/arm/gic.txt >> @@ -49,6 +49,11 @@ Optional >> regions, used when the GIC doesn't have banked registers. The offset is >> cpu-offset * cpu-nr. >> >> +- routable-irqs : Total number of gic irq inputs which are not directly >> + connected from the peripherals, but are routed dynamically >> + by a crossbar/multiplexer preceding the GIC. The GIC irq >> + input line is assigned dynamically when the corresponding >> + peripheral's crossbar line is mapped. > arm,routable-irqs ok will change here as well. Thanks for reviewing. Regards, Sricharan -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Hi Thomas,
Thanks a lot for reviewing this.
On Thursday 24 October 2013 02:42 PM, Thomas Gleixner wrote:
> On Mon, 30 Sep 2013, Sricharan R wrote:
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 1760ceb..c5778ab 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic.c
>> @@ -72,6 +72,8 @@ struct gic_chip_data {
>>
>> static DEFINE_RAW_SPINLOCK(irq_controller_lock);
>>
>> +const struct irq_domain_ops *gic_routable_irq_domain_ops;
>> +
>> /*
>> * The GIC mapping of CPU interfaces does not necessarily match
>> * the logical CPU numbering. Let's use a mapping as returned
>> @@ -675,11 +677,26 @@ static int gic_irq_domain_map(struct irq_domain *d,
>> unsigned int irq,
>> irq_set_chip_and_handler(irq, &gic_chip,
>> handle_fasteoi_irq);
>> set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
>> +
>> +if (gic_routable_irq_domain_ops &&
>> +gic_routable_irq_domain_ops->map)
>> +gic_routable_irq_domain_ops->map(d, irq, hw);
> Shudder. Why are you sprinkling these if (ops && ops->fun)
> conditionals all over the place instead of having a default ops
> implementation which handles the non crossbar case by proper empty
> functions. That code is not on a hot path so it does not matter at
> all.
>
Ok, Understand. Will add default ops to avoid these checks.
>> }
>> irq_set_chip_data(irq, d->host_data);
>> return 0;
>> }
>>
>> +static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
>> +{
>> +irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
>> +
>> +if (hw > 32) {
> Groan. This wants to be in the ops->unmap function. It's not related
> to the GIC core code.
Ok, will move this to unmap ops of the crossbar.
>> +if (gic_routable_irq_domain_ops &&
>> +gic_routable_irq_domain_ops->unmap)
>> +gic_routable_irq_domain_ops->unmap(d, irq);
>> +}
>> +}
>> +
>> static int gic_irq_domain_xlate(struct irq_domain *d,
>> struct device_node *controller,
>> const u32 *intspec, unsigned int intsize,
>> @@ -694,8 +711,15 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
>> *out_hwirq = intspec[1] + 16;
>>
>> /* For SPIs, we need to add 16 more to get the GIC irq ID number */
>> -if (!intspec[0])
>> -*out_hwirq += 16;
>> +if (!intspec[0]) {
>> +if (gic_routable_irq_domain_ops &&
>> +gic_routable_irq_domain_ops->xlate)
>> +*out_hwirq = gic_routable_irq_domain_ops->xlate(d,
>> +controller, intspec, intsize,
>> +out_hwirq, out_type);
>> +else
>> +*out_hwirq += 16;
>> +}
> So if you have a default xlate ops implementation then this boils down to
>
> if (!intspec[0])
> *out_hwirq = routing_ops->xlate()
>
> And the default (non crossbar) implementation would be:
>
> return *out_hwirq + 16;
>
Ok. This is better. Will change here.
Regards,
Sricharan
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Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Sep 30, 2013, at 8:59 AM, Sricharan R wrote:
> In some socs the gic can be preceded by a crossbar IP which
> routes the peripheral interrupts to the gic inputs. The peripheral
> interrupts are associated with a fixed crossbar input line and the
> crossbar routes that to one of the free gic input line.
>
> The DT entries for peripherals provides the fixed crossbar input line
> as its interrupt number and the mapping code should associate this with
> a free gic input line. This patch adds the support inside the gic irqchip
> to handle such routable irqs. The routable irqs are registered in a linear
> domain. The registered routable domain's callback should be implemented
> to get a free irq and to configure the IP to route it.
>
> Cc: Thomas Gleixner
> Cc: Linus Walleij
> Cc: Santosh Shilimkar
> Cc: Russell King
> Cc: Tony Lindgren
> Cc: Rajendra Nayak
> Cc: Marc Zyngier
> Cc: Grant Likely
> Cc: Rob Herring
> Signed-off-by: Sricharan R
> ---
> Documentation/devicetree/bindings/arm/gic.txt |5 +++
> arch/arm/boot/dts/dra7.dtsi |1 +
> drivers/irqchip/irq-gic.c | 57 +
> include/linux/irqchip/arm-gic.h |8 +++-
> 4 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt
> b/Documentation/devicetree/bindings/arm/gic.txt
> index 3dfb0c0..2d8c680 100644
> --- a/Documentation/devicetree/bindings/arm/gic.txt
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -49,6 +49,11 @@ Optional
> regions, used when the GIC doesn't have banked registers. The offset is
> cpu-offset * cpu-nr.
>
> +- routable-irqs : Total number of gic irq inputs which are not directly
> + connected from the peripherals, but are routed dynamically
> + by a crossbar/multiplexer preceding the GIC. The GIC irq
> + input line is assigned dynamically when the corresponding
> + peripheral's crossbar line is mapped.
arm,routable-irqs
> Example:
>
> intc: interrupt-controller@fff11000 {
- k
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Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Mon, 30 Sep 2013, Sricharan R wrote:
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 1760ceb..c5778ab 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -72,6 +72,8 @@ struct gic_chip_data {
>
> static DEFINE_RAW_SPINLOCK(irq_controller_lock);
>
> +const struct irq_domain_ops *gic_routable_irq_domain_ops;
> +
> /*
> * The GIC mapping of CPU interfaces does not necessarily match
> * the logical CPU numbering. Let's use a mapping as returned
> @@ -675,11 +677,26 @@ static int gic_irq_domain_map(struct irq_domain *d,
> unsigned int irq,
> irq_set_chip_and_handler(irq, &gic_chip,
>handle_fasteoi_irq);
> set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
> +
> + if (gic_routable_irq_domain_ops &&
> + gic_routable_irq_domain_ops->map)
> + gic_routable_irq_domain_ops->map(d, irq, hw);
Shudder. Why are you sprinkling these if (ops && ops->fun)
conditionals all over the place instead of having a default ops
implementation which handles the non crossbar case by proper empty
functions. That code is not on a hot path so it does not matter at
all.
> }
> irq_set_chip_data(irq, d->host_data);
> return 0;
> }
>
> +static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
> +{
> + irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
> +
> + if (hw > 32) {
Groan. This wants to be in the ops->unmap function. It's not related
to the GIC core code.
> + if (gic_routable_irq_domain_ops &&
> + gic_routable_irq_domain_ops->unmap)
> + gic_routable_irq_domain_ops->unmap(d, irq);
> + }
> +}
> +
> static int gic_irq_domain_xlate(struct irq_domain *d,
> struct device_node *controller,
> const u32 *intspec, unsigned int intsize,
> @@ -694,8 +711,15 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
> *out_hwirq = intspec[1] + 16;
>
> /* For SPIs, we need to add 16 more to get the GIC irq ID number */
> - if (!intspec[0])
> - *out_hwirq += 16;
> + if (!intspec[0]) {
> + if (gic_routable_irq_domain_ops &&
> + gic_routable_irq_domain_ops->xlate)
> + *out_hwirq = gic_routable_irq_domain_ops->xlate(d,
> + controller, intspec, intsize,
> + out_hwirq, out_type);
> + else
> + *out_hwirq += 16;
> + }
So if you have a default xlate ops implementation then this boils down to
if (!intspec[0])
*out_hwirq = routing_ops->xlate()
And the default (non crossbar) implementation would be:
return *out_hwirq + 16;
Thanks,
tglx
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Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Mon, Sep 30, 2013 at 4:16 PM, Marc Zyngier wrote: > On 30/09/13 14:59, Sricharan R wrote: >> In some socs the gic can be preceded by a crossbar IP which >> routes the peripheral interrupts to the gic inputs. The peripheral >> interrupts are associated with a fixed crossbar input line and the >> crossbar routes that to one of the free gic input line. >> >> The DT entries for peripherals provides the fixed crossbar input line >> as its interrupt number and the mapping code should associate this with >> a free gic input line. This patch adds the support inside the gic irqchip >> to handle such routable irqs. The routable irqs are registered in a linear >> domain. The registered routable domain's callback should be implemented >> to get a free irq and to configure the IP to route it. > > Isn't this just another chained interrupt controller? How is it GIC > specific? I thought so from the beginning but I was dead wrong, as pointed out by tglx it is basically a hardware .map function, so its usecase will map to the irqdomain .map/.unmap so to say. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Monday 30 September 2013 07:52 PM, Santosh Shilimkar wrote: > On Monday 30 September 2013 10:16 AM, Marc Zyngier wrote: >> On 30/09/13 14:59, Sricharan R wrote: >>> In some socs the gic can be preceded by a crossbar IP which >>> routes the peripheral interrupts to the gic inputs. The peripheral >>> interrupts are associated with a fixed crossbar input line and the >>> crossbar routes that to one of the free gic input line. >>> >>> The DT entries for peripherals provides the fixed crossbar input line >>> as its interrupt number and the mapping code should associate this with >>> a free gic input line. This patch adds the support inside the gic irqchip >>> to handle such routable irqs. The routable irqs are registered in a linear >>> domain. The registered routable domain's callback should be implemented >>> to get a free irq and to configure the IP to route it. >> Isn't this just another chained interrupt controller? How is it GIC >> specific? >> > No it isn't a irq controller rather a event router. Patch is missing > reference to the previous discussion. Previous discussion is here [1] > > Regards, > Santosh > > [1] https://lkml.org/lkml/2013/9/13/413 > Sorry, missed adding that and thanks for pointing it. Regards, Sricharan -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On 30/09/13 15:22, Santosh Shilimkar wrote: > On Monday 30 September 2013 10:16 AM, Marc Zyngier wrote: >> On 30/09/13 14:59, Sricharan R wrote: >>> In some socs the gic can be preceded by a crossbar IP which >>> routes the peripheral interrupts to the gic inputs. The peripheral >>> interrupts are associated with a fixed crossbar input line and the >>> crossbar routes that to one of the free gic input line. >>> >>> The DT entries for peripherals provides the fixed crossbar input line >>> as its interrupt number and the mapping code should associate this with >>> a free gic input line. This patch adds the support inside the gic irqchip >>> to handle such routable irqs. The routable irqs are registered in a linear >>> domain. The registered routable domain's callback should be implemented >>> to get a free irq and to configure the IP to route it. >> >> Isn't this just another chained interrupt controller? How is it GIC >> specific? >> > No it isn't a irq controller rather a event router. Patch is missing > reference to the previous discussion. Previous discussion is here [1] > > Regards, > Santosh > > [1] https://lkml.org/lkml/2013/9/13/413 Right. I need to go and understand that bit first. Thanks Santosh. M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On Monday 30 September 2013 10:16 AM, Marc Zyngier wrote: > On 30/09/13 14:59, Sricharan R wrote: >> In some socs the gic can be preceded by a crossbar IP which >> routes the peripheral interrupts to the gic inputs. The peripheral >> interrupts are associated with a fixed crossbar input line and the >> crossbar routes that to one of the free gic input line. >> >> The DT entries for peripherals provides the fixed crossbar input line >> as its interrupt number and the mapping code should associate this with >> a free gic input line. This patch adds the support inside the gic irqchip >> to handle such routable irqs. The routable irqs are registered in a linear >> domain. The registered routable domain's callback should be implemented >> to get a free irq and to configure the IP to route it. > > Isn't this just another chained interrupt controller? How is it GIC > specific? > No it isn't a irq controller rather a event router. Patch is missing reference to the previous discussion. Previous discussion is here [1] Regards, Santosh [1] https://lkml.org/lkml/2013/9/13/413 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
On 30/09/13 14:59, Sricharan R wrote: > In some socs the gic can be preceded by a crossbar IP which > routes the peripheral interrupts to the gic inputs. The peripheral > interrupts are associated with a fixed crossbar input line and the > crossbar routes that to one of the free gic input line. > > The DT entries for peripherals provides the fixed crossbar input line > as its interrupt number and the mapping code should associate this with > a free gic input line. This patch adds the support inside the gic irqchip > to handle such routable irqs. The routable irqs are registered in a linear > domain. The registered routable domain's callback should be implemented > to get a free irq and to configure the IP to route it. Isn't this just another chained interrupt controller? How is it GIC specific? M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 1/6] DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/arm/gic.txt |5 +++
arch/arm/boot/dts/dra7.dtsi |1 +
drivers/irqchip/irq-gic.c | 57 +
include/linux/irqchip/arm-gic.h |8 +++-
4 files changed, 61 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..2d8c680 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -49,6 +49,11 @@ Optional
regions, used when the GIC doesn't have banked registers. The offset is
cpu-offset * cpu-nr.
+- routable-irqs: Total number of gic irq inputs which are not directly
+ connected from the peripherals, but are routed dynamically
+ by a crossbar/multiplexer preceding the GIC. The GIC irq
+ input line is assigned dynamically when the corresponding
+ peripheral's crossbar line is mapped.
Example:
intc: interrupt-controller@fff11000 {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a5d9350..b35cb12 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -55,6 +55,7 @@
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ routable_irqs = <160>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>;
};
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1760ceb..c5778ab 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -72,6 +72,8 @@ struct gic_chip_data {
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+const struct irq_domain_ops *gic_routable_irq_domain_ops;
+
/*
* The GIC mapping of CPU interfaces does not necessarily match
* the logical CPU numbering. Let's use a mapping as returned
@@ -675,11 +677,26 @@ static int gic_irq_domain_map(struct irq_domain *d,
unsigned int irq,
irq_set_chip_and_handler(irq, &gic_chip,
handle_fasteoi_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ if (gic_routable_irq_domain_ops &&
+ gic_routable_irq_domain_ops->map)
+ gic_routable_irq_domain_ops->map(d, irq, hw);
}
irq_set_chip_data(irq, d->host_data);
return 0;
}
+static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
+{
+ irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
+
+ if (hw > 32) {
+ if (gic_routable_irq_domain_ops &&
+ gic_routable_irq_domain_ops->unmap)
+ gic_routable_irq_domain_ops->unmap(d, irq);
+ }
+}
+
static int gic_irq_domain_xlate(struct irq_domain *d,
struct device_node *controller,
const u32 *intspec, unsigned int intsize,
@@ -694,8 +711,15 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
*out_hwirq = intspec[1] + 16;
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
- if (!intspec[0])
- *out_hwirq += 16;
+ if (!intspec[0]) {
+ if (gic_routable_irq_domain_ops &&
+ gic_routable_irq_domain_ops->xlate)
+ *out_hwirq = gic_routable_irq_domain_ops->xlate(d,
+ controller, intspec, intsize,
+ out_hwirq, out_type);
+ else
+ *out_hwirq += 16;
+ }
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
return 0;
@@ -722,6 +746,7 @@ static struct notifier_block __cpuinitdata gic_cpu_notifier
= {
const struct irq_domain_ops gic_irq_domain_ops = {
.map = gic_irq_domain_map,
+
