[PATCH v3] phy: ti-pipe3: Add SATA DPLL support
From: Roger Quadros
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
Changes from v2:
* kept only the drivers/phy part
drivers/phy/phy-ti-pipe3.c | 76
1 file changed, 55 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy->dpll_map;
- for (i = 0; i < ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return &dpll_map[i].params;
+ rate = clk_get_rate(phy->sys_clk);
+
+ for (; dpll_map->rate; dpll_map++) {
+ if (rate == dpll_map->rate)
+ return &dpll_map->params;
}
+ dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy->sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy->dev,
- "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
val &= ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *match;
- if (!node)
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
+ if (!match)
return -EINVAL;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
@@ -263,6 +281,12 @@ static int ti_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ phy->dpll_map = (struct pipe3_dpll_map *)match->data;
+ if (!phy->dpll_map) {
+ dev_err(&pdev->dev, "no DPLL data\n"
Re: [PATCH v4] phy: omap-control: update dra7 and am437 usb2 Documentation bindings
On Friday 07 March 2014 01:55 PM, Kishon Vijay Abraham I wrote: From: Felipe Balbi From: Roger Quadros There seems to be some problem with this patch. Pls ignore this. Thanks Kishon The dra7-usb2 and am437-usb2 bindings have not yet been used. Change them to be more elegant. Acked-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- Changes from v3: * changed the compatible name to 'ti,control-phy-usb2-dra7' and 'ti,control-phy-usb2-am437' Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 41dc132..8694aae 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -9,9 +9,9 @@ Required properties: e.g. USB2_PHY on OMAP5. "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control e.g. USB3 PHY and SATA PHY on OMAP5. - "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on + "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on DRA7 platform. - "ti,control-phy-am437usb2" - if it has power down register like USB2 PHY on + "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on AM437 platform. - reg : Address and length of the register set for the device. It contains the address of "otghs_control" for control-phy-otghs or "power" register -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4] phy: omap-control: update dra7 and am437 usb2 bindings
From: Roger Quadros
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
Changes from v3:
Changed the compatible value to that suggested by Tony.
ti,control-phy-usb2-dra7 and ti,control-phy-usb2-am437.
Changes from v2:
Kept only the drivers/phy part in this patch
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = &pipe3_data,
},
{
- .compatible = "ti,control-phy-dra7usb2",
+ .compatible = "ti,control-phy-usb2-dra7",
.data = &dra7usb2_data,
},
{
- .compatible = "ti,control-phy-am437usb2",
+ .compatible = "ti,control-phy-usb2-am437",
.data = &am437usb2_data,
},
{},
--
1.7.9.5
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Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding
Felipe, On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote: Add "wkupclk" and "refclk" information to DT binding information. Signed-off-by: Roger Quadros --- so, should I take this one ? yes.. the ti-phy.txt is only in your tree. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
Signed-off-by: Kishon Vijay Abraham I
---
Changes from v5:
fixes the following compilation error
drivers/usb/phy/phy-twl6030-usb.c:30:32:
fatal error: linux/usb/omap_usb.h: No such file or directory
drivers/phy/phy-omap-usb2.c |2 +-
drivers/usb/phy/phy-twl6030-usb.c |2 +-
include/linux/{usb => phy}/omap_usb.h |3 ---
3 files changed, 2 insertions(+), 5 deletions(-)
rename include/linux/{usb => phy}/omap_usb.h (95%)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 705af5a..9c3f056 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -21,7 +21,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/usb/phy/phy-twl6030-usb.c
b/drivers/usb/phy/phy-twl6030-usb.c
index 214172b..04778cf 100644
--- a/drivers/usb/phy/phy-twl6030-usb.c
+++ b/drivers/usb/phy/phy-twl6030-usb.c
@@ -27,7 +27,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/include/linux/usb/omap_usb.h b/include/linux/phy/omap_usb.h
similarity index 95%
rename from include/linux/usb/omap_usb.h
rename to include/linux/phy/omap_usb.h
index 6ae2936..19d343c3 100644
--- a/include/linux/usb/omap_usb.h
+++ b/include/linux/phy/omap_usb.h
@@ -33,13 +33,10 @@ struct usb_dpll_params {
struct omap_usb {
struct usb_phy phy;
struct phy_companion*comparator;
- void __iomem*pll_ctrl_base;
struct device *dev;
struct device *control_dev;
struct clk *wkupclk;
- struct clk *sys_clk;
struct clk *optclk;
- u8 is_suspended:1;
};
#definephy_to_omapusb(x) container_of((x), struct omap_usb, phy)
--
1.7.9.5
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Re: [PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
On Friday 07 March 2014 10:20 PM, Felipe Balbi wrote:
On Fri, Mar 07, 2014 at 10:18:08PM +0530, Kishon Vijay Abraham I wrote:
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
does this depend in any other patch ? I get the following when applying
*only* this patch on top of v3.14-rc5:
yeah.. this is for linux-phy tree. I'll take this patch.
Thanks
Kishon
drivers/phy/phy-omap-usb2.c: In function ‘omap_usb2_suspend’:
drivers/phy/phy-omap-usb2.c:106:21: error: ‘struct omap_usb’ has no member
named ‘is_suspended’
if (suspend && !phy->is_suspended) {
^
drivers/phy/phy-omap-usb2.c:109:6: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy->is_suspended = 1;
^
drivers/phy/phy-omap-usb2.c:110:28: error: ‘struct omap_usb’ has no member
named ‘is_suspended’
} else if (!suspend && phy->is_suspended) {
^
drivers/phy/phy-omap-usb2.c:117:6: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy->is_suspended = 0;
^
drivers/phy/phy-omap-usb2.c: In function ‘omap_usb2_probe’:
drivers/phy/phy-omap-usb2.c:194:5: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy->is_suspended = 1;
^
make[1]: *** [drivers/phy/phy-omap-usb2.o] Error 1
make: *** [drivers/phy/] Error 2
make: *** Waiting for unfinished jobs
CC [M] drivers/usb/phy/phy-mxs-usb.o
drivers/usb/phy/phy-omap-usb3.c:22:32: fatal error: linux/usb/omap_usb.h: No
such file or directory
#include
^
compilation terminated.
make[1]: *** [drivers/usb/phy/phy-omap-usb3.o] Error 1
make[1]: *** Waiting for unfinished jobs
make: *** [drivers/usb/phy/] Error 2
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Re: [PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
On Friday 07 March 2014 11:10 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 11:09:02PM +0530, Kishon Vijay Abraham I wrote: On Friday 07 March 2014 10:20 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 10:18:08PM +0530, Kishon Vijay Abraham I wrote: No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/. Also removed the unused members of struct omap_usb (after phy-omap-pipe3 started using it's own header file) does this depend in any other patch ? I get the following when applying *only* this patch on top of v3.14-rc5: yeah.. this is for linux-phy tree. I'll take this patch. looks like you're doing two things at once (renaming the header and removing some unnecessary fields). At least mention the second thing. The second line of the commit message mentions just that ;-) Regards Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes
Hi Roger,
On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi | 110 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 ---
2 files changed, 110 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
};
+
+ omap_control_usb2phy1: control-phy@4a002300 {
+ compatible = "ti,control-phy-usb2";
+ reg = <0x4a002300 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb3phy1: control-phy@4a002370 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002370 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb2phy2: control-phy@0x4a002e74 {
+ compatible = "ti,control-phy-usb2-dra7";
+ reg = <0x4a002e74 0x4>;
+ reg-names = "power";
+ };
+
+ /* OCP2SCP1 */
+ ocp2scp@4a08 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x4a08 0x20>;
+ ti,hwmods = "ocp2scp1";
+
+ usb2_phy1: phy@4a084000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a084000 0x400>;
+ ctrl-module = <&omap_control_usb2phy1>;
+ clocks = <&usb_phy1_always_on_clk32k>,
+<&usb_otg_ss1_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy2: phy@4a085000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a085000 0x400>;
+ ctrl-module = <&omap_control_usb2phy2>;
+ clocks = <&usb_phy2_always_on_clk32k>,
+<&usb_otg_ss2_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy1: phy@4a084400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_usb3phy1>;
+ clocks = <&usb_phy3_always_on_clk32k>,
+<&sys_clkin1>,
+<&usb_otg_ss1_refclk960m>,
+<&dpll_core_h13x2_ck>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk",
+ "optclk";
Do we use this 'optclk' in driver?
-Kishon
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Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes
On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
Hi Roger,
On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7.dtsi | 110
++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 ---
2 files changed, 110 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
};
+
+omap_control_usb2phy1: control-phy@4a002300 {
+compatible = "ti,control-phy-usb2";
+reg = <0x4a002300 0x4>;
+reg-names = "power";
+};
+
+omap_control_usb3phy1: control-phy@4a002370 {
+compatible = "ti,control-phy-pipe3";
+reg = <0x4a002370 0x4>;
+reg-names = "power";
+};
+
+omap_control_usb2phy2: control-phy@0x4a002e74 {
+compatible = "ti,control-phy-usb2-dra7";
+reg = <0x4a002e74 0x4>;
+reg-names = "power";
+};
+
+/* OCP2SCP1 */
+ocp2scp@4a08 {
+compatible = "ti,omap-ocp2scp";
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+reg = <0x4a08 0x20>;
+ti,hwmods = "ocp2scp1";
+
+usb2_phy1: phy@4a084000 {
+compatible = "ti,omap-usb2";
+reg = <0x4a084000 0x400>;
+ctrl-module = <&omap_control_usb2phy1>;
+clocks = <&usb_phy1_always_on_clk32k>,
+ <&usb_otg_ss1_refclk960m>;
+clock-names ="wkupclk",
+"refclk";
+#phy-cells = <0>;
+};
+
+usb2_phy2: phy@4a085000 {
+compatible = "ti,omap-usb2";
+reg = <0x4a085000 0x400>;
+ctrl-module = <&omap_control_usb2phy2>;
+clocks = <&usb_phy2_always_on_clk32k>,
+ <&usb_otg_ss2_refclk960m>;
+clock-names ="wkupclk",
+"refclk";
+#phy-cells = <0>;
+};
+
+usb3_phy1: phy@4a084400 {
+compatible = "ti,omap-usb3";
+reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ctrl-module = <&omap_control_usb3phy1>;
+clocks = <&usb_phy3_always_on_clk32k>,
+ <&sys_clkin1>,
+ <&usb_otg_ss1_refclk960m>,
+ <&dpll_core_h13x2_ck>;
+clock-names ="wkupclk",
+"sysclk",
+"refclk",
+"optclk";
Do we use this 'optclk' in driver?
No we don't. Still the device seems to work without it.
This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.
I think it should be enabled. Did you check the status of this clock in
CM_L3INIT_CLKSTCTRL? Moreover USB_LFPS_TX_GFCLK is an interface clock,
so IIUC setting the module mode will enable it.
Btw how did you tell dpll_core_h13x2_ck enables USB_LFPS_TX_GFCLK?
Cheers
Kishon
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Re: [PATCH 1/2] extcon: of: Remove unnecessary function call by using the name of device_node
Hi,
On Tuesday 18 March 2014 05:34 PM, Chanwoo Choi wrote:
> This patch remove unnecessary function call in of_extcon_get_extcon_dev()
> by using the name of device_node structure.
>
> Signed-off-by: Chanwoo Choi
> ---
> drivers/extcon/of_extcon.c | 12 ++--
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/extcon/of_extcon.c b/drivers/extcon/of_extcon.c
> index 72173ec..0a29f82 100644
> --- a/drivers/extcon/of_extcon.c
> +++ b/drivers/extcon/of_extcon.c
> @@ -32,7 +32,6 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct device
> *dev, int index)
> {
> struct device_node *node;
> struct extcon_dev *edev;
> - struct platform_device *extcon_parent_dev;
>
> if (!dev->of_node) {
> dev_dbg(dev, "device does not have a device node entry\n");
> @@ -46,16 +45,9 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct device
> *dev, int index)
> return ERR_PTR(-ENODEV);
> }
>
> - extcon_parent_dev = of_find_device_by_node(node);
> - if (!extcon_parent_dev) {
> - dev_dbg(dev, "unable to find device by node\n");
> - return ERR_PTR(-EPROBE_DEFER);
> - }
> -
> - edev = extcon_get_extcon_dev(dev_name(&extcon_parent_dev->dev));
> + edev = extcon_get_extcon_dev(node->name);
Since you no longer want to use device names I think you should add this too to
warn users if they rely on using the device name.
diff --git a/drivers/extcon/extcon-class.c b/drivers/extcon/extcon-class.c
index bc4c789..025eb39 100644
--- a/drivers/extcon/extcon-class.c
+++ b/drivers/extcon/extcon-class.c
@@ -601,7 +601,6 @@ int extcon_dev_register(struct extcon_dev *edev)
edev->dev.class = extcon_class;
edev->dev.release = extcon_dev_release;
- edev->name = edev->name ? edev->name : dev_name(edev->dev.parent);
//The user should always pass the 'name' as we no longer use device name while
getting extcon device. And this name should also be the 'node' name?
if (IS_ERR_OR_NULL(edev->name)) {
dev_err(&edev->dev,
"extcon device name is null\n");
Btw changing to node name from device name breaks dwc3 in OMAP5 and you would
need this too..
diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c
index 2aea4bc..cea8cd3 100644
--- a/drivers/extcon/extcon-palmas.c
+++ b/drivers/extcon/extcon-palmas.c
@@ -188,6 +188,7 @@ static int palmas_usb_probe(struct platform_device *pdev)
palmas_usb->edev.supported_cable = palmas_extcon_cable;
palmas_usb->edev.dev.parent = palmas_usb->dev;
+ palmas_usb->edev.name = "palmas_usb";
palmas_usb->edev.mutually_exclusive = mutually_exclusive;
status = extcon_dev_register(&palmas_usb->edev);
Cheers
Kishon
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Re: [PATCH 1/2] extcon: of: Remove unnecessary function call by using the name of device_node
Hi,
On Thursday 20 March 2014 07:52 AM, Chanwoo Choi wrote:
> Hi,
>
> On 03/19/2014 09:08 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Tuesday 18 March 2014 05:34 PM, Chanwoo Choi wrote:
>>> This patch remove unnecessary function call in of_extcon_get_extcon_dev()
>>> by using the name of device_node structure.
>>>
>>> Signed-off-by: Chanwoo Choi
>>> ---
>>> drivers/extcon/of_extcon.c | 12 ++--
>>> 1 file changed, 2 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/extcon/of_extcon.c b/drivers/extcon/of_extcon.c
>>> index 72173ec..0a29f82 100644
>>> --- a/drivers/extcon/of_extcon.c
>>> +++ b/drivers/extcon/of_extcon.c
>>> @@ -32,7 +32,6 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct device
>>> *dev, int index)
>>> {
>>> struct device_node *node;
>>> struct extcon_dev *edev;
>>> - struct platform_device *extcon_parent_dev;
>>>
>>> if (!dev->of_node) {
>>> dev_dbg(dev, "device does not have a device node entry\n");
>>> @@ -46,16 +45,9 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct
>>> device *dev, int index)
>>> return ERR_PTR(-ENODEV);
>>> }
>>>
>>> - extcon_parent_dev = of_find_device_by_node(node);
>>> - if (!extcon_parent_dev) {
>>> - dev_dbg(dev, "unable to find device by node\n");
>>> - return ERR_PTR(-EPROBE_DEFER);
>>> - }
>>> -
>>> - edev = extcon_get_extcon_dev(dev_name(&extcon_parent_dev->dev));
>>> + edev = extcon_get_extcon_dev(node->name);
>>
>> Since you no longer want to use device names I think you should add this too
>> to
>> warn users if they rely on using the device name.
>
> Previous of_extcon_get_extcon_dev() support only platform device using
> of_find_device_by_node.
>
> If extcon device is based on i2c/spi/pci and so on,
> of_extcon_get_extcon_dev() can't
> find device instance for device name. So, I change device name from the name
> of platform device
> to the name of dt node.
That's fine. But we have to fix extcon_dev_register() too, to not use device
names right? We have to warn extcon users not to use device names right?
>
>
>> diff --git a/drivers/extcon/extcon-class.c b/drivers/extcon/extcon-class.c
>> index bc4c789..025eb39 100644
>> --- a/drivers/extcon/extcon-class.c
>> +++ b/drivers/extcon/extcon-class.c
>> @@ -601,7 +601,6 @@ int extcon_dev_register(struct extcon_dev *edev)
>> edev->dev.class = extcon_class;
>> edev->dev.release = extcon_dev_release;
>>
>> - edev->name = edev->name ? edev->name : dev_name(edev->dev.parent);
>> //The user should always pass the 'name' as we no longer use device name
>> while
>> getting extcon device. And this name should also be the 'node' name?
>> if (IS_ERR_OR_NULL(edev->name)) {
>> dev_err(&edev->dev,
>> "extcon device name is null\n");
>>
>> Btw changing to node name from device name breaks dwc3 in OMAP5 and you would
>> need this too..
>>
>> diff --git a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c
>> index 2aea4bc..cea8cd3 100644
>> --- a/drivers/extcon/extcon-palmas.c
>> +++ b/drivers/extcon/extcon-palmas.c
>> @@ -188,6 +188,7 @@ static int palmas_usb_probe(struct platform_device *pdev)
>>
>> palmas_usb->edev.supported_cable = palmas_extcon_cable;
>> palmas_usb->edev.dev.parent = palmas_usb->dev;
>> + palmas_usb->edev.name = "palmas_usb";
>> palmas_usb->edev.mutually_exclusive = mutually_exclusive;
>>
>> status = extcon_dev_register(&palmas_usb->edev);
>>
>> Cheers
>> Kishon
>>
>
> If node name is same as extcon device name, don't need some modification.
> Also, you can modify node name in some OMAP dts file insead of modification
> of extcon-palmas.c
node name in OMAP dts is already 'palmas_usb'. But since we were not setting
'edev.name' in extcon-palmas.c, extcon_dev_register used device name of palmas
(palmas_usb.7 in my case). So extcon-palmas.c needs the fix.
Cheers
Kishon
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Re: [PATCH 1/2] extcon: of: Remove unnecessary function call by using the name of device_node
Hi,
On Thursday 20 March 2014 12:26 PM, Chanwoo Choi wrote:
> Hi,
>
> On 03/20/2014 02:20 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 20 March 2014 07:52 AM, Chanwoo Choi wrote:
>>> Hi,
>>>
>>> On 03/19/2014 09:08 PM, Kishon Vijay Abraham I wrote:
>>>> Hi,
>>>>
>>>> On Tuesday 18 March 2014 05:34 PM, Chanwoo Choi wrote:
>>>>> This patch remove unnecessary function call in of_extcon_get_extcon_dev()
>>>>> by using the name of device_node structure.
>>>>>
>>>>> Signed-off-by: Chanwoo Choi
>>>>> ---
>>>>> drivers/extcon/of_extcon.c | 12 ++--
>>>>> 1 file changed, 2 insertions(+), 10 deletions(-)
>>>>>
>>>>> diff --git a/drivers/extcon/of_extcon.c b/drivers/extcon/of_extcon.c
>>>>> index 72173ec..0a29f82 100644
>>>>> --- a/drivers/extcon/of_extcon.c
>>>>> +++ b/drivers/extcon/of_extcon.c
>>>>> @@ -32,7 +32,6 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct
>>>>> device *dev, int index)
>>>>> {
>>>>> struct device_node *node;
>>>>> struct extcon_dev *edev;
>>>>> - struct platform_device *extcon_parent_dev;
>>>>>
>>>>> if (!dev->of_node) {
>>>>> dev_dbg(dev, "device does not have a device node entry\n");
>>>>> @@ -46,16 +45,9 @@ struct extcon_dev *of_extcon_get_extcon_dev(struct
>>>>> device *dev, int index)
>>>>> return ERR_PTR(-ENODEV);
>>>>> }
>>>>>
>>>>> - extcon_parent_dev = of_find_device_by_node(node);
>>>>> - if (!extcon_parent_dev) {
>>>>> - dev_dbg(dev, "unable to find device by node\n");
>>>>> - return ERR_PTR(-EPROBE_DEFER);
>>>>> - }
>>>>> -
>>>>> - edev = extcon_get_extcon_dev(dev_name(&extcon_parent_dev->dev));
>>>>> + edev = extcon_get_extcon_dev(node->name);
>>>>
>>>> Since you no longer want to use device names I think you should add this
>>>> too to
>>>> warn users if they rely on using the device name.
>>>
>>> Previous of_extcon_get_extcon_dev() support only platform device using
>>> of_find_device_by_node.
>>>
>>> If extcon device is based on i2c/spi/pci and so on,
>>> of_extcon_get_extcon_dev() can't
>>> find device instance for device name. So, I change device name from the
>>> name of platform device
>>> to the name of dt node.
>>
>> That's fine. But we have to fix extcon_dev_register() too, to not use device
>> names right? We have to warn extcon users not to use device names right?
>
> I don't think so. extcon_get_edev_by_phandle() shows wrong node->name as
> following:
The wrong node->name was given by the extcon provider but the error is being
reported in the consumer.
> The consumer could detect the cause of problem which can't get extcon device
> after
> checking error log message.
>
> edev = extcon_get_extcon_dev(node->name);
> if (!edev) {
> dev_err(dev, "unable to get extcon device : %s\n", node->name);
> return ERR_PTR(-ENODEV);
> }
>
> I don't want to add more log message.
I'm not sure if that log message is helpful in anyway to identify the problem
was because of the wrong node->name.
>
>>>
>>>
>>>> diff --git a/drivers/extcon/extcon-class.c b/drivers/extcon/extcon-class.c
>>>> index bc4c789..025eb39 100644
>>>> --- a/drivers/extcon/extcon-class.c
>>>> +++ b/drivers/extcon/extcon-class.c
>>>> @@ -601,7 +601,6 @@ int extcon_dev_register(struct extcon_dev *edev)
>>>> edev->dev.class = extcon_class;
>>>> edev->dev.release = extcon_dev_release;
>>>>
>>>> - edev->name = edev->name ? edev->name : dev_name(edev->dev.parent);
>>>> //The user should always pass the 'name' as we no longer use device name
>>>> while
>>>> getting extcon device. And this name should also be the 'node' name?
>>>> if (IS_ERR_OR_NULL(edev->name)) {
>>>> dev_err(&edev->dev,
>>>> "extcon device name is null\n");
>>>>
>>>> Btw changing to node name from device
[RFC PATCH 01/12] phy: phy-omap-pipe3: Add support for PCIe PHY
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c | 99 +-
2 files changed, 84 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 788fb0f..e628a23 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -49,8 +49,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".
- "ti,omap-usb3" is deprecated.
+ - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
+ "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in "reg".
@@ -62,6 +62,10 @@ Required properties:
* "wkupclk" - wakeup clock.
* "sysclk" - system clock.
* "refclk" - reference clock.
+ * "dpll_ref" - external dpll ref clk
+ * "dpll_ref_m2" - external dpll ref clk
+ * "phy-div" - divider for apll
+ * "div-clk" - apll clock
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 5913676..d43019d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -80,6 +80,7 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
};
@@ -215,6 +216,9 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+ return 0;
+
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
if (val & PLL_IDLE) {
@@ -238,8 +242,11 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
- /* SATA DPLL can't be powered down due to Errata i783 */
- if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
+ /* SATA DPLL can't be powered down due to Errata i783 and PCIe
+* does not have internal DPLL
+*/
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
+ of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
return 0;
/* Put DPLL in IDLE mode */
@@ -286,32 +293,41 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *control_node;
struct platform_device *control_pdev;
const struct of_device_id *match;
-
- match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
- if (!match)
- return -EINVAL;
+ struct clk *clk;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
return -ENOMEM;
}
+ phy->dev= &pdev->dev;
- phy->dpll_map = (struct pipe3_dpll_map *)match->data;
- if (!phy->dpll_map) {
- dev_err(&pdev->dev, "no DPLL data\n");
- return -EINVAL;
- }
+ if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table),
+ &pdev->dev);
+ if (!match)
+ return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
- phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(phy->pll_ctrl_base))
- return PTR_ERR(phy->pll_ctrl_base);
+ phy->dpll_map = (struct pipe3_dpll_map *)match->data;
+ if (!phy->dpll_map) {
+ dev_err(&pdev->dev, "no DPLL data\n");
+ return -EINVAL;
+ }
- phy->dev= &pdev->dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pll_ctrl");
+ phy->pll_ctrl_base = devm_ior
[RFC PATCH 12/12] ARM: OMAP: Enable PCI for DRA7
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 46f8c53..352f252 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -86,6 +86,8 @@ config SOC_DRA7XX select HAVE_SMP select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI + select ARCH_SUPPORTS_MSI config ARCH_OMAP2PLUS bool -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 11/12] ARM: dts: dra7: Add dt data for PCIe controller
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 7ac372b..10def39 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -701,6 +701,30 @@
};
};
+ pcie@5100 {
+ compatible = "ti,dra7xx-pcie";
+ reg = <0x51002000 0x14c>, <0x5100 0x2000>,
<0x4A002540 0x1f>;
+ reg-names = "ti_conf", "rc_dbics", "mmr_unlock";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ti,device_type = <3>;
+ ranges = <0x0800 0 0x20001000 0x20001000 0
0x2000
+ 0x8100 0 0 0x20003000 0
0x0001
+ 0x8200 0 0x20013000 0x20013000 0
0xffed000>;
+ #interrupt-cells = <1>;
+ base-mask = <0x 0x0fff>;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 233>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+ resets = <&prm_resets &device_reset>;
+ reset-names = "reset";
+ };
+
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a14 0x1100>, <0x4a141100 0x7>;
--
1.7.9.5
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[RFC PATCH 10/12] ARM: dts: dra7: Add dt data for PCIe PHY
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 73c61d0..7ac372b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -683,6 +683,22 @@
clock-names = "sysclk";
#phy-cells = <0>;
};
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+<&dpll_pcie_ref_m2ldo_ck>,
+<&optfclk_pciephy_32khz>,
+<&optfclk_pciephy_clk>,
+<&optfclk_pciephy_div_clk>,
+<&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ ti,hwmods = "pcie1-phy";
+ };
};
sata: sata@4a141100 {
--
1.7.9.5
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[RFC PATCH 09/12] ARM: dts: dra7: Add dt data for PCIe PHY control module
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f3565ac..73c61d0 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -656,6 +656,14 @@
clock-names = "sysclk";
};
+ omap_control_pcie1phy: omap-control-pciephy@0x4a003c40 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a003c40 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = "ti,omap-ocp2scp";
--
1.7.9.5
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[RFC PATCH 02/12] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile|1 +
drivers/pci/host/pcie-dra7xx.c | 411 ++
4 files changed, 457 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
create mode 100644 drivers/pci/host/pcie-dra7xx.c
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
new file mode 100644
index 000..0528c47
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -0,0 +1,35 @@
+TI PCI Controllers
+
+PCIe Designware Controller
+This node should have the properties described in "designware-pcie.txt".
+ - compatible: Should be "ti,dra7xx-pcie""
+ - reg : Address and length of the register set for the device.
+ - phys : the phandle for the PHY device (used by generic PHY framework)
+ - phy-names : the names of the PHY corresponding to the PHYs present in the
+ *phy* phandle.
+ - resets: phandle used if reset is handled be soc
+ - reset-names: name given to the phandle
+ - ti,device-type: Should be 1 - EP TYPE, 2 - LEG EP TYPE OR 3 - RC TYPE
+
+Example:
+pcie@5100 {
+ compatible = "ti,dra7xx-pcie";
+ reg = <0x51002000 0x14c>, <0x5100 0x2000>, <0x4A002540 0x1f>,
<0x4A003c24 0x4>, <0x4AE07310 0x4>;
+ interrupts = <0 129 0x4>, <0 134 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ti,device_type = <3>;
+ ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /*
Configuration Space */
+ 0x8100 0 0 0x20003000 0 0x0001 /* IO Space
*/
+ 0x8200 0 0x20013000 0x20013000 0 0xffed000>; /* MEM Space
*/
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 134>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+ resets = <&prm_resets &device_reset>;
+ reset-names = "reset";
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..5066a3c 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -1,6 +1,16 @@
menu "PCI host controller drivers"
depends on PCI
+config PCIE_DRA7XX
+ bool "TI DRA7xx PCIe controller"
+ select PCIE_DW
+ depends on OF || HAS_IOMEM || TI_PIPE3
+ help
+Enables support for the PCIE controller present in DRA7xx SoC. There
+are two instances of PCIE controller in DRA7xx. This controller can
+act both as EP and RC. This reuses the same Designware core as used
+by other SoCs.
+
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..90a275d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCIE_DRA7XX) += pcie-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pcie-dra7xx.c b/drivers/pci/host/pcie-dra7xx.c
new file mode 100644
index 000..69f3720
--- /dev/null
+++ b/drivers/pci/host/pcie-dra7xx.c
@@ -0,0 +1,411 @@
+/*
+ * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
+ *
+ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Authors: Kishon Vijay Abraham I
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+/* PCIe controller wrapper TI configuration registers */
+
+#definePCIECTRL_TI_CONF_IRQSTATUS_MAIN 0x0024
+#definePCIECTRL_TI_CONF_IRQENABLE_SET_MAIN 0x0028
+#defineERR_SYS BIT(0)
+#defineERR_FATAL BIT(1)
+#defineERR_NONFATALBIT(2)
+#defineERR_COR BIT(3)
+#defineERR_AXI BIT(4)
+#defineERR_ECRC
[RFC PATCH 05/12] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
From: Keerthy
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d909484..9e0bb09 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
- clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
--
1.7.9.5
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[RFC PATCH 07/12] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 9397265..c789b00 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2459,6 +2496,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2824,6 +2877,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
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[RFC PATCH 08/12] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 9e0bb09..5f13189 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
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[RFC PATCH 06/12] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch/arm/mach-omap2/prm7xx.h |4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index befe7ce..9397265 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = "pcie1-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = "pcie2-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2420,6 +2459,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b30,
@@ -2769,6 +2824,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET
[RFC PATCH 03/12] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for programming
the outbound translation window the *base* should be programmed as 0x000_.
Whenever we try to write to say 0x2000_, it will be translated to whatever
we have programmed in the translation window with base as 0x000_.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 39 ++--
drivers/pci/host/pcie-designware.h |1 +
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..c574dd3 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -27,6 +27,7 @@ Optional properties for fsl,imx6q-pcie
- power-on-gpio: gpio pin number of power-enable signal
- wake-up-gpio: gpio pin number of incoming wakeup signal
- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
+- base-mask: address mask for the PCIe controller target port
Example:
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 17ce88f..98b661c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -464,6 +464,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
return -EINVAL;
}
+ if (of_property_read_u64(np, "base-mask", &pp->base_mask))
+ pp->base_mask = ~(0x0ULL);
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
MAX_MSI_IRQS, &msi_domain_ops,
@@ -503,12 +506,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg0_base;
+
+ cfg0_base = pp->cfg0_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : CFG0 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
+ dw_pcie_writel_rc(pp, cfg0_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg0_base + pp->config.cfg0_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -518,14 +524,17 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port
*pp, u32 busdev)
static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg1_base;
+
+ cfg1_base = pp->cfg1_base & pp->base_mask;
/* Program viewport 1 : OUTBOUND : CFG1 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
- dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
+ dw_pcie_writel_rc(pp, cfg1_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg1_base + pp->config.cfg1_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -533,14 +542,17 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port
*pp, u32 busdev)
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
{
+ u64 mem_base;
+
+ mem_base = pp->mem_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : MEM */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
-
[RFC PATCH 00/12] PCIe support for DRA7xx
This patch series adds support for PCIe in DRA7xx including drivers and dt data. PCIe in DRA7xx uses desingware IP and hence this re-uses the pcie desingware driver (pcie-designware.c) by Jingoo. This patch series depends on a few patches that is already in -next. Tested broadcom PCIe card and XIO2000 bridge along with DGE530T ethernet card. Keerthy (2): ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I (10): phy: phy-omap-pipe3: Add support for PCIe PHY pci: host: pcie-dra7xx: add support for pcie-dra7xx controller pci: host: pcie-designware: Use *base-mask* for configuring the iATU arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY ARM: dts: dra7: Add dt data for PCIe PHY control module ARM: dts: dra7: Add dt data for PCIe PHY ARM: dts: dra7: Add dt data for PCIe controller ARM: OMAP: Enable PCI for DRA7 .../devicetree/bindings/pci/designware-pcie.txt|1 + Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++ Documentation/devicetree/bindings/phy/ti-phy.txt |8 +- arch/arm/boot/dts/dra7.dtsi| 48 +++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 11 +- arch/arm/mach-omap2/Kconfig|2 + arch/arm/mach-omap2/cm2_7xx.h |4 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 ++ arch/arm/mach-omap2/prm7xx.h |4 + drivers/pci/host/Kconfig | 10 + drivers/pci/host/Makefile |1 + drivers/pci/host/pcie-designware.c | 39 +- drivers/pci/host/pcie-designware.h |1 + drivers/pci/host/pcie-dra7xx.c | 411 drivers/phy/phy-ti-pipe3.c | 99 - 15 files changed, 750 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt create mode 100644 drivers/pci/host/pcie-dra7xx.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 04/12] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock
From: Keerthy Add divider table to optfclk_pciephy_div clock. Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index e96da9a..d909484 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 02/12] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
On Wednesday 26 March 2014 08:15 PM, Rob Herring wrote:
> On Wed, Mar 26, 2014 at 8:57 AM, Kishon Vijay Abraham I wrote:
>> Added support for pcie controller in dra7xx. This driver re-uses
>> the designware core code that is already present in kernel.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++
>> drivers/pci/host/Kconfig | 10 +
>> drivers/pci/host/Makefile|1 +
>> drivers/pci/host/pcie-dra7xx.c | 411
>> ++
>> 4 files changed, 457 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
>> create mode 100644 drivers/pci/host/pcie-dra7xx.c
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> new file mode 100644
>> index 000..0528c47
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -0,0 +1,35 @@
>> +TI PCI Controllers
>> +
>> +PCIe Designware Controller
>> +This node should have the properties described in "designware-pcie.txt".
>> + - compatible: Should be "ti,dra7xx-pcie""
>> + - reg : Address and length of the register set for the device.
>> + - phys : the phandle for the PHY device (used by generic PHY framework)
>> + - phy-names : the names of the PHY corresponding to the PHYs present in the
>> + *phy* phandle.
>> + - resets: phandle used if reset is handled be soc
>
> s/be/by/ ?
>
>> + - reset-names: name given to the phandle
>> + - ti,device-type: Should be 1 - EP TYPE, 2 - LEG EP TYPE OR 3 - RC TYPE
>
> I don't think this makes sense. I'd imagine we'd need the binding to
> look quite a bit different if endpoint mode was actually supported. I
right, it makes sense to remove the ti,device-type altogether as this driver
only supports RC.
> think I would start defining endpoint mode with a different compatible
> string and go from there.
>
>> +
>> +Example:
>> +pcie@5100 {
>> + compatible = "ti,dra7xx-pcie";
>> + reg = <0x51002000 0x14c>, <0x5100 0x2000>, <0x4A002540 0x1f>,
>> <0x4A003c24 0x4>, <0x4AE07310 0x4>;
>
> This is different number of entries from your actual dts. You need to
> define how many reg entries, what they are, and the order.
Ok. Will fix it.
Thanks
Kishon
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Re: [RFC PATCH 02/12] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
On Thursday 27 March 2014 09:13 AM, Jingoo Han wrote:
> On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
>>
>> Added support for pcie controller in dra7xx. This driver re-uses
>> the designware core code that is already present in kernel.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>
> Hi Kishon,
> Long time no see! I added trivial comments.
yeah, these were in my TODO for a long time. Sorry for it though.
>
>> ---
>> Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++
>> drivers/pci/host/Kconfig | 10 +
>> drivers/pci/host/Makefile|1 +
>> drivers/pci/host/pcie-dra7xx.c | 411
>> ++
>
> How about using 'pci-' prefix?
> As it was discussed earlier, 'pci-' prefix is more proper.
>
>> 4 files changed, 457 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
>> create mode 100644 drivers/pci/host/pcie-dra7xx.c
>
> [.]
>
>> --- /dev/null
>> +++ b/drivers/pci/host/pcie-dra7xx.c
>
> [.]
>
>> +#define PCIECTRL_TI_CONF_IRQSTATUS_MAIN 0x0024
>> +#define PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN 0x0028
>
> I don't think that it's good to add vendor names such as TI
> to SFR names.
>
> How about adding 'DRA7XX' or just removing 'TI'?
>
> 1. PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
ok.
>
> 2. PCIECTRL_CONF_IRQSTATUS_MAIN
>
> [.]
>
>> +enum dra7xx_pcie_device_type {
>> +DRA7XX_PCIE_UNKNOWN_TYPE,
>> +DRA7XX_PCIE_EP_TYPE,
>> +DRA7XX_PCIE_LEG_EP_TYPE,
>> +DRA7XX_PCIE_RC_TYPE,
>> +};
>
> This driver can support only RC mode, so, these enum can be removed.
>
> [.]
>
>> +of_property_read_u32(node, "ti,device-type", &device_type);
>> +switch (device_type) {
>> +case DRA7XX_PCIE_RC_TYPE:
>> +dra7xx_pcie_writel(dra7xx->base,
>> +PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_RC);
>> +break;
>> +case DRA7XX_PCIE_EP_TYPE:
>> +dra7xx_pcie_writel(dra7xx->base,
>> +PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP);
>> +break;
>> +case DRA7XX_PCIE_LEG_EP_TYPE:
>> +dra7xx_pcie_writel(dra7xx->base,
>> +PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_LEG_EP);
>> +break;
>> +default:
>> +dev_dbg(dev, "UNKNOWN device type %d\n", device_type);
>> +}
>
> Thus, this switch can be removed.
sure.
Thanks
Kishon
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Re: [PATCH v3 0/7] USB support for DRA7-evm
On Tuesday 06 May 2014 12:49 PM, Roger Quadros wrote: > Hi Kishon, > > Could you please pick the first 2 patches in this series for phy-next? > They are independent of the rest. Thanks. sure.. will be queuing it shortly. Thanks Kishon > > cheers, > -roger > > On 05/05/2014 12:54 PM, Roger Quadros wrote: >> Hi, >> >> This series enables the 2 USB ports on the DRA7-evm. >> >> NOTE: USB1 port is hard coded to work in peripheral mode and USB2 port >> in host mode. This is due to missing ID pin interrupt in pre ver.E boards. >> >> USB1 port doesn't in peripheral mode out of the box due to missing VBUS >> detection >> and mailbox write. To test this I had to do a manual write to enable >> VBUSVALID >> in the USB_UTMI_OTG_STATUS register. >> omapconf set bit 0x48880084 1 >> >> USB2 port works well in host mode. >> >> Patches are based on 3.15-rc3. >> >> cheers, >> -roger >> >> Changelog: >> >> v3: >> -Rearraged patches. PHY related stuff first. >> -Addressed backward compatibility issue for phy-omap-usb2. >> >> v2: >> -Rebased on v3.15-rc3 >> >> --- >> Roger Quadros (7): >> phy: omap-usb2: Use generic clock names "wkupclk" and "refclk" >> phy: omap-usb2: Add clock names to Documentation binding >> ARM: dts: omap4+: Add clocks to USB2 PHY node >> ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate >> ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss >> ARM: dts: dra7: Add USB related nodes >> dts: dra7-evm: add USB support >> >> Documentation/devicetree/bindings/phy/ti-phy.txt | 7 ++ >> arch/arm/boot/dts/dra7-evm.dts | 24 >> arch/arm/boot/dts/dra7.dtsi | 149 >> +++ >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 +- >> arch/arm/boot/dts/omap4.dtsi | 2 + >> arch/arm/boot/dts/omap5.dtsi | 2 + >> arch/arm/mach-omap2/omap_hwmod_7xx_data.c| 22 ++-- >> drivers/phy/phy-omap-usb2.c | 30 +++-- >> 8 files changed, 229 insertions(+), 19 deletions(-) >> > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock
From: Keerthy Add divider table to optfclk_pciephy_div clock. The Documentation for divider clock can be found at ../clock/ti/divider.txt Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c767687..55e95c5 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 15/17] ARM: OMAP: Enable PCI for DRA7
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Cc: Tony Lindgren Cc: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d43..b179e80 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,6 +75,8 @@ config SOC_DRA7XX select ARM_GIC select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI + select ARCH_SUPPORTS_MSI config ARCH_OMAP2PLUS bool -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node
Added *resets* and *reset-names* properies for PCIe dt node.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Dan Murphy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 20b1a09..7bc0555 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1031,6 +1031,8 @@
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy";
+ resets = <&prm_resets &device_reset>;
+ reset-names = "reset";
};
sata: sata@4a141100 {
--
1.7.9.5
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[PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Cc: Tony Lindgren
Cc: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 0d3c8c0..653b5f6 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -903,6 +903,29 @@
clock-names = "sysclk";
#phy-cells = <0>;
};
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4A094000 0x80>, /* phy_rx */
+ <0x4A094400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+<&dpll_pcie_ref_m2ldo_ck>,
+<&optfclk_pciephy_32khz>,
+<&optfclk_pciephy_clk>,
+<&optfclk_pciephy_div_clk>,
+<&optfclk_pciephy_div>,
+<&apll_pcie_in_clk_mux>,
+<&pciesref_acs_clk_ck>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div",
+ "apll_mux", "refclk_ext";
+ #phy-cells = <0>;
+ ti,hwmods = "pcie1-phy";
+ ti,ext-clk;
+ };
};
omap_dwc3_1@4888 {
--
1.7.9.5
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[TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt |2 ++
drivers/pci/host/pci-dra7xx.c| 10 ++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 6cb6f09..cfb95c0 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -9,6 +9,8 @@ This node should have the properties described in
"designware-pcie.txt".
- phys : the phandle for the PHY device (used by generic PHY framework)
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
+ - resets: phandle used if reset is handled be soc
+ - reset-names: name given to the phandle
Example:
pcie@5100 {
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index a37c25c..17d64ee 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include "pcie-designware.h"
@@ -281,6 +282,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
struct resource *res;
struct dra7xx_pcie *dra7xx;
struct device *dev = &pdev->dev;
+ struct reset_control *rstc;
dra7xx = devm_kzalloc(&pdev->dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -304,6 +306,14 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
if (!base)
return -ENOMEM;
+ rstc = devm_reset_control_get(dev, "reset");
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ return ret;
+
phy = devm_phy_get(dev, "pcie-phy");
if (IS_ERR(phy))
return PTR_ERR(phy);
--
1.7.9.5
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[PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren
Cc: Bjorn Helgaas
Cc: Jingoo Han
Cc: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 653b5f6..20b1a09 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1011,6 +1011,28 @@
};
};
+ pcie@5100 {
+ compatible = "ti,dra7xx-pcie";
+ reg = <0x51002000 0x14c>, <0x5100 0x2000>;
+ reg-names = "ti_conf", "rc_dbics";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ti,device_type = <3>;
+ ranges = <0x0800 0 0x20001000 0x20001000 0
0x2000
+ 0x8100 0 0 0x20003000 0
0x0001
+ 0x8200 0 0x20013000 0x20013000 0
0xffed000>;
+ #interrupt-cells = <1>;
+ base-mask = <0x 0x0fff>;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 233>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+ };
+
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a14 0x1100>, <0x4a141100 0x7>;
--
1.7.9.5
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[PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 44993ec..e1bd052 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
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[PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren
Cc: Russell King
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 1282a42..a51fa7f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2388,6 +2425,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2751,6 +2804,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
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[PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren
Cc: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f0ca46d..0d3c8c0 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -876,6 +876,14 @@
};
};
+ omap_control_pcie1phy: omap-control-pciephy@0x4a003c40 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34
0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = "ti,omap-ocp2scp";
--
1.7.9.5
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[PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren
Cc: Russell King
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch/arm/mach-omap2/prm7xx.h |4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b9bb476..1282a42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = "pcie1-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = "pcie2-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b30,
@@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_
[PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Bjorn Helgaas
Cc: Mohit Kumar
Cc: Jingoo Han
Cc: Marek Vasut
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 33 ++
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile|1 +
drivers/pci/host/pci-dra7xx.c| 385 ++
4 files changed, 429 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
create mode 100644 drivers/pci/host/pci-dra7xx.c
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
new file mode 100644
index 000..6cb6f09
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -0,0 +1,33 @@
+TI PCI Controllers
+
+PCIe Designware Controller
+This node should have the properties described in "designware-pcie.txt".
+ - compatible: Should be "ti,dra7xx-pcie""
+ - reg : Address and length of the register set for the device.
+ - reg-names : "ti_conf" for the TI specific registers and rc_dbics for the
+ "designware" registers.
+ - phys : the phandle for the PHY device (used by generic PHY framework)
+ - phy-names : the names of the PHY corresponding to the PHYs present in the
+ *phy* phandle.
+
+Example:
+pcie@5100 {
+ compatible = "ti,dra7xx-pcie";
+ reg = <0x51002000 0x14c>, <0x5100 0x2000>;
+ reg-names = "ti_conf", "rc_dbics";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ti,device_type = <3>;
+ ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /*
Configuration Space */
+ 0x8100 0 0 0x20003000 0 0x0001 /* IO Space
*/
+ 0x8200 0 0x20013000 0x20013000 0 0xffed000>; /* MEM Space
*/
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 134>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy";
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..7be6393 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -1,6 +1,16 @@
menu "PCI host controller drivers"
depends on PCI
+config PCI_DRA7XX
+ bool "TI DRA7xx PCIe controller"
+ select PCIE_DW
+ depends on OF || HAS_IOMEM || TI_PIPE3
+ help
+Enables support for the PCIE controller present in DRA7xx SoC. There
+are two instances of PCIE controller in DRA7xx. This controller can
+act both as EP and RC. This reuses the same Designware core as used
+by other SoCs.
+
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..5216f55 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
new file mode 100644
index 000..a37c25c
--- /dev/null
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -0,0 +1,385 @@
+/*
+ * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
+ *
+ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Authors: Kishon Vijay Abraham I
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+/* PCIe controller wrapper DRA7XX configuration registers */
+
+#definePCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
+#definePCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
+#defineERR_SYS BIT(0)
+#defineERR_FATAL BIT(1)
+#defineERR_NONFATALBIT(2)
+#defineERR_COR BIT(3)
+#defineERR_AXI BIT(4)
+#defineERR_ECRCBIT(5)
+#define
[PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
From: Keerthy
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 55e95c5..44993ec 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
- clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
--
1.7.9.5
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[PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
APLL used by PCIE phy can either use external clock as input or the clock
from DPLL. Added support for the APLL to use external clock as input here.
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++
drivers/phy/phy-ti-pipe3.c | 75 ++
2 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index bc9afb5..d50f8ee 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -76,6 +76,10 @@ Required properties:
* "dpll_ref_m2" - external dpll ref clk
* "phy-div" - divider for apll
* "div-clk" - apll clock
+ * "apll_mux" - mux for pcie apll
+ * "refclk_ext" - external reference clock for pcie apll
+ - ti,ext-clk: To specifiy if PCIE apll should use external clock. Applicable
+ only to PCIE PHY.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index d43019d..5513aa0 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -293,7 +293,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *control_node;
struct platform_device *control_pdev;
const struct of_device_id *match;
- struct clk *clk;
+ struct clk *clk, *pclk;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
@@ -302,6 +302,20 @@ static int ti_pipe3_probe(struct platform_device *pdev)
}
phy->dev= &pdev->dev;
+ control_node = of_parse_phandle(node, "ctrl-module", 0);
+ if (!control_node) {
+ dev_err(&pdev->dev, "Failed to get control device phandle\n");
+ return -EINVAL;
+ }
+
+ control_pdev = of_find_device_by_node(control_node);
+ if (!control_pdev) {
+ dev_err(&pdev->dev, "Failed to get control device\n");
+ return -EINVAL;
+ }
+
+ phy->control_dev = &control_pdev->dev;
+
if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
match = of_match_device(of_match_ptr(ti_pipe3_id_table),
&pdev->dev);
@@ -345,19 +359,40 @@ static int ti_pipe3_probe(struct platform_device *pdev)
}
if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
- clk = devm_clk_get(phy->dev, "dpll_ref");
- if (IS_ERR(clk)) {
- dev_err(&pdev->dev, "unable to get dpll ref clk\n");
- return PTR_ERR(clk);
+ if (!of_property_read_bool(node, "ti,ext-clk")) {
+ clk = devm_clk_get(phy->dev, "dpll_ref");
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev,
+ "unable to get dpll ref clk\n");
+ return PTR_ERR(clk);
+ }
+ clk_set_rate(clk, 15);
+
+ clk = devm_clk_get(phy->dev, "dpll_ref_m2");
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev,
+ "unable to get dpll ref m2 clk\n");
+ return PTR_ERR(clk);
+ }
+ clk_set_rate(clk, 1);
+ } else {
+ omap_control_pcie_tx_rx_control(phy->control_dev,
+ OMAP_CTRL_PCIE_PHY_RX_ACSPCIE);
+
+ clk = clk_get(phy->dev, "apll_mux");
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "unable to get apll mux
clk\n");
+ return PTR_ERR(clk);
+ }
+
+ pclk = clk_get(phy->dev, "refclk_ext");
+ if (IS_ERR(pclk)) {
+ dev_err(&pdev->dev, "unable to get ext ref clk
for apll\n");
+ return PTR_ERR(pclk);
+ }
+
+ clk_set_parent(clk, pclk);
}
- clk_set_rate(clk, 15);
-
- clk = devm_clk_get(phy->dev, "dpll_ref_m2");
- if (IS_ERR(clk)) {
- dev_err(&pdev->dev, "unable to get dpll ref m2
[PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/phy/ti-phy.txt |4 +--
drivers/phy/phy-omap-control.c | 41 ++
drivers/phy/phy-ti-pipe3.c |4 ++-
include/linux/phy/omap_control_phy.h |9 +
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d50f8ee..5653dc4 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -18,9 +18,9 @@ Required properties:
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of "otghs_control" for control-phy-otghs or "power" register
- for other types and "control_sma" for control-phy-pcie
+ for other types and "control_sma", "pcie_pcs" for control-phy-pcie
- reg-names: should be "otghs_control" for control-phy-otghs,
- "control_sma" for control-phy-pcie and "power" for other types.
+ "control_sma", "pcie_pcs" for control-phy-pcie and "power" for other types.
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,control-phy-otghs";
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 47a1b6c..6ba551b 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -61,6 +61,41 @@ void omap_control_pcie_tx_rx_control(struct device *dev, u8
ctrl)
EXPORT_SYMBOL_GPL(omap_control_pcie_tx_rx_control);
/**
+ * omap_control_pcie_pcs - set the PCS delay count
+ * @dev: the control module device
+ * @id: index of the pcie PHY (should be 1 or 2)
+ * @delay: 8 bit delay value
+ */
+void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
+{
+ u32 val;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err("%s: invalid device\n", __func__);
+ return;
+ }
+
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, "%s: invalid control phy device\n", __func__);
+ return;
+ }
+
+ if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
+ dev_err(dev, "%s: unsupported operation\n", __func__);
+ return;
+ }
+
+ val = readl(control_phy->pcie_pcs);
+ val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
+ (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
+ val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
+ writel(val, control_phy->pcie_pcs);
+}
+EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
+
+/**
* omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
@@ -335,6 +370,12 @@ static int omap_control_phy_probe(struct platform_device
*pdev)
control_phy->ctrl_sma = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(control_phy->ctrl_sma))
return PTR_ERR(control_phy->ctrl_sma);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pcie_pcs");
+ control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(control_phy->pcie_pcs))
+ return PTR_ERR(control_phy->pcie_pcs);
}
dev_set_drvdata(control_phy->dev, control_phy);
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 5513aa0..a1a0e35 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -216,8 +216,10 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
- if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
+ omap_control_pcie_pcs(phy->control_dev, 0x1, 0xF1);
return 0;
+ }
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
diff --git a/include/linux/phy/omap_control_phy.h
b/include/linux/phy/omap_control_phy.h
index 15cfbfe..6127c04 100644
--- a/include/linux/phy/omap_control_phy.h
+++ b/include/linux/phy/omap_control_phy.h
@@ -35,6 +35,7 @@ struct omap_control_phy {
u32 __iomem *power;
u32 __iomem *power_aux;
u32 __i
[PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c | 99 +-
2 files changed, 84 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 9ce458f..cf3de7e 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -56,8 +56,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".
- "ti,omap-usb3" is deprecated.
+ - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
+ "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in "reg".
@@ -69,6 +69,10 @@ Required properties:
* "wkupclk" - wakeup clock.
* "sysclk" - system clock.
* "refclk" - reference clock.
+ * "dpll_ref" - external dpll ref clk
+ * "dpll_ref_m2" - external dpll ref clk
+ * "phy-div" - divider for apll
+ * "div-clk" - apll clock
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 5913676..d43019d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -80,6 +80,7 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
};
@@ -215,6 +216,9 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+ return 0;
+
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
if (val & PLL_IDLE) {
@@ -238,8 +242,11 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
- /* SATA DPLL can't be powered down due to Errata i783 */
- if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
+ /* SATA DPLL can't be powered down due to Errata i783 and PCIe
+* does not have internal DPLL
+*/
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
+ of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
return 0;
/* Put DPLL in IDLE mode */
@@ -286,32 +293,41 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *control_node;
struct platform_device *control_pdev;
const struct of_device_id *match;
-
- match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
- if (!match)
- return -EINVAL;
+ struct clk *clk;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
return -ENOMEM;
}
+ phy->dev= &pdev->dev;
- phy->dpll_map = (struct pipe3_dpll_map *)match->data;
- if (!phy->dpll_map) {
- dev_err(&pdev->dev, "no DPLL data\n");
- return -EINVAL;
- }
+ if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table),
+ &pdev->dev);
+ if (!match)
+ return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
- phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(phy->pll_ctrl_base))
- return PTR_ERR(phy->pll_ctrl_base);
+ phy->dpll_map = (struct pipe3_dpll_map *)match->data;
+ if (!phy->dpll_map) {
+ dev_err(&pdev->dev, "no DPLL data\n");
+ return -EINVAL;
+ }
- phy->dev= &pdev->dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pll_ctrl");
+ phy->pll_ctrl_base = devm_ior
[PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for programming
the outbound translation window the *base* should be programmed as 0x000_.
Whenever we try to write to say 0x2000_, it will be translated to whatever
we have programmed in the translation window with base as 0x000_.
Cc: Bjorn Helgaas
Cc: Marek Vasut
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Jingoo Han
Acked-by: Mohit Kumar
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 39 ++--
drivers/pci/host/pcie-designware.h |1 +
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..c574dd3 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -27,6 +27,7 @@ Optional properties for fsl,imx6q-pcie
- power-on-gpio: gpio pin number of power-enable signal
- wake-up-gpio: gpio pin number of incoming wakeup signal
- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
+- base-mask: address mask for the PCIe controller target port
Example:
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c4e3732..243f148 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -463,6 +463,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
return -EINVAL;
}
+ if (of_property_read_u64(np, "base-mask", &pp->base_mask))
+ pp->base_mask = ~0x0ULL;
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
MAX_MSI_IRQS, &msi_domain_ops,
@@ -502,12 +505,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg0_base;
+
+ cfg0_base = pp->cfg0_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : CFG0 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
+ dw_pcie_writel_rc(pp, cfg0_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg0_base + pp->config.cfg0_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -517,13 +523,16 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port
*pp, u32 busdev)
static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
{
+ u64 cfg1_base;
+
+ cfg1_base = pp->cfg1_base & pp->base_mask;
/* Program viewport 1 : OUTBOUND : CFG1 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
+ dw_pcie_writel_rc(pp, cfg1_base, PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, (cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, cfg1_base + pp->config.cfg1_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
@@ -532,13 +541,16 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port
*pp, u32 busdev)
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
{
+ u64 mem_base;
+
+ mem_base = pp->mem_base & pp->base_mask;
/* Program viewport 0 : OUTBOUND : MEM */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), P
[PATCH 02/17] phy: omap-control: add external clock support for PCIe PHY
Export an API to be called by PIPE3 PHY to enable external clock for
PCIE PHY. Added a new compatible for PCIE in omap-control in order to
enable it.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/phy/ti-phy.txt |9 ++--
drivers/phy/phy-omap-control.c | 51 +-
include/linux/phy/omap_control_phy.h | 14 ++
3 files changed, 70 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cf3de7e..bc9afb5 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,15 +9,18 @@ Required properties:
e.g. USB2_PHY on OMAP5.
"ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
+ "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
+ set PCS delay value.
+ e.g. PCIE PHY in DRA7x
"ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
DRA7 platform.
"ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of "otghs_control" for control-phy-otghs or "power" register
- for other types.
- - reg-names: should be "otghs_control" control-phy-otghs and "power" for
- other types.
+ for other types and "control_sma" for control-phy-pcie
+ - reg-names: should be "otghs_control" for control-phy-otghs,
+ "control_sma" for control-phy-pcie and "power" for other types.
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,control-phy-otghs";
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 311b4f9..47a1b6c 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -27,6 +27,40 @@
#include
/**
+ * omap_control_pcie_tx_rx_control - PCIe RX and TX control of ACSPCIe
+ * @dev: the control module device
+ * @ctrl: 1, 2 or 3 based on controlling either RX or TX or both of ACSPCIe
+ */
+void omap_control_pcie_tx_rx_control(struct device *dev, u8 ctrl)
+{
+ u32 val;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err("%s: invalid device\n", __func__);
+ return;
+ }
+
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, "%s: invalid control phy device\n", __func__);
+ return;
+ }
+
+ if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
+ dev_err(dev, "%s: unsupported operation\n", __func__);
+ return;
+ }
+
+ val = readl(control_phy->ctrl_sma);
+ val &= ~(OMAP_CTRL_PCIE_TX_RX_CONTROL_MASK <<
+ OMAP_CTRL_PCIE_TX_RX_CONTROL_SHIFT);
+ val |= ctrl << OMAP_CTRL_PCIE_TX_RX_CONTROL_SHIFT;
+ writel(val, control_phy->ctrl_sma);
+}
+EXPORT_SYMBOL_GPL(omap_control_pcie_tx_rx_control);
+
+/**
* omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
@@ -61,6 +95,7 @@ void omap_control_phy_power(struct device *dev, int on)
val |= OMAP_CTRL_DEV_PHY_PD;
break;
+ case OMAP_CTRL_TYPE_PCIE:
case OMAP_CTRL_TYPE_PIPE3:
rate = clk_get_rate(control_phy->sys_clk);
rate = rate/100;
@@ -211,6 +246,7 @@ EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
+static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
static const enum omap_control_phy_type dra7usb2_data =
OMAP_CTRL_TYPE_DRA7USB2;
static const enum omap_control_phy_type am437usb2_data =
OMAP_CTRL_TYPE_AM437USB2;
@@ -228,6 +264,10 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = &pipe3_data,
},
{
+ .compatible = "ti,control-phy-pcie",
+ .data = &pcie_data,
+ },
+ {
.compatible = "ti,control-phy-usb2-dra7",
.data = &dra7usb2_data,
},
@@ -279,7 +319,8 @@ static int omap_control_phy_probe(struct platform_device
*pdev)
}
}
- if (co
[PATCH 00/17] PCIe support for DRA7xx
This patch series adds support for PCIe in DRA7xx including drivers and dt data. PCIe in DRA7xx uses desingware IP and hence this re-uses the pcie desingware driver (pcie-designware.c) by Jingoo. The last couple of patches are marked as *TEMP* since the TI reset driver [1] is not yet merged and is in RFC. Tested broadcom PCIe card and XIO2000 bridge along with DGE530T ethernet card. Changes from RFC: * Added external clock support for PCIE APLL * Miscellaneous cleanups in Documentation, macro naming etc.. [1] -> http://www.spinics.net/lists/linux-omap/msg106411.html Keerthy (2): ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I (15): phy: phy-omap-pipe3: Add support for PCIe PHY phy: omap-control: add external clock support for PCIe PHY phy: ti-pipe3: add external clock support for PCIe PHY phy: pipe3: insert delay to enumerate in GEN2 mode pci: host: pcie-dra7xx: add support for pcie-dra7xx controller pci: host: pcie-designware: Use *base-mask* for configuring the iATU arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY ARM: dts: dra7: Add dt data for PCIe PHY control module ARM: dts: dra7: Add dt data for PCIe PHY ARM: dts: dra7: Add dt data for PCIe controller ARM: OMAP: Enable PCI for DRA7 pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe ARM: dts: dra7: Add *resets* property for PCIe dt node .../devicetree/bindings/pci/designware-pcie.txt|1 + Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++ Documentation/devicetree/bindings/phy/ti-phy.txt | 21 +- arch/arm/boot/dts/dra7.dtsi| 55 +++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 11 +- arch/arm/mach-omap2/Kconfig|2 + arch/arm/mach-omap2/cm2_7xx.h |4 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 ++ arch/arm/mach-omap2/prm7xx.h |4 + drivers/pci/host/Kconfig | 10 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-dra7xx.c | 395 drivers/pci/host/pcie-designware.c | 39 +- drivers/pci/host/pcie-designware.h |1 + drivers/phy/phy-omap-control.c | 92 - drivers/phy/phy-ti-pipe3.c | 142 +-- include/linux/phy/omap_control_phy.h | 23 ++ 17 files changed, 898 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt create mode 100644 drivers/pci/host/pci-dra7xx.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Hi,
On Tuesday 06 May 2014 07:14 PM, Marek Vasut wrote:
> On Tuesday, May 06, 2014 at 03:33:51 PM, Kishon Vijay Abraham I wrote:
>> Added support for pcie controller in dra7xx. This driver re-uses
>> the designware core code that is already present in kernel.
>
> [...]
>
>> +#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
>> +
>> +static inline u32 dra7xx_pcie_readl(void __iomem *base, u32 offset)
>
> Just pass struct dra7xx_pcie * instead of *base here , it will make the code
> below shorter.
>
>> +{
>> +return readl(base + offset);
>> +}
>> +
>> +static inline void dra7xx_pcie_writel(void __iomem *base, u32 offset, u32
>> value) +{
>
> DTTO.
>
>> +writel(value, base + offset);
>> +}
>> +
>> +static int dra7xx_pcie_link_up(struct pcie_port *pp)
>> +{
>> +struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>> +u32 reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_PHY_CS);
>> +
>> +if (reg & LINK_UP)
>> +return true;
>> +return false;
>
> return reg & LINK_UP;
>
>> +}
>> +
>> +static int dra7xx_pcie_establish_link(struct pcie_port *pp)
>> +{
>> +u32 reg;
>> +int retries = 1000;
>> +struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>> +
>> +if (dw_pcie_link_up(pp)) {
>> +dev_err(pp->dev, "link is already up\n");
>
> This will spew, since the .link_up (and thus this function) can be called
> repeatedly. The subsystem will query if the link is up via this function.
*dra7xx_pcie_establish_link* is not the callback for link_up function, so it's
actually called only once.
>
>> +return 0;
>> +}
>> +
>> +reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
>> +reg |= LTSSM_EN;
>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
>> +
>> +while (--retries) {
>
> Use retries--
>
>> +reg = dra7xx_pcie_readl(dra7xx->base,
>> +PCIECTRL_DRA7XX_CONF_PHY_CS);
>> +if (reg & LINK_UP)
>> +break;
>> +usleep_range(10, 20);
>> +}
>> +
>> +if (retries <= 0) {
>
> Then check if retries == 0 and retries can be unsigned int.
>
>> +dev_err(pp->dev, "link is not up\n");
>> +return -ETIMEDOUT;
>> +}
>> +
>> +return 0;
>> +}
> [...]
>> +static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>> +{
>> +u32 reg;
>> +int ret;
>> +int irq;
>> +struct phy *phy;
>> +void __iomem *base;
>> +struct resource *res;
>> +struct dra7xx_pcie *dra7xx;
>> +struct device *dev = &pdev->dev;
>> +
>> +dra7xx = devm_kzalloc(&pdev->dev, sizeof(*dra7xx), GFP_KERNEL);
>> +if (!dra7xx)
>> +return -ENOMEM;
>> +
>> +irq = platform_get_irq(pdev, 0);
>> +if (irq < 0) {
>> +dev_err(dev, "missing IRQ resource\n");
>> +return -EINVAL;
>> +}
>> +
>> +ret = devm_request_irq(&pdev->dev, irq, dra7xx_pcie_irq_handler,
>> + IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
>> +if (ret) {
>> +dev_err(&pdev->dev, "failed to request irq\n");
>> +return ret;
>> +}
>> +
>> +res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
>> +base = devm_ioremap_nocache(dev, res->start, resource_size(res));
>> +if (!base)
>> +return -ENOMEM;
>> +
>> +phy = devm_phy_get(dev, "pcie-phy");
>> +if (IS_ERR(phy))
>> +return PTR_ERR(phy);
>> +
>> +ret = phy_init(phy);
>> +if (ret < 0)
>> +return ret;
>> +
>> +ret = phy_power_on(phy);
>> +if (ret < 0)
>> +goto err_power_on;
>> +
>> +dra7xx->base = base;
>> +dra7xx->phy = phy;
>> +dra7xx->dev = dev;
>> +
>> +pm_runtime_enable(&pdev->dev);
>> +ret = pm_runtime_get_sync(&pdev->dev);
>> +if (IS_ERR_VALUE(ret)) {
>> +dev_err(dev, "pm_runtime_get_sync failed\n");
>> +goto err_runtime_get;
>> +}
>> +
>> +reg = dra7xx_pcie_readl(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
>> +reg &= ~LTSSM_EN;
>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
>
> platform_set_drvdata() should be here, before you add the port.
>
>> +ret = add_pcie_port(dra7xx, pdev);
>> +if (ret < 0)
>> +goto err_add_port;
>> +
>> +platform_set_drvdata(pdev, dra7xx);
Al-right. Will fix this and all your other comments.
Thanks
Kishon
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Re: [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Hi,
On Tuesday 06 May 2014 07:24 PM, Arnd Bergmann wrote:
> On Tuesday 06 May 2014 19:03:51 Kishon Vijay Abraham I wrote:
>> Added support for pcie controller in dra7xx. This driver re-uses
>> the designware core code that is already present in kernel.
>>
>> Cc: Bjorn Helgaas
>> Cc: Mohit Kumar
>> Cc: Jingoo Han
>> Cc: Marek Vasut
>> Signed-off-by: Kishon Vijay Abraham I
>
> Looks pretty good overall, just a few details I noticed:
>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> new file mode 100644
>> index 000..6cb6f09
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -0,0 +1,33 @@
>> +TI PCI Controllers
>> +
>> +PCIe Designware Controller
>> +This node should have the properties described in "designware-pcie.txt".
>> + - compatible: Should be "ti,dra7xx-pcie""
>
> No "xx" in compatible strings please. Just make name this after the first
> chip to use this particular interface.
ok.
>
>> + - reg : Address and length of the register set for the device.
>> + - reg-names : "ti_conf" for the TI specific registers and rc_dbics for the
>> + "designware" registers.
>
> The description uses inconsistent quotation marks. You should also have
> a fixed order in the binding, such as
>
> - reg : Two register ranges as listed in the reg-names property
> - reg-names : The first entry must be "ti-conf" for the TI specific registers
> The second entry must be "rc-dbics" for the designware pcie
> registers.
ok, looks better.
>
>> + - phys : the phandle for the PHY device (used by generic PHY framework)
>> + - phy-names : the names of the PHY corresponding to the PHYs present in the
>> + *phy* phandle.
>
> It's not just a phandle, it can be any phy specifier including additional
> argument cells.
>
> The second line should just read
>
> - phy-names : must be "pcie-phy"
will fix this.
>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index a6f67ec..7be6393 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -1,6 +1,16 @@
>> menu "PCI host controller drivers"
>> depends on PCI
>>
>> +config PCI_DRA7XX
>> +bool "TI DRA7xx PCIe controller"
>> +select PCIE_DW
>> +depends on OF || HAS_IOMEM || TI_PIPE3
>
> I think you mean &&, not || here.
ah.. indeed.
>
>> +static inline u32 x(void __iomem *base, u32 offset)
>> +{
>> +return readl(base + offset);
>> +}
>> +
>> +static inline void dra7xx_pcie_writel(void __iomem *base, u32 offset, u32
>> value)
>> +{
>> +writel(value, base + offset);
>> +}
>
> These don't actually seem to add any value, you need more characters
> to call the inline function than to open-code it.
>
>> +static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
>> +{
>> +struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>> +
>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
>> + ~INTERRUPTS);
>> +dra7xx_pcie_writel(dra7xx->base,
>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
>> + ~LEG_EP_INTERRUPTS & ~MSI);
>> +
>> +if (IS_ENABLED(CONFIG_PCI_MSI))
>> +dra7xx_pcie_writel(dra7xx->base,
>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
>> +else
>> +dra7xx_pcie_writel(dra7xx->base,
>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
>> + LEG_EP_INTERRUPTS);
>
> Doesn't this just enable one or the other? In general I'd assume you need
> both INTx and MSI, at least if MSI is available.
Not sure since the programming sequence in the TRM explicitly states either
legacy interrupts or MSI interrupts should be enabled but not both.
>
> It probably doesn't hurt to always turn them all on.
>
>> +static int add_pcie_port(struct dra7xx_pcie *dra7xx,
>> + struct platform_device *pdev)
>> +{
>> +int ret;
>> +struct pcie_port *pp;
>> +struct resource *res;
>> +struct device *dev = &pdev->dev;
>> +
>> +pp = &dra7xx->pp
Re: [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Hi,
On Tuesday 06 May 2014 10:05 PM, Jason Gunthorpe wrote:
> On Tue, May 06, 2014 at 07:03:51PM +0530, Kishon Vijay Abraham I wrote:
>> +Example:
>> +pcie@5100 {
>> +compatible = "ti,dra7xx-pcie";
>> +reg = <0x51002000 0x14c>, <0x5100 0x2000>;
>> +reg-names = "ti_conf", "rc_dbics";
>> +interrupts = <0 232 0x4>, <0 233 0x4>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>> +ti,device_type = <3>;
>> +ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /*
>> Configuration Space */
>
> Configuration space should not show up in the ranges, please don't
> copy that mistake from other drivers, put it in reg.
But then it needs pcie-designware.c to be modified and it will be breaking
other platforms no?
>
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0x0 0 &gic 134>;
>
> The HW cannot decode INTA/B/C/D?
>
>> +#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
>> +#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
>> +#define INTABIT(0)
>> +#define INTBBIT(1)
>> +#define INTCBIT(2)
>> +#define INTDBIT(3)
>> +#define MSI BIT(4)
>> +#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
>
> Oh, it can, it would be wise to export this from the driver. Look at
> the latest patches from Srikanth Thokala for the Xilinx PCI driver to
> see how this should look
ok.. will have a look at it.
Thanks
Kishon
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Re: [PATCH 3/5] usb: dwc3: dwc3-omap: Add dwc3_omap_extcon_register function
On Thursday 08 May 2014 02:51 PM, George Cherian wrote:
> Move the extcon related code to its own function.
> Improve code readability, decrease the dwc3_probe() size.
>
> Signed-off-by: George Cherian
> ---
> drivers/usb/dwc3/dwc3-omap.c | 65
> ++--
> 1 file changed, 39 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
> index b739a24..0b9b1d8 100644
> --- a/drivers/usb/dwc3/dwc3-omap.c
> +++ b/drivers/usb/dwc3/dwc3-omap.c
> @@ -450,6 +450,42 @@ static void dwc3_omap_set_utmi_mode(struct dwc3_omap
> *omap)
> dwc3_omap_write_utmi_status(omap, reg);
> }
>
> +static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
> +{
> + u32 ret;
'ret' shouldn't be unsigned.
Thanks
Kishon
> + struct device_node *node = omap->dev->of_node;
> + struct extcon_dev *edev;
> +
> + if (of_property_read_bool(node, "extcon")) {
> + edev = extcon_get_edev_by_phandle(omap->dev, 0);
> + if (IS_ERR(edev)) {
> + dev_vdbg(omap->dev, "couldn't get extcon device\n");
> + return -EPROBE_DEFER;
> + }
> +
> + omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
> + ret = extcon_register_interest(&omap->extcon_vbus_dev,
> +edev->name, "USB",
> +&omap->vbus_nb);
> + if (ret < 0)
> + dev_vdbg(omap->dev, "failed to register notifier for
> USB\n");
> +
> + omap->id_nb.notifier_call = dwc3_omap_id_notifier;
> + ret = extcon_register_interest(&omap->extcon_id_dev,
> +edev->name, "USB-HOST",
> +&omap->id_nb);
> + if (ret < 0)
> + dev_vdbg(omap->dev, "failed to register notifier for
> USB-HOST\n");
> +
> + if (extcon_get_cable_state(edev, "USB") == true)
> + dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
> + if (extcon_get_cable_state(edev, "USB-HOST") == true)
> + dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
> + }
> +
> + return 0;
> +}
> +
> static int dwc3_omap_probe(struct platform_device *pdev)
> {
> struct device_node *node = pdev->dev.of_node;
> @@ -457,7 +493,6 @@ static int dwc3_omap_probe(struct platform_device *pdev)
> struct dwc3_omap*omap;
> struct resource *res;
> struct device *dev = &pdev->dev;
> - struct extcon_dev *edev;
> struct regulator*vbus_reg = NULL;
>
> int ret = -ENOMEM;
> @@ -529,31 +564,9 @@ static int dwc3_omap_probe(struct platform_device *pdev)
>
> dwc3_omap_enable_irqs(omap);
>
> - if (of_property_read_bool(node, "extcon")) {
> - edev = extcon_get_edev_by_phandle(dev, 0);
> - if (IS_ERR(edev)) {
> - dev_vdbg(dev, "couldn't get extcon device\n");
> - ret = -EPROBE_DEFER;
> - goto err2;
> - }
> -
> - omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
> - ret = extcon_register_interest(&omap->extcon_vbus_dev,
> - edev->name, "USB", &omap->vbus_nb);
> - if (ret < 0)
> - dev_vdbg(dev, "failed to register notifier for USB\n");
> - omap->id_nb.notifier_call = dwc3_omap_id_notifier;
> - ret = extcon_register_interest(&omap->extcon_id_dev, edev->name,
> - "USB-HOST", &omap->id_nb);
> - if (ret < 0)
> - dev_vdbg(dev,
> - "failed to register notifier for USB-HOST\n");
> -
> - if (extcon_get_cable_state(edev, "USB") == true)
> - dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
> - if (extcon_get_cable_state(edev, "USB-HOST") == true)
> - dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
> - }
> + ret = dwc3_omap_extcon_register(omap);
> + if (ret < 0)
> + goto err2;
>
> ret = of_platform_populate(node, NULL, NULL, dev);
> if (ret) {
>
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Re: [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller
Hi Arnd,
On Wednesday 07 May 2014 03:00 PM, Arnd Bergmann wrote:
> On Wednesday 07 May 2014 14:14:55 Kishon Vijay Abraham I wrote:
>>>> +static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
>>>> +{
>>>> +struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
>>>> +
>>>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
>>>> + ~INTERRUPTS);
>>>> +dra7xx_pcie_writel(dra7xx->base,
>>>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
>>>> INTERRUPTS);
>>>> +dra7xx_pcie_writel(dra7xx->base, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
>>>> + ~LEG_EP_INTERRUPTS & ~MSI);
>>>> +
>>>> +if (IS_ENABLED(CONFIG_PCI_MSI))
>>>> +dra7xx_pcie_writel(dra7xx->base,
>>>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
>>>> MSI);
>>>> +else
>>>> +dra7xx_pcie_writel(dra7xx->base,
>>>> + PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
>>>> + LEG_EP_INTERRUPTS);
>>>
>>> Doesn't this just enable one or the other? In general I'd assume you need
>>> both INTx and MSI, at least if MSI is available.
>>
>> Not sure since the programming sequence in the TRM explicitly states either
>> legacy interrupts or MSI interrupts should be enabled but not both.
>
> Hmm, I think that means you can't have MSI at all. You have to support
> legacy PCI devices that can't do MSI.
>
> Do you know if you have a modern GIC implementation with MSI support
> in these SoCs? It would be better anyway to use the GIC for doing
In DRA7 it is not there. I'm not sure in other platforms.
> MSI, so you can just ignore the internal MSI controller here.
>
>>>> +static int add_pcie_port(struct dra7xx_pcie *dra7xx,
>>>> + struct platform_device *pdev)
>>>> +{
>>>> +int ret;
>>>> +struct pcie_port *pp;
>>>> +struct resource *res;
>>>> +struct device *dev = &pdev->dev;
>>>> +
>>>> +pp = &dra7xx->pp;
>>>> +pp->dev = dev;
>>>> +pp->ops = &dra7xx_pcie_host_ops;
>>>> +
>>>> +spin_lock_init(&pp->conf_lock);
>>>> +
>>>> +pp->irq = platform_get_irq(pdev, 1);
>>>> +if (pp->irq < 0) {
>>>> +dev_err(dev, "missing IRQ resource\n");
>>>> +return -EINVAL;
>>>> +}
>>>>
>>>
>>> The binding does not list a mandatory "interrupts" property, so
>>> this should not be treated as an error.
>>
>> actually the 'interrupts' property is documented in pci/designware-pcie.txt.
>
> Hmm, but you don't seem to use it the same way as documented there.
> I'm not sure what 'level interrupt, pulse interrupt, special interrupt'
> in the parent binding are, but they don't seem to be the ones you use
> here.
Yeah. I'll update my Documentation. Thanks for pointing this out.
Thanks
Kishon
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Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hi, On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote: > On Thursday 08 May 2014 18:05:11 Jingoo Han wrote: >> On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote: >>> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote: >>>> In DRA7, the cpu sees 32bit address, but the pcie controller can see only >>>> 28bit >>>> address. So whenever the cpu issues a read/write request, the 4 most >>>> significant bits are used by L3 to determine the target controller. >>>> For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe >>>> controller but >>>> the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for >>>> programming >>>> the outbound translation window the *base* should be programmed as >>>> 0x000_. >>>> Whenever we try to write to say 0x2000_, it will be translated to >>>> whatever >>>> we have programmed in the translation window with base as 0x000_. >>>> >>>> Cc: Bjorn Helgaas >>>> Cc: Marek Vasut >>>> Signed-off-by: Kishon Vijay Abraham I >>>> Acked-by: Jingoo Han >>>> Acked-by: Mohit Kumar >>> >>> Sorry, but NAK. >>> >>> We have a standard 'dma-ranges' property to handle this, so use it. >>> >>> See the x-gene PCIe driver patches for an example. Please also talk >>> to Santosh about it, as he is implementing generic support for >>> parsing dma-ranges in platform devices at the moment. >> >> Hi Arnd, >> >> Do you mean the following patch? >> http://www.spinics.net/lists/kernel/msg1737725.html >> > > That is the patch Santosh did for platform devices, which is related but not > what I meant here. For the PCI inbound window setup, please have a look > at https://lkml.org/lkml/2014/3/19/607 For some reason lkml is not showing any contents. Do you have a different link? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hi Arnd, On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote: > On Thursday 08 May 2014 18:05:11 Jingoo Han wrote: >> On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote: >>> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote: >>>> In DRA7, the cpu sees 32bit address, but the pcie controller can see only >>>> 28bit >>>> address. So whenever the cpu issues a read/write request, the 4 most >>>> significant bits are used by L3 to determine the target controller. >>>> For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe >>>> controller but >>>> the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for >>>> programming >>>> the outbound translation window the *base* should be programmed as >>>> 0x000_. >>>> Whenever we try to write to say 0x2000_, it will be translated to >>>> whatever >>>> we have programmed in the translation window with base as 0x000_. >>>> >>>> Cc: Bjorn Helgaas >>>> Cc: Marek Vasut >>>> Signed-off-by: Kishon Vijay Abraham I >>>> Acked-by: Jingoo Han >>>> Acked-by: Mohit Kumar >>> >>> Sorry, but NAK. >>> >>> We have a standard 'dma-ranges' property to handle this, so use it. >>> >>> See the x-gene PCIe driver patches for an example. Please also talk >>> to Santosh about it, as he is implementing generic support for >>> parsing dma-ranges in platform devices at the moment. >> >> Hi Arnd, >> >> Do you mean the following patch? >> http://www.spinics.net/lists/kernel/msg1737725.html >> > > That is the patch Santosh did for platform devices, which is related but not > what I meant here. For the PCI inbound window setup, please have a look > at https://lkml.org/lkml/2014/3/19/607 Do you think it can be used for *outbound* window setup too? The problem is the *ranges* property defines both the pci address and cpu address which should have been enough to program the ob translation window, but the hw is designed so that the controller sees only the 28 bits. (The most significant 4 bits is for the l3 to address the controller). Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hi Arnd, On Tuesday 13 May 2014 06:17 PM, Arnd Bergmann wrote: > On Tuesday 13 May 2014 18:01:59 Kishon Vijay Abraham I wrote: >> On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote: >>> On Thursday 08 May 2014 18:05:11 Jingoo Han wrote: >>>> On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote: >>>>> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote: >>>>>> In DRA7, the cpu sees 32bit address, but the pcie controller can see >>>>>> only 28bit >>>>>> address. So whenever the cpu issues a read/write request, the 4 most >>>>>> significant bits are used by L3 to determine the target controller. >>>>>> For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe >>>>>> controller but >>>>>> the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for >>>>>> programming >>>>>> the outbound translation window the *base* should be programmed as >>>>>> 0x000_. >>>>>> Whenever we try to write to say 0x2000_, it will be translated to >>>>>> whatever >>>>>> we have programmed in the translation window with base as 0x000_. >>>>>> >>>>>> Cc: Bjorn Helgaas >>>>>> Cc: Marek Vasut >>>>>> Signed-off-by: Kishon Vijay Abraham I >>>>>> Acked-by: Jingoo Han >>>>>> Acked-by: Mohit Kumar >>>>> >>>>> Sorry, but NAK. >>>>> >>>>> We have a standard 'dma-ranges' property to handle this, so use it. >>>>> >>>>> See the x-gene PCIe driver patches for an example. Please also talk >>>>> to Santosh about it, as he is implementing generic support for >>>>> parsing dma-ranges in platform devices at the moment. >>>> >>>> Hi Arnd, >>>> >>>> Do you mean the following patch? >>>> http://www.spinics.net/lists/kernel/msg1737725.html >>>> >>> >>> That is the patch Santosh did for platform devices, which is related but not >>> what I meant here. For the PCI inbound window setup, please have a look >>> at https://lkml.org/lkml/2014/3/19/607 >> >> Do you think it can be used for *outbound* window setup too? The problem is >> the >> *ranges* property defines both the pci address and cpu address which should >> have been enough to program the ob translation window, but the hw is designed >> so that the controller sees only the 28 bits. (The most significant 4 bits is >> for the l3 to address the controller). > > I'm not following what the problem is. You should always be able to describe > in the inbound window (that is from the CPU perspective) using dma-ranges > and the outbound window using ranges. > > If you have a case where the outbound translation is a 256MB (i.e. 28bit) > section of the CPU address space, that could be represented as > > ranges = <0x8200 0 0 0xb000 0 0x1000>; > > or > > ranges = <0x8200 0 0xb000 0xb000 0 0x1000>; > > depending on whether you want the BARs to be programmed using a low > address 0x0-0x0fff or an address matching the window > 0xb000-0xbfff. The problem is, for configuring the window starting at 0xb000, the ATU should be programmed 0x000 (the cpu address for it will be 0xb000 though). Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
hi Arnd, On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote: > On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote: >> On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote: >>>> If you have a case where the outbound translation is a 256MB (i.e. 28bit) >>>> section of the CPU address space, that could be represented as >>>> >>>> ranges = <0x8200 0 0 0xb000 0 0x1000>; >>>> >>>> or >>>> >>>> ranges = <0x8200 0 0xb000 0xb000 0 0x1000>; >>>> >>>> depending on whether you want the BARs to be programmed using a low >>>> address 0x0-0x0fff or an address matching the window >>>> 0xb000-0xbfff. >>> >>> The problem is, for configuring the window starting at 0xb000, the ATU >>> should be programmed 0x000 (the cpu address for it will be 0xb000 >>> though). >>> >> >> Then use the first of the two? >> > > To clarify: using <0x8200 0 0 0xb000 0 0x1000> will give you > a mem_offset of 0xb000, which should work just fine for this case. > > What I don't understand is why the ATU cares about whether the outbound > address is 0x000 or 0xb000 if it just decodes the lower 28 bit > anyway. Did you mean that we have to program the BARs using low addresses > regardless of what is programmed in the ATU? That would make more sense, > and it also matches what I suggested. No, It's not like it decodes only the lower 28bits. The BARs is programmed with 32 bit value. My pcie dt node has ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /* CONFIG */ 0x8100 0 0 0x20003000 0 0x0001 /* IO */ 0x8200 0 0x20013000 0x20013000 0 0xffed000>; /* MEM */ Consider MEM address space.. Here both PCI address and CPU address is 0x20013000. So when there is a write to cpu addr 0x20013000 [writel(virt_addr(0x20013000)], we want it to be translated to PCI addr 0x20013000. So in 'ATU', we would expect *base* to be programmed to *0x20013000* and target to be programmed to *0x20013000*. But that's not the case for DRA7xx. For DRA7xx *base* should be programmed to *0x0013000* and target should be programmed to *0x20013000*. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hi Arnd,
On Wednesday 14 May 2014 06:15 PM, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 11:14:45 Kishon Vijay Abraham I wrote:
>> hi Arnd,
>>
>> On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
>>> On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
>>>> On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
>>>>>> If you have a case where the outbound translation is a 256MB (i.e. 28bit)
>>>>>> section of the CPU address space, that could be represented as
>>>>>>
>>>>>> ranges = <0x8200 0 0 0xb000 0 0x1000>;
>>>>>>
>>>>>> or
>>>>>>
>>>>>> ranges = <0x8200 0 0xb000 0xb000 0 0x1000>;
>>>>>>
>>>>>> depending on whether you want the BARs to be programmed using a low
>>>>>> address 0x0-0x0fff or an address matching the window
>>>>>> 0xb000-0xbfff.
>>>>>
>>>>> The problem is, for configuring the window starting at 0xb000, the ATU
>>>>> should be programmed 0x000 (the cpu address for it will be 0xb000
>>>>> though).
>>>>>
>>>>
>>>> Then use the first of the two?
>>>>
>>>
>>> To clarify: using <0x8200 0 0 0xb000 0 0x1000> will give you
>>> a mem_offset of 0xb000, which should work just fine for this case.
>>>
>>> What I don't understand is why the ATU cares about whether the outbound
>>> address is 0x000 or 0xb000 if it just decodes the lower 28 bit
>>> anyway. Did you mean that we have to program the BARs using low addresses
>>> regardless of what is programmed in the ATU? That would make more sense,
>>> and it also matches what I suggested.
>>
>> No, It's not like it decodes only the lower 28bits. The BARs is programmed
>> with
>> 32 bit value.
>>
>> My pcie dt node has
>> ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /* CONFIG */
>>0x8100 0 0 0x20003000 0 0x0001 /* IO */
>>0x8200 0 0x20013000 0x20013000 0 0xffed000>; /* MEM */
>>
>> Consider MEM address space..
>>
>> Here both PCI address and CPU address is 0x20013000. So when there is a write
>> to cpu addr 0x20013000 [writel(virt_addr(0x20013000)], we want it to be
>> translated to PCI addr 0x20013000. So in 'ATU', we would expect *base* to be
>> programmed to *0x20013000* and target to be programmed to *0x20013000*. But
>> that's not the case for DRA7xx. For DRA7xx *base* should be programmed to
>> *0x0013000* and target should be programmed to *0x20013000*.
>
> Ok, got it, thanks for your patience.
>
> I think this would best be modeled as a separate bus node that contains the
> restriction, like this:
>
> / {
> #address-cells = <1>; // or <2> if you support > 4GB address space
> #size-cells = <1>;
>
> soc {
> #address-cells <1>;
> #size-cells = <1>;
> ranges;
> dma-ranges;
>
> ... // all normal devices
>
> axi@2000 {
> #size-cells = <1>;
> #address-cells = <1>;
> dma-ranges; // can access all 4GB outbound
> ranges = <0 0x2000 0x1000>; // 28-bit bus
>
> pci@0 {
> reg = <0x00x1000>, // internal regs
> <0x1000 0x2000>; // config space
> dma-ranges; // 32-bit outbound
> ranges = <0x8100 0 0 0x3000 0
> 0x0001 /* IO */
> 0x8200 0 0x20013000 0x13000 0
> 0xffed000>; /* MEM */
> };
> };
> };
> };
Nice :-)
Thanks
Kishon
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Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi Roger,
On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
> Hi Kishon,
>
> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
>> APLL used by PCIE phy can either use external clock as input or the clock
>> from DPLL. Added support for the APLL to use external clock as input here.
>>
>> Cc: Rajendra Nayak
>> Cc: Tero Kristo
>> Cc: Paul Walmsley
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++
>> drivers/phy/phy-ti-pipe3.c | 75
>> ++
>> 2 files changed, 52 insertions(+), 27 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> index bc9afb5..d50f8ee 100644
>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>> @@ -76,6 +76,10 @@ Required properties:
>> * "dpll_ref_m2" - external dpll ref clk
>> * "phy-div" - divider for apll
>> * "div-clk" - apll clock
>> + * "apll_mux" - mux for pcie apll
>> + * "refclk_ext" - external reference clock for pcie apll
>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock.
>> Applicable
>> + only to PCIE PHY.
>
> Instead of specifying both clock sources "dpll_ref_clock", "refclk_ext" and
> then specifying a 3rd control option "ti,ext-clk" to select one of the 2
> sources, why can't the DT just supply one clock source, i.e. the one that is
> being used in the board instance? The driver should then just configure the
> clock rate that is needed at that node. Shouldn't the clock framework
> automatically take care of muxing and parent rates?
Want the dt to have all the clocks used by the controller. "ti,ext-clk" should
go in the board dt file (suggested by Nishanth).
The point is at some point later if some one wants to change the clock source,
it should be a simple enabling "ti,ext-clk" flag instead of finding the clock
phandle etc..
>
>>
>> Optional properties:
>> - ctrl-module : phandle of the control module used by PHY driver to power
>> on
>> diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
>> index d43019d..5513aa0 100644
>> --- a/drivers/phy/phy-ti-pipe3.c
>> +++ b/drivers/phy/phy-ti-pipe3.c
>> @@ -293,7 +293,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
>> struct device_node *control_node;
>> struct platform_device *control_pdev;
>> const struct of_device_id *match;
>> -struct clk *clk;
>> +struct clk *clk, *pclk;
>>
>> phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
>> if (!phy) {
>> @@ -302,6 +302,20 @@ static int ti_pipe3_probe(struct platform_device *pdev)
>> }
>> phy->dev= &pdev->dev;
>>
>> +control_node = of_parse_phandle(node, "ctrl-module", 0);
>> +if (!control_node) {
>> +dev_err(&pdev->dev, "Failed to get control device phandle\n");
>> +return -EINVAL;
>> +}
>> +
>> +control_pdev = of_find_device_by_node(control_node);
>> +if (!control_pdev) {
>> +dev_err(&pdev->dev, "Failed to get control device\n");
>> +return -EINVAL;
>> +}
>> +
>> +phy->control_dev = &control_pdev->dev;
>> +
>
> Why this code was moved move is not part of patch description/subject.
external clock support needs 'control_dev', so had to move the get control
device part before configuring the clocks.
>
>> if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
>> match = of_match_device(of_match_ptr(ti_pipe3_id_table),
>> &pdev->dev);
>> @@ -345,19 +359,40 @@ static int ti_pipe3_probe(struct platform_device *pdev)
>> }
>>
>> if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
>> -clk = devm_clk_get(phy->dev, "dpll_ref");
>> -if (IS_ERR(clk)) {
>> -dev_err(&pdev->dev, "unable to get dpll ref clk\n");
>> -return PTR_ERR(clk);
>> +if (!of_property_read_bool(node, "ti,ext-clk")) {
>> +clk = devm_clk_get(phy->dev, "dpll_ref");
>> +
Re: [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
On Wednesday 14 May 2014 06:53 PM, Roger Quadros wrote:
> Hi Kishon,
>
>
> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
>> Added missing 32khz clock used by PCIe PHY.
>> The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
>
> Typo in $subject
> s/clocks/clock
Will fix it.
Thanks
Kishon
>
> --
> cheers,
> -roger
>
>>
>> Cc: Tony Lindgren
>> Cc: Rajendra Nayak
>> Cc: Tero Kristo
>> Cc: Paul Walmsley
>> Cc: Rob Herring
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/boot/dts/dra7xx-clocks.dtsi |8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 44993ec..e1bd052 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1165,6 +1165,14 @@
>> reg = <0x021c>, <0x0220>;
>> };
>>
>> +optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
>> +compatible = "ti,gate-clock";
>> +clocks = <&sys_32k_ck>;
>> +#clock-cells = <0>;
>> +reg = <0x13b0>;
>> +ti,bit-shift = <8>;
>> +};
>> +
>> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
>> compatible = "ti,divider-clock";
>> clocks = <&apll_pcie_ck>;
>>
>
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Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi Nishanth, On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote: > On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I > wrote: >> Hi Roger, >> >> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote: >>> Hi Kishon, >>> >>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote: >>>> APLL used by PCIE phy can either use external clock as input or the clock >>>> from DPLL. Added support for the APLL to use external clock as input here. >>>> >>>> Cc: Rajendra Nayak >>>> Cc: Tero Kristo >>>> Cc: Paul Walmsley >>>> Signed-off-by: Kishon Vijay Abraham I >>>> --- >>>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++ >>>> drivers/phy/phy-ti-pipe3.c | 75 >>>> ++ >>>> 2 files changed, 52 insertions(+), 27 deletions(-) >>>> >>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>> index bc9afb5..d50f8ee 100644 >>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>> @@ -76,6 +76,10 @@ Required properties: >>>> * "dpll_ref_m2" - external dpll ref clk >>>> * "phy-div" - divider for apll >>>> * "div-clk" - apll clock >>>> + * "apll_mux" - mux for pcie apll >>>> + * "refclk_ext" - external reference clock for pcie apll >>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock. >>>> Applicable >>>> + only to PCIE PHY. >>> >>> Instead of specifying both clock sources "dpll_ref_clock", "refclk_ext" and >>> then specifying a 3rd control option "ti,ext-clk" to select one of the 2 >>> sources, why can't the DT just supply one clock source, i.e. the one that >>> is being used in the board instance? The driver should then just configure >>> the clock rate that is needed at that node. Shouldn't the clock framework >>> automatically take care of muxing and parent rates? >> >> Want the dt to have all the clocks used by the controller. "ti,ext-clk" >> should >> go in the board dt file (suggested by Nishanth). >> The point is at some point later if some one wants to change the clock >> source, >> it should be a simple enabling "ti,ext-clk" flag instead of finding the clock >> phandle etc.. > > Wonder if that is implicit by the presence of "refclk_ext" in the > clocks provided? IMO the presence of "refclk_ext" is useless unless the board indicates it provides the clock source. refclk_ext holds phandle for *fixed-clock*, so irrespective of whether the board provides a clock or not, it can have that handle for configuring in PRCM. However if the board does not provide the clock source, configuring refclk_ext in PRCM is useless. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi Nishant, On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote: > On Thu, May 15, 2014 at 4:25 AM, Roger Quadros wrote: >> On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote: >>> Hi Nishanth, >>> >>> On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote: >>>> On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I >>>> wrote: >>>>> Hi Roger, >>>>> >>>>> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote: >>>>>> Hi Kishon, >>>>>> >>>>>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote: >>>>>>> APLL used by PCIE phy can either use external clock as input or the >>>>>>> clock >>>>>>> from DPLL. Added support for the APLL to use external clock as input >>>>>>> here. >>>>>>> >>>>>>> Cc: Rajendra Nayak >>>>>>> Cc: Tero Kristo >>>>>>> Cc: Paul Walmsley >>>>>>> Signed-off-by: Kishon Vijay Abraham I >>>>>>> --- >>>>>>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++ >>>>>>> drivers/phy/phy-ti-pipe3.c | 75 >>>>>>> ++ >>>>>>> 2 files changed, 52 insertions(+), 27 deletions(-) >>>>>>> >>>>>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>> index bc9afb5..d50f8ee 100644 >>>>>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>> @@ -76,6 +76,10 @@ Required properties: >>>>>>> * "dpll_ref_m2" - external dpll ref clk >>>>>>> * "phy-div" - divider for apll >>>>>>> * "div-clk" - apll clock >>>>>>> + * "apll_mux" - mux for pcie apll >>>>>>> + * "refclk_ext" - external reference clock for pcie apll >>>>>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock. >>>>>>> Applicable >>>>>>> + only to PCIE PHY. >>>>>> >>>>>> Instead of specifying both clock sources "dpll_ref_clock", "refclk_ext" >>>>>> and then specifying a 3rd control option "ti,ext-clk" to select one of >>>>>> the 2 sources, why can't the DT just supply one clock source, i.e. the >>>>>> one that is being used in the board instance? The driver should then >>>>>> just configure the clock rate that is needed at that node. Shouldn't the >>>>>> clock framework automatically take care of muxing and parent rates? >>>>> >>>>> Want the dt to have all the clocks used by the controller. "ti,ext-clk" >>>>> should >>>>> go in the board dt file (suggested by Nishanth). >>>>> The point is at some point later if some one wants to change the clock >>>>> source, >>>>> it should be a simple enabling "ti,ext-clk" flag instead of finding the >>>>> clock >>>>> phandle etc.. >>>> >>>> Wonder if that is implicit by the presence of "refclk_ext" in the >>>> clocks provided? >>> >>> IMO the presence of "refclk_ext" is useless unless the board indicates it >>> provides the clock source. >>> >>> refclk_ext holds phandle for *fixed-clock*, so irrespective of whether the >>> board provides a clock or not, it can have that handle for configuring in >>> PRCM. >>> However if the board does not provide the clock source, configuring >>> refclk_ext >>> in PRCM is useless. >> >> I think what Nishant meant is that if "refclk_ext" is provided it means that >> the driver >> should use that over "dpll_ref_clock" so no need of a separate "ti,ext-clk" >> flag. > > yes, thank you for clarifying - it does indeed redundant to have > "ti,ext-clk". and apologies on being a little obscure in the comment. Irrespective of whether external reference clock is used or not, all DRA7 (apll) has an input for external reference clock (and also a PRCM register for programming it) and it has to be specified in dt no? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi,
On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote:
> On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I wrote:
>> Hi Nishant,
>>
>> On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote:
>>> On Thu, May 15, 2014 at 4:25 AM, Roger Quadros wrote:
>>>> On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote:
>>>>> Hi Nishanth,
>>>>>
>>>>> On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote:
>>>>>> On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I
>>>>>> wrote:
>>>>>>> Hi Roger,
>>>>>>>
>>>>>>> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote:
>>>>>>>> Hi Kishon,
>>>>>>>>
>>>>>>>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote:
>>>>>>>>> APLL used by PCIE phy can either use external clock as input or the
>>>>>>>>> clock
>>>>>>>>> from DPLL. Added support for the APLL to use external clock as input
>>>>>>>>> here.
>>>>>>>>>
>>>>>>>>> Cc: Rajendra Nayak
>>>>>>>>> Cc: Tero Kristo
>>>>>>>>> Cc: Paul Walmsley
>>>>>>>>> Signed-off-by: Kishon Vijay Abraham I
>>>>>>>>> ---
>>>>>>>>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++
>>>>>>>>> drivers/phy/phy-ti-pipe3.c | 75
>>>>>>>>> ++
>>>>>>>>> 2 files changed, 52 insertions(+), 27 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>>>>>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>>>>>>> index bc9afb5..d50f8ee 100644
>>>>>>>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>>>>>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
>>>>>>>>> @@ -76,6 +76,10 @@ Required properties:
>>>>>>>>> * "dpll_ref_m2" - external dpll ref clk
>>>>>>>>> * "phy-div" - divider for apll
>>>>>>>>> * "div-clk" - apll clock
>>>>>>>>> + * "apll_mux" - mux for pcie apll
>>>>>>>>> + * "refclk_ext" - external reference clock for pcie apll
>>>>>>>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock.
>>>>>>>>> Applicable
>>>>>>>>> + only to PCIE PHY.
>>>>>>>>
>>>>>>>> Instead of specifying both clock sources "dpll_ref_clock",
>>>>>>>> "refclk_ext" and then specifying a 3rd control option "ti,ext-clk" to
>>>>>>>> select one of the 2 sources, why can't the DT just supply one clock
>>>>>>>> source, i.e. the one that is being used in the board instance? The
>>>>>>>> driver should then just configure the clock rate that is needed at
>>>>>>>> that node. Shouldn't the clock framework automatically take care of
>>>>>>>> muxing and parent rates?
>>>>>>>
>>>>>>> Want the dt to have all the clocks used by the controller. "ti,ext-clk"
>>>>>>> should
>>>>>>> go in the board dt file (suggested by Nishanth).
>>>>>>> The point is at some point later if some one wants to change the clock
>>>>>>> source,
>>>>>>> it should be a simple enabling "ti,ext-clk" flag instead of finding the
>>>>>>> clock
>>>>>>> phandle etc..
>>>>>>
>>>>>> Wonder if that is implicit by the presence of "refclk_ext" in the
>>>>>> clocks provided?
>>>>>
>>>>> IMO the presence of "refclk_ext" is useless unless the board indicates it
>>>>> provides the clock source.
>>>>>
>>>>> refclk_ext holds phandle for *fixed-clock*, so irrespective of whether the
>>>>> board provides a clock or not, it can have that handle for configuring in
>>>>> PRCM.
>>>>> However if the board does not provide the clock source, configuring
>>>>> refclk_ext
>>>>> in PRCM is useless.
>>>>
>>>> I think what Nishant meant is that if "refclk_ext" is provided it means
>>>> that the driver
>>>> should use that over "dpll_ref_clock" so no need of a separate
>>>> "ti,ext-clk" flag.
>>>
>>> yes, thank you for clarifying - it does indeed redundant to have
>>> "ti,ext-clk". and apologies on being a little obscure in the comment.
>>
>> Irrespective of whether external reference clock is used or not, all DRA7
>> (apll) has an input for external reference clock (and also a PRCM register
>> for
>> programming it) and it has to be specified in dt no?
>
> Why is that a binding for ti-phy? that is a problem for the APLL clock
> driver (selecting it's own source). PHY properties should describe
> itself -> let the bindings of the APLL describe itself. please dont
> mix the two up.
The apll clock node is like this
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "mux-clock";
clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x4a00821c 0x4>;
bit-mask = <0x80>;
};
The external reference clock is denoted by *pciesref_acs_clk_ck*.
refclk_ext holds the phandle to *pciesref_acs_clk_ck* and is used in
"clk_set_parent" to set the parent of apll mux.
Thanks
Kishon
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Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi, On Thursday 15 May 2014 06:03 PM, Nishanth Menon wrote: > On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote: >>> On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I >>> wrote: >>>> Hi Nishant, >>>> >>>> On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote: >>>>> On Thu, May 15, 2014 at 4:25 AM, Roger Quadros wrote: >>>>>> On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote: >>>>>>> Hi Nishanth, >>>>>>> >>>>>>> On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote: >>>>>>>> On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I >>>>>>>> wrote: >>>>>>>>> Hi Roger, >>>>>>>>> >>>>>>>>> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote: >>>>>>>>>> Hi Kishon, >>>>>>>>>> >>>>>>>>>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote: >>>>>>>>>>> APLL used by PCIE phy can either use external clock as input or the >>>>>>>>>>> clock >>>>>>>>>>> from DPLL. Added support for the APLL to use external clock as >>>>>>>>>>> input here. >>>>>>>>>>> >>>>>>>>>>> Cc: Rajendra Nayak >>>>>>>>>>> Cc: Tero Kristo >>>>>>>>>>> Cc: Paul Walmsley >>>>>>>>>>> Signed-off-by: Kishon Vijay Abraham I >>>>>>>>>>> --- >>>>>>>>>>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++ >>>>>>>>>>> drivers/phy/phy-ti-pipe3.c | 75 >>>>>>>>>>> ++ >>>>>>>>>>> 2 files changed, 52 insertions(+), 27 deletions(-) >>>>>>>>>>> >>>>>>>>>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> index bc9afb5..d50f8ee 100644 >>>>>>>>>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> @@ -76,6 +76,10 @@ Required properties: >>>>>>>>>>> * "dpll_ref_m2" - external dpll ref clk >>>>>>>>>>> * "phy-div" - divider for apll >>>>>>>>>>> * "div-clk" - apll clock >>>>>>>>>>> + * "apll_mux" - mux for pcie apll >>>>>>>>>>> + * "refclk_ext" - external reference clock for pcie apll >>>>>>>>>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock. >>>>>>>>>>> Applicable >>>>>>>>>>> + only to PCIE PHY. >>>>>>>>>> >>>>>>>>>> Instead of specifying both clock sources "dpll_ref_clock", >>>>>>>>>> "refclk_ext" and then specifying a 3rd control option "ti,ext-clk" >>>>>>>>>> to select one of the 2 sources, why can't the DT just supply one >>>>>>>>>> clock source, i.e. the one that is being used in the board instance? >>>>>>>>>> The driver should then just configure the clock rate that is needed >>>>>>>>>> at that node. Shouldn't the clock framework automatically take care >>>>>>>>>> of muxing and parent rates? >>>>>>>>> >>>>>>>>> Want the dt to have all the clocks used by the controller. >>>>>>>>> "ti,ext-clk" should >>>>>>>>> go in the board dt file (suggested by Nishanth). >>>>>>>>> The point is at some point later if some one wants to change the >>>>>>>>> clock source, >>>>>>>>> it should be a simple enabling "ti,ext-clk" flag instead of finding >>>&
Re: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Hi Arnd,
On Wednesday 14 May 2014 06:15 PM, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 11:14:45 Kishon Vijay Abraham I wrote:
>> hi Arnd,
>>
>> On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
>>> On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
>>>> On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
>>>>>> If you have a case where the outbound translation is a 256MB (i.e. 28bit)
>>>>>> section of the CPU address space, that could be represented as
>>>>>>
>>>>>> ranges = <0x8200 0 0 0xb000 0 0x1000>;
>>>>>>
>>>>>> or
>>>>>>
>>>>>> ranges = <0x8200 0 0xb000 0xb000 0 0x1000>;
>>>>>>
>>>>>> depending on whether you want the BARs to be programmed using a low
>>>>>> address 0x0-0x0fff or an address matching the window
>>>>>> 0xb000-0xbfff.
>>>>>
>>>>> The problem is, for configuring the window starting at 0xb000, the ATU
>>>>> should be programmed 0x000 (the cpu address for it will be 0xb000
>>>>> though).
>>>>>
>>>>
>>>> Then use the first of the two?
>>>>
>>>
>>> To clarify: using <0x8200 0 0 0xb000 0 0x1000> will give you
>>> a mem_offset of 0xb000, which should work just fine for this case.
>>>
>>> What I don't understand is why the ATU cares about whether the outbound
>>> address is 0x000 or 0xb000 if it just decodes the lower 28 bit
>>> anyway. Did you mean that we have to program the BARs using low addresses
>>> regardless of what is programmed in the ATU? That would make more sense,
>>> and it also matches what I suggested.
>>
>> No, It's not like it decodes only the lower 28bits. The BARs is programmed
>> with
>> 32 bit value.
>>
>> My pcie dt node has
>> ranges = <0x0800 0 0x20001000 0x20001000 0 0x2000 /* CONFIG */
>>0x8100 0 0 0x20003000 0 0x0001 /* IO */
>>0x8200 0 0x20013000 0x20013000 0 0xffed000>; /* MEM */
>>
>> Consider MEM address space..
>>
>> Here both PCI address and CPU address is 0x20013000. So when there is a write
>> to cpu addr 0x20013000 [writel(virt_addr(0x20013000)], we want it to be
>> translated to PCI addr 0x20013000. So in 'ATU', we would expect *base* to be
>> programmed to *0x20013000* and target to be programmed to *0x20013000*. But
>> that's not the case for DRA7xx. For DRA7xx *base* should be programmed to
>> *0x0013000* and target should be programmed to *0x20013000*.
>
> Ok, got it, thanks for your patience.
>
> I think this would best be modeled as a separate bus node that contains the
> restriction, like this:
>
> / {
> #address-cells = <1>; // or <2> if you support > 4GB address space
> #size-cells = <1>;
>
> soc {
> #address-cells <1>;
> #size-cells = <1>;
> ranges;
> dma-ranges;
>
> ... // all normal devices
>
> axi@2000 {
> #size-cells = <1>;
> #address-cells = <1>;
> dma-ranges; // can access all 4GB outbound
> ranges = <0 0x2000 0x1000>; // 28-bit bus
>
> pci@0 {
> reg = <0x00x1000>, // internal regs
> <0x1000 0x2000>; // config space
The internal reg address space starts at 0x5100. By Using this <0
0x2000 0x1000>; as ranges, we are not able to get the memory resource
properly. Can we use multiple ranges? how do we specify which ranges the *reg*
property to use?
Btw I was using *simple-bus* as compatible to *axi*. Or should I create a new
*axi* driver to create the pcie memory resources myself?
Thanks
Kishon
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Re: [PATCH 03/17] phy: ti-pipe3: add external clock support for PCIe PHY
Hi, On Thursday 15 May 2014 06:03 PM, Nishanth Menon wrote: > On 05/15/2014 07:18 AM, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Thursday 15 May 2014 05:42 PM, Nishanth Menon wrote: >>> On Thu, May 15, 2014 at 6:59 AM, Kishon Vijay Abraham I >>> wrote: >>>> Hi Nishant, >>>> >>>> On Thursday 15 May 2014 05:16 PM, Nishanth Menon wrote: >>>>> On Thu, May 15, 2014 at 4:25 AM, Roger Quadros wrote: >>>>>> On 05/15/2014 12:15 PM, Kishon Vijay Abraham I wrote: >>>>>>> Hi Nishanth, >>>>>>> >>>>>>> On Wednesday 14 May 2014 09:04 PM, Nishanth Menon wrote: >>>>>>>> On Wed, May 14, 2014 at 10:19 AM, Kishon Vijay Abraham I >>>>>>>> wrote: >>>>>>>>> Hi Roger, >>>>>>>>> >>>>>>>>> On Wednesday 14 May 2014 06:46 PM, Roger Quadros wrote: >>>>>>>>>> Hi Kishon, >>>>>>>>>> >>>>>>>>>> On 05/06/2014 04:33 PM, Kishon Vijay Abraham I wrote: >>>>>>>>>>> APLL used by PCIE phy can either use external clock as input or the >>>>>>>>>>> clock >>>>>>>>>>> from DPLL. Added support for the APLL to use external clock as >>>>>>>>>>> input here. >>>>>>>>>>> >>>>>>>>>>> Cc: Rajendra Nayak >>>>>>>>>>> Cc: Tero Kristo >>>>>>>>>>> Cc: Paul Walmsley >>>>>>>>>>> Signed-off-by: Kishon Vijay Abraham I >>>>>>>>>>> --- >>>>>>>>>>> Documentation/devicetree/bindings/phy/ti-phy.txt |4 ++ >>>>>>>>>>> drivers/phy/phy-ti-pipe3.c | 75 >>>>>>>>>>> ++ >>>>>>>>>>> 2 files changed, 52 insertions(+), 27 deletions(-) >>>>>>>>>>> >>>>>>>>>>> diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> index bc9afb5..d50f8ee 100644 >>>>>>>>>>> --- a/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt >>>>>>>>>>> @@ -76,6 +76,10 @@ Required properties: >>>>>>>>>>> * "dpll_ref_m2" - external dpll ref clk >>>>>>>>>>> * "phy-div" - divider for apll >>>>>>>>>>> * "div-clk" - apll clock >>>>>>>>>>> + * "apll_mux" - mux for pcie apll >>>>>>>>>>> + * "refclk_ext" - external reference clock for pcie apll >>>>>>>>>>> + - ti,ext-clk: To specifiy if PCIE apll should use external clock. >>>>>>>>>>> Applicable >>>>>>>>>>> + only to PCIE PHY. >>>>>>>>>> >>>>>>>>>> Instead of specifying both clock sources "dpll_ref_clock", >>>>>>>>>> "refclk_ext" and then specifying a 3rd control option "ti,ext-clk" >>>>>>>>>> to select one of the 2 sources, why can't the DT just supply one >>>>>>>>>> clock source, i.e. the one that is being used in the board instance? >>>>>>>>>> The driver should then just configure the clock rate that is needed >>>>>>>>>> at that node. Shouldn't the clock framework automatically take care >>>>>>>>>> of muxing and parent rates? >>>>>>>>> >>>>>>>>> Want the dt to have all the clocks used by the controller. >>>>>>>>> "ti,ext-clk" should >>>>>>>>> go in the board dt file (suggested by Nishanth). >>>>>>>>> The point is at some point later if some one wants to change the >>>>>>>>> clock source, >>>>>>>>> it should be a simple enabling "ti,ext-clk" flag instead of finding >>>&
[PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on DRA7 SOCs. Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Kishon Vijay Abraham I --- arch/arm/mach-omap2/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index cb31d43..b179e80 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,6 +75,8 @@ config SOC_DRA7XX select ARM_GIC select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR + select MIGHT_HAVE_PCI + select ARCH_SUPPORTS_MSI config ARCH_OMAP2PLUS bool -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 15/18] ARM: dts: dra7: Add dt data for PCIe controller
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Cc: Bjorn Helgaas
Cc: Jingoo Han
Cc: Jason Gunthorpe
Cc: Marek Vasut
Cc: Arnd Bergmann
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 69 +++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index eaeccaf..1239f0d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1036,6 +1036,75 @@
};
};
+ axi@0 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x5100 0x5100 0x3000
+ 0x00x2000 0x1000>;
+ pcie@5100 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x5100 0x2000>, <0x51002000 0x14c>,
<0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x03000 0
0x0001
+ 0x8200 0 0x20013000 0x13000 0
0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 1>,
+ <0 0 0 2 &pcie1_intc 2>,
+ <0 0 0 3 &pcie1_intc 3>,
+ <0 0 0 4 &pcie1_intc 4>;
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ axi@1 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x5180 0x5180 0x3000
+ 0x00x3000 0x1000>;
+ status = "disabled";
+ pcie@5100 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x5180 0x2000>, <0x51802000 0x14c>,
<0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 355 0x4>, <0 356 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x03000 0
0x0001
+ 0x8200 0 0x30013000 0x13000 0
0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie2";
+ phys = <&pcie2_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 1>,
+ <0 0 0 2 &pcie2_intc 2>,
+ <0 0 0 3 &pcie2_intc 3>,
+ <0 0 0 4 &pcie2_intc 4>;
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+
[TEMP PATCH v2 18/18] ARM: dts: dra7: Add *resets* property for PCIe dt node
Added *resets* and *reset-names* properies for PCIe dt node. The documention for this node can be found @ ../bindings/pci/ti-pci.txt. Cc: Dan Murphy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1239f0d..03494b2 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1055,6 +1055,8 @@ #interrupt-cells = <1>; num-lanes = <1>; ti,hwmods = "pcie1"; + resets = <&prm_resets &device_reset>; + reset-names = "reset"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; interrupt-map-mask = <0 0 0 7>; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[TEMP PATCH v2 17/18] PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe
Get reset nodes from dt and use reset framework APIs to reset PCIe.
This is needed since reset is handled by the SoC.
Cc: Dan Murphy
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt |4
drivers/pci/host/pci-dra7xx.c| 10 ++
2 files changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index d07d2eb..3649c2e 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -22,6 +22,8 @@ PCIe Designware Controller
num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+ - resets: phandle used if reset is handled be soc
+ - reset-names: name given to the phandle
Example:
axi {
@@ -45,6 +47,8 @@ axi {
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
+ resets = <&prm_resets &device_reset>;
+ reset-names = "reset";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 1>,
<0 0 0 2 &pcie_intc 2>,
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 8fb3a2e..17f5e6a 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include "pcie-designware.h"
@@ -332,6 +333,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
char name[10];
+ struct reset_control *rstc;
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -355,6 +357,14 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
if (!base)
return -ENOMEM;
+ rstc = devm_reset_control_get(dev, "reset");
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ return ret;
+
phy_count = of_property_count_strings(np, "phy-names");
if (phy_count < 0) {
dev_err(dev, "unable to find the strings\n");
--
1.7.9.5
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[PATCH v2 12/18] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e1bd052..3d8c9c2 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,7 +1165,7 @@
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ optfclk_pciephy1_32khz: optfclk_pciephy_32khz@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
@@ -1183,7 +1183,7 @@
ti,max-div = <2>;
};
- optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ optfclk_pciephy1_clk: optfclk_pciephy_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
@@ -1191,7 +1191,7 @@
ti,bit-shift = <9>;
};
- optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
--
1.7.9.5
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[PATCH v2 14/18] ARM: dts: dra7: Add dt data for PCIe PHY
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3c7e7f2..eaeccaf 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -912,6 +912,45 @@
clock-names = "sysclk";
#phy-cells = <0>;
};
+
+ pcie1_phy: pciephy@4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4A094000 0x80>, /* phy_rx */
+ <0x4A094400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+<&dpll_pcie_ref_m2ldo_ck>,
+<&optfclk_pciephy1_32khz>,
+<&optfclk_pciephy1_clk>,
+<&optfclk_pciephy1_div_clk>,
+<&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ ti,hwmods = "pcie1-phy";
+ };
+
+ pcie2_phy: pciephy@4a095000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4A095000 0x80>, /* phy_rx */
+ <0x4A095400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+<&dpll_pcie_ref_m2ldo_ck>,
+<&optfclk_pciephy2_32khz>,
+<&optfclk_pciephy2_clk>,
+<&optfclk_pciephy2_div_clk>,
+<&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ ti,hwmods = "pcie2-phy";
+ status = "disabled";
+ };
};
omap_dwc3_1@4888 {
--
1.7.9.5
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[PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3d8c9c2..a9ff0dc 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1173,6 +1173,14 @@
ti,bit-shift = <8>;
};
+ optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@@ -1191,6 +1199,14 @@
ti,bit-shift = <9>;
};
+ optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <9>;
+ };
+
optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
@@ -1199,6 +1215,14 @@
ti,bit-shift = <10>;
};
+ optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b4>;
+ ti,bit-shift = <10>;
+ };
+
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
--
1.7.9.5
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[PATCH v2 11/18] ARM: dts: dra7: Add dt data for PCIe PHY control module
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f0ca46d..3c7e7f2 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -803,6 +803,23 @@
status = "disabled";
};
+ omap_control_pcie1phy: omap-control-pciephy@0x4a003c40 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34
0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ omap_control_pcie2phy: omap-control-pciephy@0x4a003c44 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34
0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ status = "disabled";
+ };
+
omap_control_usb2phy1: control-phy@4a002300 {
compatible = "ti,control-phy-usb2";
reg = <0x4a002300 0x4>;
--
1.7.9.5
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[PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for programming
the outbound translation window the *base* should be programmed as 0x000_.
Whenever we try to write to say 0x2000_, it will be translated to whatever
we have programmed in the translation window with base as 0x000_.
This is needed when the dt node is modelled something like below
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x00x2000 0x1000 // 28-bit bus
0x5100 0x5100 0x3000>;
pcie@5100 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x5100 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x8100 0 0 0x03000 0 0x0001
0x8200 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the controller
address for configuration space is 0x13000. The controller address should be
used while programming the ATU (in order for translation to happen properly in
DRA7xx).
Cc: Jason Gunthorpe
Cc: Bjorn Helgaas
Cc: Mohit Kumar
Cc: Jingoo Han
Cc: Marek Vasut
Cc: Arnd Bergmann
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/host/pcie-designware.c | 49
drivers/pci/host/pcie-designware.h |4 +++
2 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 603b386..9dfd2d4 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -397,8 +397,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
struct of_pci_range range;
struct of_pci_range_parser parser;
struct resource *cfg_res;
- u32 val;
- int i;
+ u32 val, na, ns;
+ const __be32 *addrp;
+ int i, index;
+
+ /* Find the address cell size and the number of cells in order to get
+* the untranslated address.
+*/
+ of_property_read_u32(np, "#address-cells", &na);
+ ns = of_n_size_cells(np);
cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
if (cfg_res) {
@@ -406,6 +413,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp->config.cfg1_size = resource_size(cfg_res)/2;
pp->cfg0_base = cfg_res->start;
pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
+
+ /* Find the untranslated configuration space address */
+ index = of_property_match_string(np, "reg-names", "config");
+ addrp = of_get_address(np, index, false, false);
+ pp->cfg0_mod_addr = of_read_number(addrp, ns);
+ pp->cfg1_mod_addr = pp->cfg0_mod_addr + pp->config.cfg0_size;
} else {
dev_err(pp->dev, "missing *config* reg space\n");
}
@@ -431,12 +444,20 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp->config.io_size = resource_size(&pp->io);
pp->config.io_bus_addr = range.pci_addr;
pp->io_base = range.cpu_addr;
+
+ /* Find the untranslated IO space address */
+ pp->io_mod_addr = of_read_number(parser.range -
+parser.np + na, ns);
}
if (restype == IORESOURCE_MEM) {
of_pci_range_to_resource(&range, np, &pp->mem);
pp->mem.name = "MEM";
pp->config.mem_size = resource_size(&pp->mem);
pp->config.mem_bus_addr = range.pci_addr;
+
+ /* Find the untranslated MEM space address */
+ pp->mem_mod_addr = of_read_number(parser.range -
+ parser.np + na, ns);
}
if (restype == 0) {
of_pci_range_to_resource(&range, np, &pp->cfg);
@@ -444,6 +465,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
pp->config.cfg1_size = resource_size(&pp->cfg)/2;
p
[PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Cc: Tony Lindgren
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Kumar Gala
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 44993ec..e1bd052 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
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[PATCH v2 09/18] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren
Cc: Russell King
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 1282a42..a51fa7f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2388,6 +2425,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2751,6 +2804,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
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[PATCH v2 08/18] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren
Cc: Russell King
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch/arm/mach-omap2/prm7xx.h |4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b9bb476..1282a42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = "pcie1-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = "pcie2-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b30,
@@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_
[PATCH v2 05/18] PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Cc: Jason Gunthorpe
Cc: Bjorn Helgaas
Cc: Mohit Kumar
Cc: Jingoo Han
Cc: Marek Vasut
Cc: Arnd Bergmann
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 59 +++
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile|1 +
drivers/pci/host/pci-dra7xx.c| 460 ++
4 files changed, 530 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt
create mode 100644 drivers/pci/host/pci-dra7xx.c
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
new file mode 100644
index 000..d07d2eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -0,0 +1,59 @@
+TI PCI Controllers
+
+PCIe Designware Controller
+ - compatible: Should be "ti,dra7-pcie""
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ The second entry must be "rc-dbics" for the designware pcie
+ registers
+ The third entry must be "config" for the PCIe configurationspace
+ - phys : list of PHY specifiers (used by generic PHY framework)
+ - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of PHYs as specified in *phys* property.
+ - ti,hwmods : Name of the hwmod associated to the pcie, "pcie",
+ where is the instance number of the pcie from the HW spec.
+ - interrupts : Two interrupt entries must be specified. The first one is for
+ main interrupt line and the second for MSI interrupt line.
+ - #address-cells,
+ #size-cells,
+ #interrupt-cells,
+ device_type,
+ ranges,
+ num-lanes,
+ interrupt-map-mask,
+ interrupt-map : as specified in ../designware-pcie.txt
+
+Example:
+axi {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x5100 0x5100 0x3000
+ 0x00x2000 0x1000>;
+ pcie@5100 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x5100 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8100 0 0 0x03000 0 0x0001
+ 0x8200 0 0x20013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 1>,
+ <0 0 0 2 &pcie_intc 2>,
+ <0 0 0 3 &pcie_intc 3>,
+ <0 0 0 4 &pcie_intc 4>;
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a6f67ec..58ccb414 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -1,6 +1,16 @@
menu "PCI host controller drivers"
depends on PCI
+config PCI_DRA7XX
+ bool "TI DRA7xx PCIe controller"
+ select PCIE_DW
+ depends on OF && HAS_IOMEM && TI_PIPE3
+ help
+Enables support for the PCIE controller present in DRA7xx SoC. There
+are two instances of PCIE controller in DRA7xx. This controller can
+act both as EP and RC. This reuses the same Designware core as used
+by other SoCs.
+
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..5216f55 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-dra7xx.
[PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
From: Keerthy
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Cc: Rajendra Nayak
Cc: Tero Kristo
Cc: Paul Walmsley
Signed-off-by: Keerthy
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 55e95c5..44993ec 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
- clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
--
1.7.9.5
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[PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
space in the designware driver.
Cc: Jason Gunthorpe
Cc: Bjorn Helgaas
Cc: Mohit Kumar
Cc: Jingoo Han
Cc: Marek Vasut
Cc: Arnd Bergmann
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/designware-pcie.txt|1 +
drivers/pci/host/pcie-designware.c | 17 +++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d6fae13..8314360 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ The configuration address space should also be specified here.
- interrupts: interrupt values for level interrupt,
pulse interrupt, special interrupt.
- clocks: from common clock binding: handle to pci clock.
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c4e3732..603b386 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include "pcie-designware.h"
@@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
int __init dw_pcie_host_init(struct pcie_port *pp)
{
struct device_node *np = pp->dev->of_node;
+ struct platform_device *pdev = to_platform_device(pp->dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
+ struct resource *cfg_res;
u32 val;
int i;
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+ if (cfg_res) {
+ pp->config.cfg0_size = resource_size(cfg_res)/2;
+ pp->config.cfg1_size = resource_size(cfg_res)/2;
+ pp->cfg0_base = cfg_res->start;
+ pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
+ } else {
+ dev_err(pp->dev, "missing *config* reg space\n");
+ }
+
if (of_pci_range_parser_init(&parser, np)) {
dev_err(pp->dev, "missing ranges property\n");
return -EINVAL;
@@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
of_pci_range_to_resource(&range, np, &pp->cfg);
pp->config.cfg0_size = resource_size(&pp->cfg)/2;
pp->config.cfg1_size = resource_size(&pp->cfg)/2;
+ pp->cfg0_base = pp->cfg.start;
+ pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
}
}
@@ -441,8 +456,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
}
}
- pp->cfg0_base = pp->cfg.start;
- pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
pp->mem_base = pp->mem.start;
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
--
1.7.9.5
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[PATCH v2 01/18] phy: phy-omap-pipe3: Add support for PCIe PHY
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Roger Quadros
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c | 99 +-
2 files changed, 84 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 9ce458f..cf3de7e 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -56,8 +56,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".
- "ti,omap-usb3" is deprecated.
+ - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
+ "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in "reg".
@@ -69,6 +69,10 @@ Required properties:
* "wkupclk" - wakeup clock.
* "sysclk" - system clock.
* "refclk" - reference clock.
+ * "dpll_ref" - external dpll ref clk
+ * "dpll_ref_m2" - external dpll ref clk
+ * "phy-div" - divider for apll
+ * "div-clk" - apll clock
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 5913676..d43019d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -80,6 +80,7 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
};
@@ -215,6 +216,9 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
+ return 0;
+
/* Bring it out of IDLE if it is IDLE */
val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
if (val & PLL_IDLE) {
@@ -238,8 +242,11 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
- /* SATA DPLL can't be powered down due to Errata i783 */
- if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
+ /* SATA DPLL can't be powered down due to Errata i783 and PCIe
+* does not have internal DPLL
+*/
+ if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
+ of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
return 0;
/* Put DPLL in IDLE mode */
@@ -286,32 +293,41 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *control_node;
struct platform_device *control_pdev;
const struct of_device_id *match;
-
- match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
- if (!match)
- return -EINVAL;
+ struct clk *clk;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
return -ENOMEM;
}
+ phy->dev= &pdev->dev;
- phy->dpll_map = (struct pipe3_dpll_map *)match->data;
- if (!phy->dpll_map) {
- dev_err(&pdev->dev, "no DPLL data\n");
- return -EINVAL;
- }
+ if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table),
+ &pdev->dev);
+ if (!match)
+ return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
- phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(phy->pll_ctrl_base))
- return PTR_ERR(phy->pll_ctrl_base);
+ phy->dpll_map = (struct pipe3_dpll_map *)match->data;
+ if (!phy->dpll_map) {
+ dev_err(&pdev->dev, "no DPLL data\n");
+ return -EINVAL;
+ }
- phy->dev= &pdev->dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "pll_ctrl");
+ phy->
[PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock
From: Keerthy Add divider table to optfclk_pciephy_div clock. The Documentation for divider clock can be found at ../clock/ti/divider.txt Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c767687..55e95c5 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; }; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 00/18] PCIe support for DRA7xx
This patch series adds support for PCIe in DRA7xx including drivers and dt data. PCIe in DRA7xx uses desingware IP and hence this re-uses the pcie desingware driver (pcie-designware.c) by Jingoo. The last couple of patches are marked as *TEMP* since the TI reset driver [1] is not yet merged and is in RFC. Tested broadcom PCIe card and XIO2000 bridge along with DGE530T ethernet card. Changes from v1: * removed external clock support fro APLL since the clock framework patches are still in RFC. * The configuration address space should be given in *reg* and made the corresponding driver changes in pcie-designware.c * Used untraslated address while programming ATU since that is needed for DRA7. With this PCIe should be made the child node of axi. * Used a new irq domain for PCIe legacy interrupts. * Added clocks and dt data for the second instance of PCIe controller (with status = disabled). Changes from RFC: * Added external clock support for PCIE APLL * Miscellaneous cleanups in Documentation, macro naming etc.. [1] -> http://www.spinics.net/lists/linux-omap/msg106411.html Keerthy (2): ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I (16): phy: phy-omap-pipe3: Add support for PCIe PHY phy: pipe3: insert delay to enumerate in GEN2 mode PCI: designware: Configuration space should be specified in 'reg' PCI: designware: use untranslated address while programming ATU PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY ARM: dts: dra7: Add dt data for PCIe PHY control module ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance ARM: dts: dra7: Add dt data for PCIe PHY ARM: dts: dra7: Add dt data for PCIe controller ARM: OMAP: Enable PCI for DRA7 PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe ARM: dts: dra7: Add *resets* property for PCIe dt node .../devicetree/bindings/pci/designware-pcie.txt|1 + Documentation/devicetree/bindings/pci/ti-pci.txt | 63 +++ Documentation/devicetree/bindings/phy/ti-phy.txt | 20 +- arch/arm/boot/dts/dra7.dtsi| 127 ++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 39 +- arch/arm/mach-omap2/Kconfig|2 + arch/arm/mach-omap2/cm2_7xx.h |4 + arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 + arch/arm/mach-omap2/prm7xx.h |4 + drivers/pci/host/Kconfig | 10 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-dra7xx.c | 470 drivers/pci/host/pcie-designware.c | 66 ++- drivers/pci/host/pcie-designware.h |4 + drivers/phy/phy-omap-control.c | 52 ++- drivers/phy/phy-ti-pipe3.c | 101 - include/linux/phy/omap_control_phy.h | 10 + 17 files changed, 1041 insertions(+), 45 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti-pci.txt create mode 100644 drivers/pci/host/pci-dra7xx.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 02/18] phy: pipe3: insert delay to enumerate in GEN2 mode
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated
consistently. Added an API to be called from PHY drivers to set this delay
value and called it from PIPE3 driver to set the delay value.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Roger Quadros
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++---
drivers/phy/phy-omap-control.c | 52 +-
drivers/phy/phy-ti-pipe3.c |4 +-
include/linux/phy/omap_control_phy.h | 10 +
4 files changed, 71 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cf3de7e..36bb6c9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,15 +9,17 @@ Required properties:
e.g. USB2_PHY on OMAP5.
"ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
+ "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
+ set PCS delay value.
+ e.g. PCIE PHY in DRA7x
"ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
DRA7 platform.
"ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of "otghs_control" for control-phy-otghs or "power" register
- for other types.
- - reg-names: should be "otghs_control" control-phy-otghs and "power" for
- other types.
+ - reg : register ranges as listed in the reg-names property
+ - reg-names: "otghs_control" for control-phy-otghs
+ "power", "pcie_pcs" and "control_sma" for control-phy-pcie
+ "power" for all other types
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,control-phy-otghs";
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 311b4f9..9487bf1 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -27,6 +27,41 @@
#include
/**
+ * omap_control_pcie_pcs - set the PCS delay count
+ * @dev: the control module device
+ * @id: index of the pcie PHY (should be 1 or 2)
+ * @delay: 8 bit delay value
+ */
+void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
+{
+ u32 val;
+ struct omap_control_phy *control_phy;
+
+ if (IS_ERR(dev) || !dev) {
+ pr_err("%s: invalid device\n", __func__);
+ return;
+ }
+
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, "%s: invalid control phy device\n", __func__);
+ return;
+ }
+
+ if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
+ dev_err(dev, "%s: unsupported operation\n", __func__);
+ return;
+ }
+
+ val = readl(control_phy->pcie_pcs);
+ val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
+ (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
+ val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
+ writel(val, control_phy->pcie_pcs);
+}
+EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
+
+/**
* omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
@@ -61,6 +96,7 @@ void omap_control_phy_power(struct device *dev, int on)
val |= OMAP_CTRL_DEV_PHY_PD;
break;
+ case OMAP_CTRL_TYPE_PCIE:
case OMAP_CTRL_TYPE_PIPE3:
rate = clk_get_rate(control_phy->sys_clk);
rate = rate/100;
@@ -211,6 +247,7 @@ EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
+static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
static const enum omap_control_phy_type dra7usb2_data =
OMAP_CTRL_TYPE_DRA7USB2;
static const enum omap_control_phy_type am437usb2_data =
OMAP_CTRL_TYPE_AM437USB2;
@@ -228,6 +265,10 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = &pipe3_data,
},
{
+ .compatible = "ti,control-phy-pcie",
+ .data = &pcie_data,
+ },
+ {
.compatible = "ti,control-phy-usb2-dra7",
.data
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hi,
On Thursday 29 May 2014 12:41 PM, Mohit KUMAR DCG wrote:
> Hello Kishon,
>
>> -Original Message-----
>> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
>> Sent: Thursday, May 29, 2014 12:08 PM
>> To: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
>> ker...@lists.infradead.org; linux-omap@vger.kernel.org; linux-
>> p...@vger.kernel.org; linux-ker...@vger.kernel.org
>> Cc: a...@arndb.de; t...@atomide.com; jg1@samsung.com;
>> kis...@ti.com; Jason Gunthorpe; Bjorn Helgaas; Mohit KUMAR DCG; Marek
>> Vasut
>> Subject: [PATCH v2 03/18] PCI: designware: Configuration space should be
>> specified in 'reg'
>>
>> The configuration address space has so far been specified in *ranges*,
>> however it should be specified in *reg* making it a platform MEM resource.
>> Hence used 'platform_get_resource_*' API to get configuration address
>> space in the designware driver.
>>
>> Cc: Jason Gunthorpe
>> Cc: Bjorn Helgaas
>> Cc: Mohit Kumar
>> Cc: Jingoo Han
>> Cc: Marek Vasut
>> Cc: Arnd Bergmann
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> .../devicetree/bindings/pci/designware-pcie.txt|1 +
>> drivers/pci/host/pcie-designware.c | 17 +++--
>> 2 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> index d6fae13..8314360 100644
>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> @@ -6,6 +6,7 @@ Required properties:
>> as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
>> - reg: base addresses and lengths of the pcie controller,
>> the phy controller, additional register for the phy controller.
>> +The configuration address space should also be specified here.
>> - interrupts: interrupt values for level interrupt,
>> pulse interrupt, special interrupt.
>> - clocks: from common clock binding: handle to pci clock.
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-
>> designware.c
>> index c4e3732..603b386 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -20,6 +20,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>>
>> #include "pcie-designware.h"
>> @@ -392,11 +393,23 @@ static const struct irq_domain_ops
>> msi_domain_ops = { int __init dw_pcie_host_init(struct pcie_port *pp) {
>> struct device_node *np = pp->dev->of_node;
>> +struct platform_device *pdev = to_platform_device(pp->dev);
>> struct of_pci_range range;
>> struct of_pci_range_parser parser;
>> +struct resource *cfg_res;
>> u32 val;
>> int i;
>>
>> +cfg_res = platform_get_resource_byname(pdev,
>> IORESOURCE_MEM, "config");
>> +if (cfg_res) {
>> +pp->config.cfg0_size = resource_size(cfg_res)/2;
>> +pp->config.cfg1_size = resource_size(cfg_res)/2;
>> +pp->cfg0_base = cfg_res->start;
>> +pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
>> +} else {
>> +dev_err(pp->dev, "missing *config* reg space\n");
>> +}
>> +
>> if (of_pci_range_parser_init(&parser, np)) {
>> dev_err(pp->dev, "missing ranges property\n");
>> return -EINVAL;
>> @@ -429,6 +442,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>> of_pci_range_to_resource(&range, np, &pp->cfg);
>> pp->config.cfg0_size = resource_size(&pp->cfg)/2;
>> pp->config.cfg1_size = resource_size(&pp->cfg)/2;
>> +pp->cfg0_base = pp->cfg.start;
>> +pp->cfg1_base = pp->cfg.start + pp-
>>> config.cfg0_size;
>
> - As you are getting cfg address space as MEM resource, so remove above code
> that
> gets the configuration space from dt range. Also correct dt for pcie cfg
> space for the platforms
> based on this driver.
Ok. Will send that as a separate patch converting all platforms to use MEM
resource.
Thanks
Kishon
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Re: [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7
Hi,
On Thursday 29 May 2014 12:18 PM, Jingoo Han wrote:
> On Thursday, May 29, 2014 3:38 PM, Kishon Vijay Abraham I wrote:
>>
>> Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
>> DRA7 SOCs.
>>
>> Cc: Tony Lindgren
>> Cc: Rob Herring
>> Cc: Pawel Moll
>> Cc: Mark Rutland
>> Cc: Kumar Gala
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/mach-omap2/Kconfig |2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>> index cb31d43..b179e80 100644
>> --- a/arch/arm/mach-omap2/Kconfig
>> +++ b/arch/arm/mach-omap2/Kconfig
>> @@ -75,6 +75,8 @@ config SOC_DRA7XX
>> select ARM_GIC
>> select HAVE_ARM_ARCH_TIMER
>> select IRQ_CROSSBAR
>> +select MIGHT_HAVE_PCI
>> +select ARCH_SUPPORTS_MSI
>
> Hi Kishon,
>
> Please, don't select ARCH_SUPPORTS_MSI, because this kconfig
> option was already removed in v3.12 by the commit ebd97be635
> ('PCI: remove ARCH_SUPPORTS_MSI kconfig option'). So, there is
> NO need to select 'ARCH_SUPPORTS_MSI'.
Thanks for spotting it. Will remove it.
Thanks
Kishon
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hi,
On Thursday 29 May 2014 10:02 PM, Murali Karicheri wrote:
> On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
>> The configuration address space has so far been specified in *ranges*,
>> however it should be specified in *reg* making it a platform MEM resource.
>> Hence used 'platform_get_resource_*' API to get configuration address
>> space in the designware driver.
>>
>> Cc: Jason Gunthorpe
>> Cc: Bjorn Helgaas
>> Cc: Mohit Kumar
>> Cc: Jingoo Han
>> Cc: Marek Vasut
>> Cc: Arnd Bergmann
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> .../devicetree/bindings/pci/designware-pcie.txt|1 +
>> drivers/pci/host/pcie-designware.c | 17 +++--
>> 2 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> index d6fae13..8314360 100644
>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>> @@ -6,6 +6,7 @@ Required properties:
>> as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
>> - reg: base addresses and lengths of the pcie controller,
>> the phy controller, additional register for the phy controller.
>> +The configuration address space should also be specified here.
> Kishon,
>
> I am working on the Keystone PCI driver for which v1 is already posted. Want
> to
> clarify
> following.
> 1. Original text for reg states "base addresses and lengths of the pcie
> controller,
> the phy controller, additional register for the phy controller" and
> you
> added
> "The configuration address space should also be specified here"
>
>and the code below added resource name "config"
>
> Does PCI designware follow some convention? Does it mean after applying this
> patch
> config name is mandatory or optional? Below code you are not returning error.
> Can you
> or author of PCI designware clarify what is expected to be present as
> mandatory
> and
> what is optional.
>From whatever I could make out from the comments for my previous version,
'config' is mandatory for all new platforms adding support for PCIe DW. However
since there already exists platforms that use 'ranges', I'm not returning
error. Once all the platforms that use DW is modified to use 'reg', will return
error.
>
> Does config refers to RC's config space or EP's config space or both? The code
> below divide
In the case of DRA7, it's the space from where you read the configuration space
contents of the EP (we have separate address space for the configuration space
of RC denoted by *rc_dbics* in this patch series). But there are other
platforms where RC does not have a separate configuration address space.
> the size by 2. So it appears to be RC's + EP's config space. Please clarify.
No. divide by 2 is for cfg1 and cfg1 is used by PCIe bridges.
>
>> - interrupts: interrupt values for level interrupt,
>> pulse interrupt, special interrupt.
>> - clocks: from common clock binding: handle to pci clock.
>> diff --git a/drivers/pci/host/pcie-designware.c
>> b/drivers/pci/host/pcie-designware.c
>> index c4e3732..603b386 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -20,6 +20,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include "pcie-designware.h"
>> @@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
>> int __init dw_pcie_host_init(struct pcie_port *pp)
>> {
>> struct device_node *np = pp->dev->of_node;
>> +struct platform_device *pdev = to_platform_device(pp->dev);
>> struct of_pci_range range;
>> struct of_pci_range_parser parser;
>> +struct resource *cfg_res;
>> u32 val;
>> int i;
>> +cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> "config");
>> +if (cfg_res) {
>> +pp->config.cfg0_size = resource_size(cfg_res)/2;
>> +pp->config.cfg1_size = resource_size(cfg_res)/2;
>> +pp->cfg0_base = cfg_res->start;
>> +pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
>> +} else {
>> +dev_err(pp->dev, "missing *config* reg space\n");
> This should return error -EINVAL.
ah.. it'll brea
Re: usb: musb: omap: Add device tree support for omap musb glue
Hi, On Wednesday 11 June 2014 12:32 AM, Dan Carpenter wrote: > Hello Kishon Vijay Abraham I, > > The patch 00a0b1d58af873d8: "usb: musb: omap: Add device tree support > for omap musb glue", from Sep 11 2012, leads to the following static > checker warning: > > drivers/usb/musb/omap2430.c:569 omap2430_probe() > warn: does endianness matter for 'config->num_eps'? > > drivers/usb/musb/omap2430.c >565 >566 of_property_read_u32(np, "mode", (u32 *)&pdata->mode); >567 of_property_read_u32(np, "interface-type", >568 (u32 > *)&data->interface_type); >569 of_property_read_u32(np, "num-eps", (u32 > *)&config->num_eps); > > ^^^ > > This is not endian safe, but more importantly ->num_eps is a u8 so when > we write 32 bits to it, we are corrupting ->dma_channels, > ->dyn_fifo_size, and ->vendor_ctrl. On little endian, it's going to be > setting them to zero so it might not cause and immediate problem. > > The way to do this is to use a 32 bit temporary variable and then save > the value to ->num_eps afterward. Create a small function to do this in > a nice way. Sure. Will do it. Thanks Kishon > > All the casts here are a bit scary. > >570 of_property_read_u32(np, "ram-bits", (u32 > *)&config->ram_bits); >571 of_property_read_u32(np, "power", (u32 > *)&pdata->power); > > regards, > dan carpenter > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU
Hi Arnd,
On Thursday 29 May 2014 12:08 PM, Kishon Vijay Abraham I wrote:
> In DRA7, the cpu sees 32bit address, but the pcie controller can see only
> 28bit
> address. So whenever the cpu issues a read/write request, the 4 most
> significant bits are used by L3 to determine the target controller.
> For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller
> but
> the PCIe controller will see only (0x000_ - 0xFFF_FFF). So for programming
> the outbound translation window the *base* should be programmed as 0x000_.
> Whenever we try to write to say 0x2000_, it will be translated to whatever
> we have programmed in the translation window with base as 0x000_.
>
> This is needed when the dt node is modelled something like below
> axi {
> compatible = "simple-bus";
> #size-cells = <1>;
> #address-cells = <1>;
> ranges = <0x00x2000 0x1000 // 28-bit bus
> 0x5100 0x5100 0x3000>;
> pcie@5100 {
> reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x5100 0x2000>;
> reg-names = "config", "ti_conf", "rc_dbics";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x8100 0 0 0x03000 0 0x0001
> 0x8200 0 0x20013000 0x13000 0 0xffed000>;
> };
> };
>
> Here the CPU address for configuration space is 0x20013000 and the controller
> address for configuration space is 0x13000. The controller address should be
> used while programming the ATU (in order for translation to happen properly in
> DRA7xx).
I've fixed this up with what you suggested in the v1 of the series. Do you
think this is fine?
Thanks
Kishon
>
> Cc: Jason Gunthorpe
> Cc: Bjorn Helgaas
> Cc: Mohit Kumar
> Cc: Jingoo Han
> Cc: Marek Vasut
> Cc: Arnd Bergmann
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/pci/host/pcie-designware.c | 49
>
> drivers/pci/host/pcie-designware.h |4 +++
> 2 files changed, 42 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c
> b/drivers/pci/host/pcie-designware.c
> index 603b386..9dfd2d4 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -397,8 +397,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> struct of_pci_range range;
> struct of_pci_range_parser parser;
> struct resource *cfg_res;
> - u32 val;
> - int i;
> + u32 val, na, ns;
> + const __be32 *addrp;
> + int i, index;
> +
> + /* Find the address cell size and the number of cells in order to get
> + * the untranslated address.
> + */
> + of_property_read_u32(np, "#address-cells", &na);
> + ns = of_n_size_cells(np);
>
> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> if (cfg_res) {
> @@ -406,6 +413,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> pp->config.cfg1_size = resource_size(cfg_res)/2;
> pp->cfg0_base = cfg_res->start;
> pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
> +
> + /* Find the untranslated configuration space address */
> + index = of_property_match_string(np, "reg-names", "config");
> + addrp = of_get_address(np, index, false, false);
> + pp->cfg0_mod_addr = of_read_number(addrp, ns);
> + pp->cfg1_mod_addr = pp->cfg0_mod_addr + pp->config.cfg0_size;
> } else {
> dev_err(pp->dev, "missing *config* reg space\n");
> }
> @@ -431,12 +444,20 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> pp->config.io_size = resource_size(&pp->io);
> pp->config.io_bus_addr = range.pci_addr;
> pp->io_base = range.cpu_addr;
> +
> + /* Find the untranslated IO space address */
> + pp->io_mod_addr = of_read_number(parser.range -
> + parser.np + na, ns);
> }
> if (restype == IORESOURCE_MEM) {
> of_pci_range_to_resource(&range, np, &pp->mem);
> pp->mem.name = "MEM";
> pp->config.mem_size = resource_size(&pp->mem);
> pp->config.mem_bus_addr = range.pci_addr;
> +
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
Hi,
On Friday 30 May 2014 07:45 PM, Karicheri, Muralidharan wrote:
>> -Original Message-
>> From: Murali Karicheri [mailto:m-kariche...@ti.com]
>> Sent: Thursday, May 29, 2014 12:32 PM
>> To: ABRAHAM, KISHON VIJAY
>> Cc: devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
>> ker...@lists.infradead.org; linux-omap@vger.kernel.org;
>> linux-...@vger.kernel.org; linux-
>> ker...@vger.kernel.org; a...@arndb.de; t...@atomide.com; jg1@samsung.com;
>> Jason Gunthorpe; Bjorn Helgaas; Mohit Kumar; Marek Vasut
>> Subject: Re: [PATCH v2 03/18] PCI: designware: Configuration space should be
>> specified
>> in 'reg'
>>
>> On 5/29/2014 2:38 AM, ABRAHAM, KISHON VIJAY wrote:
>>> The configuration address space has so far been specified in *ranges*,
>>> however it should be specified in *reg* making it a platform MEM resource.
>>> Hence used 'platform_get_resource_*' API to get configuration address
>>> space in the designware driver.
>>>
>>> Cc: Jason Gunthorpe
>>> Cc: Bjorn Helgaas
>>> Cc: Mohit Kumar
>>> Cc: Jingoo Han
>>> Cc: Marek Vasut
>>> Cc: Arnd Bergmann
>>> Signed-off-by: Kishon Vijay Abraham I
>>> ---
>>> .../devicetree/bindings/pci/designware-pcie.txt|1 +
>>> drivers/pci/host/pcie-designware.c | 17
>>> +++--
>>> 2 files changed, 16 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> index d6fae13..8314360 100644
>>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>> @@ -6,6 +6,7 @@ Required properties:
>>> as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
>>> - reg: base addresses and lengths of the pcie controller,
>>> the phy controller, additional register for the phy controller.
>>> + The configuration address space should also be specified here.
>> Kishon,
>>
>> I am working on the Keystone PCI driver for which v1 is already posted.
>> Want to clarify
>> following.
>> 1. Original text for reg states "base addresses and lengths of the pcie
>> controller,
>> the phy controller, additional register for the phy controller"
>> and you added
>> "The configuration address space should also be specified here"
>>
>>and the code below added resource name "config"
>>
>> Does PCI designware follow some convention? Does it mean after applying this
>> patch
>> config name is mandatory or optional? Below code you are not returning
>> error. Can you or
>> author of PCI designware clarify what is expected to be present as mandatory
>> and what is
>> optional.
>>
>> Does config refers to RC's config space or EP's config space or both?
>> The code below divide
>> the size by 2. So it appears to be RC's + EP's config space. Please clarify.
>>
>>> - interrupts: interrupt values for level interrupt,
>>> pulse interrupt, special interrupt.
>>> - clocks: from common clock binding: handle to pci clock.
>>> diff --git a/drivers/pci/host/pcie-designware.c
>>> b/drivers/pci/host/pcie-designware.c
>>> index c4e3732..603b386 100644
>>> --- a/drivers/pci/host/pcie-designware.c
>>> +++ b/drivers/pci/host/pcie-designware.c
>>> @@ -20,6 +20,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>> #include
>>>
>>> #include "pcie-designware.h"
>>> @@ -392,11 +393,23 @@ static const struct irq_domain_ops msi_domain_ops = {
>>> int __init dw_pcie_host_init(struct pcie_port *pp)
>>> {
>>> struct device_node *np = pp->dev->of_node;
>>> + struct platform_device *pdev = to_platform_device(pp->dev);
>>> struct of_pci_range range;
>>> struct of_pci_range_parser parser;
>>> + struct resource *cfg_res;
>>> u32 val;
>>> int i;
>>>
>>> + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
>>> + if (cfg_res) {
>>> + pp->config.cfg0_size = resource_size(cfg_res)/2;
>>> + pp->config.cfg1_size = resource_size(cfg_res)/2;
>>> + pp->cfg0_base = cfg_res->start;
>>> + pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
>>> + } else {
>>> + dev_err(pp->dev, "missing *config* reg space\n");
>> This should return error -EINVAL.
Just read the other thread and Grant Likely suggested the host controller
driver should be backward compatible [1]. So we can't return -EINVAL here.
So I'd assume this patch is fine as is? Arnd? Jingoo?
[1] -> https://lkml.org/lkml/2014/6/3/124
Thanks
Kishon
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Re: [PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock
Hi Tero, On Thursday 19 June 2014 04:40 PM, Tero Kristo wrote: > On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >> From: Keerthy >> >> Add divider table to optfclk_pciephy_div clock. The Documentation >> for divider clock can be found at ../clock/ti/divider.txt > > This patch requires a better changelog. Why is the change done, any TRM refs > etc.? The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. We have to do a bypass (divided by 1) in order to get the correct PCIE_PHY_DIV_GCLK frequency. Thanks Kishon > > -Tero > >> >> Cc: Rajendra Nayak >> Cc: Tero Kristo >> Cc: Paul Walmsley >> Signed-off-by: Keerthy >> Signed-off-by: Kishon Vijay Abraham I >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi |1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index c767687..55e95c5 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -1170,6 +1170,7 @@ >> clocks = <&apll_pcie_ck>; >> #clock-cells = <0>; >> reg = <0x021c>; >> +ti,dividers = <2>, <1>; >> ti,bit-shift = <8>; >> ti,max-div = <2>; >> }; >> > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
Hi Tero,
On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote:
> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>> From: Keerthy
>>
>> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
>> from dpll_pcie_ref_ck.
>
> Why? Needs a better changelog also.
Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.
Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.
So the actual output of dpll should be dpll_pcie_ref_m2ldo_ck instead of
dpll_pcie_ref_ck (which is the input of apll mux).
Thanks
Kishon
>
> -Tero
>
>>
>> Cc: Rajendra Nayak
>> Cc: Tero Kristo
>> Cc: Paul Walmsley
>> Signed-off-by: Keerthy
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 55e95c5..44993ec 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1152,7 +1152,7 @@
>>
>> apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
>> compatible = "ti,mux-clock";
>> -clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
>> +clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
>> #clock-cells = <0>;
>> reg = <0x021c 0x4>;
>> ti,bit-shift = <7>;
>>
>
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Re: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Hi Tero,
On Thursday 19 June 2014 04:46 PM, Tero Kristo wrote:
> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>> Added missing 32khz clock used by PCIe PHY.
>> The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
>
> You can drop the node documentation ref, and rather add a TRM reference about
> hardware details. Other than that, looks good to me.
You mean something like why 32KHz clock is used (**PRCM.PCIE_32K_GFCLK (based
on PRM.SYS_32K) for debounce and wakeup logic inside the PCIe1_PHY_RX**)? Or
something like **Figure 26-19. PCIe PHY Subsystem Integration of DRA TRM vE
shows how 32KHz clock is being used** ?
Thanks
Kishon
>
> -Tero
>
>>
>> Cc: Tony Lindgren
>> Cc: Rajendra Nayak
>> Cc: Tero Kristo
>> Cc: Paul Walmsley
>> Cc: Tony Lindgren
>> Cc: Rob Herring
>> Cc: Pawel Moll
>> Cc: Mark Rutland
>> Cc: Kumar Gala
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/boot/dts/dra7xx-clocks.dtsi |8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 44993ec..e1bd052 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1165,6 +1165,14 @@
>> reg = <0x021c>, <0x0220>;
>> };
>>
>> +optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
>> +compatible = "ti,gate-clock";
>> +clocks = <&sys_32k_ck>;
>> +#clock-cells = <0>;
>> +reg = <0x13b0>;
>> +ti,bit-shift = <8>;
>> +};
>> +
>> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
>> compatible = "ti,divider-clock";
>> clocks = <&apll_pcie_ck>;
>>
>
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Re: [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Hi,
On Thursday 19 June 2014 04:50 PM, Tero Kristo wrote:
> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
>> Added missing clocks used by second instance of PCIe PHY.
>> The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
>
> Drop the ref to the binding doc and rather add a ref to TRM about the clock
> layout. Also, is the register offset wrong on these? Should be 0x13b8, no, or
> is my TRM version wrong?
Er.. you are right. It should be 0x13b8.
Thanks
Kishon
>
> -Tero
>
>>
>> Cc: Rajendra Nayak
>> Cc: Tero Kristo
>> Cc: Paul Walmsley
>> Cc: Tony Lindgren
>> Cc: Rob Herring
>> Cc: Pawel Moll
>> Cc: Mark Rutland
>> Cc: Kumar Gala
>> Signed-off-by: Keerthy
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 24
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> index 3d8c9c2..a9ff0dc 100644
>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
>> @@ -1173,6 +1173,14 @@
>> ti,bit-shift = <8>;
>> };
>>
>> +optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {
>> +compatible = "ti,gate-clock";
>> +clocks = <&sys_32k_ck>;
>> +#clock-cells = <0>;
>> +reg = <0x13b4>;
>> +ti,bit-shift = <8>;
>> +};
>> +
>> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
>> compatible = "ti,divider-clock";
>> clocks = <&apll_pcie_ck>;
>> @@ -1191,6 +1199,14 @@
>> ti,bit-shift = <9>;
>> };
>>
>> +optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {
>> +compatible = "ti,gate-clock";
>> +clocks = <&apll_pcie_ck>;
>> +#clock-cells = <0>;
>> +reg = <0x13b4>;
>> +ti,bit-shift = <9>;
>> +};
>> +
>> optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
>> compatible = "ti,gate-clock";
>> clocks = <&optfclk_pciephy_div>;
>> @@ -1199,6 +1215,14 @@
>> ti,bit-shift = <10>;
>> };
>>
>> +optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {
>> +compatible = "ti,gate-clock";
>> +clocks = <&optfclk_pciephy_div>;
>> +#clock-cells = <0>;
>> +reg = <0x13b4>;
>> +ti,bit-shift = <10>;
>> +};
>> +
>> apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
>> #clock-cells = <0>;
>> compatible = "fixed-factor-clock";
>>
>
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Re: [PATCH 1/2] ARM: DRA7: hwmod: Add OCP2SCP3 module
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros
> Tested-by: Roger Quadros
I used this patch for testing PCIe.
Tested-by: Kishon Vijay Abraham I
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 20b4398..cedef6b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
> },
> };
>
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_ocp2scp3_hwmod,
> + .clk= "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> + .name = "ocp2scp3",
> + .class = &dra7xx_ocp2scp_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs =
> DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> + .context_offs =
> DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_HWCTRL,
> + },
> + },
> +};
> +
> /*
> * 'qspi' class
> *
> @@ -2672,6 +2696,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
> __initdata = {
> &dra7xx_l4_per1__mmc4,
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> + &dra7xx_l4_cfg__ocp2scp3,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
>
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[PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren
Cc: Russell King
Cc: Paul Walmsley
Signed-off-by: Kishon Vijay Abraham I
Tested-by: Kishon Vijay Abraham I
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..934aa9d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
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[PATCH 0/2] arm: hwmod: dra7: Add PCIe data and PCIe PHY data
[1] is split into separate series in order for individual subsystem Maintainers to pick up the patches. This series handles the PCIe hwmod data for DRA7. Please find the bootlog with these hwmod patches @ [2] [1] -> https://lkml.org/lkml/2014/5/29/258 [2] -> http://paste.ubuntu.com/7701601/ Kishon Vijay Abraham I (2): arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems arch/arm/mach-omap2/cm2_7xx.h |4 ++ arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 + arch/arm/mach-omap2/prm7xx.h |4 ++ 3 files changed, 120 insertions(+) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren
Cc: Russell King
Cc: Paul Walmsley
Signed-off-by: Kishon Vijay Abraham I
Tested-by: Kishon Vijay Abraham I
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/cm2_7xx.h |4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +
arch/arm/mach-omap2/prm7xx.h |4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3deb76e..6ff40a6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = "pcie1-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = "pcie2-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_phy_hwmod,
+ .clk= "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b30,
@@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[]
__initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFF
Re: [PATCH 1/3] phy: omap-usb2: Manage PHY 3.3V supply regulator
Hi Roger,
On Monday 30 June 2014 04:30 PM, Roger Quadros wrote:
> On some SoCs e.g. J6 the 3.3V supply to the USB2 PHY can be
> powered down when the PHY is not in use. Add regulator
> management code to control this power line.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/phy/phy-omap-usb2.c | 25 +
> include/linux/phy/omap_usb.h | 1 +
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
> index 7007c11..2afc79c 100644
> --- a/drivers/phy/phy-omap-usb2.c
> +++ b/drivers/phy/phy-omap-usb2.c
> @@ -30,6 +30,7 @@
> #include
> #include
> #include
> +#include
>
> #define USB2PHY_DISCON_BYP_LATCH (1 << 31)
> #define USB2PHY_ANA_CONFIG1 0x4c
> @@ -107,6 +108,14 @@ static int omap_usb_power_off(struct phy *x)
>
> omap_control_phy_power(phy->control_dev, 0);
>
> + if (phy->pwr) {
> + int ret;
> +
> + ret = regulator_disable(phy->pwr);
> + if (ret)
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -114,6 +123,14 @@ static int omap_usb_power_on(struct phy *x)
> {
> struct omap_usb *phy = phy_get_drvdata(x);
>
> + if (phy->pwr) {
> + int ret;
> +
> + ret = regulator_enable(phy->pwr);
> + if (ret)
> + return ret;
> + }
> +
Shouldn't we do this in phy_power_on/phy_power_off in phy-core?
Cheers
Kishon
> omap_control_phy_power(phy->control_dev, 1);
>
> return 0;
> @@ -253,6 +270,14 @@ static int omap_usb2_probe(struct platform_device *pdev)
> phy->control_dev = &control_pdev->dev;
> omap_control_phy_power(phy->control_dev, 0);
>
> + /* phy-supply */
> + phy->pwr = devm_regulator_get_optional(phy->dev, "phy");
> + if (IS_ERR(phy->pwr)) {
> + if (PTR_ERR(phy->pwr) == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> + phy->pwr = NULL;
> + }
> +
> otg->set_host = omap_usb_set_host;
> otg->set_peripheral = omap_usb_set_peripheral;
> if (phy_data->flags & OMAP_USB2_HAS_SET_VBUS)
> diff --git a/include/linux/phy/omap_usb.h b/include/linux/phy/omap_usb.h
> index dc2c541..e2c46df 100644
> --- a/include/linux/phy/omap_usb.h
> +++ b/include/linux/phy/omap_usb.h
> @@ -40,6 +40,7 @@ struct omap_usb {
> struct clk *wkupclk;
> struct clk *optclk;
> u8 flags;
> + struct regulator*pwr;
> };
>
> struct usb_phy_data {
>
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Re: [PATCH 1/3] phy: omap-usb2: Manage PHY 3.3V supply regulator
Hi,
On Tuesday 01 July 2014 03:43 PM, Roger Quadros wrote:
> On 07/01/2014 12:56 PM, Kishon Vijay Abraham I wrote:
>> Hi Roger,
>>
>> On Monday 30 June 2014 04:30 PM, Roger Quadros wrote:
>>> On some SoCs e.g. J6 the 3.3V supply to the USB2 PHY can be
>>> powered down when the PHY is not in use. Add regulator
>>> management code to control this power line.
>>>
>>> Signed-off-by: Roger Quadros
>>> ---
>>> drivers/phy/phy-omap-usb2.c | 25 +
>>> include/linux/phy/omap_usb.h | 1 +
>>> 2 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
>>> index 7007c11..2afc79c 100644
>>> --- a/drivers/phy/phy-omap-usb2.c
>>> +++ b/drivers/phy/phy-omap-usb2.c
>>> @@ -30,6 +30,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>>
>>> #define USB2PHY_DISCON_BYP_LATCH (1 << 31)
>>> #define USB2PHY_ANA_CONFIG1 0x4c
>>> @@ -107,6 +108,14 @@ static int omap_usb_power_off(struct phy *x)
>>>
>>> omap_control_phy_power(phy->control_dev, 0);
>>>
>>> + if (phy->pwr) {
>>> + int ret;
>>> +
>>> + ret = regulator_disable(phy->pwr);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -114,6 +123,14 @@ static int omap_usb_power_on(struct phy *x)
>>> {
>>> struct omap_usb *phy = phy_get_drvdata(x);
>>>
>>> + if (phy->pwr) {
>>> + int ret;
>>> +
>>> + ret = regulator_enable(phy->pwr);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> +
>>
>> Shouldn't we do this in phy_power_on/phy_power_off in phy-core?
>
> I thought about that earlier, but could not find a way to defer probing if
> the regulator is not-yet probed.
> Any clues how it could be done in phy-core?
We can try to do regulator_get in phy_create and return EPROBE_DEFER if the
regulator_get returns EPROBE_DEFER no?
Cheers
Kishon
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Re: [PATCH 1/3] phy: omap-usb2: Manage PHY 3.3V supply regulator
On Tuesday 01 July 2014 03:55 PM, Roger Quadros wrote:
> On 07/01/2014 01:20 PM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Tuesday 01 July 2014 03:43 PM, Roger Quadros wrote:
>>> On 07/01/2014 12:56 PM, Kishon Vijay Abraham I wrote:
>>>> Hi Roger,
>>>>
>>>> On Monday 30 June 2014 04:30 PM, Roger Quadros wrote:
>>>>> On some SoCs e.g. J6 the 3.3V supply to the USB2 PHY can be
>>>>> powered down when the PHY is not in use. Add regulator
>>>>> management code to control this power line.
>>>>>
>>>>> Signed-off-by: Roger Quadros
>>>>> ---
>>>>> drivers/phy/phy-omap-usb2.c | 25 +
>>>>> include/linux/phy/omap_usb.h | 1 +
>>>>> 2 files changed, 26 insertions(+)
>>>>>
>>>>> diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
>>>>> index 7007c11..2afc79c 100644
>>>>> --- a/drivers/phy/phy-omap-usb2.c
>>>>> +++ b/drivers/phy/phy-omap-usb2.c
>>>>> @@ -30,6 +30,7 @@
>>>>> #include
>>>>> #include
>>>>> #include
>>>>> +#include
>>>>>
>>>>> #define USB2PHY_DISCON_BYP_LATCH (1 << 31)
>>>>> #define USB2PHY_ANA_CONFIG1 0x4c
>>>>> @@ -107,6 +108,14 @@ static int omap_usb_power_off(struct phy *x)
>>>>>
>>>>> omap_control_phy_power(phy->control_dev, 0);
>>>>>
>>>>> + if (phy->pwr) {
>>>>> + int ret;
>>>>> +
>>>>> + ret = regulator_disable(phy->pwr);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> return 0;
>>>>> }
>>>>>
>>>>> @@ -114,6 +123,14 @@ static int omap_usb_power_on(struct phy *x)
>>>>> {
>>>>> struct omap_usb *phy = phy_get_drvdata(x);
>>>>>
>>>>> + if (phy->pwr) {
>>>>> + int ret;
>>>>> +
>>>>> + ret = regulator_enable(phy->pwr);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>
>>>> Shouldn't we do this in phy_power_on/phy_power_off in phy-core?
>>>
>>> I thought about that earlier, but could not find a way to defer probing if
>>> the regulator is not-yet probed.
>>> Any clues how it could be done in phy-core?
>>
>> We can try to do regulator_get in phy_create and return EPROBE_DEFER if the
>> regulator_get returns EPROBE_DEFER no?
>
> Yes indeed, we can. I missed the phy_create() and was only looking at
> phy_init() and phy_power_*() :P.
> I'll post a v2 soon.
cool. Thanks :-)
-Kishon
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