Re: [PATCH 00/03] arm64: dts: r8a7795: IPMMU upstream USB integration
Hi Joerg, On Mon, Apr 3, 2017 at 8:22 PM, Joerg Roedel wrote: > On Tue, Mar 28, 2017 at 06:32:33PM +0900, Magnus Damm wrote: >> The recommended IPMMU driver patch stack consists of the following series: >> [PATCH v7 00/07] iommu/ipmmu-vmsa: IPMMU multi-arch update V7 >> [PATCH v3 00/09] iommu/ipmmu-vmsa: r8a7795 support V3 > > These two patch-sets have unaddressed comments. Please address these and > get a Reviewed-by from Robin on the re-posts. Thanks, yes will do! Best, / magnus
[PATCH i2c-tools 1/2] i2ctransfer: replace broken "force" handling
Probably because of a bad rebase, the old and bogus handling (v1) of "force"
slipped into the latest version of the patch (v3). Apply the better
version from v2 which does the error handling correct and makes the code
a lot easier to understand.
Signed-off-by: Wolfram Sang
---
tools/i2ctransfer.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/tools/i2ctransfer.c b/tools/i2ctransfer.c
index 0f7ddd5..bc027c3 100644
--- a/tools/i2ctransfer.c
+++ b/tools/i2ctransfer.c
@@ -199,8 +199,6 @@ int main(int argc, char *argv[])
arg_ptr = end;
if (*arg_ptr) {
- int whole_range_ok;
-
if (*arg_ptr++ != '@') {
fprintf(stderr, "Error: Unknown
seperator after length\n");
goto err_out_with_arg;
@@ -211,16 +209,22 @@ int main(int argc, char *argv[])
* the address here.
*/
- address = parse_i2c_address(arg_ptr);
- /* With 'force', allow whole address range */
- whole_range_ok = force && address == -2;
- if (address < 0 && !whole_range_ok)
- goto err_out_with_arg;
-
- /* Ensure address is not busy */
- if (!force && set_slave_addr(file, address, 0))
- goto err_out_with_arg;
-
+ if (!force) {
+ address = parse_i2c_address(arg_ptr);
+ if (address < 0)
+ goto err_out_with_arg;
+
+ /* Ensure address is not busy */
+ if (set_slave_addr(file, address, 0))
+ goto err_out_with_arg;
+ } else {
+ /* 'force' allows whole address range */
+ address = strtol(arg_ptr, &end, 0);
+ if (arg_ptr == end || *end || address >
0x7f) {
+ fprintf(stderr, "Error: Invalid
chip address\n");
+ goto err_out_with_arg;
+ }
+ }
} else {
/* Reuse last address if possible */
if (address < 0) {
--
2.11.0
[PATCH i2c-tools 2/2] i2ctransfer: grammar fixes in manpage
Signed-off-by: Wolfram Sang --- tools/i2ctransfer.8 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/i2ctransfer.8 b/tools/i2ctransfer.8 index 28b3388..d17df3c 100644 --- a/tools/i2ctransfer.8 +++ b/tools/i2ctransfer.8 @@ -74,7 +74,7 @@ This number should correspond to one of the busses listed by The next parameter is one or multiple .I desc blocks. -The number of blocks is limited by the Linux Kernel and defined in I2C_RDWR_IOCTL_MAX_MSGS (42 as of v4.10). +The number of blocks is limited by the Linux Kernel and defined with I2C_RDWR_IOCTL_MAX_MSGS (42 as of v4.10). .I desc blocks are composed like this: @@ -86,7 +86,7 @@ specifies if the message is read or write .TP .B specifies the number of bytes read or written in this message. -It is parsed as an unsigned 16 bit integer, but note that the Linux Kernel apply an additional upper limit (8192 as of v4.10). +It is parsed as an unsigned 16 bit integer, but note that the Linux Kernel applies an additional upper limit (8192 as of v4.10). .TP .B [@address] specifies the 7-bit address of the chip to be accessed for this message, and is an integer. -- 2.11.0
Re: [PATCH v3 0/7] rtc: Reuse rtc-sh driver to support RZ/A1
Hi, On 29/03/2017 at 10:30:28 -0700, Chris Brandt wrote: > Basically, the same RTC that was used in SuperH devices is now used in > RZ/A1 devices. Therefore with some slight changes, that driver can be > reused. > > Additionally, since ARM architectures require Device Tree configurations, > device tree support has been added. > > This was tested on RZ/A1H RSK board. Once the correct time was programmed > into the RTC running off a 32.768kHz crystal, you can retain an accurate > system clock between reboots (hard and soft) until power is finally removed > from the board (there is no batter backup on the RSK board). > > v3: > * remove 'power-domains' from example in documentation > * update commit message subject and body of dt-bindings > > v2: > * removed HAVE_CLK from Kconfig > * when using DT, look for "fck" instead of "rtc0" > * changed (res == NULL) to (!res) > * added Reviewed-by for rtc-sh.c > * added interrupt-names and clock-names > * clocks now include counting sources > * added clock-names "fck", "rtc_x1", "rtc_x3", "extal" > * changed 'is a RTC' to 'is an RTC' in commit message > * changed "rtc0" to "rtc" > * Added clock nodes for RTC_X1 and RTC_X3 pin inputs > * each commit now has a log message > > > Chris Brandt (7): > rtc: rtc-sh: add support for rza series > dt-bindings: rtc: document the rtc-sh bindings I applied those two, I'll let Simon take the device tree patches. Thanks! > ARM: dts: r7s72100: add rtc clock to device tree > ARM: dts: r7s72100: add RTC_X clock inputs to device tree > ARM: dts: r7s72100: add rtc to device tree > ARM: dts: rskrza1: set rtc_x1 clock value > ARM: dts: rskrza1: add rtc DT support -- Alexandre Belloni, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
[PATCH] arm: dts: genmai: Enable rtc and rtc_x1 clock
Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero and enable the realtime clock.
Signed-off-by: Jacopo Mondi
---
This patch depends on Chris Brandt's series
"rtc: Reuse rtc-sh driver to support RZ/A1"
Please queue this on top of that.
arch/arm/boot/dts/r7s72100-genmai.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts
b/arch/arm/boot/dts/r7s72100-genmai.dts
index 118a8e2..52a7b58 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -44,6 +44,10 @@
clock-frequency = <4800>;
};
+&rtc_x1_clk {
+ clock-frequency = <32768>;
+};
+
&mtu2 {
status = "okay";
};
@@ -59,6 +63,10 @@
};
};
+&rtc {
+ status = "okay";
+};
+
&scif2 {
status = "okay";
};
--
2.7.4
Re: [PATCH v3 2/7] dt-bindings: rtc: document the rtc-sh bindings
On Wed, Mar 29, 2017 at 10:30:30AM -0700, Chris Brandt wrote: > Add the binding documentation for rtc-sh which is an RTC for > SuperH and RZ/A SoCs. > > Signed-off-by: Chris Brandt > --- > v3: > * remove 'power-domains' from example > * update commit message subject and body > v2: > * added interrupt-names and clock-names > * clocks now include counting sources > * changed 'is a RTC' to 'is an RTC' in commit message > --- > Documentation/devicetree/bindings/rtc/rtc-sh.txt | 28 > > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/rtc-sh.txt Acked-by: Rob Herring
Re: [PATCH v4 1/4] Documentation: dt-bindings: iio: Add max9611 ADC
On Mon, Mar 27, 2017 at 05:12:55PM +0200, Jacopo Mondi wrote:
> Add device tree bindings documentation for Maxim max9611/max9612 current
> sense amplifier.
"dt-bindings: iio: adc: ..." for the subject.
>
> Signed-off-by: Jacopo Mondi
> ---
> .../devicetree/bindings/iio/adc/max9611.txt| 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/max9611.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/max9611.txt
> b/Documentation/devicetree/bindings/iio/adc/max9611.txt
> new file mode 100644
> index 000..8430d3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/max9611.txt
> @@ -0,0 +1,26 @@
> +* Maxim max9611/max9612 current sense amplifier with 12-bits ADC interface
> +
> +Maxim max9611/max9612 is an high-side current sense amplifier with integrated
> +12-bits ADC communicating over I2c bus.
> +The device node for this driver shall be a child of a I2c controller.
> +
> +Required properties
> + - compatible: Should be "maxim,max9611" or "maxim,max9612"
> + - reg: The 7-bits long I2c address of the device
> + - shunt-resistor-uohm: Value, in uOhm, of the current sense shunt resistor
As Jonathan said.
> +
> +Example:
> +
> +&i2c4 {
> + csa: adc@7c {
> + compatible = "maxim,max9611";
> + reg = <0x7c>;
> +
> + shunt-resistor-uohm = <5000>;
> + };
> +};
> +
> +This device node describes a current sense amplifier sitting on I2c4 bus
> +with address 0x7c (read address is 0xf9, write address is 0xf8).
> +A sense resistor of 0,005 Ohm is installed between RS+ and RS-
> current-sensing
> +inputs.
> --
> 2.7.4
>
Re: [PATCH] can: rcar_can: Do not print virtual addresses
On 04/03/2017 01:11 PM, Geert Uytterhoeven wrote:
During probe, the rcar_can driver prints:
rcar_can e6e8.can: device registered (regs @ e08bc000, IRQ76)
The "regs" value is a virtual address, exposing internal information,
hence stop printing it. The (useful) physical address is already
printed as part of the device name.
Fixes: fd1159318e55e901 ("can: add Renesas R-Car CAN driver")
Signed-off-by: Geert Uytterhoeven
[...]
Acked-by: Sergei Shtylyov
MBR, Sergei
Re: [PATCH 00/03] arm64: dts: r8a7795: IPMMU upstream USB integration
On Tue, Mar 28, 2017 at 06:32:33PM +0900, Magnus Damm wrote: > The recommended IPMMU driver patch stack consists of the following series: > [PATCH v7 00/07] iommu/ipmmu-vmsa: IPMMU multi-arch update V7 > [PATCH v3 00/09] iommu/ipmmu-vmsa: r8a7795 support V3 These two patch-sets have unaddressed comments. Please address these and get a Reviewed-by from Robin on the re-posts. Joerg
Re: [PATCH] ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
On Mon, Apr 03, 2017 at 11:55:19AM +0200, Geert Uytterhoeven wrote:
> The X2 crystal oscillator on the Koelsch development board provides a
> 74.25 MHz clock, not a 148.5 MHz clock.
>
> Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel
> clocks to DT")
> Signed-off-by: Geert Uytterhoeven
> ---
> Confirmed by schematics, user manual, and physical inspection of 2
> Koelsch instances (my scope has not enough bandwidth to measure the
> actual frequency).
>
> Probably this was copied from r8a7790-lager.dts, as Lager does have two
> identical crystal oscillators X2 and X13.
>
> Note that X2 is socketed, so it can be changed.
Thanks, I have queued this up.
Re: [PATCH] ARM: dts: r8a7794: Add Z2 clock
On Mon, Apr 03, 2017 at 11:54:03AM +0200, Geert Uytterhoeven wrote: > Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, > and link the first CPU node to it. > > Signed-off-by: Geert Uytterhoeven Thanks, I have queued this up.
Re: [PATCH] ARM: dts: r8a7792: Correct Z clock
On Mon, Apr 03, 2017 at 11:53:08AM +0200, Geert Uytterhoeven wrote:
> Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
> not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
> fixed divider.
> This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
>
> Hence:
> - Remove the Z clock output from the cpg_clocks node, as this implied
> a programmable clock,
> - Add the Z clock as a fixed factor clock,
> - Let the first CPU node point to the new Z clock,
> - Remove the Z clock index from the bindings (this definition was used
> by r8a7792.dtsi only, and was not a contract between DT and driver).
>
> Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
> Signed-off-by: Geert Uytterhoeven
Thanks, I have queued this up.
Re: [PATCH 0/3] ARM: dts: rcar-gen2: Correct parent of SSI[0-9] clocks
On Mon, Apr 03, 2017 at 11:45:40AM +0200, Geert Uytterhoeven wrote: > Hi Simon, Magnus, Morimoto-san, > > The SSI-ALL gate clock is located in between the P clock and the > individual SSI[0-9] clocks, hence the former should be listed as their > parent. > > This patch series corrects the parents in the DTSes r8a7790, r8a7791, > and r8a7793. The DTS for r8a7794, and the CPG/MSSR-based clock drivers > for r8a7743, r8a7745, and r8a7795 already describe the correct parent. > > Thanks! Thanks, I have queued these up.
Re: [PATCH v2 0/3] soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
On Fri, Mar 31, 2017 at 11:01:53AM +0200, Geert Uytterhoeven wrote: > Hi Simon, Magnus, > > This patch series adds power domain support for R-Car H3 ES2.0, which > differs from ES1.x in some areas. > > The goal is twofold: > 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary > for now, > 2. Make it clear which code supports ES1.x, so it can easily be > identified and removed later, when production SoCs are deemed > ubiquitous. > > This is achieved by detecting the SoC revision at runtime using the > soc_device_match() API, and fixing up the power area table to match the > actual SoC revision. > > Changes compared to v1: > - Minor changes to the patch descriptions. > > As PM Domains are initialized quite early, the Renesas SoC device must > be initialized earlier, and this series thus depends on the pull > request "[git pull] base: soc: Improvements for the SoC bus and > soc_device_match()" I've just sent. > > For testers, this series and its dependencies are available in the > topic/r8a7795es2-sysc-v2 branch of my renesas-drivers git repository at > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git. > An integration branch for testing on the R-Car H3 ES2.0 based Salvator-X > development board is provided as topic/r8a7795es2-integration. > > This has been tested on Salvator-X with R-Car H3 ES1.0, ES1.1, and ES2.0 > SoCs. > > Thanks for applying! Thanks, done.
Re: [git pull] base: soc: Improvements for the SoC bus and soc_device_match()
On Fri, Mar 31, 2017 at 10:54:20AM +0200, Geert Uytterhoeven wrote:
> Hi Greg,
> Hi Arnd, Kevin, Olof,
> Hi Magnus, Simon,
>
> The following changes since commit c470abd4fde40ea6a0846a2beab642a578c0b8cd:
>
> Linux 4.10 (2017-02-19 14:34:00 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> tags/soc-device-match-tag2
>
> for you to fetch changes up to 6e12db376b60b7158e4e6006af60566f8c68f7ab:
>
> base: soc: Allow early registration of a single SoC device (2017-03-29
> 21:43:26 +0200)
Hi Geert,
I have pulled this into the renesas tree.
Hi Greg,
I would be most grateful if you could pull the above tag too.
>
> base: soc: Improvements for the SoC bus and soc_device_match()
>
> This is a dependency for handling different SoC revisions in the Renesas
> R-Car SYSC driver, which manages PM Domains and thus needs to be
> initialized from an early_initcall().
>
> Hence this will serve as an immutable branch between the driver core,
> arm-soc, and renesas trees, to allow queueing the Renesas R-Car SYSC
> changes on top in the renesas tree.
>
> All changes in this pull request have been Acked by Arnd.
>
> Thanks for pulling!
>
> Geert Uytterhoeven (2):
> base: soc: Let soc_device_match() return no match when called too early
> base: soc: Allow early registration of a single SoC device
>
> drivers/base/soc.c | 52 ++--
> 1 file changed, 34 insertions(+), 18 deletions(-)
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
>
Re: [PATCH] ARM: dts: r7s72100: fix ethernet clock parent
On Thu, Mar 30, 2017 at 02:16:09PM -0700, Chris Brandt wrote:
> Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not
> the 33MHz Peripheral 0 (P0) clock.
>
> Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree")
> Signed-off-by: Chris Brandt
Thanks, I have queued this up.
Re: [PATCH] pinctrl: sh-pfc: r8a7791: grand I2C rename
On Fri, Mar 31, 2017 at 01:01:04PM +0200, Geert Uytterhoeven wrote:
> Hi Sergei,
>
> On Thu, Mar 30, 2017 at 6:53 PM, Sergei Shtylyov
> wrote:
> > The R8A7791 PFC driver was apparently based on the preliminary revisions
> > of the user's manual, which called all the I2C signals {SCL|SDA} and
> > MOD_SEL register fields SEL_IIC without making a difference between two
> > types of the I2C controllers used. The recent manual calls the signals
> > {I2C|IIC}_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC} finally
> > making this difference. Follow the suit, also renaming the I2C{7|8} pin
> > arrays and groups/functions (luckily, they haven't been used so far).
> >
> > Signed-off-by: Sergei Shtylyov
>
> Thanks for your patch!
>
> > drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 521
> > +--
> > 1 file changed, 264 insertions(+), 257 deletions(-)
> >
> > Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> > ===
> > --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> > +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> > @@ -119,22 +119,22 @@ enum {
> > /* IPSR0 */
> > FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
> > FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
> > - FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
> > + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
>
> While I have no issue with renaming internal definitions...
>
> > @@ -4507,12 +4514,12 @@ static const struct sh_pfc_pin_group pin
> > SH_PFC_PIN_GROUP(i2c4),
> > SH_PFC_PIN_GROUP(i2c4_b),
> > SH_PFC_PIN_GROUP(i2c4_c),
> > - SH_PFC_PIN_GROUP(i2c7),
> > - SH_PFC_PIN_GROUP(i2c7_b),
> > - SH_PFC_PIN_GROUP(i2c7_c),
> > - SH_PFC_PIN_GROUP(i2c8),
> > - SH_PFC_PIN_GROUP(i2c8_b),
> > - SH_PFC_PIN_GROUP(i2c8_c),
> > + SH_PFC_PIN_GROUP(iic0),
> > + SH_PFC_PIN_GROUP(iic0_b),
> > + SH_PFC_PIN_GROUP(iic0_c),
> > + SH_PFC_PIN_GROUP(iic1),
> > + SH_PFC_PIN_GROUP(iic1_b),
> > + SH_PFC_PIN_GROUP(iic1_c),
>
> I do object against renaming the user-visible names, like pin groups...
>
> > @@ -5298,8 +5305,8 @@ static const struct sh_pfc_function pinm
> > SH_PFC_FUNCTION(i2c2),
> > SH_PFC_FUNCTION(i2c3),
> > SH_PFC_FUNCTION(i2c4),
> > - SH_PFC_FUNCTION(i2c7),
> > - SH_PFC_FUNCTION(i2c8),
> > + SH_PFC_FUNCTION(iic0),
> > + SH_PFC_FUNCTION(iic1),
>
> ... and pin functions. Technically, they are part of the DT bindings,
> and thus are not allowed to change.
>
> IMHO either the user-visible names should be left alone, or the new names
> should be added as alternatives, next to the existing names.
>
> What do other people think?
I think that any user-visible changes need to have a very strong reason.
[PATCH] can: rcar_can: Do not print virtual addresses
During probe, the rcar_can driver prints:
rcar_can e6e8.can: device registered (regs @ e08bc000, IRQ76)
The "regs" value is a virtual address, exposing internal information,
hence stop printing it. The (useful) physical address is already
printed as part of the device name.
Fixes: fd1159318e55e901 ("can: add Renesas R-Car CAN driver")
Signed-off-by: Geert Uytterhoeven
---
drivers/net/can/rcar/rcar_can.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index caed4e6960f8c77f..11662f479e760ba7 100644
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -826,8 +826,7 @@ static int rcar_can_probe(struct platform_device *pdev)
devm_can_led_init(ndev);
- dev_info(&pdev->dev, "device registered (regs @ %p, IRQ%d)\n",
-priv->regs, ndev->irq);
+ dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq);
return 0;
fail_candev:
--
2.7.4
[PATCH 2/3] ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index a6478ca3f4ca7554..4d0c2ce59900f811 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1126,7 +1126,7 @@
};
/* External CAN clock */
- can_clk: can_clk {
+ can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
--
2.7.4
[PATCH 1/3] ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index fe6b8c2a2d711536..99269aaca6fc953e 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1101,7 +1101,7 @@
};
/* External CAN clock */
- can_clk: can_clk {
+ can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
--
2.7.4
[PATCH 0/3] arm: dts: renesas: Drop _clk suffix from clock node names
Hi Simon, Magnus,
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
This patch removes the remaining offenders in the various Renesas DTSes.
Thanks!
Geert Uytterhoeven (3):
ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node
name
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 3/3] arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index f25241921067dcef..639aa085d9966676 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -56,7 +56,7 @@
reg = <0x0 0x4800 0x0 0x3800>;
};
- x12_clk: x12_clk {
+ x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
--
2.7.4
[PATCH] clk: renesas: r8a7745: Remove PLL configs for MD19=0
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
Manual Rev.1.00, MD19=0 is a prohibited setting.
Hence stop looking at MD19, and remove all PLL configurations for
MD19=0.
Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a7745-cpg-mssr.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 08db21cc6436bdc5..9e2360a8e14b860e 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -190,31 +190,22 @@ static const unsigned int r8a7745_crit_mod_clks[]
__initconst = {
*MD EXTAL PLL0PLL1PLL3
* 14 13 19(MHz) *1 *2
*---
- * 0 0 0 15 x200/3 x208/2 x106
* 0 0 1 15 x200/3 x208/2 x88
- * 0 1 0 20 x150/3 x156/2 x80
* 0 1 1 20 x150/3 x156/2 x66
- * 1 0 0 26 / 2 x230/3 x240/2 x122
* 1 0 1 26 / 2 x230/3 x240/2 x102
- * 1 1 0 30 / 2 x200/3 x208/2 x106
* 1 1 1 30 / 2 x200/3 x208/2 x88
*
* *1 :Table 7.5b indicates VCO output (PLL0 = VCO/3)
* *2 :Table 7.5b indicates VCO output (PLL1 = VCO/2)
*/
-#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 12) | \
-(((md) & BIT(13)) >> 12) | \
-(((md) & BIT(19)) >> 19))
+#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
+(((md) & BIT(13)) >> 13))
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL divPLL1 mult PLL3 mult PLL0 mult */
- { 1,208,106,200 },
{ 1,208,88, 200 },
- { 1,156,80, 150 },
{ 1,156,66, 150 },
- { 2,240,122,230 },
{ 2,240,102,230 },
- { 2,208,106,200 },
{ 2,208,88, 200 },
};
--
2.7.4
[PATCH] clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.
Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a7745-cpg-mssr.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 2f15ba786c3b0ea1..08db21cc6436bdc5 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -167,16 +167,12 @@ static const struct mssr_mod_clk r8a7745_mod_clks[]
__initconst = {
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1",1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0",1021, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
- DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
DEF_MOD("scifa3", 1106, R8A7745_CLK_MP),
DEF_MOD("scifa4", 1107, R8A7745_CLK_MP),
DEF_MOD("scifa5", 1108, R8A7745_CLK_MP),
--
2.7.4
[PATCH] clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.
This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.
Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/clk-rcar-gen2.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c
b/drivers/clk/renesas/clk-rcar-gen2.c
index f39519edc645ca87..51a2479ed5d7c817 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -272,11 +272,14 @@ struct cpg_pll_config {
unsigned int extal_div;
unsigned int pll1_mult;
unsigned int pll3_mult;
+ unsigned int pll0_mult; /* For R-Car V2H and E2 only */
};
static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
- { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
- { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+ { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
+ { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
+ { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
+ { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
};
/* SDHI divisors */
@@ -298,6 +301,12 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
static u32 cpg_mode __initdata;
+static const char * const pll0_mult_match[] = {
+ "renesas,r8a7792-cpg-clocks",
+ "renesas,r8a7794-cpg-clocks",
+ NULL
+};
+
static struct clk * __init
rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
const struct cpg_pll_config *config,
@@ -318,9 +327,15 @@ rcar_gen2_cpg_register_clock(struct device_node *np,
struct rcar_gen2_cpg *cpg,
* clock implementation and we currently have no need to change
* the multiplier value.
*/
- u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ if (of_device_compatible_match(np, pll0_mult_match)) {
+ /* R-Car V2H and E2 do not have PLL0CR */
+ mult = config->pll0_mult;
+ div = 3;
+ } else {
+ u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
+ }
parent_name = "main";
- mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
} else if (!strcmp(name, "pll1")) {
parent_name = "main";
mult = config->pll1_mult / 2;
--
2.7.4
[PATCH] ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
The X2 crystal oscillator on the Koelsch development board provides a
74.25 MHz clock, not a 148.5 MHz clock.
Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks
to DT")
Signed-off-by: Geert Uytterhoeven
---
Confirmed by schematics, user manual, and physical inspection of 2
Koelsch instances (my scope has not enough bandwidth to measure the
actual frequency).
Probably this was copied from r8a7790-lager.dts, as Lager does have two
identical crystal oscillators X2 and X13.
Note that X2 is socketed, so it can be changed.
---
arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts
b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 59beb8402a36007b..001e6116c47c7c3b 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -292,7 +292,7 @@
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <14850>;
+ clock-frequency = <7425>;
};
x13_clk: x13-clock {
--
2.7.4
[PATCH] ARM: dts: r8a7794: Add Z2 clock
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 2f6e94fd408cc858..a19b884fb25897fc 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -43,6 +43,7 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <10>;
+ clocks = <&z2_clk>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>;
};
@@ -1064,6 +1065,13 @@
clock-div = <2>;
clock-mult = <1>;
};
+ z2_clk: z2 {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
--
2.7.4
[PATCH] ARM: dts: r8a7794: Add Z2 clock
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 2f6e94fd408cc858..a19b884fb25897fc 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -43,6 +43,7 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <10>;
+ clocks = <&z2_clk>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
next-level-cache = <&L2_CA7>;
};
@@ -1064,6 +1065,13 @@
clock-div = <2>;
clock-mult = <1>;
};
+ z2_clk: z2 {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
--
2.7.4
[PATCH] ARM: dts: r8a7792: Correct Z clock
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7792.dtsi| 11 +--
include/dt-bindings/clock/r8a7792-clock.h | 1 -
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 6c0797ebc08f029c..0efecb232ee52ce0 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -46,7 +46,7 @@
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <10>;
- clocks = <&cpg_clocks R8A7792_CLK_Z>;
+ clocks = <&z_clk>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
};
@@ -766,7 +766,7 @@
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
-"lb", "qspi", "z";
+"lb", "qspi";
#power-domain-cells = <0>;
};
@@ -778,6 +778,13 @@
clock-div = <2>;
clock-mult = <1>;
};
+ z_clk: z {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
diff --git a/include/dt-bindings/clock/r8a7792-clock.h
b/include/dt-bindings/clock/r8a7792-clock.h
index 94dd16a1e6e6963d..5be90bc23bd79097 100644
--- a/include/dt-bindings/clock/r8a7792-clock.h
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -17,7 +17,6 @@
#define R8A7792_CLK_PLL3 3
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
-#define R8A7792_CLK_Z 6
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
--
2.7.4
[PATCH 0/3] ARM: dts: rcar-gen2: Correct parent of SSI[0-9] clocks
Hi Simon, Magnus, Morimoto-san,
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
This patch series corrects the parents in the DTSes r8a7790, r8a7791,
and r8a7793. The DTS for r8a7794, and the CPG/MSSR-based clock drivers
for r8a7743, r8a7745, and r8a7795 already describe the correct parent.
Thanks!
Geert Uytterhoeven (3):
ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
arch/arm/boot/dts/r8a7790.dtsi | 7 +--
arch/arm/boot/dts/r8a7791.dtsi | 7 +--
arch/arm/boot/dts/r8a7793.dtsi | 7 +--
3 files changed, 15 insertions(+), 6 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 1/3] ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7790.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 534525665bb3a922..fe6b8c2a2d711536 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1443,8 +1443,11 @@
compatible = "renesas,r8a7790-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
+ <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&mstp10_clks R8A7790_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
<&mstp10_clks R8A7790_CLK_SCU_ALL>,
--
2.7.4
[PATCH 2/3] ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7791.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index b319ef4d57b0eb7a..a6478ca3f4ca7554 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1447,8 +1447,11 @@
compatible = "renesas,r8a7791-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
+ <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&mstp10_clks R8A7791_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>,
<&mstp10_clks R8A7791_CLK_SCU_ALL>,
--
2.7.4
[PATCH 3/3] ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree")
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7793.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9fcf3a9ca0846047..4de6041d61f9d4ec 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1269,8 +1269,11 @@
compatible = "renesas,r8a7793-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
clocks = <&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&p_clk>,
+ <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>,
+ <&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&mstp10_clks R8A7793_CLK_SSI_ALL>,
<&p_clk>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>,
<&mstp10_clks R8A7793_CLK_SCU_ALL>,
--
2.7.4
Re: [alsa-devel] [RFC][PATCH] ASoC: soc-core: verify Sound Card normality
On Mon, 03 Apr 2017 10:26:05 +0200, Kuninori Morimoto wrote: > > > Hi Takashi-san > > > > So, we can call snd_soc_unregister_card() whenever CPU/Codec/Platform > > > were unregsiterd. > > > > In theory yes, but you should be careful to do so, e.g. make sure that > > it won't be called again by the removal/unbind of other components / > > drivers. > > > > I suggested snd_card_disconnect() because it doesn't release resources > > by itself, but it just disconnects from the further accesses. So, > > double-free won't happen in this case. It makes the hotunplug safer > > as long as the drivers manage the resource releases properly. > > I had checked many unbind/bind pattern/order on 2nd [RFC] patch which I > posted. > At first, I believe Oops on unbind/bind issue was solved on it. > 2nd, if my understanding was correct, it doesn't have double-free issue, > or something like that. > But, I'm not 100% sure about 2nd, thus it has [RFC] on patch. Ah, I see that snd_soc_unregister_card() has the check of card->instantiated, so it should be fine to call multiple times. thanks, Takashi
Re: [RFC][PATCH] ASoC: soc-core: verify Sound Card normality
Hi Mark.
Sorry, this is v2 patch.
- Subject: Re: [RFC][PATCH] ASoC: soc-core: verify Sound Card normality
+ Subject: Re: [RFC][PATCH v2] ASoC: soc-core: verify Sound Card
normality
> Current ALSA SoC Sound Card basically consists of CPU/Codec/Platform
> components. If system uses Kernel modules, we can disable these drivers
> by using rmmod command. In such case, we can't disable
> CPU/Codec/Platform driver without disabling Sound Card driver.
>
> But on the other hand, we can disable these drivers by using unbind
> command. In such case, we can disable these drivers randomly.
> In this case, we can create dirty Sound Card which is missing necessary
> components.
>
> (1) If user disabled Sound Card first, but did nothing to other drivers,
> user can't use Sound because Sound Card is no longer exists.
> (2) If user disabled CPU/Codec/Platform driver randomly, but did nothing
> to Sound Card, user still be able to use Sound Card, because dirty Sound
> Card still exists. In this case, Sound system will be crashed if user
> started sound playback/capture. But we can't block such random unbind
> now.
>
> To avoid Sound Card crash in (2) case, we need to unregister Sound Card
> whenever CPU/Codec/Platform component were unregistered.
> This patch solves this issue.
>
> Signed-off-by: Kuninori Morimoto
> ---
> sound/soc/soc-core.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
> index 07e4eec..52760bd 100644
> --- a/sound/soc/soc-core.c
> +++ b/sound/soc/soc-core.c
> @@ -3236,6 +3236,11 @@ static void snd_soc_component_cleanup(struct
> snd_soc_component *component)
>
> static void snd_soc_component_del_unlocked(struct snd_soc_component
> *component)
> {
> + struct snd_soc_card *card = component->card;
> +
> + if (card)
> + snd_soc_unregister_card(card);
> +
> list_del(&component->list);
> }
>
> --
> 1.9.1
>
Re: [alsa-devel] [RFC][PATCH] ASoC: soc-core: verify Sound Card normality
Hi Takashi-san > > So, we can call snd_soc_unregister_card() whenever CPU/Codec/Platform > > were unregsiterd. > > In theory yes, but you should be careful to do so, e.g. make sure that > it won't be called again by the removal/unbind of other components / > drivers. > > I suggested snd_card_disconnect() because it doesn't release resources > by itself, but it just disconnects from the further accesses. So, > double-free won't happen in this case. It makes the hotunplug safer > as long as the drivers manage the resource releases properly. I had checked many unbind/bind pattern/order on 2nd [RFC] patch which I posted. At first, I believe Oops on unbind/bind issue was solved on it. 2nd, if my understanding was correct, it doesn't have double-free issue, or something like that. But, I'm not 100% sure about 2nd, thus it has [RFC] on patch. Best regards --- Kuninori Morimoto
Re: [PATCH] pinctrl: sh-pfc: r8a7791: add R8A7743 support
Hi Sergei,
On Sun, Apr 2, 2017 at 12:08 AM, Sergei Shtylyov
wrote:
> Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
> however it doesn't have several automotive specific peripherals. Along
> with adding 'struct sh_pfc_soc_info' for R8A7743, annotate all items
> that only exist on the R-Car SoCs.
>
> Signed-off-by: Sergei Shtylyov
Thanks for your (big) patch!
> --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> @@ -1,8 +1,8 @@
> /*
> - * r8a7791 processor support - PFC hardware block.
> + * r8a7791/r8a7743 processor support - PFC hardware block.
> *
> * Copyright (C) 2013 Renesas Electronics Corporation
> - * Copyright (C) 2014-2015 Cogent Embedded, Inc.
> + * Copyright (C) 2014-2017 Cogent Embedded, Inc.
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License version 2
> @@ -129,11 +129,12 @@ enum {
> FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
> FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
> FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
> - FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
> - FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
> - FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
> - FN_A15, FN_BPFCLK_C,
> - FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
> + FN_A12, FN_FMCLK /* R8A779x only */, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
> + FN_A13, FN_ATAG0_N_C, FN_BPFCLK /* R8A779x only */, FN_MSIOF1_SS1_D,
> + FN_A14, FN_ATADIR0_N_C, FN_FMIN /* R8A779x only */,
> + FN_FMIN_C /* R8A779x only */, FN_MSIOF1_SYNC_D,
> + FN_A15, FN_BPFCLK_C /* R8A779x only */,
> + FN_A16, FN_DREQ2_B, FN_FMCLK_C /* R8A779x only */, FN_SCIFA1_SCK_B,
I don't know if it's worth annotating all bits...
> @@ -1702,7 +1789,7 @@ static const struct sh_pfc_pin pinmux_pi
> PINMUX_GPIO_GP_ALL(),
> };
>
> -/* - ADI
> */
> +/* - ADI (R8A779x only)
> - */
> static const unsigned int adi_common_pins[] = {
> /* ADIDATA, ADICS/SAMP, ADICLK */
> RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
... and pins (and groups and register bit fields), as they're used
only indirectly.
> @@ -4420,14 +4507,14 @@ static const unsigned int vin2_clk_mux[]
> };
>
> static const struct sh_pfc_pin_group pinmux_groups[] = {
> - SH_PFC_PIN_GROUP(adi_common),
> - SH_PFC_PIN_GROUP(adi_chsel0),
> - SH_PFC_PIN_GROUP(adi_chsel1),
> - SH_PFC_PIN_GROUP(adi_chsel2),
> - SH_PFC_PIN_GROUP(adi_common_b),
> - SH_PFC_PIN_GROUP(adi_chsel0_b),
> - SH_PFC_PIN_GROUP(adi_chsel1_b),
> - SH_PFC_PIN_GROUP(adi_chsel2_b),
> + SH_PFC_PIN_GROUP(adi_common), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel0), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel1), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel2), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_common_b), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel0_b), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel1_b), /* R8A779x only */
> + SH_PFC_PIN_GROUP(adi_chsel2_b), /* R8A779x only */
> SH_PFC_PIN_GROUP(audio_clk_a),
> SH_PFC_PIN_GROUP(audio_clk_b),
> SH_PFC_PIN_GROUP(audio_clk_b_b),
> @@ -4524,7 +4611,7 @@ static const struct sh_pfc_pin_group pin
> SH_PFC_PIN_GROUP(intc_irq1),
> SH_PFC_PIN_GROUP(intc_irq2),
> SH_PFC_PIN_GROUP(intc_irq3),
> - SH_PFC_PIN_GROUP(mlb_3pin),
> + SH_PFC_PIN_GROUP(mlb_3pin), /* R8A7794 only */
R8A779x ;-)
> SH_PFC_PIN_GROUP(mmc_data1),
> SH_PFC_PIN_GROUP(mmc_data4),
> SH_PFC_PIN_GROUP(mmc_data8),
> @@ -5288,7 +5377,7 @@ static const char * const vin2_groups[]
> };
>
> static const struct sh_pfc_function pinmux_functions[] = {
> - SH_PFC_FUNCTION(adi),
> + SH_PFC_FUNCTION(adi), /* R8A779x only */
> SH_PFC_FUNCTION(audio_clk),
> SH_PFC_FUNCTION(avb),
> SH_PFC_FUNCTION(can0),
> @@ -5308,7 +5397,7 @@ static const struct sh_pfc_function pinm
> SH_PFC_FUNCTION(iic0),
> SH_PFC_FUNCTION(iic1),
> SH_PFC_FUNCTION(intc),
> - SH_PFC_FUNCTION(mlb),
> + SH_PFC_FUNCTION(mlb), /* R8A779x only */
> SH_PFC_FUNCTION(mmc),
> SH_PFC_FUNCTION(msiof0),
> SH_PFC_FUNCTION(msiof1),
For pinmux_groups[] and pinmux_functions[] I agree they should be annotated.
However, you could achieve the same by using separate arrays for r8a7791
and r8a7743, with the added benefits that users cannot select nonexisting groups
and functions, and that only existing groups and functions are exposed
through debugfs
(/sys/kernel/debug/pinctrl/e606.pfc/pin{conf-groups,groups,mux-fu
[PATCH] cs-2000-cp: keep Reserved bit on each register
From: Kuninori Morimoto
Thus CS2000 datasheet is indicating below, this patch
follows it.
WARNING: All "Reserved" registers must maintain their default
state to ensure proper functional operation.
Signed-off-by: Kuninori Morimoto
Tested-by: Hiroyuki Yokoyama
---
drivers/clk/clk-cs2000-cp.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index 3fca052..f5915ff 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -36,15 +36,27 @@
/* DEVICE_CTRL */
#define PLL_UNLOCK (1 << 7)
+#define AUXOUTDIS (1 << 1)
+#define CLKOUTDIS (1 << 0)
/* DEVICE_CFG1 */
#define RSEL(x)(((x) & 0x3) << 3)
#define RSEL_MASK RSEL(0x3)
#define ENDEV1 (0x1)
+/* DEVICE_CFG2 */
+#define AUTORMOD (1 << 3)
+#define LOCKCLK(x) (((x) & 0x3) << 1)
+#define LOCKCLK_MASK LOCKCLK(0x3)
+#define FRACNSRC (1 << 0)
+
/* GLOBAL_CFG */
#define ENDEV2 (0x1)
+/* FUNC_CFG1 */
+#define REFCLKDIV(x) (((x) & 0x3) << 3)
+#define REFCLKDIV_MASK REFCLKDIV(0x3)
+
#define CH_SIZE_ERR(ch)((ch < 0) || (ch >= CH_MAX))
#define hw_to_priv(_hw)container_of(_hw, struct cs2000_priv,
hw)
#define priv_to_client(priv) (priv->client)
@@ -127,7 +139,9 @@ static int cs2000_clk_in_bound_rate(struct cs2000_priv
*priv,
else
return -EINVAL;
- return cs2000_bset(priv, FUNC_CFG1, 0x3 << 3, val << 3);
+ return cs2000_bset(priv, FUNC_CFG1,
+ REFCLKDIV_MASK,
+ REFCLKDIV(val));
}
static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
@@ -153,7 +167,10 @@ static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
{
/* enable both AUX_OUT, CLK_OUT */
- return cs2000_write(priv, DEVICE_CTRL, enable ? 0 : 0x3);
+ return cs2000_bset(priv, DEVICE_CTRL,
+ (AUXOUTDIS | CLKOUTDIS),
+ enable ? 0 :
+ (AUXOUTDIS | CLKOUTDIS));
}
static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out)
@@ -243,7 +260,9 @@ static int cs2000_ratio_select(struct cs2000_priv *priv,
int ch)
if (ret < 0)
return ret;
- ret = cs2000_write(priv, DEVICE_CFG2, 0x0);
+ ret = cs2000_bset(priv, DEVICE_CFG2,
+ (AUTORMOD | LOCKCLK_MASK | FRACNSRC),
+ 0);
if (ret < 0)
return ret;
--
1.9.1
Re: [PATCH] pinctrl: sh-pfc: r8a7791: grand I2C rename
On Fri, Mar 31, 2017 at 1:01 PM, Geert Uytterhoeven
wrote:
> On Thu, Mar 30, 2017 at 6:53 PM, Sergei Shtylyov
> wrote:
>> The R8A7791 PFC driver was apparently based on the preliminary revisions
>> of the user's manual, which called all the I2C signals {SCL|SDA} and
>> MOD_SEL register fields SEL_IIC without making a difference between two
>> types of the I2C controllers used. The recent manual calls the signals
>> {I2C|IIC}_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC} finally
>> making this difference. Follow the suit, also renaming the I2C{7|8} pin
>> arrays and groups/functions (luckily, they haven't been used so far).
>>
>> Signed-off-by: Sergei Shtylyov
>> --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
>> +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
>> @@ -119,22 +119,22 @@ enum {
>> /* IPSR0 */
>> FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
>> FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
>> - FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
>> + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
>
> While I have no issue with renaming internal definitions...
>
>> @@ -4507,12 +4514,12 @@ static const struct sh_pfc_pin_group pin
>> SH_PFC_PIN_GROUP(i2c4),
>> SH_PFC_PIN_GROUP(i2c4_b),
>> SH_PFC_PIN_GROUP(i2c4_c),
>> - SH_PFC_PIN_GROUP(i2c7),
>> - SH_PFC_PIN_GROUP(i2c7_b),
>> - SH_PFC_PIN_GROUP(i2c7_c),
>> - SH_PFC_PIN_GROUP(i2c8),
>> - SH_PFC_PIN_GROUP(i2c8_b),
>> - SH_PFC_PIN_GROUP(i2c8_c),
>> + SH_PFC_PIN_GROUP(iic0),
>> + SH_PFC_PIN_GROUP(iic0_b),
>> + SH_PFC_PIN_GROUP(iic0_c),
>> + SH_PFC_PIN_GROUP(iic1),
>> + SH_PFC_PIN_GROUP(iic1_b),
>> + SH_PFC_PIN_GROUP(iic1_c),
>
> I do object against renaming the user-visible names, like pin groups...
>
>> @@ -5298,8 +5305,8 @@ static const struct sh_pfc_function pinm
>> SH_PFC_FUNCTION(i2c2),
>> SH_PFC_FUNCTION(i2c3),
>> SH_PFC_FUNCTION(i2c4),
>> - SH_PFC_FUNCTION(i2c7),
>> - SH_PFC_FUNCTION(i2c8),
>> + SH_PFC_FUNCTION(iic0),
>> + SH_PFC_FUNCTION(iic1),
>
> ... and pin functions. Technically, they are part of the DT bindings,
> and thus are not allowed to change.
>
> IMHO either the user-visible names should be left alone, or the new names
> should be added as alternatives, next to the existing names.
If we go the second route, that could easily be supported using new
SH_PFC_PIN_GROUP_ALIAS() and SH_PFC_FUNCTION_ALIAS() macros,
to be used like
SH_PFC_PIN_GROUP(i2c7, iic0);
SH_PFC_FUNCTION_ALIAS(i2c7, iic0);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] pinctrl: sh-pfc: r8a7791: fix IPSR comment typos
Hi Sergii,
On Fri, Mar 31, 2017 at 10:29 PM, Sergei Shtylyov
wrote:
> The IPSR field names in the comments have been fat-fingered in a couple
> places -- fix those silly typos...
Thanks!
> Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support")
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Geert Uytterhoeven
> ---
> This patch is against the 'fixes' branch of Linus Walleij's
> 'linux-pinctrl.git'
> repo plus 3 R8A7791 fixes posted in the last couple days...
>
> drivers/pinctrl/sh-pfc/pfc-r8a7791.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> ===
> --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> @@ -5711,7 +5711,7 @@ static const struct pinmux_cfg_reg pinmu
> },
> { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
> 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
> - /* IP2_31_20 [2] */
> + /* IP2_31_30 [2] */
> 0, 0, 0, 0,
> /* IP2_29_27 [3] */
> FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
There's another one a few lines below:
- /* IP2_12_0 [3] */
+ /* IP2_12_10 [3] */
I'll fix that up when applying...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
