Re: [RFC v3 11/25] watchdog: renesas_wdt: Add R-Car Gen2 support
On Tue, Jan 30, 2018 at 08:22:44PM +, Fabrizio Castro wrote:
> On R-Car Gen2 and RZ/G1 the rwdt clock needs to be always ON, therefore
> when suspending to RAM we need to explicitly disable the counting by
> clearing TME from RWTCSRA.
> Also, on some systems RWDT is the only piece of HW that allows the SoC
> to be restarted, therefore this patch implements the restart callback.
>
> Signed-off-by: Fabrizio Castro
> Signed-off-by: Ramesh Shanmugasundaram
>
> ---
> Wolfram, was the restart callback implementation missing for a reason?
> Is its implementation going to break any Gen3 platform?
>
The changes clearly are way more than claimed in the subject. Adding
restart handler and PM support may be prerequisites for Gen2, but the
changes apply to Gen3 as well. What happened to "one patch per logical
change" ?
> v1->v3:
> * unified Gen2 and Gen3 drivers.
>
> drivers/watchdog/renesas_wdt.c | 61
> ++
> 1 file changed, 56 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index 831ef83..eedb016 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -107,6 +107,24 @@ static unsigned int rwdt_get_timeleft(struct
> watchdog_device *wdev)
> return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
> }
>
> +static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
> + void *data)
> +{
> + struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
> +
> + pm_runtime_get_sync(wdev->parent);
> +
> + rwdt_write(priv, 0x00, RWTCSRB);
> + rwdt_write(priv, 0x00, RWTCSRA);
> + rwdt_write(priv, 0x, RWTCNT);
> +
> + while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
> + cpu_relax();
> +
> + rwdt_write(priv, 0x80, RWTCSRA);
> + return 0;
> +}
> +
> static const struct watchdog_info rwdt_ident = {
> .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
> .identity = "Renesas WDT Watchdog",
> @@ -118,6 +136,7 @@ static const struct watchdog_ops rwdt_ops = {
> .stop = rwdt_stop,
> .ping = rwdt_init_timeout,
> .get_timeleft = rwdt_get_timeleft,
> + .restart = rwdt_restart,
> };
>
> static int rwdt_probe(struct platform_device *pdev)
> @@ -203,13 +222,42 @@ static int rwdt_remove(struct platform_device *pdev)
> return 0;
> }
>
> -/*
> - * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for
> SMP
> - * to work there, one also needs a RESET (RST) driver which does not exist
> yet
> - * due to HW issues. This needs to be solved before adding compatibles here.
> - */
Have those issues been resolved ?
> +#ifdef CONFIG_PM
> +static int rwdt_suspend(struct device *dev)
> +{
> + struct platform_device *pdev;
> + struct rwdt_priv *priv;
> +
> + pdev = to_platform_device(dev);
> + priv = platform_get_drvdata(pdev);
> + if (watchdog_active(&priv->wdev)) {
> + rwdt_write(priv, priv->cks, RWTCSRA);
> + }
> + return 0;
> +}
> +
> +static int rwdt_resume(struct device *dev)
> +{
> + struct platform_device *pdev;
> + struct rwdt_priv *priv;
> +
> + pdev = to_platform_device(dev);
> + priv = platform_get_drvdata(pdev);
> + if (watchdog_active(&priv->wdev)) {
> + rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
> + }
> + return 0;
> +}
> +
> +static const struct dev_pm_ops rwdt_pm = {
> + .suspend = rwdt_suspend,
> + .resume = rwdt_resume,
> +};
> +#endif
> +
> static const struct of_device_id rwdt_ids[] = {
> { .compatible = "renesas,rcar-gen3-wdt", },
> + { .compatible = "renesas,rcar-gen2-wdt", },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, rwdt_ids);
> @@ -218,6 +266,9 @@ static struct platform_driver rwdt_driver = {
> .driver = {
> .name = "renesas_wdt",
> .of_match_table = rwdt_ids,
> +#ifdef CONFIG_PM
> + .pm = &rwdt_pm,
> +#endif
> },
> .probe = rwdt_probe,
> .remove = rwdt_remove,
> --
> 2.7.4
>
[RFC v3 25/25] ARM: dts: iwg22m: Add watchdog support to SoM dtsi
This patch enables the watchdog from within the iwg20m SoM dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* no change
arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index 8d0a392b..29b6e10 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -91,6 +91,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
--
2.7.4
[RFC v3 24/25] ARM: dts: iwg20m: Add watchdog support to SoM dtsi
This patch enables the watchdog from within the iwg20m SoM dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* no change
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 1d3e950..d364685 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -91,6 +91,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
--
2.7.4
[RFC v3 18/25] clk: renesas: r8a7794: Add rwdt clock
Add "rwdt" clock to r8a7794_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* no change
drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index ec091a4..2a40bbe 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -121,6 +121,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[]
__initconst = {
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7794_CLK_R),
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
@@ -190,6 +191,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[]
__initconst = {
};
static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402),/* RWDT */
MOD_CLK_ID(408),/* INTC-SYS (GIC) */
};
--
2.7.4
[RFC v3 23/25] ARM: dts: r8a7794: Add watchdog support to SoC dtsi
This commit adds watchdog support to the r8a7794 dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* rwdt moved before gpio@e605
arch/arm/boot/dts/r8a7794.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index e47c5f4..1c9b149 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -119,6 +119,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7794-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a7794",
"renesas,rcar-gen2-gpio";
--
2.7.4
[RFC v3 21/25] ARM: dts: r8a7790: Add watchdog support to SoC dtsi
This commit adds watchdog support to the r8a7790 dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* rwdt moved before gpio@e605
arch/arm/boot/dts/r8a7790.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a84bf35..83d6704 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -218,6 +218,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7790-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a7790",
"renesas,rcar-gen2-gpio";
--
2.7.4
[RFC v3 19/25] ARM: dts: r8a7743: Add watchdog support to SoC dtsi
This patch adds watchdog support to the r8a7743 SoC dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* no change
arch/arm/boot/dts/r8a7743.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index c2943d7..1d4505f 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -368,6 +368,16 @@
reg = <0 0xe616 0 0x100>;
};
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7743-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7743-sysc";
reg = <0 0xe618 0 0x200>;
--
2.7.4
[RFC v3 22/25] ARM: dts: r8a7791: Add watchdog support to SoC dtsi
This commit adds watchdog support to the r8a7791 dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* rwdt moved before gpio@e605
arch/arm/boot/dts/r8a7791.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index d2a4546..80e20ecd 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -142,6 +142,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7791-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a7791",
"renesas,rcar-gen2-gpio";
--
2.7.4
[RFC v3 16/25] clk: renesas: r8a7790: Add rwdt clock
Add "rwdt" clock to r8a7790_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* no change
drivers/clk/renesas/r8a7790-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c
b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 46bb55b..f936cb7 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -140,6 +140,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[]
__initconst = {
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7790_CLK_R),
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
@@ -211,6 +212,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[]
__initconst = {
};
static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402),/* RWDT */
MOD_CLK_ID(408),/* INTC-SYS (GIC) */
};
--
2.7.4
[RFC v3 17/25] clk: renesas: r8a7791/r8a7793: Add rwdt clock
Add "rwdt" clock to r8a7791_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* no change
drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index c0b51f9..820b220 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[]
__initconst = {
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7791_CLK_R),
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
@@ -209,6 +210,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[]
__initconst = {
};
static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402),/* RWDT */
MOD_CLK_ID(408),/* INTC-SYS (GIC) */
};
--
2.7.4
[RFC v3 20/25] ARM: dts: r8a7745: Add watchdog support to SoC dtsi
This patch adds watchdog support to the r8a7745 SoC dtsi.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
Reviewed-by: Geert Uytterhoeven
---
v1->v3:
* no change
arch/arm/boot/dts/r8a7745.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6bc1cf4..5d1b8f2 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -321,6 +321,16 @@
reg = <0 0xe616 0 0x100>;
};
+ rwdt: watchdog@e602 {
+ compatible = "renesas,r8a7745-wdt",
+"renesas,rcar-gen2-wdt";
+ reg = <0 0xe602 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
sysc: system-controller@e618 {
compatible = "renesas,r8a7745-sysc";
reg = <0 0xe618 0 0x200>;
--
2.7.4
[RFC v3 15/25] clk: renesas: r8a7745: Add rwdt clock
Add "rwdt" clock to r8a7745_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* no change
drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c
b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 2859504..87f5a36 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -114,6 +114,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[]
__initconst = {
DEF_MOD("cmt1", 329, R8A7745_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7745_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7745_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7745_CLK_R),
DEF_MOD("irqc", 407, R8A7745_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7745_CLK_ZS),
DEF_MOD("audio-dmac0", 502, R8A7745_CLK_HP),
@@ -180,6 +181,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[]
__initconst = {
};
static const unsigned int r8a7745_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402),/* RWDT */
MOD_CLK_ID(408),/* INTC-SYS (GIC) */
};
--
2.7.4
[RFC v3 13/25] ARM: shmobile: defconfig: Enable CONFIG_RENESAS_WDT
R-Car Gen2 and RZ/G1 platforms come with a watchdog IP, therefore enable its driver by default. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram --- v1->v3: * CONFIG_RENESAS_WDT_GEN2 -> CONFIG_RENESAS_WDT arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 578434c..d5cdad8 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -132,6 +132,7 @@ CONFIG_CPU_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=y +CONFIG_RENESAS_WDT=y CONFIG_MFD_AS3711=y CONFIG_MFD_DA9063=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -- 2.7.4
[RFC v3 14/25] clk: renesas: r8a7743: Add rwdt clock
Add "rwdt" clock to r8a7743_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* no change
drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c
b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index 6dc0b30..d3c8b1e 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -117,6 +117,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[]
__initconst = {
DEF_MOD("cmt1", 329, R8A7743_CLK_R),
DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP),
DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP),
+ DEF_MOD("rwdt", 402, R8A7743_CLK_R),
DEF_MOD("irqc", 407, R8A7743_CLK_CP),
DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS),
DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP),
@@ -195,6 +196,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[]
__initconst = {
};
static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(402),/* RWDT */
MOD_CLK_ID(408),/* INTC-SYS (GIC) */
};
--
2.7.4
[RFC v3 12/25] ARM: shmobile: rcar-gen2: Add watchdog support
This patch adds watchdog support by installing shmobile_boot_vector_gen2
to ICRAM1 when enough memory is available, in which case we also keep a
copy of MPIDR to complete the reset vector logic.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v2->v3:
* purge shmobile_wdt_clock status and save mpidr of boot cpu
v1->v2:
* make the reset vector backward compatible
arch/arm/mach-shmobile/platsmp-apmu.c | 1 +
arch/arm/mach-shmobile/pm-rcar-gen2.c | 13 ++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c
b/arch/arm/mach-shmobile/platsmp-apmu.c
index 4422b61..ba732ef 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -191,6 +191,7 @@ static void __init shmobile_smp_apmu_setup_boot(void)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
+ shmobile_boot_fn_gen2 = shmobile_boot_fn;
}
void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index e5f215c..bfad202 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include "common.h"
#include "rcar-gen2.h"
@@ -37,7 +38,6 @@
#define CA7RESCNT_CODE 0x5a5a
#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
-
/* On-chip RAM */
#define ICRAM1 0xe63c /* Inter Connect RAM1 (4 KiB) */
@@ -119,8 +119,15 @@ void __init rcar_gen2_pm_init(void)
p = ioremap(res.start, resource_size(&res));
if (!p)
return;
-
- memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+ /* install the reset vector, use the largest version if we have enough
+* memory available */
+ if (resource_size(&res) >= shmobile_boot_size_gen2) {
+ shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
+ memcpy_toio(p, shmobile_boot_vector_gen2,
+ shmobile_boot_size_gen2);
+ } else {
+ memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
+ }
iounmap(p);
/* setup reset vectors */
--
2.7.4
[RFC v3 10/25] dt-bindings: watchdog: renesas-wdt: Add R-Car Gen2 support
This commit documents the compatibility with R-Car Gen2 and RZ/G devices by defining the generic compatible string "renesas,rcar-gen2-wdt". Also, this patch expands the list of SoC-specific compatible strings to include RZ/G and R-Car Gen2 devices. Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram --- v1->v3: * made description less generic and added compatible strings for r8a779[0-4] .../devicetree/bindings/watchdog/renesas-wdt.txt | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt index bf6d1ca..a983a74 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt @@ -1,17 +1,25 @@ Renesas Watchdog Timer (WDT) Controller Required properties: -- compatible : Should be "renesas,-wdt", and - "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback. + - compatible : Must be "renesas,-wdt", followed by a generic + fallback compatible string when compatible with the generic + version. Examples with soctypes are: +- "renesas,r8a7743-wdt" (RZ/G1M) +- "renesas,r8a7745-wdt" (RZ/G1E) +- "renesas,r8a7790-wdt" (R-Car H2) +- "renesas,r8a7791-wdt" (R-Car M2-W) +- "renesas,r8a7792-wdt" (R-Car V2H) +- "renesas,r8a7793-wdt" (R-Car M2-N) +- "renesas,r8a7794-wdt" (R-Car E2) - "renesas,r8a7795-wdt" (R-Car H3) - "renesas,r8a7796-wdt" (R-Car M3-W) - "renesas,r8a77995-wdt" (R-Car D3) - "renesas,r7s72100-wdt" (RZ/A1) + The generic compatible string must be: +- "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G +- "renesas,rcar-gen3-wdt" for R-Car Gen3 - When compatible with the generic version, nodes must list the SoC-specific - version corresponding to the platform first, followed by the generic - version. - reg : Should contain WDT registers location and length - clocks : the clock feeding the watchdog timer. -- 2.7.4
[RFC v3 11/25] watchdog: renesas_wdt: Add R-Car Gen2 support
On R-Car Gen2 and RZ/G1 the rwdt clock needs to be always ON, therefore
when suspending to RAM we need to explicitly disable the counting by
clearing TME from RWTCSRA.
Also, on some systems RWDT is the only piece of HW that allows the SoC
to be restarted, therefore this patch implements the restart callback.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
Wolfram, was the restart callback implementation missing for a reason?
Is its implementation going to break any Gen3 platform?
v1->v3:
* unified Gen2 and Gen3 drivers.
drivers/watchdog/renesas_wdt.c | 61 ++
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index 831ef83..eedb016 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -107,6 +107,24 @@ static unsigned int rwdt_get_timeleft(struct
watchdog_device *wdev)
return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
}
+static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
+ void *data)
+{
+ struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
+
+ pm_runtime_get_sync(wdev->parent);
+
+ rwdt_write(priv, 0x00, RWTCSRB);
+ rwdt_write(priv, 0x00, RWTCSRA);
+ rwdt_write(priv, 0x, RWTCNT);
+
+ while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
+ cpu_relax();
+
+ rwdt_write(priv, 0x80, RWTCSRA);
+ return 0;
+}
+
static const struct watchdog_info rwdt_ident = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
.identity = "Renesas WDT Watchdog",
@@ -118,6 +136,7 @@ static const struct watchdog_ops rwdt_ops = {
.stop = rwdt_stop,
.ping = rwdt_init_timeout,
.get_timeleft = rwdt_get_timeleft,
+ .restart = rwdt_restart,
};
static int rwdt_probe(struct platform_device *pdev)
@@ -203,13 +222,42 @@ static int rwdt_remove(struct platform_device *pdev)
return 0;
}
-/*
- * This driver does also fit for R-Car Gen2 (r8a779[0-4]) WDT. However, for SMP
- * to work there, one also needs a RESET (RST) driver which does not exist yet
- * due to HW issues. This needs to be solved before adding compatibles here.
- */
+#ifdef CONFIG_PM
+static int rwdt_suspend(struct device *dev)
+{
+ struct platform_device *pdev;
+ struct rwdt_priv *priv;
+
+ pdev = to_platform_device(dev);
+ priv = platform_get_drvdata(pdev);
+ if (watchdog_active(&priv->wdev)) {
+ rwdt_write(priv, priv->cks, RWTCSRA);
+ }
+ return 0;
+}
+
+static int rwdt_resume(struct device *dev)
+{
+ struct platform_device *pdev;
+ struct rwdt_priv *priv;
+
+ pdev = to_platform_device(dev);
+ priv = platform_get_drvdata(pdev);
+ if (watchdog_active(&priv->wdev)) {
+ rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
+ }
+ return 0;
+}
+
+static const struct dev_pm_ops rwdt_pm = {
+ .suspend = rwdt_suspend,
+ .resume = rwdt_resume,
+};
+#endif
+
static const struct of_device_id rwdt_ids[] = {
{ .compatible = "renesas,rcar-gen3-wdt", },
+ { .compatible = "renesas,rcar-gen2-wdt", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rwdt_ids);
@@ -218,6 +266,9 @@ static struct platform_driver rwdt_driver = {
.driver = {
.name = "renesas_wdt",
.of_match_table = rwdt_ids,
+#ifdef CONFIG_PM
+ .pm = &rwdt_pm,
+#endif
},
.probe = rwdt_probe,
.remove = rwdt_remove,
--
2.7.4
[RFC v3 05/25] ARM: dts: r8a7791: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index dc65935..d2a4546 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -407,7 +407,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 09/25] soc: renesas: rcar-rst: Enable watchdog as reset trigger for Gen2
This patch allows for platform specific quirks as some of the SoC need
further customization for the watchdog to work properly, like for R-Car
Gen2 and for RZ/G.
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* gen2_configuration -> rcar_rst_enable_wdt_reset
drivers/soc/renesas/rcar-rst.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 3316b02..93febe6 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -13,8 +13,18 @@
#include
#include
+#define WDTRSTCR_RESET 0xA55A0002
+#define WDTRSTCR 0x0054
+
+static int rcar_rst_enable_wdt_reset(void __iomem *base)
+{
+ iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
+ return 0;
+}
+
struct rst_config {
- unsigned int modemr;/* Mode Monitoring Register Offset */
+ unsigned int modemr;/* Mode Monitoring Register Offset */
+ int (*configure)(void *base); /* Platform specific configuration */
};
static const struct rst_config rcar_rst_gen1 __initconst = {
@@ -23,6 +33,11 @@ static const struct rst_config rcar_rst_gen1 __initconst = {
static const struct rst_config rcar_rst_gen2 __initconst = {
.modemr = 0x60,
+ .configure = rcar_rst_enable_wdt_reset,
+};
+
+static const struct rst_config rcar_rst_gen3 __initconst = {
+ .modemr = 0x60,
};
static const struct of_device_id rcar_rst_matches[] __initconst = {
@@ -38,11 +53,11 @@ static const struct of_device_id rcar_rst_matches[]
__initconst = {
{ .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
{ .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
- /* R-Car Gen3 is handled like R-Car Gen2 */
- { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 },
- { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 },
- { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 },
- { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 },
+ /* R-Car Gen3 */
+ { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
{ /* sentinel */ }
};
@@ -71,6 +86,14 @@ static int __init rcar_rst_init(void)
rcar_rst_base = base;
cfg = match->data;
saved_mode = ioread32(base + cfg->modemr);
+ if (cfg->configure) {
+ error = cfg->configure(base);
+ if (error) {
+ pr_warn("%pOF: Cannot run SoC specific configuration\n",
+ np);
+ goto out_put;
+ }
+ }
pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
--
2.7.4
[RFC v3 07/25] ARM: dts: r8a7793: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index aa7d779..bde6969 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -392,7 +392,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 04/25] ARM: dts: r8a7790: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 3bbcc0b..a84bf35 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -443,7 +443,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 08/25] ARM: dts: r8a7794: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d588efa..e47c5f4 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -348,7 +348,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 06/25] ARM: dts: r8a7792: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7792.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 268987f..bea0f12 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -341,7 +341,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 03/25] ARM: dts: r8a7745: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7745.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index ddc3da2..6bc1cf4 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -755,7 +755,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 01/25] ARM: shmobile: Add watchdog support
On R-Car Gen2 and RZ/G1 platforms, we use the SBAR registers to make non boot CPUs run a routine designed to bring up SMP and deal with hot plug. The value contained in the SBAR registers is not initialized by a WDT triggered reset, which means that after a WDT triggered reset we jump to the SMP bring up routine, preventing the system from executing the bootrom code. The purpose of this patch is to jump to the bootrom code in case of a WDT triggered reset, and keep the SMP functionality untouched. In order to tell if the code had been called due to the WDT overflowing we are testing WOVF from register RWTCSRA. The new function shmobile_boot_vector_gen2 isn't replacing shmobile_boot_vector for backward compatibility reasons. The kernel will install the best option (either shmobile_boot_vector or shmobile_boot_vector_gen2) to ICRAM1 after parsing the device tree, according to the amount of memory available. Since shmobile_boot_vector has become bigger, "reg" property of nodes compatible with "renesas,smp-sram" now need to be set to a value greater or equal to "<0 0x60>". Signed-off-by: Fabrizio Castro Signed-off-by: Ramesh Shanmugasundaram --- v2->v3: * purge shmobile_wdt_clock_status variable, and add shmobile_boot_cpu_gen2 v1->v2: * reinstated shmobile_boot_vector and added shmobile_boot_vector_gen2 arch/arm/mach-shmobile/common.h | 6 + arch/arm/mach-shmobile/headsmp.S | 55 2 files changed, 61 insertions(+) diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h index a8fa4f7..d8c11f5 100644 --- a/arch/arm/mach-shmobile/common.h +++ b/arch/arm/mach-shmobile/common.h @@ -7,6 +7,12 @@ extern void shmobile_init_delay(void); extern void shmobile_boot_vector(void); extern unsigned long shmobile_boot_fn; extern unsigned long shmobile_boot_size; +#ifdef CONFIG_ARCH_RCAR_GEN2 +extern void shmobile_boot_vector_gen2(void); +extern unsigned long shmobile_boot_fn_gen2; +extern unsigned long shmobile_boot_cpu_gen2; +extern unsigned long shmobile_boot_size_gen2; +#endif /* CONFIG_ARCH_RCAR_GEN2 */ extern void shmobile_smp_boot(void); extern void shmobile_smp_sleep(void); extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 32e0bf6..cef8e8c 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,6 +16,11 @@ #include #include +#define SCTLR_MMU 0x01 +#define BOOTROM_ADDRESS0xE634 +#define RWTCSRA_ADDRESS 0xE6020004 +#define RWTCSRA_WOVF 0x10 + /* * Reset vector for secondary CPUs. * This will be mapped at address 0 by SBAR register. @@ -37,6 +42,56 @@ shmobile_boot_fn: shmobile_boot_size: .long . - shmobile_boot_vector +#ifdef CONFIG_ARCH_RCAR_GEN2 +/* + * Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs. + * This will be mapped at address 0 by SBAR register. + */ +ENTRY(shmobile_boot_vector_gen2) + mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR + ldr r1, shmobile_boot_cpu_gen2 + cmp r0, r1 + bne shmobile_smp_continue_gen2 + + mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR + and r0, r1, #SCTLR_MMU + cmp r0, #SCTLR_MMU + beq shmobile_smp_continue_gen2 + + ldr r0, rwtcsra + mov r1, #0 + ldrbr1, [r0] + and r0, r1, #RWTCSRA_WOVF + cmp r0, #RWTCSRA_WOVF + bne shmobile_smp_continue_gen2 + + ldr r0, bootrom + bx r0 + +shmobile_smp_continue_gen2: + ldr r1, shmobile_boot_fn_gen2 + bx r1 + +ENDPROC(shmobile_boot_vector_gen2) + + .align 4 +rwtcsra: + .word RWTCSRA_ADDRESS +bootrom: + .word BOOTROM_ADDRESS + .globl shmobile_boot_cpu_gen2 +shmobile_boot_cpu_gen2: + .word 0x + + .align 2 + .globl shmobile_boot_fn_gen2 +shmobile_boot_fn_gen2: + .space 4 + .globl shmobile_boot_size_gen2 +shmobile_boot_size_gen2: + .long . - shmobile_boot_vector_gen2 +#endif /* CONFIG_ARCH_RCAR_GEN2 */ + /* * Per-CPU SMP boot function/argument selection code based on MPIDR */ -- 2.7.4
[RFC v3 02/25] ARM: dts: r8a7743: Adjust SMP routine size
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro
Signed-off-by: Ramesh Shanmugasundaram
---
v1->v3:
* increased size to 0x100
arch/arm/boot/dts/r8a7743.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 47b62f6..c2943d7 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -973,7 +973,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
- reg = <0 0x10>;
+ reg = <0 0x100>;
};
};
--
2.7.4
[RFC v3 00/25] Fix watchdog on Renesas R-Car Gen2 and RZ/G1
Dear All, while trying to add watchdog support to RZ/G1M and RZ/G1E I discovered that it couldn't work out of the box. R-Car Gen2 and RZ/G1 are very similar from a design perspective, and therefore the same problem is observable on R-Car Gen2 too. To deal with SMP on R-Car Gen2 and RZ/G1, we install a reset vector to ICRAM1 and we program the [S]BAR registers so that when we turn ON the non-boot CPUs they are redirected to the reset vector installed by Linux in ICRAM1, and eventually they continue the execution to RAM, where the SMP bring-up code will take care of the rest. The content of the [S]BAR registers survives a watchdog triggered reset, and as such after the watchdog fires the boot core will try and execute the SMP bring-up code instead of jumping to the bootrom code. This series is a proposal for a fix to the aforementioned problem. The main strategy for the solution is to let the reset vector decide if it needs to jump to shmobile_boot_fn or to the bootrom code. In a watchdog triggered reset scenario, since the [S]BAR registers keep their values, the boot CPU will jump into the newly designed reset vector, the assembly routine will eventually test WOVF (a bit in register RWTCSRA that indicates if the watchdog counter has overflown, the value of this bit gets retained in this scenario), and jump to the bootrom code which will in turn load up the bootloader, etc. When bringing up SMP or using CPU hotplug, the reset vector will jump to shmobile_boot_fn instead. v3 takes into account all the feedbacks recieved, and implements a different logic in the reset vector in order to get rid of shmobile_wdt_clock_status. This work was rebased on top of tag renesas-devel-20180122-v4.15-rc9 from the below repository: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git What do you guys think about this? Any volunteer for testing this work? Comments welcome! Best Regards, Fabrizio Castro (25): ARM: shmobile: Add watchdog support ARM: dts: r8a7743: Adjust SMP routine size ARM: dts: r8a7745: Adjust SMP routine size ARM: dts: r8a7790: Adjust SMP routine size ARM: dts: r8a7791: Adjust SMP routine size ARM: dts: r8a7792: Adjust SMP routine size ARM: dts: r8a7793: Adjust SMP routine size ARM: dts: r8a7794: Adjust SMP routine size soc: renesas: rcar-rst: Enable watchdog as reset trigger for Gen2 dt-bindings: watchdog: renesas-wdt: Add R-Car Gen2 support watchdog: renesas_wdt: Add R-Car Gen2 support ARM: shmobile: rcar-gen2: Add watchdog support ARM: shmobile: defconfig: Enable RENESAS_WDT_GEN clk: renesas: r8a7743: Add rwdt clock clk: renesas: r8a7745: Add rwdt clock clk: renesas: r8a7790: Add rwdt clock clk: renesas: r8a7791/r8a7793: Add rwdt clock clk: renesas: r8a7794: Add rwdt clock ARM: dts: r8a7743: Add watchdog support to SoC dtsi ARM: dts: r8a7745: Add watchdog support to SoC dtsi ARM: dts: r8a7790: Add watchdog support to SoC dtsi ARM: dts: r8a7791: Add watchdog support to SoC dtsi ARM: dts: r8a7794: Add watchdog support to SoC dtsi ARM: dts: iwg20m: Add watchdog support to SoM dtsi ARM: dts: iwg22m: Add watchdog support to SoM dtsi .../devicetree/bindings/watchdog/renesas-wdt.txt | 18 +-- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 5 ++ arch/arm/boot/dts/r8a7743.dtsi | 12 - arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 5 ++ arch/arm/boot/dts/r8a7745.dtsi | 12 - arch/arm/boot/dts/r8a7790.dtsi | 12 - arch/arm/boot/dts/r8a7791.dtsi | 12 - arch/arm/boot/dts/r8a7792.dtsi | 2 +- arch/arm/boot/dts/r8a7793.dtsi | 2 +- arch/arm/boot/dts/r8a7794.dtsi | 12 - arch/arm/configs/shmobile_defconfig| 1 + arch/arm/mach-shmobile/common.h| 6 +++ arch/arm/mach-shmobile/headsmp.S | 55 +++ arch/arm/mach-shmobile/platsmp-apmu.c | 1 + arch/arm/mach-shmobile/pm-rcar-gen2.c | 13 +++-- drivers/clk/renesas/r8a7743-cpg-mssr.c | 2 + drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 + drivers/clk/renesas/r8a7790-cpg-mssr.c | 2 + drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 + drivers/clk/renesas/r8a7794-cpg-mssr.c | 2 + drivers/soc/renesas/rcar-rst.c | 35 ++--- drivers/watchdog/renesas_wdt.c | 61 -- 22 files changed, 248 insertions(+), 26 deletions(-) -- 2.7.4
Re: [PATCH v2 0/9] ARM: dts: gen2: add IP core switcher for all busses
On Tue, Jan 30, 2018 at 11:51:37AM +0100, Wolfram Sang wrote: > On Sun, Dec 31, 2017 at 12:23:11PM +0100, Wolfram Sang wrote: > > Here is the updated series to add the I2C IP core switcher to all busses of > > Gen2 boards where some kind of switching is possible (mostly to/from GPIO). > > > > These patches were tested locally on Lager and Alt, and remotely on Koelsch, > > Porter and Gose. We have no Silk board available but the patch follows the > > same > > style as the other patches. In addition, these patches have been > > double-checked > > by vimdiff-comparing the i2c-bus blobs before and after this patchset. > > > > As discussed previously: the tested boards boot fine. No regression > > encountered > > there. However, changing masters at runtime for HDMI-named busses and > > PWR-named > > busses will likely cause kernel warnings and maybe OOPSes. This is due to > > the > > rebind-issues in the V4L and regulator subsystems. For the former, fixing is > > WIP. For the latter, it is unknown how to deal with rebinding in general > > (but > > I'd need to look at this issue again if this is desired). It was decided > > that > > we consider those follow-up problems which should not hold back these > > patches > > anymore. The EXIO named busses seemed to work fine as far as this could be > > remotely tested. > > > > Changes since V1: > > > > * fixed I2C4 pinmux for Koelsch and Gose (thanks Geert for the report!) > > * rebased to current renesas/dt-for-v4.16 > > * fixed typo in branch name (s/topc/topic/) > > > > The branch can be found here: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git > > renesas/topic/ip-switch-rework-2017 > > > > It is based on v4.15-rc1 + renesas/dt-for-v4.16 merged in. > > > > Please review, comment... > > Simon, any issues left before applying this series? I'm a bit uncomfortable about the OOpses, but if that was the consensus (in San Sebastian?) then I'm happy to accept these patches. Could you rebase the series? It does not seem to apply (likely due to my recent clean-up efforts).
[PATCH] mmc: MMC_SDHI_{SYS,INTERNAL}_DMAC should depend on HAS_DMA
If NO_DMA=y:
ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_sys_dmac.ko] undefined!
ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_internal_dmac.ko]
undefined!
Add dependencies on HAS_DMA to fix this.
Fixes: e578afab6e5f57e7 ("mmc: renesas_sdhi: remove wrong depends on to enable
compile test")
Signed-off-by: Geert Uytterhoeven
---
drivers/mmc/host/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 67bd3344dd03a1ae..0eae619419d9ddeb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -605,7 +605,7 @@ config MMC_SDHI
config MMC_SDHI_SYS_DMAC
tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
- depends on MMC_SDHI
+ depends on MMC_SDHI && HAS_DMA
default MMC_SDHI if (SUPERH || ARM)
help
This provides DMA support for SDHI SD/SDIO controllers
@@ -615,7 +615,7 @@ config MMC_SDHI_SYS_DMAC
config MMC_SDHI_INTERNAL_DMAC
tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
depends on ARM64 || COMPILE_TEST
- depends on MMC_SDHI
+ depends on MMC_SDHI && HAS_DMA
default MMC_SDHI if ARM64
help
This provides DMA support for SDHI SD/SDIO controllers
--
2.7.4
renesas-drivers-2018-01-30-v4.15
I have pushed renesas-drivers-2018-01-30-v4.15 to
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
This tree is meant to ease development of platform support and drivers
for Renesas ARM SoCs. It is created by merging (a) the for-next branches
of various subsystem trees and (b) branches with driver code submitted
or planned for submission to maintainers into the development branch of
Simon Horman's renesas.git tree.
Today's version is based on renesas-devel-20180129-v4.15.
Included branches with driver code:
- clk-renesas
- sh-pfc
- topic/rcar-genpd-wakeup-v3-rebased1
- topic/r8a77970-eagle-pfc-v1
- topic/r8a77970-eagle-gpio-v1
- topic/r8a77970-eagle-i2c-v1
- topic/25lc040-dt-v2
-
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git#topic/rcar-gen3-z-clk-v5
-
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git#topic/cpufreq-automatic
-
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git#topic/rcar-gen3-cpufreq-little-dts
-
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git#topic/ipmmu-driver-v6
- git://linuxtv.org/pinchartl/media.git#drm-du-iommu-v1-20171115
- git://linuxtv.org/pinchartl/media.git#tags/vsp1-discom-v1-20171215
- git://linuxtv.org/pinchartl/media.git#tags/drm-next-colorkey-v1-20171215
-
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git#renesas/topic/ip-switch-rework-2017
- git://git.ragnatech.se/linux#for-renesas-drivers
Included fixes:
- regulator: Fix s2idle
- [LOCAL] arm64: defconfig: Update renesas_defconfig
Included subsystem trees:
- git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git#linux-next
- git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-next
-
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-next
- git://git.infradead.org/users/dedekind/l2-mtd-2.6.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git#tty-next
- git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git#i2c/for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#usb-next
- git://people.freedesktop.org/~airlied/linux#drm-next
- git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git#next
- git://linuxtv.org/mchehab/media-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git#for-next
- git://git.linaro.org/people/daniel.lezcano/linux.git#clockevents/next
- git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git#testing/next
- git://git.infradead.org/users/vkoul/slave-dma.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git#staging-next
- git://git.armlinux.org.uk/~rmk/linux-arm.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-next
- git://git.infradead.org/users/jcooper/linux.git#irqchip/for-next
- git://github.com/bzolnier/linux.git#fbdev-for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git#for-next
-
git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#for-next
- git://www.linux-watchdog.org/linux-watchdog-next.git#master
- git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-next
- git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git#for-next/core
- git://anongit.freedesktop.org/drm/drm-misc#for-linux-next
- git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git#next
-
git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git#next
- git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-next
- git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v2 0/9] ARM: dts: gen2: add IP core switcher for all busses
On Sun, Dec 31, 2017 at 12:23:11PM +0100, Wolfram Sang wrote: > Here is the updated series to add the I2C IP core switcher to all busses of > Gen2 boards where some kind of switching is possible (mostly to/from GPIO). > > These patches were tested locally on Lager and Alt, and remotely on Koelsch, > Porter and Gose. We have no Silk board available but the patch follows the > same > style as the other patches. In addition, these patches have been > double-checked > by vimdiff-comparing the i2c-bus blobs before and after this patchset. > > As discussed previously: the tested boards boot fine. No regression > encountered > there. However, changing masters at runtime for HDMI-named busses and > PWR-named > busses will likely cause kernel warnings and maybe OOPSes. This is due to the > rebind-issues in the V4L and regulator subsystems. For the former, fixing is > WIP. For the latter, it is unknown how to deal with rebinding in general (but > I'd need to look at this issue again if this is desired). It was decided that > we consider those follow-up problems which should not hold back these patches > anymore. The EXIO named busses seemed to work fine as far as this could be > remotely tested. > > Changes since V1: > > * fixed I2C4 pinmux for Koelsch and Gose (thanks Geert for the report!) > * rebased to current renesas/dt-for-v4.16 > * fixed typo in branch name (s/topc/topic/) > > The branch can be found here: > > git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git > renesas/topic/ip-switch-rework-2017 > > It is based on v4.15-rc1 + renesas/dt-for-v4.16 merged in. > > Please review, comment... Simon, any issues left before applying this series? signature.asc Description: PGP signature
Re: [PATCH v2 5/5] dt-bindings: at24: add bindings for Rohm BR24T01
On Mon, Jan 29, 2018 at 04:45:48PM +0100, Ulrich Hecht wrote: > Both manufacturer and name variant. > > Signed-off-by: Ulrich Hecht Reviewed-by: Wolfram Sang signature.asc Description: PGP signature
Re: [PATCH v2 3/5] arm64: renesas: draak: enable I2C controller 1
On Mon, Jan 29, 2018 at 04:45:46PM +0100, Ulrich Hecht wrote: > No devices to add, I2C1 has an external connector only. > > Signed-off-by: Ulrich Hecht > Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang signature.asc Description: PGP signature
Re: [PATCH v2 2/5] arm64: renesas: draak: enable I2C controller 0 and EEPROM
On Mon, Jan 29, 2018 at 04:45:45PM +0100, Ulrich Hecht wrote: > Enables EEPROM on I2C0 on the Draak board. > > Signed-off-by: Ulrich Hecht > Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang signature.asc Description: PGP signature
Re: [PATCH v2 1/5] arm64: renesas: r8a77995: add I2C support
On Mon, Jan 29, 2018 at 04:45:44PM +0100, Ulrich Hecht wrote: > Defines R-Car D3 I2C controllers 0-3. > > Signed-off-by: Ulrich Hecht > Reviewed-by: Geert Uytterhoeven Acked-by: Wolfram Sang signature.asc Description: PGP signature
[PATCH v8 01/11] dt-bindings: media: Add Renesas CEU bindings
Add bindings documentation for Renesas Capture Engine Unit (CEU).
Signed-off-by: Jacopo Mondi
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
Acked-by: Hans Verkuil
---
.../devicetree/bindings/media/renesas,ceu.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/renesas,ceu.txt
diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt
b/Documentation/devicetree/bindings/media/renesas,ceu.txt
new file mode 100644
index 000..3fc66df
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/renesas,ceu.txt
@@ -0,0 +1,81 @@
+Renesas Capture Engine Unit (CEU)
+--
+
+The Capture Engine Unit is the image capture interface found in the Renesas
+SH Mobile and RZ SoCs.
+
+The interface supports a single parallel input with data bus width of 8 or 16
+bits.
+
+Required properties:
+- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H
+ and RZ/A1M SoCs.
+- reg: Registers address base and size.
+- interrupts: The interrupt specifier.
+
+The CEU supports a single parallel input and should contain a single 'port'
+subnode with a single 'endpoint'. Connection to input devices are modeled
+according to the video interfaces OF bindings specified in:
+Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Optional endpoint properties applicable to parallel input bus described in
+the above mentioned "video-interfaces.txt" file are supported.
+
+- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH
respectively.
+ If property is not present, default is active high.
+- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH
respectively.
+ If property is not present, default is active high.
+
+Example:
+
+The example describes the connection between the Capture Engine Unit and an
+OV7670 image sensor connected to i2c1 interface.
+
+ceu: ceu@e821 {
+ reg = <0xe821 0x209c>;
+ compatible = "renesas,r7s72100-ceu";
+ interrupts = ;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ status = "okay";
+
+ port {
+ ceu_in: endpoint {
+ remote-endpoint = <&ov7670_out>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+i2c1: i2c@fcfee400 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+
+ clock-frequency = <10>;
+
+ ov7670: camera@21 {
+ compatible = "ovti,ov7670";
+ reg = <0x21>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vio_pins>;
+
+ reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov7670_out: endpoint {
+ remote-endpoint = <&ceu_in>;
+
+ hsync-active = <1>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
--
2.7.4
[PATCH v8 04/11] ARM: dts: r7s72100: Add Capture Engine Unit (CEU)
Add Capture Engine Unit (CEU) node to device tree.
Signed-off-by: Jacopo Mondi
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
Acked-by: Hans Verkuil
---
arch/arm/boot/dts/r7s72100.dtsi | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a..5fe62f9 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -135,9 +135,9 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xfcfe042c 4>;
- clocks = <&p0_clk>;
- clock-indices = ;
- clock-output-names = "rtc";
+ clocks = <&b_clk>, <&p0_clk>;
+ clock-indices = ;
+ clock-output-names = "ceu", "rtc";
};
mstp7_clks: mstp7_clks@fcfe0430 {
@@ -667,4 +667,13 @@
power-domains = <&cpg_clocks>;
status = "disabled";
};
+
+ ceu: ceu@e821 {
+ reg = <0xe821 0x3000>;
+ compatible = "renesas,r7s72100-ceu";
+ interrupts = ;
+ clocks = <&mstp6_clks R7S72100_CLK_CEU>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
+ };
};
--
2.7.4
[PATCH v8 00/11] Renesas Capture Engine Unit (CEU) V4L2 driver
Hello, this 8th round has two minor modifications compared to v7: - Fixed Geert's comments on RZ/A1-H/L/M in bindings documentation - Calculate the PLL divisor/multiplier to generate the proper pixel clock for ov772x in place of using static tables. Series based on top of Hans': [PATCHv2 0/9] media: replace g/s_parm by g/s_frame_interval and makes use of newly introduced v4l2_g/s_parm_cap() functions from v4l2-common in CEU's g/s_parm() callbacks. A branch for testing is available at: git://jmondi.org/linux ceu/media-tree-parm/base with few patches for Migo-R and GR-Peach applied on top of Hans' media-tree/parm branch. Copying from v7 cover letter: The 2 new patches in the series: [11/11] has been added to silence a v4l2-compliance error, and modifies ov7670 driver to set all fields of 'struct v4l2_mbus_format' during set_format operation, including ycbcr_enc, quantization and xfer_func. As the patch commit reports, this suppresses the following v4l2-compliance error: fail: v4l2-test-formats.cpp(335): ycbcr_enc >= 0xff v8: Did the same for ov772x [7/11] has been required by Hans to add frame interval handling to ov772x driver. As this is quite a big change I kept it in a separate patch to ease review, it can eventually be squashed on [6/11] if accepted. v8: Calculate PLL divider/multiplier in place of using static tables. If for TW9910 video decoder the same is required (frame interval handling) I'm in favour of moving that driver to staging as it was proposed for ov772x before this series. v4l2-compliance now reports a 0 error count: Total: 43, Succeeded: 43, Failed: 0, Warnings: 0 Hans, you asked me to run v4l2-compliance with the -f option, I cannot do that on my tiny GR-Peach as with its limited available system memory it cannot allocate the number of requested buffers for that test. I can try to tweak that if necessary. I won't stress here why I cannot do that on Migo-R, long story short, I need a special compiler with DSP support to run anything but the little initramfs I have received for SH7722. I've been able to tweak yavta to work and test capture and frame rate handling with it, but v4l2-compliance is much more complex and I don't think I'll be able run it on that platform. Below, v4l2-compliance output: --- v4l2-compliance SHA : 20b6624f4bb84353e690d897688fd7ac12d6a881 Driver Info: Driver name : renesas-ceu Card type : Renesas CEU e821.ceu Bus info : platform:renesas-ceu-e821.c Driver version: 4.15.0 Capabilities : 0x84201000 Video Capture Multiplanar Streaming Extended Pix Format Device Capabilities Device Caps : 0x04201000 Video Capture Multiplanar Streaming Extended Pix Format Compliance test for device /dev/video0 (not using libv4l2): Required ioctls: test VIDIOC_QUERYCAP: OK Allow for multiple opens: test second video open: OK test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK test VIDIOC_LOG_STATUS: OK (Not Supported) Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 1 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Test input 0: Control ioctls: test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 12 Private Controls: 0 Format ioctls: test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK fail: v4l2-test-formats.cpp(1162): ret && node->has_frmintervals test VIDIOC_G/S_PARM: OK test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK
[PATCH v8 03/11] media: platform: Add Renesas CEU driver
Add driver for Renesas Capture Engine Unit (CEU). The CEU interface supports capturing 'data' (YUV422) and 'images' (NV[12|21|16|61]). This driver aims to replace the soc_camera-based sh_mobile_ceu one. Tested with ov7670 camera sensor, providing YUYV_2X8 data on Renesas RZ platform GR-Peach. Tested with ov7725 camera sensor on SH4 platform Migo-R. Signed-off-by: Jacopo Mondi Reviewed-by: Laurent Pinchart --- drivers/media/platform/Kconfig |9 + drivers/media/platform/Makefile |1 + drivers/media/platform/renesas-ceu.c | 1661 ++ 3 files changed, 1671 insertions(+) create mode 100644 drivers/media/platform/renesas-ceu.c diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 614fbef..f9cc058 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -144,6 +144,15 @@ config VIDEO_STM32_DCMI To compile this driver as a module, choose M here: the module will be called stm32-dcmi. +config VIDEO_RENESAS_CEU + tristate "Renesas Capture Engine Unit (CEU) driver" + depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA + depends on ARCH_SHMOBILE || ARCH_R7S72100 || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + ---help--- + This is a v4l2 driver for the Renesas CEU Interface + source "drivers/media/platform/soc_camera/Kconfig" source "drivers/media/platform/exynos4-is/Kconfig" source "drivers/media/platform/am437x/Kconfig" diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 7f30804..85e1121 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_VIDEO_SH_VOU)+= sh_vou.o obj-$(CONFIG_SOC_CAMERA) += soc_camera/ obj-$(CONFIG_VIDEO_RCAR_DRIF) += rcar_drif.o +obj-$(CONFIG_VIDEO_RENESAS_CEU)+= renesas-ceu.o obj-$(CONFIG_VIDEO_RENESAS_FCP)+= rcar-fcp.o obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o obj-$(CONFIG_VIDEO_RENESAS_JPU)+= rcar_jpu.o diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c new file mode 100644 index 000..d0ac500 --- /dev/null +++ b/drivers/media/platform/renesas-ceu.c @@ -0,0 +1,1661 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * V4L2 Driver for Renesas Capture Engine Unit (CEU) interface + * Copyright (C) 2017-2018 Jacopo Mondi + * + * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c" + * Copyright (C) 2008 Magnus Damm + * + * Based on V4L2 Driver for PXA camera host - "pxa_camera.c", + * Copyright (C) 2006, Sascha Hauer, Pengutronix + * Copyright (C) 2008, Guennadi Liakhovetski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRIVER_NAME"renesas-ceu" + +/* CEU registers offsets and masks. */ +#define CEU_CAPSR 0x00 /* Capture start register */ +#define CEU_CAPCR 0x04 /* Capture control register*/ +#define CEU_CAMCR 0x08 /* Capture interface control register */ +#define CEU_CAMOR 0x10 /* Capture interface offset register */ +#define CEU_CAPWR 0x14 /* Capture interface width register*/ +#define CEU_CAIFR 0x18 /* Capture interface input format register */ +#define CEU_CRCNTR 0x28 /* CEU register control register */ +#define CEU_CRCMPR 0x2c /* CEU register forcible control register */ +#define CEU_CFLCR 0x30 /* Capture filter control register */ +#define CEU_CFSZR 0x34 /* Capture filter size clip register */ +#define CEU_CDWDR 0x38 /* Capture destination width register */ +#define CEU_CDAYR 0x3c /* Capture data address Y register */ +#define CEU_CDACR 0x40 /* Capture data address C register */ +#define CEU_CFWCR 0x5c /* Firewall operation control register */ +#define CEU_CDOCR 0x64 /* Capture data output control register*/ +#define CEU_CEIER 0x70 /* Capture event interrupt enable register */ +#define CEU_CETCR 0x74 /* Capture event flag clear register */ +#define CEU_CSTSR 0x7c /* Capture status register */ +#define CEU_CSRTR 0x80 /* Capture software reset register */ + +/* Data synchronous fetch mode. */ +#define CEU_CAMCR_JPEG BIT(4) + +/* Input components ordering: CEU_CAMCR.DTARY field. */ +#define CEU_CAMCR_DTARY_8_UYVY (0x00 << 8) +#define CEU_CAMCR_DTARY_8_VYUY (0x01 << 8) +#define CEU_CAMCR_DTARY_8_YUYV (0x02 << 8) +#define CEU_CAMCR_DTARY_8_YVYU (0x03 << 8) +/* TODO: input components orderi
[PATCH v8 02/11] include: media: Add Renesas CEU driver interface
Add renesas-ceu header file.
Do not remove the existing sh_mobile_ceu.h one as long as the original
driver does not go away.
Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
Acked-by: Hans Verkuil
---
include/media/drv-intf/renesas-ceu.h | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 include/media/drv-intf/renesas-ceu.h
diff --git a/include/media/drv-intf/renesas-ceu.h
b/include/media/drv-intf/renesas-ceu.h
new file mode 100644
index 000..52841d1
--- /dev/null
+++ b/include/media/drv-intf/renesas-ceu.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * renesas-ceu.h - Renesas CEU driver interface
+ *
+ * Copyright 2017-2018 Jacopo Mondi
+ */
+
+#ifndef __MEDIA_DRV_INTF_RENESAS_CEU_H__
+#define __MEDIA_DRV_INTF_RENESAS_CEU_H__
+
+#define CEU_MAX_SUBDEVS2
+
+struct ceu_async_subdev {
+ unsigned long flags;
+ unsigned char bus_width;
+ unsigned char bus_shift;
+ unsigned int i2c_adapter_id;
+ unsigned int i2c_address;
+};
+
+struct ceu_platform_data {
+ unsigned int num_subdevs;
+ struct ceu_async_subdev subdevs[CEU_MAX_SUBDEVS];
+};
+
+#endif /* ___MEDIA_DRV_INTF_RENESAS_CEU_H__ */
--
2.7.4
[PATCH v8 06/11] media: i2c: ov772x: Remove soc_camera dependencies
Remove soc_camera framework dependencies from ov772x sensor driver.
- Handle clock and gpios
- Register async subdevice
- Remove soc_camera specific g/s_mbus_config operations
- Change image format colorspace from JPEG to SRGB as the two use the
same colorspace information but JPEG makes assumptions on color
components quantization that do not apply to the sensor
- Remove sizes crop from get_selection as driver can't scale
- Add kernel doc to driver interface header file
- Adjust build system
This commit does not remove the original soc_camera based driver as long
as other platforms depends on soc_camera-based CEU driver.
Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
---
drivers/media/i2c/Kconfig | 11 +++
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov772x.c | 172 ++---
include/media/i2c/ov772x.h | 6 +-
4 files changed, 133 insertions(+), 57 deletions(-)
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 9f18cd2..e71e968 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -645,6 +645,17 @@ config VIDEO_OV5670
To compile this driver as a module, choose M here: the
module will be called ov5670.
+config VIDEO_OV772X
+ tristate "OmniVision OV772x sensor support"
+ depends on I2C && VIDEO_V4L2
+ depends on MEDIA_CAMERA_SUPPORT
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the OmniVision
+ OV772x camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ov772x.
+
config VIDEO_OV7640
tristate "OmniVision OV7640 sensor support"
depends on I2C && VIDEO_V4L2
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index c0f94cd..b0489a1 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o
obj-$(CONFIG_VIDEO_OV6650) += ov6650.o
obj-$(CONFIG_VIDEO_OV7640) += ov7640.o
obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
+obj-$(CONFIG_VIDEO_OV772X) += ov772x.o
obj-$(CONFIG_VIDEO_OV7740) += ov7740.o
obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c
index 8063835..23106d7 100644
--- a/drivers/media/i2c/ov772x.c
+++ b/drivers/media/i2c/ov772x.c
@@ -1,6 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* ov772x Camera Driver
*
+ * Copyright (C) 2017 Jacopo Mondi
+ *
* Copyright (C) 2008 Renesas Solutions Corp.
* Kuninori Morimoto
*
@@ -9,27 +12,25 @@
* Copyright 2006-7 Jonathan Corbet
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2008, Guennadi Liakhovetski
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
+#include
+#include
+#include
+#include
#include
#include
#include
-#include
#include
-#include
#include
#include
#include
-#include
-#include
+
#include
-#include
+#include
#include
+#include
/*
* register offset
@@ -393,8 +394,10 @@ struct ov772x_win_size {
struct ov772x_priv {
struct v4l2_subdevsubdev;
struct v4l2_ctrl_handler hdl;
- struct v4l2_clk *clk;
+ struct clk *clk;
struct ov772x_camera_info*info;
+ struct gpio_desc *pwdn_gpio;
+ struct gpio_desc *rstb_gpio;
const struct ov772x_color_format *cfmt;
const struct ov772x_win_size *win;
unsigned shortflag_vflip:1;
@@ -409,7 +412,7 @@ struct ov772x_priv {
static const struct ov772x_color_format ov772x_cfmts[] = {
{
.code = MEDIA_BUS_FMT_YUYV8_2X8,
- .colorspace = V4L2_COLORSPACE_JPEG,
+ .colorspace = V4L2_COLORSPACE_SRGB,
.dsp3 = 0x0,
.dsp4 = DSP_OFMT_YUV,
.com3 = SWAP_YUV,
@@ -417,7 +420,7 @@ static const struct ov772x_color_format ov772x_cfmts[] = {
},
{
.code = MEDIA_BUS_FMT_YVYU8_2X8,
- .colorspace = V4L2_COLORSPACE_JPEG,
+ .colorspace = V4L2_COLORSPACE_SRGB,
.dsp3 = UV_ON,
.dsp4 = DSP_OFMT_YUV,
.com3 = SWAP_YUV,
@@ -425,7 +428,7 @@ static const struct ov772x_color_format ov772x_cfmts[] = {
},
{
.code = MEDIA_BUS_FMT_UYVY8_2X8,
- .colorspace = V4L2_COLORSPACE_JPEG,
+ .colorspace = V4L2_COLORSPACE_SRGB,
.dsp3 = 0x0,
.dsp4 = DSP_OFMT_YUV,
.com3 = 0x0,
@@ -550,7 +553,7 @@ st
[PATCH v8 05/11] media: i2c: Copy ov772x soc_camera sensor driver
Copy the soc_camera based driver in v4l2 sensor driver directory. This commit just copies the original file without modifying it. No modification to KConfig and Makefile as soc_camera framework dependencies need to be removed first in next commit. Signed-off-by: Jacopo Mondi Acked-by: Laurent Pinchart Acked-by: Hans Verkuil --- drivers/media/i2c/ov772x.c | 1124 1 file changed, 1124 insertions(+) create mode 100644 drivers/media/i2c/ov772x.c diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c new file mode 100644 index 000..8063835 --- /dev/null +++ b/drivers/media/i2c/ov772x.c @@ -0,0 +1,1124 @@ +/* + * ov772x Camera Driver + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Kuninori Morimoto + * + * Based on ov7670 and soc_camera_platform driver, + * + * Copyright 2006-7 Jonathan Corbet + * Copyright (C) 2008 Magnus Damm + * Copyright (C) 2008, Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * register offset + */ +#define GAIN0x00 /* AGC - Gain control gain setting */ +#define BLUE0x01 /* AWB - Blue channel gain setting */ +#define RED 0x02 /* AWB - Red channel gain setting */ +#define GREEN 0x03 /* AWB - Green channel gain setting */ +#define COM10x04 /* Common control 1 */ +#define BAVG0x05 /* U/B Average Level */ +#define GAVG0x06 /* Y/Gb Average Level */ +#define RAVG0x07 /* V/R Average Level */ +#define AECH0x08 /* Exposure Value - AEC MSBs */ +#define COM20x09 /* Common control 2 */ +#define PID 0x0A /* Product ID Number MSB */ +#define VER 0x0B /* Product ID Number LSB */ +#define COM30x0C /* Common control 3 */ +#define COM40x0D /* Common control 4 */ +#define COM50x0E /* Common control 5 */ +#define COM60x0F /* Common control 6 */ +#define AEC 0x10 /* Exposure Value */ +#define CLKRC 0x11 /* Internal clock */ +#define COM70x12 /* Common control 7 */ +#define COM80x13 /* Common control 8 */ +#define COM90x14 /* Common control 9 */ +#define COM10 0x15 /* Common control 10 */ +#define REG16 0x16 /* Register 16 */ +#define HSTART 0x17 /* Horizontal sensor size */ +#define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */ +#define VSTART 0x19 /* Vertical frame (row) start high 8-bit */ +#define VSIZE 0x1A /* Vertical sensor size */ +#define PSHFT 0x1B /* Data format - pixel delay select */ +#define MIDH0x1C /* Manufacturer ID byte - high */ +#define MIDL0x1D /* Manufacturer ID byte - low */ +#define LAEC0x1F /* Fine AEC value */ +#define COM11 0x20 /* Common control 11 */ +#define BDBASE 0x22 /* Banding filter Minimum AEC value */ +#define DBSTEP 0x23 /* Banding filter Maximum Setp */ +#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ +#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ +#define VPT 0x26 /* AGC/AEC Fast mode operating region */ +#define REG28 0x28 /* Register 28 */ +#define HOUTSIZE0x29 /* Horizontal data output size MSBs */ +#define EXHCH 0x2A /* Dummy pixel insert MSB */ +#define EXHCL 0x2B /* Dummy pixel insert LSB */ +#define VOUTSIZE0x2C /* Vertical data output size MSBs */ +#define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ +#define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */ +#define YAVE0x2F /* Y/G Channel Average value */ +#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */ +#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */ +#define HREF0x32 /* Image start and size control */ +#define DM_LNL 0x33 /* Dummy line low 8 bits */ +#define DM_LNH 0x34 /* Dummy line high 8 bits */ +#define ADOFF_B 0x35 /* AD offset compensation value for B channel */ +#define ADOFF_R 0x36 /* AD offset compensation value for R channel */ +#define ADOFF_GB0x37 /* AD offset compensation value for Gb channel */ +#define ADOFF_GR0x38 /* AD offset compensation value for Gr channel */ +#define OFF_B 0x39 /* Analog process B channel offset value */ +#define OFF_R 0x3A /* Analog process R channel offset value */ +#define OFF_GB 0x3B /* Analog process Gb channel offset value */ +#define OFF_GR 0x3C /* Analog process Gr channel offset value */ +#define COM12 0x3D /* Common control 12 */ +#define COM13 0x3E /* Common control 13 */ +#define COM14 0x3F /* Common
[PATCH v8 07/11] media: i2c: ov772x: Support frame interval handling
Add support to ov772x driver for frame intervals handling and enumeration.
Tested with 10MHz and 24MHz input clock at VGA and QVGA resolutions for
10, 15 and 30 frame per second rates.
Signed-off-by: Jacopo Mondi
---
drivers/media/i2c/ov772x.c | 210 +
1 file changed, 193 insertions(+), 17 deletions(-)
diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c
index 23106d7..28de254 100644
--- a/drivers/media/i2c/ov772x.c
+++ b/drivers/media/i2c/ov772x.c
@@ -250,6 +250,7 @@
#define AEC_1p2 0x10 /* 01: 1/2 window */
#define AEC_1p4 0x20 /* 10: 1/4 window */
#define AEC_2p3 0x30 /* 11: Low 2/3 window */
+#define COM4_RESERVED 0x01 /* Reserved bit */
/* COM5 */
#define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
@@ -267,6 +268,10 @@
/* AEC max step control */
#define AEC_NO_LIMIT0x01 /* 0 : AEC incease step has limit */
/* 1 : No limit to AEC increase step */
+/* CLKRC */
+ /* Input clock divider register */
+#define CLKRC_RESERVED 0x80 /* Reserved bit */
+#define CLKRC_DIV(n)((n) - 1)
/* COM7 */
/* SCCB Register Reset */
@@ -373,6 +378,19 @@
#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
/*
+ * Frame size (including blanking lines)
+ */
+#define VGA_FRAME_SIZE (510 * 748)
+#define QVGA_FRAME_SIZE(278 * 576)
+
+/*
+ * Input clock frequencies
+ */
+static const u8 ov772x_com4_vals[] = { PLL_BYPASS, PLL_4x, PLL_6x, PLL_8x };
+static const unsigned int ov772x_pll_mult[] = { 1, 4, 6, 8 };
+#define OV772X_PLL_N_MULT ARRAY_SIZE(ov772x_pll_mult)
+
+/*
* struct
*/
@@ -388,6 +406,7 @@ struct ov772x_color_format {
struct ov772x_win_size {
char *name;
unsigned char com7_bit;
+ unsigned int sizeimage;
struct v4l2_rect rect;
};
@@ -404,6 +423,7 @@ struct ov772x_priv {
unsigned shortflag_hflip:1;
/* band_filter = COM8[5] ? 256 - BDBASE : 0 */
unsigned shortband_filter;
+ unsigned int fps;
};
/*
@@ -487,27 +507,35 @@ static const struct ov772x_color_format ov772x_cfmts[] = {
static const struct ov772x_win_size ov772x_win_sizes[] = {
{
- .name = "VGA",
- .com7_bit = SLCT_VGA,
+ .name = "VGA",
+ .com7_bit = SLCT_VGA,
+ .sizeimage = 381480,
.rect = {
- .left = 140,
- .top = 14,
- .width = VGA_WIDTH,
- .height = VGA_HEIGHT,
+ .left = 140,
+ .top= 14,
+ .width = VGA_WIDTH,
+ .height = VGA_HEIGHT,
},
}, {
- .name = "QVGA",
- .com7_bit = SLCT_QVGA,
+ .name = "QVGA",
+ .com7_bit = SLCT_QVGA,
+ .sizeimage = 160128,
.rect = {
- .left = 252,
- .top = 6,
- .width = QVGA_WIDTH,
- .height = QVGA_HEIGHT,
+ .left = 252,
+ .top= 6,
+ .width = QVGA_WIDTH,
+ .height = QVGA_HEIGHT,
},
},
};
/*
+ * frame rate settings lists
+ */
+unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 };
+#define OV772X_N_FRAME_INTERVALS ARRAY_SIZE(ov772x_frame_intervals)
+
+/*
* general function
*/
@@ -574,6 +602,124 @@ static int ov772x_s_stream(struct v4l2_subdev *sd, int
enable)
return 0;
}
+static int ov772x_set_frame_rate(struct ov772x_priv *priv,
+struct v4l2_fract *tpf,
+const struct ov772x_color_format *cfmt,
+const struct ov772x_win_size *win)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
+ unsigned int fps = tpf->denominator / tpf->numerator;
+ unsigned int fin = clk_get_rate(priv->clk);
+ unsigned int rate_prev;
+ unsigned int fsize;
+ unsigned int pclk;
+ unsigned int rate;
+ unsigned int idx;
+ unsigned int i;
+ u8 clkrc = 0;
+ u8 com4 = 0;
+ int ret;
+
+ /* Approximate to the closest supported frame interval. */
+ rate_prev = ~0L;
+ for (i = 0, idx = 0; i < OV772X_N_FRAME_INTERVALS; i++) {
+ rate = abs(fps - ov772x_frame_intervals[i]);
+ if (rate < rate_prev) {
+ idx = i;
+ rate_prev = rate;
+ }
+ }
+
[PATCH v8 09/11] media: i2c: tw9910: Remove soc_camera dependencies
Remove soc_camera framework dependencies from tw9910 sensor driver.
- Handle clock and gpios
- Register async subdevice
- Remove soc_camera specific g/s_mbus_config operations
- Add kernel doc to driver interface header file
- Adjust build system
This commit does not remove the original soc_camera based driver as long
as other platforms depends on soc_camera-based CEU driver.
Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
Acked-by: Hans Verkuil
---
drivers/media/i2c/Kconfig | 9 +++
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/tw9910.c | 162 -
include/media/i2c/tw9910.h | 9 +++
4 files changed, 120 insertions(+), 61 deletions(-)
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index e71e968..0460613 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -423,6 +423,15 @@ config VIDEO_TW9906
To compile this driver as a module, choose M here: the
module will be called tw9906.
+config VIDEO_TW9910
+ tristate "Techwell TW9910 video decoder"
+ depends on VIDEO_V4L2 && I2C
+ ---help---
+ Support for Techwell TW9910 NTSC/PAL/SECAM video decoder.
+
+ To compile this driver as a module, choose M here: the
+ module will be called tw9910.
+
config VIDEO_VPX3220
tristate "vpx3220a, vpx3216b & vpx3214c video decoders"
depends on VIDEO_V4L2 && I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index b0489a1..23c3ac6 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_VIDEO_TVP7002) += tvp7002.o
obj-$(CONFIG_VIDEO_TW2804) += tw2804.o
obj-$(CONFIG_VIDEO_TW9903) += tw9903.o
obj-$(CONFIG_VIDEO_TW9906) += tw9906.o
+obj-$(CONFIG_VIDEO_TW9910) += tw9910.o
obj-$(CONFIG_VIDEO_CS3308) += cs3308.o
obj-$(CONFIG_VIDEO_CS5345) += cs5345.o
obj-$(CONFIG_VIDEO_CS53L32A) += cs53l32a.o
diff --git a/drivers/media/i2c/tw9910.c b/drivers/media/i2c/tw9910.c
index bdb5e0a..96792df 100644
--- a/drivers/media/i2c/tw9910.c
+++ b/drivers/media/i2c/tw9910.c
@@ -1,6 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* tw9910 Video Driver
*
+ * Copyright (C) 2017 Jacopo Mondi
+ *
* Copyright (C) 2008 Renesas Solutions Corp.
* Kuninori Morimoto
*
@@ -10,12 +13,10 @@
* Copyright 2006-7 Jonathan Corbet
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2008, Guennadi Liakhovetski
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
+#include
+#include
#include
#include
#include
@@ -25,9 +26,7 @@
#include
#include
-#include
#include
-#include
#include
#define GET_ID(val) ((val & 0xF8) >> 3)
@@ -228,8 +227,10 @@ struct tw9910_scale_ctrl {
struct tw9910_priv {
struct v4l2_subdev subdev;
- struct v4l2_clk *clk;
+ struct clk *clk;
struct tw9910_video_info*info;
+ struct gpio_desc*pdn_gpio;
+ struct gpio_desc*rstb_gpio;
const struct tw9910_scale_ctrl *scale;
v4l2_std_id norm;
u32 revision;
@@ -582,13 +583,66 @@ static int tw9910_s_register(struct v4l2_subdev *sd,
}
#endif
+static int tw9910_power_on(struct tw9910_priv *priv)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
+ int ret;
+
+ if (priv->clk) {
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return ret;
+ }
+
+ if (priv->pdn_gpio) {
+ gpiod_set_value(priv->pdn_gpio, 0);
+ usleep_range(500, 1000);
+ }
+
+ /*
+* FIXME: The reset signal is connected to a shared GPIO on some
+* platforms (namely the SuperH Migo-R). Until a framework becomes
+* available to handle this cleanly, request the GPIO temporarily
+* to avoid conflicts.
+*/
+ priv->rstb_gpio = gpiod_get_optional(&client->dev, "rstb",
+GPIOD_OUT_LOW);
+ if (IS_ERR(priv->rstb_gpio)) {
+ dev_info(&client->dev, "Unable to get GPIO \"rstb\"");
+ return PTR_ERR(priv->rstb_gpio);
+ }
+
+ if (priv->rstb_gpio) {
+ gpiod_set_value(priv->rstb_gpio, 1);
+ usleep_range(500, 1000);
+ gpiod_set_value(priv->rstb_gpio, 0);
+ usleep_range(500, 1000);
+
+ gpiod_put(priv->rstb_gpio);
+ }
+
+ return 0;
+}
+
+static int tw9910_power_off(struct tw9910_priv *priv)
+{
+ clk_disable_unprepare(priv->clk);
+
+ if (priv->pdn_gpio) {
+ gpiod_set_value(priv->pdn_gpio, 1);
+ usleep_range(500, 1000);
+ }
+
+ re
[PATCH v8 08/11] media: i2c: Copy tw9910 soc_camera sensor driver
Copy the soc_camera based driver in v4l2 sensor driver directory. This commit just copies the original file without modifying it. No modification to KConfig and Makefile as soc_camera framework dependencies need to be removed first in next commit. Signed-off-by: Jacopo Mondi Acked-by: Laurent Pinchart Acked-by: Hans Verkuil --- drivers/media/i2c/tw9910.c | 999 + 1 file changed, 999 insertions(+) create mode 100644 drivers/media/i2c/tw9910.c diff --git a/drivers/media/i2c/tw9910.c b/drivers/media/i2c/tw9910.c new file mode 100644 index 000..bdb5e0a --- /dev/null +++ b/drivers/media/i2c/tw9910.c @@ -0,0 +1,999 @@ +/* + * tw9910 Video Driver + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Kuninori Morimoto + * + * Based on ov772x driver, + * + * Copyright (C) 2008 Kuninori Morimoto + * Copyright 2006-7 Jonathan Corbet + * Copyright (C) 2008 Magnus Damm + * Copyright (C) 2008, Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define GET_ID(val) ((val & 0xF8) >> 3) +#define GET_REV(val) (val & 0x07) + +/* + * register offset + */ +#define ID 0x00 /* Product ID Code Register */ +#define STATUS10x01 /* Chip Status Register I */ +#define INFORM 0x02 /* Input Format */ +#define OPFORM 0x03 /* Output Format Control Register */ +#define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */ +#define OUTCTR10x05 /* Output Control I */ +#define ACNTL1 0x06 /* Analog Control Register 1 */ +#define CROP_HI0x07 /* Cropping Register, High */ +#define VDELAY_LO 0x08 /* Vertical Delay Register, Low */ +#define VACTIVE_LO 0x09 /* Vertical Active Register, Low */ +#define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */ +#define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */ +#define CNTRL1 0x0C /* Control Register I */ +#define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */ +#define SCALE_HI 0x0E /* Scaling Register, High */ +#define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */ +#define BRIGHT 0x10 /* BRIGHTNESS Control Register */ +#define CONTRAST 0x11 /* CONTRAST Control Register */ +#define SHARPNESS 0x12 /* SHARPNESS Control Register I */ +#define SAT_U 0x13 /* Chroma (U) Gain Register */ +#define SAT_V 0x14 /* Chroma (V) Gain Register */ +#define HUE0x15 /* Hue Control Register */ +#define CORING10x17 +#define CORING20x18 /* Coring and IF compensation */ +#define VBICNTL0x19 /* VBI Control Register */ +#define ACNTL2 0x1A /* Analog Control 2 */ +#define OUTCTR20x1B /* Output Control 2 */ +#define SDT0x1C /* Standard Selection */ +#define SDTR 0x1D /* Standard Recognition */ +#define TEST 0x1F /* Test Control Register */ +#define CLMPG 0x20 /* Clamping Gain */ +#define IAGC 0x21 /* Individual AGC Gain */ +#define AGCGAIN0x22 /* AGC Gain */ +#define PEAKWT 0x23 /* White Peak Threshold */ +#define CLMPL 0x24 /* Clamp level */ +#define SYNCT 0x25 /* Sync Amplitude */ +#define MISSCNT0x26 /* Sync Miss Count Register */ +#define PCLAMP 0x27 /* Clamp Position Register */ +#define VCNTL1 0x28 /* Vertical Control I */ +#define VCNTL2 0x29 /* Vertical Control II */ +#define CKILL 0x2A /* Color Killer Level Control */ +#define COMB 0x2B /* Comb Filter Control */ +#define LDLY 0x2C /* Luma Delay and H Filter Control */ +#define MISC1 0x2D /* Miscellaneous Control I */ +#define LOOP 0x2E /* LOOP Control Register */ +#define MISC2 0x2F /* Miscellaneous Control II */ +#define MVSN 0x30 /* Macrovision Detection */ +#define STATUS20x31 /* Chip STATUS II */ +#define HFREF 0x32 /* H monitor */ +#define CLMD 0x33 /* CLAMP MODE */ +#define IDCNTL 0x34 /* ID Detection Control */ +#define CLCNTL10x35 /* Clamp Control I */ +#define ANAPLLCTL 0x4C +#define VBIMIN 0x4D +#define HSLOWCTL 0x4E +#define WSS3 0x4F +#define FILLDATA 0x50 +#define SDID 0x51 +#define DID0x52 +#define WSS1 0x53 +#define WSS2 0x54 +#define VVBI 0x55 +#define LCTL6 0x56 +#define LCTL7 0x57 +#define LCTL8 0x58 +#define LCTL9 0x59 +#define LCTL10 0x5A +#define LCTL11 0x5B +#define LCTL12 0x5C +#define LCTL13 0x5D +#define LC
[PATCH v8 10/11] arch: sh: migor: Use new renesas-ceu camera driver
Migo-R platform uses sh_mobile_ceu camera driver, which is now being
replaced by a proper V4L2 camera driver named 'renesas-ceu'.
Move Migo-R platform to use the v4l2 renesas-ceu camera driver
interface and get rid of soc_camera defined components used to register
sensor drivers and of platform specific enable/disable routines.
Register clock source and GPIOs for sensor drivers, so they can use
clock and gpio APIs.
Also, memory for CEU video buffers is now reserved with membocks APIs,
and need to be declared as dma_coherent during machine initialization to
remove that architecture specific part from CEU driver.
Signed-off-by: Jacopo Mondi
Reviewed-by: Laurent Pinchart
Acked-by: Hans Verkuil
---
arch/sh/boards/mach-migor/setup.c | 225 +++--
arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 2 +-
2 files changed, 101 insertions(+), 126 deletions(-)
diff --git a/arch/sh/boards/mach-migor/setup.c
b/arch/sh/boards/mach-migor/setup.c
index 0bcbe58..271dfc2 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Renesas System Solutions Asia Pte. Ltd - Migo-R
*
* Copyright (C) 2008 Magnus Damm
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
*/
+#include
#include
#include
#include
#include
#include
+#include
#include
#include
#include
@@ -23,10 +22,11 @@
#include
#include
#include
+#include
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -45,6 +45,9 @@
* 0x1800 8GB8 NAND Flash (K9K8G08U0A)
*/
+#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
+static phys_addr_t ceu_dma_membase;
+
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
@@ -301,65 +304,24 @@ static struct platform_device migor_lcdc_device = {
},
};
-static struct clk *camera_clk;
-static DEFINE_MUTEX(camera_lock);
-
-static void camera_power_on(int is_tw)
-{
- mutex_lock(&camera_lock);
-
- /* Use 10 MHz VIO_CKO instead of 24 MHz to work
-* around signal quality issues on Panel Board V2.1.
-*/
- camera_clk = clk_get(NULL, "video_clk");
- clk_set_rate(camera_clk, 1000);
- clk_enable(camera_clk); /* start VIO_CKO */
-
- /* use VIO_RST to take camera out of reset */
- mdelay(10);
- if (is_tw) {
- gpio_set_value(GPIO_PTT2, 0);
- gpio_set_value(GPIO_PTT0, 0);
- } else {
- gpio_set_value(GPIO_PTT0, 1);
- }
- gpio_set_value(GPIO_PTT3, 0);
- mdelay(10);
- gpio_set_value(GPIO_PTT3, 1);
- mdelay(10); /* wait to let chip come out of reset */
-}
-
-static void camera_power_off(void)
-{
- clk_disable(camera_clk); /* stop VIO_CKO */
- clk_put(camera_clk);
-
- gpio_set_value(GPIO_PTT3, 0);
- mutex_unlock(&camera_lock);
-}
-
-static int ov7725_power(struct device *dev, int mode)
-{
- if (mode)
- camera_power_on(0);
- else
- camera_power_off();
-
- return 0;
-}
-
-static int tw9910_power(struct device *dev, int mode)
-{
- if (mode)
- camera_power_on(1);
- else
- camera_power_off();
-
- return 0;
-}
-
-static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
- .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+static struct ceu_platform_data ceu_pdata = {
+ .num_subdevs= 2,
+ .subdevs = {
+ { /* [0] = ov772x */
+ .flags = 0,
+ .bus_width = 8,
+ .bus_shift = 0,
+ .i2c_adapter_id = 0,
+ .i2c_address= 0x21,
+ },
+ { /* [1] = tw9910 */
+ .flags = 0,
+ .bus_width = 8,
+ .bus_shift = 0,
+ .i2c_adapter_id = 0,
+ .i2c_address= 0x45,
+ },
+ },
};
static struct resource migor_ceu_resources[] = {
@@ -373,18 +335,32 @@ static struct resource migor_ceu_resources[] = {
.start = evt2irq(0x880),
.flags = IORESOURCE_IRQ,
},
- [2] = {
- /* place holder for contiguous memory */
- },
};
static struct platform_device migor_ceu_device = {
- .name = "sh_mobile_ceu",
- .id = 0, /* "ceu0" clock */
+ .name = "renesas-ceu",
+ .id = 0, /* ceu.0 */
.num_resources = ARRAY_SIZE(migor_ceu_resources),
.resource = migor_ceu_resources,
.dev= {
- .platform_data = &sh_mobile_ceu_info,
+ .plat
[PATCH v8 11/11] media: i2c: ov7670: Fully set mbus frame fmt
The sensor driver sets mbus format colorspace information and sizes, but not ycbcr encoding, quantization and xfer function. When supplied with an badly initialized mbus frame format structure, those fields need to be set explicitly not to leave them uninitialized. This is tested by v4l2-compliance, which supplies a mbus format description structure and checks for all fields to be properly set. Without this commit, v4l2-compliance fails when testing formats with: fail: v4l2-test-formats.cpp(335): ycbcr_enc >= 0xff Signed-off-by: Jacopo Mondi --- drivers/media/i2c/ov7670.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c index 25b26d4..61c472e 100644 --- a/drivers/media/i2c/ov7670.c +++ b/drivers/media/i2c/ov7670.c @@ -996,6 +996,10 @@ static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, fmt->height = wsize->height; fmt->colorspace = ov7670_formats[index].colorspace; + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + fmt->quantization = V4L2_QUANTIZATION_DEFAULT; + fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; + info->format = *fmt; return 0; -- 2.7.4
Re: [PATCH 2/2] ARM: dts: r8a7745: Add VSP support
On Wed, Jan 24, 2018 at 04:11:52PM +, Biju Das wrote: > Add VSP support to SoC DT. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson Thanks, applied manually - there was some fuzz, most likely due to recent sorting of the nodes in this file.
Re: [PATCH 1/2] ARM: dts: r8a7743: Add VSP support
On Wed, Jan 24, 2018 at 04:11:51PM +, Biju Das wrote: > Add VSP support to SoC DT. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson Thanks, applied.
Re: [PATCH v7 07/11] media: i2c: ov772x: Support frame interval handling
Hi Laurent,
On Mon, Jan 29, 2018 at 01:01:01PM +0200, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Friday, 26 January 2018 15:55:26 EET Jacopo Mondi wrote:
> > Add support to ov772x driver for frame intervals handling and enumeration.
> > Tested with 10MHz and 24MHz input clock at VGA and QVGA resolutions for
> > 10, 15 and 30 frame per second rates.
> >
> > Signed-off-by: Jacopo Mondi
> > ---
> > drivers/media/i2c/ov772x.c | 315 +-
> > 1 file changed, 310 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c
> > index 912b1b9..6d46748 100644
> > --- a/drivers/media/i2c/ov772x.c
> > +++ b/drivers/media/i2c/ov772x.c
> > @@ -250,6 +250,7 @@
> > #define AEC_1p2 0x10 /* 01: 1/2 window */
> > #define AEC_1p4 0x20 /* 10: 1/4 window */
> > #define AEC_2p3 0x30 /* 11: Low 2/3 window */
> > +#define COM4_RESERVED 0x01 /* Reserved value */
>
> I'd write "Reserved bits", "Reserved value" makes it sound like it's the value
> of the full register.
>
Ack
> > /* COM5 */
> > #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF
> > selection
> */
> > @@ -267,6 +268,19 @@
> > /* AEC max step control */
> > #define AEC_NO_LIMIT0x01 /* 0 : AEC incease step has limit */
> > /* 1 : No limit to AEC increase step */
> > +/* CLKRC */
> > + /* Input clock divider register */
> > +#define CLKRC_RESERVED 0x80 /* Reserved value */
> > +#define CLKRC_BYPASS0x40 /* Bypass input clock divider */
> > +#define CLKRC_DIV2 0x01 /* Divide input clock by 2 */
> > +#define CLKRC_DIV3 0x02 /* Divide input clock by 3 */
> > +#define CLKRC_DIV4 0x03 /* Divide input clock by 4 */
> > +#define CLKRC_DIV5 0x04 /* Divide input clock by 5 */
> > +#define CLKRC_DIV6 0x05 /* Divide input clock by 6 */
> > +#define CLKRC_DIV8 0x07 /* Divide input clock by 8 */
> > +#define CLKRC_DIV10 0x09 /* Divide input clock by 10 */
> > +#define CLKRC_DIV16 0x0f /* Divide input clock by 16 */
> > +#define CLKRC_DIV20 0x13 /* Divide input clock by 20 */
>
> How about just
>
> #define CLKRC_DIV(n) ((n) - 1)
>
Ack again,
> > /* COM7 */
> > /* SCCB Register Reset */
> > @@ -373,6 +387,12 @@
> > #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
> >
> > /*
> > + * Input clock frequencies
> > + */
> > +enum { OV772X_FIN_10MHz, OV772X_FIN_24MHz, OV772X_FIN_48MHz, OV772X_FIN_N,
> > };
> > +static unsigned int ov772x_fin_vals[] = { 1000, 2400, 4800
> > };
> > +
> > +/*
> > * struct
> > */
> >
> > @@ -391,6 +411,16 @@ struct ov772x_win_size {
> > struct v4l2_rect rect;
> > };
> >
> > +struct ov772x_pclk_config {
> > + u8 com4;
> > + u8 clkrc;
> > +};
> > +
> > +struct ov772x_frame_rate {
> > + unsigned int fps;
> > + const struct ov772x_pclk_config pclk[OV772X_FIN_N];
> > +};
> > +
> > struct ov772x_priv {
> > struct v4l2_subdevsubdev;
> > struct v4l2_ctrl_handler hdl;
> > @@ -404,6 +434,7 @@ struct ov772x_priv {
> > unsigned shortflag_hflip:1;
> > /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
> > unsigned shortband_filter;
> > + unsigned int fps;
> > };
> >
> > /*
> > @@ -508,6 +539,154 @@ static const struct ov772x_win_size ov772x_win_sizes[]
> > = { };
> >
> > /*
> > + * frame rate settings lists
> > + */
> > +unsigned int ov772x_frame_intervals[] = {10, 15, 30, 60};
> > +#define OV772X_N_FRAME_INTERVALS ARRAY_SIZE(ov772x_frame_intervals)
> > +
> > +static const struct ov772x_frame_rate vga_frame_rates[] = {
> > + { /* PCLK = 7,5 MHz */
> > + .fps= 10,
> > + .pclk = {
> > + [OV772X_FIN_10MHz] = {
> > + .com4 = PLL_6x | COM4_RESERVED,
> > + .clkrc = CLKRC_DIV8 | CLKRC_RESERVED,
> > + },
> > + [OV772X_FIN_24MHz] = {
> > + .com4 = PLL_BYPASS | COM4_RESERVED,
> > + .clkrc = CLKRC_DIV3 | CLKRC_RESERVED,
> > + },
> > + [OV772X_FIN_48MHz] = {
> > + .com4 = PLL_BYPASS | COM4_RESERVED,
> > + .clkrc = CLKRC_DIV6 | CLKRC_RESERVED,
> > + },
> > + },
> > + },
> > + { /* PCLK = 12 MHz */
> > + .fps= 15,
> > + .pclk = {
> > + [OV772X_FIN_10MHz] = {
> > + .com4 = PLL_4x | COM4_RESERVED,
> > + .clkrc = CLKRC_DIV3 | CLKRC_RESERVED,
> > + },
> > +
Re: [PATCH 3/3] ARM: dts: r8a7745: Add IPMMU DT nodes
On Wed, Jan 24, 2018 at 03:42:02PM +, Biju Das wrote: > Add the six IPMMU instances found in the r8a7745 to DT with a disabled > status. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson Thanks, I have applied this after moving the nodes so they are after the irqc node to take into account recent sorting of the nodes.
Re: [PATCH 2/3] ARM: dts: r8a7743: Add IPMMU DT nodes
On Wed, Jan 24, 2018 at 03:42:01PM +, Biju Das wrote: > Add the six IPMMU instances found in the r8a7743 to DT with a disabled > status. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson > --- > arch/arm/boot/dts/r8a7743.dtsi | 58 > ++ > 1 file changed, 58 insertions(+) Thanks, I have applied this after moving the nodes so they are after the thermal node to take into account recent sorting of the nodes.
Re: [PATCH 1/3] dt-bindings: iommu: ipmmu-vmsa: Add device tree support for r8a774[35]
On Wed, Jan 24, 2018 at 03:42:00PM +, Biju Das wrote: > Document r8a774[35] specific compatible strings. The Renesas RZ/G1[ME] > (r8a774[35]) IPMMU are identical to the R-Car Gen2 family. > > Signed-off-by: Biju Das > Reviewed-by: Chris Paterson Reviewed-by: Simon Horman
Re: [PATCH v2 0/5] R-Car D3 (r8a77995) I2C integration
On Mon, Jan 29, 2018 at 04:45:43PM +0100, Ulrich Hecht wrote: > Hi! > > This adds I2C controllers to the D3 device tree and enables I2C busses 0 > and 1 on the Draak board. (I2C2 is not connected on that board.) > > This revision addresses Geert's review comments and adds Reviewed-Bys. > See below for details. > > CU > Uli > > > Changes since v1: > - pinctrl: patch dropped, has been picked up > - i2c-rcar: patch dropped, redundant > - dtsi: added dmac2 for i2c0-2 > - dtsi: fixed internal SCL delays > - dts: fixed EEPROM compatible string > - bindings: added Rohm EEPROM > - bindings: fixed typo in i2c-rcar bindings > > > Ulrich Hecht (5): > arm64: renesas: r8a77995: add I2C support > arm64: renesas: draak: enable I2C controller 0 and EEPROM > arm64: renesas: draak: enable I2C controller 1 Thanks, I have applied the arm64 patches after updating their prefix to "arm64: dts: renesas:". > i2c: rcar: document R8A77995 bindings > dt-bindings: at24: add bindings for Rohm BR24T01 > > Documentation/devicetree/bindings/eeprom/at24.txt | 2 + > Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + > arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 28 + > arch/arm64/boot/dts/renesas/r8a77995.dtsi | 67 > ++ > 4 files changed, 98 insertions(+) > > -- > 2.7.4 >
Re: [PATCH v2 4/5] i2c: rcar: document R8A77995 bindings
On Mon, Jan 29, 2018 at 04:45:47PM +0100, Ulrich Hecht wrote: > R-Car D3 (R8A77995) SoC has a R-Car Gen3-compatible I2C controller. > > Signed-off-by: Ulrich Hecht > Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman > --- > Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt > b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt > index a777477..e91dbaf 100644 > --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt > +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt > @@ -14,6 +14,7 @@ Required properties: > "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. > "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. > "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. > + "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. > "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. > "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible > device. > -- > 2.7.4 >
