[PATCH 2/4] arm64: dts: renesas: r8a77990: Add GPIO device nodes

[Yoshihiro Shimoda]

This patch adds GPIO nodes for r8a77990 (R-Car E3).

Based on a patch from Takeshi Kihara 

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 112 ++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index efc3c0b..d94e047 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,118 @@
#size-cells = <2>;
ranges;
 
+   gpio0: gpio@e605 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe605 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 0 18>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 912>;
+   power-domains = < 32>;
+   resets = < 912>;
+   };
+
+   gpio1: gpio@e6051000 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6051000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 32 23>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 911>;
+   power-domains = < 32>;
+   resets = < 911>;
+   };
+
+   gpio2: gpio@e6052000 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6052000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 64 26>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 910>;
+   power-domains = < 32>;
+   resets = < 910>;
+   };
+
+   gpio3: gpio@e6053000 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6053000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 96 16>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 909>;
+   power-domains = < 32>;
+   resets = < 909>;
+   };
+
+   gpio4: gpio@e6054000 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6054000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 128 11>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 908>;
+   power-domains = < 32>;
+   resets = < 908>;
+   };
+
+   gpio5: gpio@e6055000 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+"renesas,gpio-rcar";
+   reg = <0 0xe6055000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 160 20>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 907>;
+   power-domains = < 32>;
+   resets = < 907>;
+   };
+
+   gpio6: gpio@e6055400 {
+   compatible = "renesas,gpio-r8a77990",
+"renesas,rcar-gen3-gpio",
+   

[PATCH 4/4] arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

[Yoshihiro Shimoda]

This patch enables EthernetAVB for r8a77990 Ebisu board.

Based on a patch from Takeshi Kihara 

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 28 ++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 63ee134..7a09d05 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "r8a77990.dtsi"
+#include 
 
 / {
model = "Renesas Ebisu board based on r8a77990";
@@ -14,6 +15,7 @@
 
aliases {
serial0 = 
+   ethernet0 = 
};
 
chosen {
@@ -28,10 +30,36 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   renesas,no-ether-link;
+   phy-handle = <>;
+   phy-mode = "rgmii-txid";
+   status = "okay";
+
+   phy0: ethernet-phy@0 {
+   rxc-skew-ps = <1500>;
+   reg = <0>;
+   interrupt-parent = <>;
+   interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+   reset-gpios = < 20 GPIO_ACTIVE_LOW>;
+   };
+};
+
 _clk {
clock-frequency = <4800>;
 };
 
+ {
+   avb_pins: avb {
+   mux {
+   groups = "avb_link", "avb_mii";
+   function = "avb";
+   };
+   };
+};
+
  {
status = "okay";
 };
-- 
1.9.1

[PATCH 3/4] arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes

[Yoshihiro Shimoda]

This patch adds EthernetAVB node for r8a77990 (R-Car E3).

Based on a patch from Takeshi Kihara 

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 +++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index d94e047..37d57fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -198,6 +198,51 @@
#power-domain-cells = <1>;
};
 
+   avb: ethernet@e680 {
+   compatible = "renesas,etheravb-r8a77990",
+"renesas,etheravb-rcar-gen3";
+   reg = <0 0xe680 0 0x800>, <0 0xe6a0 0 0x1>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+   clocks = < CPG_MOD 812>;
+   power-domains = < 32>;
+   resets = < 812>;
+   phy-mode = "rgmii";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
1.9.1

[PATCH 0/4] arm64: dts: renesas: r8a77990: Enable EthernetAVB for ebisu board

[Yoshihiro Shimoda]

This patch set is based on renesas-drivers-2018-05-02-v4.17-rc3 tag of
renesas-drivers.git.

The dt-bindings patches of GPIO and EthernetAVB are submitted now:
https://patchwork.kernel.org/patch/10393001/
https://patchwork.kernel.org/patch/10393049/

Yoshihiro Shimoda (4):
  arm64: dts: renesas: r8a77990: Add PFC device node
  arm64: dts: renesas: r8a77990: Add GPIO device nodes
  arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
  arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts |  28 +
 arch/arm64/boot/dts/renesas/r8a77990.dtsi  | 162 +
 2 files changed, 190 insertions(+)

-- 
1.9.1

[PATCH 1/4] arm64: dts: renesas: r8a77990: Add PFC device node

[Yoshihiro Shimoda]

This patch adds PFC device node for r8a77990 (R-Car E3).

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 4658029..efc3c0b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,11 @@
#size-cells = <2>;
ranges;
 
+   pfc: pin-controller@e606 {
+   compatible = "renesas,pfc-r8a77990";
+   reg = <0 0xe606 0 0x508>;
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
-- 
1.9.1

[PATCH 3/6] pinctrl: sh-pfc: r8a77990: Add bias pinconf support

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch implements control of pull-up and pull-down. On this SoC there
is no simple mapping of GP pins to bias register bits, so we need a table.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 340 +-
 1 file changed, 331 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 0af2fef..1fe8aee 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -16,15 +16,17 @@
 #include "core.h"
 #include "sh_pfc.h"
 
-#define CPU_ALL_PORT(fn, sfx)  \
-   PORT_GP_18(0, fn, sfx), \
-   PORT_GP_23(1, fn, sfx), \
-   PORT_GP_26(2, fn, sfx), \
-   PORT_GP_16(3, fn, sfx), \
-   PORT_GP_11(4, fn, sfx), \
-   PORT_GP_20(5, fn, sfx), \
-   PORT_GP_18(6, fn, sfx)
-
+#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
+  SH_PFC_PIN_CFG_PULL_DOWN)
+
+#define CPU_ALL_PORT(fn, sfx) \
+   PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
+   PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
@@ -461,6 +463,17 @@
 MOD_SEL0_2 \
 MOD_SEL0_1_0
 
+/*
+ * These pins are not able to be muxed but have other properties
+ * that can be set, such as pull-up/pull-down enable.
+ */
+#define PINMUX_STATIC \
+   FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
+   FM(AVB_TD3) \
+   FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
+   FM(ASEBRK) \
+   FM(MLB_REF)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -485,6 +498,7 @@ enum {
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
+   PINMUX_STATIC
PINMUX_MARK_END,
 #undef F_
 #undef FM
@@ -493,6 +507,13 @@ enum {
 static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
 
+   PINMUX_SINGLE(CLKOUT),
+   PINMUX_SINGLE(AVB_PHY_INT),
+   PINMUX_SINGLE(AVB_RD3),
+   PINMUX_SINGLE(AVB_RXC),
+   PINMUX_SINGLE(AVB_RX_CTL),
+   PINMUX_SINGLE(QSPI0_SSL),
+
/* IPSR0 */
PINMUX_IPSR_GPSR(IP0_3_0,   QSPI0_SPCLK),
PINMUX_IPSR_MSEL(IP0_3_0,   HSCK4_A,SEL_HSCIF4_0),
@@ -1227,10 +1248,55 @@ enum {
 
PINMUX_IPSR_GPSR(IP15_31_28,USB30_OVC),
PINMUX_IPSR_MSEL(IP15_31_28,USB0_OVC_A, 
SEL_USB_20_CH0_0),
+
+/*
+ * Static pins can not be muxed between different functions but
+ * still needs a mark entry in the pinmux list. Add each static
+ * pin to the list without an associated function. The sh-pfc
+ * core will do the right thing and skip trying to mux then pin
+ * while still applying configuration to it
+ */
+#define FM(x)   PINMUX_DATA(x##_MARK, 0),
+   PINMUX_STATIC
+#undef FM
 };
 
+/*
+ * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
+ * Physical layout rows: A - AE, cols: 1 - 25.
+ */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+#define PIN_NONE U16_MAX
+
 static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+
+   /*
+* Pins not associated with a GPIO port.
+*
+* The pin positions are different between different R8A77990
+* packages, all that is needed for the pfc driver is a unique
+* number for each pin. To this end use the pin layout from
+* R8A77990 to calculate a unique number for each pin.
+*/
+   SH_PFC_PIN_NAMED_CFG('F',  1, TRST_N,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('F',  3, TMS,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('F',  4, TCK,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('G',  2, TDI,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('G',  3, FSCLKST_N,CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('H',  1, ASEBRK,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  1, AVB_TXC,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  2, AVB_TD0,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  3, AVB_TD1,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  5, AVB_TD2,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('N',  6, AVB_TD3,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  3, AVB_TX_CTL,   CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  4, AVB_MDIO, CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('P',  5, AVB_MDC,  CFG_FLAGS),
+   SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF,  CFG_FLAGS),
+   

[PATCH 4/6] pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990
SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 365 ++
 1 file changed, 365 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fe8aee..96779a0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1299,10 +1299,375 @@ enum {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
 };
 
+/* - SCIF0 -- 
*/
+static const unsigned int scif0_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int scif0_data_a_mux[] = {
+   RX0_A_MARK, TX0_A_MARK,
+};
+
+static const unsigned int scif0_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int scif0_clk_a_mux[] = {
+   SCK0_A_MARK,
+};
+
+static const unsigned int scif0_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int scif0_ctrl_a_mux[] = {
+   RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+};
+
+static const unsigned int scif0_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int scif0_data_b_mux[] = {
+   RX0_B_MARK, TX0_B_MARK,
+};
+
+static const unsigned int scif0_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int scif0_clk_b_mux[] = {
+   SCK0_B_MARK,
+};
+
+/* - SCIF1 -- 
*/
+static const unsigned int scif1_data_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int scif1_data_mux[] = {
+   RX1_MARK, TX1_MARK,
+};
+
+static const unsigned int scif1_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 16),
+};
+
+static const unsigned int scif1_clk_mux[] = {
+   SCK1_MARK,
+};
+
+static const unsigned int scif1_ctrl_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int scif1_ctrl_mux[] = {
+   RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF2 -- 
*/
+static const unsigned int scif2_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
+};
+
+static const unsigned int scif2_data_a_mux[] = {
+   RX2_A_MARK, TX2_A_MARK,
+};
+
+static const unsigned int scif2_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int scif2_clk_a_mux[] = {
+   SCK2_A_MARK,
+};
+
+static const unsigned int scif2_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int scif2_data_b_mux[] = {
+   RX2_B_MARK, TX2_B_MARK,
+};
+
+/* - SCIF3 -- 
*/
+static const unsigned int scif3_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int scif3_data_a_mux[] = {
+   RX3_A_MARK, TX3_A_MARK,
+};
+
+static const unsigned int scif3_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(0, 1),
+};
+
+static const unsigned int scif3_clk_a_mux[] = {
+   SCK3_A_MARK,
+};
+
+static const unsigned int scif3_ctrl_a_pins[] = {
+   /* RTS, CTS */
+   RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
+};
+
+static const unsigned int scif3_ctrl_a_mux[] = {
+   RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+};
+
+static const unsigned int scif3_data_b_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+
+static const unsigned int scif3_data_b_mux[] = {
+   RX3_B_MARK, TX3_B_MARK,
+};
+
+static const unsigned int scif3_data_c_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int scif3_data_c_mux[] = {
+   RX3_C_MARK, TX3_C_MARK,
+};
+
+static const unsigned int scif3_clk_c_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int scif3_clk_c_mux[] = {
+   SCK3_C_MARK,
+};
+
+/* - SCIF4 -- 
*/
+static const unsigned int scif4_data_a_pins[] = {
+   /* RX, TX */
+   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int scif4_data_a_mux[] = {
+   RX4_A_MARK, TX4_A_MARK,
+};
+
+static const unsigned int scif4_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(1, 5),
+};
+
+static const unsigned int scif4_clk_a_mux[] = {
+   SCK4_A_MARK,
+};
+
+static const unsigned int scif4_ctrl_a_pins[] = {
+   /* RTS, 

[PATCH 2/6] pinctrl: sh-pfc: Initial R8A77990 PFC support

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch adds initial pinctrl driver to support for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt   |1 +
 drivers/pinctrl/sh-pfc/Kconfig |5 +
 drivers/pinctrl/sh-pfc/Makefile|1 +
 drivers/pinctrl/sh-pfc/core.c  |6 +
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c  | 1728 
 drivers/pinctrl/sh-pfc/sh_pfc.h|1 +
 6 files changed, 1742 insertions(+)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77990.c

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 4f5fca1..abd8fbc 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -28,6 +28,7 @@ Required Properties:
 - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible 
pin-controller.
 - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible 
pin-controller.
 - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible 
pin-controller.
+- "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible 
pin-controller.
 - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible 
pin-controller.
 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible 
pin-controller.
 
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c11b789..3c2758a 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -104,6 +104,11 @@ config PINCTRL_PFC_R8A77980
depends on ARCH_R8A77980
select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A77990
+def_bool y
+depends on ARCH_R8A77990
+select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A77995
 def_bool y
 depends on ARCH_R8A77995
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 463775f..655dc14 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)   += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)   += pfc-sh7264.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 74861b7..c78f662 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -575,6 +575,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
.data = _pinmux_info,
},
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
+   {
+   .compatible = "renesas,pfc-r8a77990",
+   .data = _pinmux_info,
+   },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A77995
{
.compatible = "renesas,pfc-r8a77995",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
new file mode 100644
index 000..0af2fef
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -0,0 +1,1728 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77990 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ *
+ * R8A7796 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ */
+
+#include 
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)  \
+   PORT_GP_18(0, fn, sfx), \
+   PORT_GP_23(1, fn, sfx), \
+   PORT_GP_26(2, fn, sfx), \
+   PORT_GP_16(3, fn, sfx), \
+   PORT_GP_11(4, fn, sfx), \
+   PORT_GP_20(5, fn, sfx), \
+   PORT_GP_18(6, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_17   F_(SDA4,IP7_27_24)
+#define GPSR0_16   F_(SCL4,IP7_23_20)
+#define GPSR0_15   F_(D15, IP7_19_16)
+#define GPSR0_14   F_(D14, IP7_15_12)
+#define GPSR0_13   F_(D13, IP7_11_8)
+#define GPSR0_12   F_(D12, IP7_7_4)
+#define GPSR0_11   F_(D11, IP7_3_0)
+#define GPSR0_10   F_(D10, IP6_31_28)
+#define GPSR0_9F_(D9,  IP6_27_24)
+#define GPSR0_8F_(D8,  IP6_23_20)
+#define GPSR0_7F_(D7,  IP6_19_16)
+#define GPSR0_6

[PATCH 6/6] pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP
pins for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 90 +++
 1 file changed, 90 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 508dc21..6c692fa 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1299,6 +1299,78 @@ enum {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
 };
 
+/* - EtherAVB --- 
*/
+static const unsigned int avb_link_pins[] = {
+   /* AVB_LINK */
+   RCAR_GP_PIN(2, 23),
+};
+
+static const unsigned int avb_link_mux[] = {
+   AVB_LINK_MARK,
+};
+
+static const unsigned int avb_magic_pins[] = {
+   /* AVB_MAGIC */
+   RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int avb_magic_mux[] = {
+   AVB_MAGIC_MARK,
+};
+
+static const unsigned int avb_phy_int_pins[] = {
+   /* AVB_PHY_INT */
+   RCAR_GP_PIN(2, 21),
+};
+
+static const unsigned int avb_phy_int_mux[] = {
+   AVB_PHY_INT_MARK,
+};
+
+static const unsigned int avb_mii_pins[] = {
+   /*
+* AVB_RX_CTL, AVB_RXC, AVB_RD0,
+* AVB_RD1, AVB_RD2, AVB_RD3,
+* AVB_TXCREFCLK
+*/
+   RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+   RCAR_GP_PIN(2, 20),
+};
+
+static const unsigned int avb_mii_mux[] = {
+   AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
+   AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+   AVB_TXCREFCLK_MARK,
+};
+
+static const unsigned int avb_avtp_pps_pins[] = {
+   /* AVB_AVTP_PPS */
+   RCAR_GP_PIN(1, 2),
+};
+
+static const unsigned int avb_avtp_pps_mux[] = {
+   AVB_AVTP_PPS_MARK,
+};
+
+static const unsigned int avb_avtp_match_a_pins[] = {
+   /* AVB_AVTP_MATCH_A */
+   RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int avb_avtp_match_a_mux[] = {
+   AVB_AVTP_MATCH_A_MARK,
+};
+
+static const unsigned int avb_avtp_capture_a_pins[] = {
+   /* AVB_AVTP_CAPTURE_A */
+   RCAR_GP_PIN(2, 25),
+};
+
+static const unsigned int avb_avtp_capture_a_mux[] = {
+   AVB_AVTP_CAPTURE_A_MARK,
+};
+
 /* - I2C  
*/
 static const unsigned int i2c1_a_pins[] = {
/* SCL, SDA */
@@ -1713,6 +1785,13 @@ enum {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+   SH_PFC_PIN_GROUP(avb_link),
+   SH_PFC_PIN_GROUP(avb_magic),
+   SH_PFC_PIN_GROUP(avb_phy_int),
+   SH_PFC_PIN_GROUP(avb_mii),
+   SH_PFC_PIN_GROUP(avb_avtp_pps),
+   SH_PFC_PIN_GROUP(avb_avtp_match_a),
+   SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c1_c),
@@ -1760,6 +1839,16 @@ enum {
SH_PFC_PIN_GROUP(scif_clk_b),
 };
 
+static const char * const avb_groups[] = {
+   "avb_link",
+   "avb_magic",
+   "avb_phy_int",
+   "avb_mii",
+   "avb_avtp_pps",
+   "avb_avtp_match_a",
+   "avb_avtp_capture_a",
+};
+
 static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@@ -1845,6 +1934,7 @@ enum {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+   SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c4),
-- 
1.9.1

[PATCH 1/6] pinctrl: sh-pfc: Add PORT_GP_11 helper macro

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 7fad897..b1a9957 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -415,9 +415,13 @@ struct sh_pfc_soc_info {
PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
 #define PORT_GP_10(bank, fn, sfx)  PORT_GP_CFG_10(bank, fn, sfx, 0)
 
-#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
-   PORT_GP_CFG_1(bank, 10, fn, sfx, cfg),  \
+   PORT_GP_CFG_1(bank, 10,  fn, sfx, cfg)
+#define PORT_GP_11(bank, fn, sfx)  PORT_GP_CFG_11(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
+   PORT_GP_CFG_11(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 #define PORT_GP_12(bank, fn, sfx)  PORT_GP_CFG_12(bank, fn, sfx, 0)
 
-- 
1.9.1

[PATCH 0/6] pinctrl: sh-pfc: Initial R8A77990 PFC support

[Yoshihiro Shimoda]

This patch set is based on renesas-drivers-2018-05-02-v4.17-rc3 tag of
renesas-drivers.git.

Takeshi Kihara (6):
  pinctrl: sh-pfc: Add PORT_GP_11 helper macro
  pinctrl: sh-pfc: Initial R8A77990 PFC support
  pinctrl: sh-pfc: r8a77990: Add bias pinconf support
  pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and
functions
  pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt   |1 +
 drivers/pinctrl/sh-pfc/Kconfig |5 +
 drivers/pinctrl/sh-pfc/Makefile|1 +
 drivers/pinctrl/sh-pfc/core.c  |6 +
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c  | 2695 
 drivers/pinctrl/sh-pfc/sh_pfc.h|9 +-
 6 files changed, 2715 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77990.c

-- 
1.9.1

[PATCH 5/6] pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions

[Yoshihiro Shimoda]

From: Takeshi Kihara 

This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to
the R8A77990 SoC.

NOTE: I2C0 and I2C3 are not pin multiplexed.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Shimoda 
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 190 ++
 1 file changed, 190 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 96779a0..508dc21 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1299,6 +1299,142 @@ enum {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
 };
 
+/* - I2C  
*/
+static const unsigned int i2c1_a_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int i2c1_a_mux[] = {
+   SCL1_A_MARK, SDA1_A_MARK,
+};
+
+static const unsigned int i2c1_b_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int i2c1_b_mux[] = {
+   SCL1_B_MARK, SDA1_B_MARK,
+};
+
+static const unsigned int i2c1_c_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int i2c1_c_mux[] = {
+   SCL1_C_MARK, SDA1_C_MARK,
+};
+
+static const unsigned int i2c1_d_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int i2c1_d_mux[] = {
+   SCL1_D_MARK, SDA1_D_MARK,
+};
+
+static const unsigned int i2c2_a_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int i2c2_a_mux[] = {
+   SCL2_A_MARK, SDA2_A_MARK,
+};
+
+static const unsigned int i2c2_b_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int i2c2_b_mux[] = {
+   SCL2_B_MARK, SDA2_B_MARK,
+};
+
+static const unsigned int i2c2_c_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int i2c2_c_mux[] = {
+   SCL2_C_MARK, SDA2_C_MARK,
+};
+
+static const unsigned int i2c2_d_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int i2c2_d_mux[] = {
+   SCL2_D_MARK, SDA2_D_MARK,
+};
+
+static const unsigned int i2c2_e_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int i2c2_e_mux[] = {
+   SCL2_E_MARK, SDA2_E_MARK,
+};
+
+static const unsigned int i2c4_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
+};
+
+static const unsigned int i2c4_mux[] = {
+   SCL4_MARK, SDA4_MARK,
+};
+
+static const unsigned int i2c5_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+
+static const unsigned int i2c5_mux[] = {
+   SCL5_MARK, SDA5_MARK,
+};
+
+static const unsigned int i2c6_a_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
+};
+
+static const unsigned int i2c6_a_mux[] = {
+   SCL6_A_MARK, SDA6_A_MARK,
+};
+
+static const unsigned int i2c6_b_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
+};
+
+static const unsigned int i2c6_b_mux[] = {
+   SCL6_B_MARK, SDA6_B_MARK,
+};
+
+static const unsigned int i2c7_a_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
+};
+
+static const unsigned int i2c7_a_mux[] = {
+   SCL7_A_MARK, SDA7_A_MARK,
+};
+
+static const unsigned int i2c7_b_pins[] = {
+   /* SCL, SDA */
+   RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+};
+
+static const unsigned int i2c7_b_mux[] = {
+   SCL7_B_MARK, SDA7_B_MARK,
+};
+
 /* - SCIF0 -- 
*/
 static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -1577,6 +1713,21 @@ enum {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+   SH_PFC_PIN_GROUP(i2c1_a),
+   SH_PFC_PIN_GROUP(i2c1_b),
+   SH_PFC_PIN_GROUP(i2c1_c),
+   SH_PFC_PIN_GROUP(i2c1_d),
+   SH_PFC_PIN_GROUP(i2c2_a),
+   SH_PFC_PIN_GROUP(i2c2_b),
+   SH_PFC_PIN_GROUP(i2c2_c),
+   SH_PFC_PIN_GROUP(i2c2_d),
+   SH_PFC_PIN_GROUP(i2c2_e),
+   SH_PFC_PIN_GROUP(i2c4),
+   SH_PFC_PIN_GROUP(i2c5),
+   SH_PFC_PIN_GROUP(i2c6_a),
+   SH_PFC_PIN_GROUP(i2c6_b),
+   SH_PFC_PIN_GROUP(i2c7_a),
+   SH_PFC_PIN_GROUP(i2c7_b),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@@ -1609,6 +1760,39 @@ enum {
SH_PFC_PIN_GROUP(scif_clk_b),
 };
 
+static const char * const i2c1_groups[] = {
+   "i2c1_a",
+   "i2c1_b",
+   "i2c1_c",
+   "i2c1_d",
+};
+
+static const char * const 

[PATCH] dt-bindings: net: ravb: Add support for r8a77990 SoC

[Yoshihiro Shimoda]

Add documentation for r8a77990 compatible string to renesas ravb device
tree bindings documentation.

Signed-off-by: Yoshihiro Shimoda 
---
 Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt 
b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 890526d..fac897d 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -21,6 +21,7 @@ Required properties:
   - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
   - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
   - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+  - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
   - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
   - "renesas,etheravb-rcar-gen3" as a fallback for the above
R-Car Gen3 devices.
-- 
1.9.1

RE: [PATCH] dt-bindings: net: ravb: Add support for r8a77990 SoC

[Yoshihiro Shimoda]

Hi All,

I'm sorry I submitted this patch to incorrect addresses.
So, would you delete this?

Best regards,
Yoshihiro Shimoda

> From: Yoshihiro Shimoda, Sent: Friday, May 11, 2018 12:13 PM
> 
> Add documentation for r8a77990 compatible string to renesas ravb device
> tree bindings documentation.
> 
> Signed-off-by: Yoshihiro Shimoda 
> ---
>  Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> index 890526d..fac897d 100644
> --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
> +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
> @@ -21,6 +21,7 @@ Required properties:
>- "renesas,etheravb-r8a77965" for the R8A77965 SoC.
>- "renesas,etheravb-r8a77970" for the R8A77970 SoC.
>- "renesas,etheravb-r8a77980" for the R8A77980 SoC.
> +  - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
>- "renesas,etheravb-r8a77995" for the R8A77995 SoC.
>- "renesas,etheravb-rcar-gen3" as a fallback for the above
>   R-Car Gen3 devices.
> --
> 1.9.1

[PATCH] dt-bindings: net: ravb: Add support for r8a77990 SoC

[Yoshihiro Shimoda]

Add documentation for r8a77990 compatible string to renesas ravb device
tree bindings documentation.

Signed-off-by: Yoshihiro Shimoda 
---
 Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt 
b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 890526d..fac897d 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -21,6 +21,7 @@ Required properties:
   - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
   - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
   - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
+  - "renesas,etheravb-r8a77990" for the R8A77990 SoC.
   - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
   - "renesas,etheravb-rcar-gen3" as a fallback for the above
R-Car Gen3 devices.
-- 
1.9.1

[PATCH] dt-bindings: gpio: rcar: Add support for r8a77990

[Yoshihiro Shimoda]

Add compatible string for R-Car E3 (r8a77990) in gpio-rcar.

Signed-off-by: Yoshihiro Shimoda 
---
 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt 
b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 9744d42..378f132 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -17,6 +17,7 @@ Required Properties:
 - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO 
controller.
 - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO 
controller.
 - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO 
controller.
+- "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO 
controller.
 - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO 
controller.
 - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
 - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO 
controller.
-- 
1.9.1

[PATCH 2/2] arm64: dts: renesas: initial V3HSK board device tree

[Sergei Shtylyov]

Add the initial device  tree for  the V3H Starter Kit board.
The board has 1 debug serial port (SCIF0); include support for it,
so that the serial console can work.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
 arch/arm64/boot/dts/renesas/Makefile   |2 
 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts |   60 +
 2 files changed, 61 insertions(+), 1 deletion(-)

Index: renesas/arch/arm64/boot/dts/renesas/Makefile
===
--- renesas.orig/arch/arm64/boot/dts/renesas/Makefile
+++ renesas/arch/arm64/boot/dts/renesas/Makefile
@@ -9,6 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
-dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
 dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===
--- /dev/null
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3H Starter Kit board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+   model = "Renesas V3H Starter Kit board";
+   compatible = "renesas,v3hsk", "renesas,r8a77980";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0 0x4800 0 0x7800>;
+   };
+};
+
+_clk {
+   clock-frequency = <1666>;
+};
+
+_clk {
+   clock-frequency = <32768>;
+};
+
+ {
+   scif0_pins: scif0 {
+   groups = "scif0_data";
+   function = "scif0";
+   };
+
+   scif_clk_pins: scif_clk {
+   groups = "scif_clk_b";
+   function = "scif_clk";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>, <_clk_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+};
+
+_clk {
+   clock-frequency = <14745600>;
+};

[PATCH 1/2] dt-bindings: arm: document Renesas V3HSK board bindings

[Sergei Shtylyov]

Document the V3H Starter Kit device tree bindings, listing it as
a supported board.

This allows to use checkpatch.pl to validate .dts files referring to
the V3HSK board.

Signed-off-by: Sergei Shtylyov 

---
 Documentation/devicetree/bindings/arm/shmobile.txt |2 ++
 1 file changed, 2 insertions(+)

Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -132,6 +132,8 @@ Boards:
 compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
   - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
 compatible = "renesas,stout", "renesas,r8a7790"
+  - V3HSK (Y-ASK-RCAR-V3H-WS10)
+compatible = "renesas,v3hsk", "renesas,r8a77980"
   - V3MSK (Y-ASK-RCAR-V3M-WS10)
 compatible = "renesas,v3msk", "renesas,r8a77970"
   - Wheat (RTP0RC7792ASKBJE)

[PATCH 0/2] Add V3H Starter Kit board support

[Sergei Shtylyov]

Hello!

Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180509-v4.17-rc4' tag. I'm adding the device tree support
for the R8A77980-based V3H Starter Kit board; only serial console is supported
for now, NFS support will require more work (it won't use EtherAVB but GEther)
and will be posted later...

[1/2] dt-bindings: arm: document Renesas V3HSK board bindings
[2/2] arm64: dts: renesas: initial V3HSK board device tree

WBR, Sergei

Re: [PATCH] arm64: dts: renesas: r8a77970: add SMP support

[Sergei Shtylyov]

Hello!

On 05/09/2018 10:05 PM, Simon Horman wrote:

 Add the device node for the second Cortex-A53 CPU core.

 Based on the original (and large) patch by Daisuke Matsushita
 .

 Signed-off-by: Vladimir Barinov 
 Signed-off-by: Sergei Shtylyov 
>>>
>>> Dupe of https://patchwork.kernel.org/patch/10032875/
>>
>>Sorry!
>>Not an exact dupe, though -- mine has clock/power #define's used,
>> yours -- only bare #s. :-)
>>
>>> From series "[PATCH 0/2] arm64: dts: renesas: r8a77970: Add SMP Support"
>>> (https://www.spinics.net/lists/linux-renesas-soc/msg19681.html)
>>
>>Hmm... what's the fate of this series?
> 
> There is now a v2 of Geert's series which incorporates your enhancements.

   I suggested to respin it. :-)

> I will apply that.

   Thank you.
   For the record, I had better luck than Geert testing SMP on Eagle: only CPU0
couldn't be offlined (and I was unable to find a workaround), others could be 
on/
offlined w/o issues. As for suspend/resume -- it did work but I could only test
s2idle (/sys/power/mem_sleep had no other variants)...

MBR, Sergei

Re: [2/9] powerpc/watchdog: fix typo 'can by' to 'can be'

[Michael Ellerman]

On Sun, 2018-05-06 at 11:23:46 UTC, Wolfram Sang wrote:
> Signed-off-by: Wolfram Sang 

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/7c18659dd498b25c6651ba83d4267b

cheers

Re: [PATCH 1/9] dt-bindings: i2c: fix typo 'can by' to 'can be'

[Wolfram Sang]

On Sun, May 06, 2018 at 01:23:45PM +0200, Wolfram Sang wrote:
> Signed-off-by: Wolfram Sang 

Applied to for-next, thanks!



signature.asc
Description: PGP signature

Re: [PATCH 0/2] Revert explicit support for Renesas R-Car Gen 3 r8a779[56] SoCs

[Rafael J. Wysocki]

On Wednesday, May 2, 2018 11:58:04 AM CEST Simon Horman wrote:
> Revert commits that added explicit support for Renesas R-Car Gen 3
> r8a779[56] SoCs to the generic cpufreq driver.
> 
> This is no longer needed since the flowing commit and to the best of my
> knowledge is not relied on by any upstream DTS: edeec420de24 ("cpufreq:
> dt-platdev: Automatically create cpufreq device with OPP v2")
> 
> Simon Horman (2):
>   Revert "cpufreq: dt: Add r8a7796 support to to use generic cpufreq
> driver"
>   Revert "cpufreq: rcar: Add support for R8A7795 SoC"
> 
>  drivers/cpufreq/cpufreq-dt-platdev.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> 

Am I expected to pick up this series?

Thanks,
Rafael

Re: Booting Salvator-X ES1 board with upstream kernel

[Gilad Ben-Yossef]

On Thu, May 10, 2018 at 11:19 AM, Magnus Damm  wrote:
> Hi Gilad,
>
> Thanks for your email.
>
> On Thu, May 10, 2018 at 5:12 PM, Gilad Ben-Yossef  wrote:
>> Hi there,
>>
>> I am trying to add support for the CryptoCell security IP in the
>> R-Rcar boards to mainline but I've run into some trouble.
>>
>> I have an R-Car 3rd gen Salvator-X ES1 board. I've been able to boot
>> Linux 4.9 on it from the rareness-bsp tree, using the defconfig and
>> the r8a7795-es1-salvator-x DTB with no problems, so the HW is fine.
>>
>> However, I can't seem to boot an upstream kernel (Linus master or
>> soc-for-v4.17 branch) on it. I just get total silence on the UART
>> after u-boot.
>>
>> Any tips or ideas for me to try?
>
> Just to clarify, are you using r8a7795 R-Car H3 SoC ES1.0, or some other SoC?
>
> Salvator-X comes in different configurations.

To the best of my knowledge I am indeed using the r8a7795 R-Car H3 SoC ES1.0

Thanks,
Gilad



-- 
Gilad Ben-Yossef
Chief Coffee Drinker

"If you take a class in large-scale robotics, can you end up in a
situation where the homework eats your dog?"
 -- Jean-Baptiste Queru

Re: Booting Salvator-X ES1 board with upstream kernel

[Magnus Damm]

Hi Gilad,

Thanks for your email.

On Thu, May 10, 2018 at 5:12 PM, Gilad Ben-Yossef  wrote:
> Hi there,
>
> I am trying to add support for the CryptoCell security IP in the
> R-Rcar boards to mainline but I've run into some trouble.
>
> I have an R-Car 3rd gen Salvator-X ES1 board. I've been able to boot
> Linux 4.9 on it from the rareness-bsp tree, using the defconfig and
> the r8a7795-es1-salvator-x DTB with no problems, so the HW is fine.
>
> However, I can't seem to boot an upstream kernel (Linus master or
> soc-for-v4.17 branch) on it. I just get total silence on the UART
> after u-boot.
>
> Any tips or ideas for me to try?

Just to clarify, are you using r8a7795 R-Car H3 SoC ES1.0, or some other SoC?

Salvator-X comes in different configurations.

Thanks,

/ magnus

Booting Salvator-X ES1 board with upstream kernel

[Gilad Ben-Yossef]

Hi there,

I am trying to add support for the CryptoCell security IP in the
R-Rcar boards to mainline but I've run into some trouble.

I have an R-Car 3rd gen Salvator-X ES1 board. I've been able to boot
Linux 4.9 on it from the rareness-bsp tree, using the defconfig and
the r8a7795-es1-salvator-x DTB with no problems, so the HW is fine.

However, I can't seem to boot an upstream kernel (Linus master or
soc-for-v4.17 branch) on it. I just get total silence on the UART
after u-boot.

Any tips or ideas for me to try?

Many thanks,
Gilad

-- 
Gilad Ben-Yossef
Chief Coffee Drinker

"If you take a class in large-scale robotics, can you end up in a
situation where the homework eats your dog?"
 -- Jean-Baptiste Queru

Re: [PATCH v2 26/26] drm/bridge: establish a link between the bridge supplier and consumer

[Andrzej Hajda]

On 04.05.2018 15:52, Peter Rosin wrote:
> If the bridge supplier is unbound, this will bring the bridge consumer
> down along with the bridge. Thus, there will no longer linger any
> dangling pointers from the bridge consumer (the drm_device) to some
> non-existent bridge supplier.
>
> Signed-off-by: Peter Rosin 
> ---
>  drivers/gpu/drm/drm_bridge.c | 18 ++
>  include/drm/drm_bridge.h |  2 ++
>  2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index 78d186b6831b..0259f0a3ff27 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -26,6 +26,7 @@
>  #include 
>  
>  #include 
> +#include 
>  #include 
>  
>  #include "drm_crtc_internal.h"
> @@ -127,12 +128,25 @@ int drm_bridge_attach(struct drm_encoder *encoder, 
> struct drm_bridge *bridge,
>   if (bridge->dev)
>   return -EBUSY;
>  
> + if (encoder->dev->dev != bridge->odev) {

I wonder why device_link_add does not handle this case (self dependency)
silently as noop, as it seems to be a correct behavior.

> + bridge->link = device_link_add(encoder->dev->dev,
> +bridge->odev, 0);
> + if (!bridge->link) {
> + dev_err(bridge->odev, "failed to link bridge to %s\n",
> + dev_name(encoder->dev->dev));
> + return -EINVAL;
> + }
> + }
> +
>   bridge->dev = encoder->dev;
>   bridge->encoder = encoder;
>  
>   if (bridge->funcs->attach) {
>   ret = bridge->funcs->attach(bridge);
>   if (ret < 0) {
> + if (bridge->link)
> + device_link_del(bridge->link);
> + bridge->link = NULL;
>   bridge->dev = NULL;
>   bridge->encoder = NULL;
>   return ret;
> @@ -159,6 +173,10 @@ void drm_bridge_detach(struct drm_bridge *bridge)
>   if (bridge->funcs->detach)
>   bridge->funcs->detach(bridge);
>  
> + if (bridge->link)
> + device_link_del(bridge->link);
> + bridge->link = NULL;
> +
>   bridge->dev = NULL;
>  }
>  
> diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
> index b656e505d11e..804189c63a4c 100644
> --- a/include/drm/drm_bridge.h
> +++ b/include/drm/drm_bridge.h
> @@ -261,6 +261,7 @@ struct drm_bridge_timings {
>   * @list: to keep track of all added bridges
>   * @timings: the timing specification for the bridge, if any (may
>   * be NULL)
> + * @link: drm consumer <-> bridge supplier

Nitpick: "<->" suggests symmetry, maybe "device link from drm consumer
to the bridge" would be better.

Anyway:
Reviewed-by: Andrzej Hajda 

 --
Regards
Andrzej

>   * @funcs: control functions
>   * @driver_private: pointer to the bridge driver's internal context
>   */
> @@ -271,6 +272,7 @@ struct drm_bridge {
>   struct drm_bridge *next;
>   struct list_head list;
>   const struct drm_bridge_timings *timings;
> + struct device_link *link;
>  
>   const struct drm_bridge_funcs *funcs;
>   void *driver_private;

RE: [PATCH v2 0/6] usb: gadget: udc: renesas_usb3: fix some major issues

[Yoshihiro Shimoda]

Hi Felipe,

> From: Yoshihiro Shimoda, Sent: Tuesday, April 10, 2018 2:39 PM
> 
> This patch set is based on v4.16.

Would you review this patch set?
I checked this is able to be applied on your testing/fixes branch.

Best regards,
Yoshihiro Shimoda

> Changes from v1:
>  - Add Reviewed-by in patch 1, 2, 3 and 4.
>  - Revise typo in patch 4.
>  - Add new patches as patch 5 and 6.
> 
> Yoshihiro Shimoda (6):
>   usb: gadget: udc: renesas_usb3: fix double phy_put()
>   usb: gadget: udc: renesas_usb3: should remove debugfs
>   usb: gadget: udc: renesas_usb3: should call pm_runtime_enable() before
> add udc
>   usb: gadget: udc: renesas_usb3: should call devm_phy_get() before add
> udc
>   usb: gadget: udc: renesas_usb3: should fail if devm_phy_get() returns
> error
>   usb: gadget: udc: renesas_usb3: disable the controller's irqs for
> reconnecting
> 
>  drivers/usb/gadget/udc/renesas_usb3.c | 37 
> +++
>  1 file changed, 25 insertions(+), 12 deletions(-)
> 
> --
> 1.9.1

Re: [PATCH v2 25/26] drm/bridge: require the owner .odev to be filled in on drm_bridge_add/attach

[Andrzej Hajda]

On 04.05.2018 15:52, Peter Rosin wrote:
> The .odev owner device will be handy to have around.
>
> Signed-off-by: Peter Rosin 
Reviewed-by: Andrzej Hajda 

 --
Regards
Andrzej
> ---
>  drivers/gpu/drm/drm_bridge.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c
> index df084db33494..78d186b6831b 100644
> --- a/drivers/gpu/drm/drm_bridge.c
> +++ b/drivers/gpu/drm/drm_bridge.c
> @@ -70,6 +70,9 @@ static LIST_HEAD(bridge_list);
>   */
>  void drm_bridge_add(struct drm_bridge *bridge)
>  {
> + if (WARN_ON(!bridge->odev))
> + return;
> +
>   mutex_lock(_lock);
>   list_add_tail(>list, _list);
>   mutex_unlock(_lock);
> @@ -115,6 +118,9 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct 
> drm_bridge *bridge,
>   if (!encoder || !bridge)
>   return -EINVAL;
>  
> + if (WARN_ON(!bridge->odev))
> + return -EINVAL;
> +
>   if (previous && (!previous->dev || previous->encoder != encoder))
>   return -EINVAL;
>  

Re: [PATCH v2 01/26] drm/bridge: allow optionally specifying an owner .odev device

[Andrzej Hajda]

On 10.05.2018 00:21, Peter Rosin wrote:
> On 2018-05-09 17:53, Peter Rosin wrote:
>> On 2018-05-09 17:08, Andrzej Hajda wrote:
>>> On 04.05.2018 15:51, Peter Rosin wrote:
 Bridge drivers can now (temporarily, in a transition phase) select if
 they want to provide a full owner device or keep just providing an
 of_node.

 By providing a full owner device, the bridge drivers no longer need
 to provide an of_node since that node is available via the owner
 device.

 When all bridge drivers provide an owner device, that will become
 mandatory and the .of_node member will be removed.

 Signed-off-by: Peter Rosin 
 ---
  drivers/gpu/drm/drm_bridge.c | 3 ++-
  drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 +++-
>>> What is the reason to put rockchip here? Shouldn't be in separate patch?
>> Because the rockchip driver peeks into the bridge struct and all the
>> changes in this patch relate to making the new .odev member optional in
>> the transition phase, when the bridge can have either a new-style odev
>> or an old style of_node.
>>
>> I guess this rockchip change could be patch 2, but it has to come first
>> after this patch and it makes no sense on its own. Hence, one patch.
>>
>> This rockchip_lvds interaction is also present in patch 24/26
>> drm/bridge: remove the .of_node member
>>
>> I can split them if you want, but I personally don't see the point.
> I had a second look, and maybe the series should start with a patch like
> this instead, so that the rockchip_lvds.c hunks can be removed from
> patch 1/26 and 24/26. That would perhaps be slightly cleaner?
>
> On the other hand, it's orthogonal and this series can be left as is
> (with the benefit of me not having to do another iteration and you all
> not having another bunch of messages to sift through). The below
> patch could easily be (adjusted and) applied later instead. Or not,
> since the right fix is to do this with the newfangled static image
> format mechanism from Jacopo Mondi, and it might be easier to just do
> it right.
>
> State your preference.

For me the current version is OK, it maybe lacks explanation why do you
need to touch rockchip, from my PoV it did not seem so obvious.
Somebody should fix rockchip to use Jacopo's approach instead of
violating abstractions, but this is another story.

With or without added missing explanation:

Reviewed-by: Andrzej Hajda 

 --
Regards
Andrzej


>
> Cheers,
> Peter
>
> >From dee27b36a36acd271459d1489336b56132097425 Mon Sep 17 00:00:00 2001
> From: Peter Rosin 
> Date: Wed, 9 May 2018 23:58:24 +0200
> Subject: [PATCH] drm/rockchip: lvds: do not dig into the DT of remote bridges
>
> The driver is trying to find the needed "data-mapping" for
> interacting with the following bridge in the graphics chain.
> But, doing so is bad since it is done w/o regard of the
> compatible of the remote bridge, so the value of "data-mapping"
> might not mean what this driver assumes. It is also pointless
> since no bridge has any documented "data-mapping" DT property
> and no dts file show any undocumented use.
>
> Just remove the inappropriate code.
>
> Signed-off-by: Peter Rosin 
> ---
>  drivers/gpu/drm/rockchip/rockchip_lvds.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c 
> b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> index 4bd94b167d2c..fa3f4bf9712f 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
> @@ -377,8 +377,6 @@ static int rockchip_lvds_bind(struct device *dev, struct 
> device *master,
>   }
>   if (lvds->panel)
>   remote = lvds->panel->dev->of_node;
> - else
> - remote = lvds->bridge->of_node;
>   if (of_property_read_string(dev->of_node, "rockchip,output", ))
>   /* default set it as output rgb */
>   lvds->output = DISPLAY_OUTPUT_RGB;