RE: [LTSI-dev] [GIT/RFC PULL LTSI-4.14] Renesas SoCs and Drivers to v4.18-rc6
Hi Simon-san, > From: Simon Horman, Sent: Thursday, July 26, 2018 12:23 AM > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-backport.git > backport/v4.14.57/snapshot-to-v4.18-rc6+fixes-flattened Our test team found that the kernel image could not probe the gpio-pca953x driver because the following commit was missing in the branch: commit 8a64e557f399090f5d1917b2f32a065da2b12be1 Author: Sergei Shtylyov Date: Thu Nov 16 23:18:32 2017 +0300 gpio: pca953x: fix vendor prefix for PCA9654 So, would you backport the commit? Best regards, Yoshihiro Shimoda
[RFC/RTF] drm: rcar-du: lvds: Handle LVDS interface reset
The processor manual prescribes to clear reset of LVDS interface in CPG/MSSR
module before display on, and to assert the same reset line at display off
time, to have the module resuming in a known state.
The module is said to be in "standby state" at initialization time, and this
requires, according to section 37.3.7 of the manual, to de-assert the reset to
have it functional.
Based on the original patch from
Koji Matsuoka
Signed-off-by: Jacopo Mondi
---
This patch upports commit:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/
?id=23b62b82a5a705d28ddac1d973ee98e6f51d54ea
Even without this patch the LVDS interface has been succesfully tested on
V3M/Eagle boards, and this makes me wonder on the real need for reset to
be handled by the driver.
I've been able to 'test' the reset assertion/deassertion on Draak, whose LVDS
interface is not yet being enabled due to missing LVDS PLL support.
If someone with a V3M/Eagle could test this to make sure this doesn't break
anything, we can then discuss on the real need for this patch to be mainlined.
Also, a series of patches to add reset to R8A7795/R8A7796/R8A77965 LVDS device
nodes will be upported if this patch is considered useful.
For the interested ones (Laurent, Geert) reset de-assertion at display on time
takes in average a hundreds of micro seconds.
Thanks
j
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c
b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index 20e8c34..acf4238 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
@@ -53,6 +54,7 @@ struct rcar_lvds {
void __iomem *mmio;
struct clk *clock;
+ struct reset_control *rst;
bool enabled;
struct drm_display_mode display_mode;
@@ -175,6 +177,12 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
if (ret < 0)
return;
+ ret = reset_control_deassert(lvds->rst);
+ if (ret < 0) {
+ clk_disable_unprepare(lvds->clock);
+ return;
+ }
+
/*
* Hardcode the channels and control signals routing for now.
*
@@ -265,6 +273,7 @@ static void rcar_lvds_disable(struct drm_bridge *bridge)
rcar_lvds_write(lvds, LVDCR0, 0);
rcar_lvds_write(lvds, LVDCR1, 0);
+ reset_control_assert(lvds->rst);
clk_disable_unprepare(lvds->clock);
lvds->enabled = false;
@@ -481,6 +490,12 @@ static int rcar_lvds_probe(struct platform_device *pdev)
return PTR_ERR(lvds->clock);
}
+ lvds->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(lvds->rst)) {
+ dev_err(&pdev->dev, "failed to get reset\n");
+ return PTR_ERR(lvds->rst);
+ }
+
drm_bridge_add(&lvds->bridge);
return 0;
--
2.7.4
Re: [PATCH] ARM: shmobile: silk: Add DA9063 PMIC node
Hi Marek,
On Mon, Jul 30, 2018 at 1:18 PM Marek Vasut wrote:
> Add DA9063 PMIC node to the I2C bus.
>
> Signed-off-by: Marek Vasut
Thanks for your patch!
Oneline-summary prefix should be "ARM: dts: silk:".
> --- a/arch/arm/boot/dts/r8a7794-silk.dts
> +++ b/arch/arm/boot/dts/r8a7794-silk.dts
> @@ -403,6 +403,18 @@
> pinctrl-names = "i2c-hdmi";
>
> clock-frequency = <40>;
> +
> + pmic@5a {
Hmm, the da9063 is actually connected to two i2c buses: i2c1 (3.3v)
and i2c7 (1.8v).
On Koelsch, we describe the 1.8v connection, as that i2c bus
("i2c_dvfs") is meant
for power control.
> + compatible = "dlg,da9063";
> + reg = <0x5a>;
> + interrupt-parent = <&irqc0>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
According to my schematics, the interrupt is connected to GP3_31?
> + interrupt-controller;
> +
> + wdt {
> + compatible = "dlg,da9063-watchdog";
> + };
> + };
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] ARM: shmobile: gose: Add DA9210 node for CPU DVFS
Hi Marek,
On Mon, Jul 30, 2018 at 1:17 PM Marek Vasut wrote:
> Add DA9210 DVFS node to the I2C bus and link it to CPU0 for DVFS.
>
> Signed-off-by: Marek Vasut
Thanks for your patch!
Oneline-summary prefix should be "ARM: dts: gose:".
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RE: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock
> Definitions
>
> Hi Biju,
>
> On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> > Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
> > Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
> > Manual.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
> > @@ -0,0 +1,59 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
> > +
> > +#include
> > +
> > +/* r8a774a1 CPG Core Clocks */
> > +#define R8A774A1_CLK_Z 0
> > +#define R8A774A1_CLK_Z21
> > +#define R8A774A1_CLK_ZG2
> > +#define R8A774A1_CLK_ZTR 3
> > +#define R8A774A1_CLK_ZTRD2 4
> > +#define R8A774A1_CLK_ZT5
> > +#define R8A774A1_CLK_ZX6
> > +#define R8A774A1_CLK_S0D1 7
> > +#define R8A774A1_CLK_S0D2 8
> > +#define R8A774A1_CLK_S0D3 9
> > +#define R8A774A1_CLK_S0D4 10
> > +#define R8A774A1_CLK_S0D6 11
> > +#define R8A774A1_CLK_S0D8 12
> > +#define R8A774A1_CLK_S0D12 13
> > +#define R8A774A1_CLK_S1D2 14
> > +#define R8A774A1_CLK_S1D4 15
> > +#define R8A774A1_CLK_S2D1 16
> > +#define R8A774A1_CLK_S2D2 17
> > +#define R8A774A1_CLK_S2D4 18
> > +#define R8A774A1_CLK_S3D1 19
> > +#define R8A774A1_CLK_S3D2 20
> > +#define R8A774A1_CLK_S3D4 21
> > +#define R8A774A1_CLK_LB22
> > +#define R8A774A1_CLK_CL23
> > +#define R8A774A1_CLK_ZB3 24
> > +#define R8A774A1_CLK_ZB3D2 25
> > +#define R8A774A1_CLK_ZB3D4 26
> > +#define R8A774A1_CLK_CR27
> > +#define R8A774A1_CLK_CRD2 28
> > +#define R8A774A1_CLK_SD0H 29
> > +#define R8A774A1_CLK_SD0 30
> > +#define R8A774A1_CLK_SD1H 31
> > +#define R8A774A1_CLK_SD1 32
> > +#define R8A774A1_CLK_SD2H 33
> > +#define R8A774A1_CLK_SD2 34
> > +#define R8A774A1_CLK_SD3H 35
> > +#define R8A774A1_CLK_SD3 36
> > +#define R8A774A1_CLK_RPC 37
> > +#define R8A774A1_CLK_RPCD2 38
> > +#define R8A774A1_CLK_MSO 39
> > +#define R8A774A1_CLK_HDMI 40
> > +#define R8A774A1_CLK_CSI0 41
> > +#define R8A774A1_CLK_CP42
> > +#define R8A774A1_CLK_POST2 43
>
> POST2 is an internal clock, which doesn't need to be referred to from DT.
> So please drop it from the bindings.
Will send V2 with the above fix.
> > +#define R8A774A1_CLK_CPEX 44
> > +#define R8A774A1_CLK_R 45
> > +#define R8A774A1_CLK_OSC 46
>
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
RE: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support
>
> Hi Biju,
>
> On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> > Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and
> > Software Reset support.
> >
> > Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
> > Hardware ((Rev. 0.61, June 12, 2018)".
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
>
> > +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
>
> > + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL,
> CPG_RCKCR, 8),
> > + DEF_DIV6_RO("r_int",CLK_RINT, CLK_EXTAL, CPG_RCKCR,
> > 32),
>
> RZ/G2M does not have the CPG_RCKCR register.
> The internal R CLK is an internal clock, hence please name it ".r".
>
> Please have a look at "clk: renesas: rcar-gen3: OSC and RCLK improvements"
> (https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=2063)
Will send V2 incorporating this changes.
> > +/*
> > + * CPG Clock Data
> > + */
> > +
> > +/*
> > + * MDEXTAL PLL0PLL1PLL2PLL3PLL4
> > + * 14 13 19 17 (MHz)
> > + *---
> > + * 0 0 0 0 16.66 x 1 x180x192x144x192x144
> > + * 0 0 0 1 16.66 x 1 x180x192x144x128x144
> > + * 0 0 1 0 Prohibited setting
> > + * 0 0 1 1 16.66 x 1 x180x192x144x192x144
> > + * 0 1 0 0 20x 1 x150x160x120x160x120
> > + * 0 1 0 1 20x 1 x150x160x120x106x120
> > + * 0 1 1 0 Prohibited setting
> > + * 0 1 1 1 20x 1 x150x160x120x160x120
> > + * 1 0 0 0 25x 1 x120x128x96 x128x96
> > + * 1 0 0 1 25x 1 x120x128x96 x84 x96
> > + * 1 0 1 0 Prohibited setting
> > + * 1 0 1 1 25x 1 x120x128x96 x128x96
> > + * 1 1 0 0 33.33 / 2 x180x192x144x192x144
> > + * 1 1 0 1 33.33 / 2 x180x192x144x128x144
> > + * 1 1 1 0 Prohibited setting
> > + * 1 1 1 1 33.33 / 2 x180x192x144x192x144
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 11) | \
> > +(((md) & BIT(13)) >> 11) | \
> > +(((md) & BIT(19)) >> 18) | \
> > +(((md) & BIT(17)) >> 17))
> > +
> > +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16]
> __initconst = {
> > + /* EXTAL divPLL1 mult/div PLL3 mult/div */
> > + { 1,192,1, 192,1, },
> > + { 1,192,1, 128,1, },
> > + { 0, /* Prohibited setting */ },
> > + { 1,192,1, 192,1, },
> > + { 1,160,1, 160,1, },
> > + { 1,160,1, 106,1, },
> > + { 0, /* Prohibited setting */ },
> > + { 1,160,1, 160,1, },
> > + { 1,128,1, 128,1, },
> > + { 1,128,1, 84, 1, },
> > + { 0, /* Prohibited setting */ },
> > + { 1,128,1, 128,1, },
> > + { 2,192,1, 192,1, },
> > + { 2,192,1, 128,1, },
> > + { 0, /* Prohibited setting */ },
> > + { 2,192,1, 192,1, },
> > +};
>
> Please add the new OSC predividers. You're gonna need them for the
> corrected OSC clock.
Will send V2 incorporating this changes.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
Re: [PATCH 5/5] clk: renesas: cpg-mssr: Add r8a774a1 support
Hi Biju,
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Add RZ/G2M (R8A774A1) Clock Pulse Generator / Module Standby and Software
> Reset support.
>
> Based on the Table 8.2b of "RZ/G Series, 2nd Generation User's Manual:
> Hardware ((Rev. 0.61, June 12, 2018)".
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
> + DEF_DIV6_RO("osc", R8A774A1_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
> + DEF_DIV6_RO("r_int",CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
RZ/G2M does not have the CPG_RCKCR register.
The internal R CLK is an internal clock, hence please name it ".r".
Please have a look at "clk: renesas: rcar-gen3: OSC and RCLK improvements"
(https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=2063)
> +/*
> + * CPG Clock Data
> + */
> +
> +/*
> + * MDEXTAL PLL0PLL1PLL2PLL3PLL4
> + * 14 13 19 17 (MHz)
> + *---
> + * 0 0 0 0 16.66 x 1 x180x192x144x192x144
> + * 0 0 0 1 16.66 x 1 x180x192x144x128x144
> + * 0 0 1 0 Prohibited setting
> + * 0 0 1 1 16.66 x 1 x180x192x144x192x144
> + * 0 1 0 0 20x 1 x150x160x120x160x120
> + * 0 1 0 1 20x 1 x150x160x120x106x120
> + * 0 1 1 0 Prohibited setting
> + * 0 1 1 1 20x 1 x150x160x120x160x120
> + * 1 0 0 0 25x 1 x120x128x96 x128x96
> + * 1 0 0 1 25x 1 x120x128x96 x84 x96
> + * 1 0 1 0 Prohibited setting
> + * 1 0 1 1 25x 1 x120x128x96 x128x96
> + * 1 1 0 0 33.33 / 2 x180x192x144x192x144
> + * 1 1 0 1 33.33 / 2 x180x192x144x128x144
> + * 1 1 1 0 Prohibited setting
> + * 1 1 1 1 33.33 / 2 x180x192x144x192x144
> + */
> +#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 11) | \
> +(((md) & BIT(13)) >> 11) | \
> +(((md) & BIT(19)) >> 18) | \
> +(((md) & BIT(17)) >> 17))
> +
> +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst
> = {
> + /* EXTAL divPLL1 mult/div PLL3 mult/div */
> + { 1,192,1, 192,1, },
> + { 1,192,1, 128,1, },
> + { 0, /* Prohibited setting */ },
> + { 1,192,1, 192,1, },
> + { 1,160,1, 160,1, },
> + { 1,160,1, 106,1, },
> + { 0, /* Prohibited setting */ },
> + { 1,160,1, 160,1, },
> + { 1,128,1, 128,1, },
> + { 1,128,1, 84, 1, },
> + { 0, /* Prohibited setting */ },
> + { 1,128,1, 128,1, },
> + { 2,192,1, 192,1, },
> + { 2,192,1, 128,1, },
> + { 0, /* Prohibited setting */ },
> + { 2,192,1, 192,1, },
> +};
Please add the new OSC predividers. You're gonna need them for the
corrected OSC clock.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 3/5] soc: renesas: rcar-rst: Add support for RZ/G2M
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 4/5] clk: renesas: Add r8a774a1 CPG Core Clock Definitions
Hi Biju,
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in
> Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's
> Manual.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
> +
> +#include
> +
> +/* r8a774a1 CPG Core Clocks */
> +#define R8A774A1_CLK_Z 0
> +#define R8A774A1_CLK_Z21
> +#define R8A774A1_CLK_ZG2
> +#define R8A774A1_CLK_ZTR 3
> +#define R8A774A1_CLK_ZTRD2 4
> +#define R8A774A1_CLK_ZT5
> +#define R8A774A1_CLK_ZX6
> +#define R8A774A1_CLK_S0D1 7
> +#define R8A774A1_CLK_S0D2 8
> +#define R8A774A1_CLK_S0D3 9
> +#define R8A774A1_CLK_S0D4 10
> +#define R8A774A1_CLK_S0D6 11
> +#define R8A774A1_CLK_S0D8 12
> +#define R8A774A1_CLK_S0D12 13
> +#define R8A774A1_CLK_S1D2 14
> +#define R8A774A1_CLK_S1D4 15
> +#define R8A774A1_CLK_S2D1 16
> +#define R8A774A1_CLK_S2D2 17
> +#define R8A774A1_CLK_S2D4 18
> +#define R8A774A1_CLK_S3D1 19
> +#define R8A774A1_CLK_S3D2 20
> +#define R8A774A1_CLK_S3D4 21
> +#define R8A774A1_CLK_LB22
> +#define R8A774A1_CLK_CL23
> +#define R8A774A1_CLK_ZB3 24
> +#define R8A774A1_CLK_ZB3D2 25
> +#define R8A774A1_CLK_ZB3D4 26
> +#define R8A774A1_CLK_CR27
> +#define R8A774A1_CLK_CRD2 28
> +#define R8A774A1_CLK_SD0H 29
> +#define R8A774A1_CLK_SD0 30
> +#define R8A774A1_CLK_SD1H 31
> +#define R8A774A1_CLK_SD1 32
> +#define R8A774A1_CLK_SD2H 33
> +#define R8A774A1_CLK_SD2 34
> +#define R8A774A1_CLK_SD3H 35
> +#define R8A774A1_CLK_SD3 36
> +#define R8A774A1_CLK_RPC 37
> +#define R8A774A1_CLK_RPCD2 38
> +#define R8A774A1_CLK_MSO 39
> +#define R8A774A1_CLK_HDMI 40
> +#define R8A774A1_CLK_CSI0 41
> +#define R8A774A1_CLK_CP42
> +#define R8A774A1_CLK_POST2 43
POST2 is an internal clock, which doesn't need to be referred to from DT.
So please drop it from the bindings.
> +#define R8A774A1_CLK_CPEX 44
> +#define R8A774A1_CLK_R 45
> +#define R8A774A1_CLK_OSC 46
With the above fixed:
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 2/5] soc: renesas: rcar-sysc: Add r8a774a1 support
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> Add support for RZ/G2M (R8A774A1) SoC power areas to the R-Car SYSC
> driver.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 1/5] dt-bindings: power: Add r8a774a1 SYSC power domain definitions
On Mon, Jul 30, 2018 at 9:54 AM Biju Das wrote:
> This patch adds power domain indices for RZ/G2M.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
RE: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support
Hi Geert, > Subject: Re: [PATCH 1/4] gpio: rcar: Enhance gpio-ranges support > A simple way to work around this is to set ngpios to the highest bit number in > use + 1. But you still need a mechanism to avoid accessing the unused bits in > the gap between 16 and 27. > I will send V2 with following changes 1) Dt binding related to changes for adding optional property " gpio-reserved-ranges" on renesas binding documentation 2) SoC Dtsi with " gpio-ranges = <&pfc 0 96 30>" 3) SoC Dtsi with" gpio-reserved-ranges = <17 10>" which defines unused gpios 4) Handle unused gpios in a) gpio_rcar_request b) gpio_rcar_set_multiple c) gpio_rcar_resume Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
