[PATCH/RFT] arm64: dts: renesas: r8a77990-ebisu: Enable i2c
From: Takeshi Kihara
This patch enables I2C3 channels for the r8a77990-ebisu.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 611f026..4a596ef 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -294,6 +294,10 @@
clock-names = "fck", "dclkin.0", "extal";
};
+&i2c3 {
+ status = "okay";
+};
+
&ohci0 {
status = "okay";
};
--
1.9.1
[PATCH/RFT] arm64: dts: renesas: r8a77990: Enable I2C DMA
From: Takeshi Kihara This patch enables I2C DMA. NOTE: I2C7 DMA is not supported by R-Car Gen3 Hardware User's Manual Rev.0.80E. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko --- This patch is based on the devel branch of Simon Horman's renesas tree. arch/arm64/boot/dts/renesas/r8a77990.dtsi | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a437862..9df0751 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -213,6 +213,9 @@ clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -227,6 +230,9 @@ clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -241,6 +247,9 @@ clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -255,6 +264,8 @@ clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -269,6 +280,8 @@ clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -283,6 +296,8 @@ clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -297,6 +312,8 @@ clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; -- 1.9.1
[PATCH/RFT] arm64: dts: renesas: r8a77990: Add I2C-DVFS device node
From: Takeshi Kihara
This patch adds I2C-DVFS device node for the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 9df0751..5d9905f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -22,7 +22,8 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
- i2c7 = &i2c7;
+ i2c7 = &i2c_dvfs;
+ i2c8 = &i2c7;
};
cpus {
@@ -337,6 +338,22 @@
reg = <0 0xe606 0 0x508>;
};
+ i2c_dvfs: i2c@e60b {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a77990",
+"renesas,rcar-gen3-iic",
+"renesas,rmobile-iic";
+ reg = <0 0xe60b 0 0x34>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 926>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
--
1.9.1
[PATCH/RFT] arm64: dts: renesas: r8a77990-ebisu: Add serial console pins
From: Takeshi Kihara
This patch adds pin control for SCIF2.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index f342dd8..611f026 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -321,6 +321,11 @@
function = "pwm5";
};
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
usb0_pins: usb {
groups = "usb0_b";
function = "usb0";
@@ -352,6 +357,9 @@
};
&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
--
1.9.1
[PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions
From: Takeshi Kihara
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 366 ++
1 file changed, 366 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fdafa4..0d0153a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1459,6 +1459,290 @@ enum {
DU_DISP_MARK,
};
+/* - HSCIF0 --*/
+static const unsigned int hscif0_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int hscif0_data_a_mux[] = {
+ HRX0_A_MARK, HTX0_A_MARK,
+};
+
+static const unsigned int hscif0_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int hscif0_clk_a_mux[] = {
+ HSCK0_A_MARK,
+};
+
+static const unsigned int hscif0_ctrl_a_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int hscif0_ctrl_a_mux[] = {
+ HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+
+static const unsigned int hscif0_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int hscif0_data_b_mux[] = {
+ HRX0_B_MARK, HTX0_B_MARK,
+};
+
+static const unsigned int hscif0_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 13),
+};
+
+static const unsigned int hscif0_clk_b_mux[] = {
+ HSCK0_B_MARK,
+};
+
+/* - HSCIF1 - */
+static const unsigned int hscif1_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int hscif1_data_a_mux[] = {
+ HRX1_A_MARK, HTX1_A_MARK,
+};
+
+static const unsigned int hscif1_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int hscif1_clk_a_mux[] = {
+ HSCK1_A_MARK,
+};
+
+static const unsigned int hscif1_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int hscif1_data_b_mux[] = {
+ HRX1_B_MARK, HTX1_B_MARK,
+};
+
+static const unsigned int hscif1_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int hscif1_clk_b_mux[] = {
+ HSCK1_B_MARK,
+};
+
+static const unsigned int hscif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int hscif1_ctrl_b_mux[] = {
+ HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+
+/* - HSCIF2 - */
+static const unsigned int hscif2_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int hscif2_data_a_mux[] = {
+ HRX2_A_MARK, HTX2_A_MARK,
+};
+
+static const unsigned int hscif2_clk_a_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(6, 14),
+};
+
+static const unsigned int hscif2_clk_a_mux[] = {
+ HSCK2_A_MARK,
+};
+
+static const unsigned int hscif2_ctrl_a_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int hscif2_ctrl_a_mux[] = {
+ HRTS2_N_A_MARK, HCTS2_N_A_MARK,
+};
+
+static const unsigned int hscif2_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int hscif2_data_b_mux[] = {
+ HRX2_B_MARK, HTX2_B_MARK,
+};
+
+/* - HSCIF3 */
+static const unsigned int hscif3_data_a_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+
+static const unsigned int hscif3_data_a_mux[] = {
+ HRX3_A_MARK, HTX3_A_MARK,
+};
+
+static const unsigned int hscif3_data_b_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int hscif3_data_b_mux[] = {
+ HRX3_B_MARK, HTX3_B_MARK,
+};
+
+static const unsigned int hscif3_clk_b_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(0, 4),
+};
+
+static const unsigned int hscif3_clk_b_mux[] = {
+ HSCK3_B_MARK,
+};
+
+static const unsigned int hscif3_data_c_pins[] = {
+ /* RX, TX */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int hscif3_data_c_mux[] = {
+ HRX3_C_MARK, HTX3_C_MARK,
+};
+
+static const unsigned int hscif3_clk_c_pins[] = {
+ /* SCK */
+ RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int hscif3_clk_c_mux[] = {
+ HSCK3_C_MARK,
+};
+
+static const unsigned int hscif3_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
+};
+
+static const unsigned int hscif3_ctrl_c_mux[] = {
+ HRTS3_N_C_MA
[PATCH/RFT] arm64: dts: renesas: r8a77990: Add all HSCIF nodes
From: Takeshi Kihara
This patch adds the device nodes for all HSCIF serial ports to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 88 +++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index f969e68..a437862 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -357,6 +357,94 @@
resets = <&cpg 407>;
};
+ hscif0: serial@e654 {
+ compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe654 0 0x60>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 520>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e655 {
+ compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe655 0 0x60>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 519>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e656 {
+ compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe656 0 0x60>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 518>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a {
+ compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe66a 0 0x60>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 517>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b {
+ compatible = "renesas,hscif-r8a77990",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+ reg = <0 0xe66b 0 0x60>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 516>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+
[PATCH/RFT] arm64: dts: renesas: r8a77990: Add SCIF-{0,1,3,4,5} device nodes
From: Takeshi Kihara
This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports to
the R8A77990 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Yoshihiro Kaneko
---
This patch is based on the devel branch of Simon Horman's renesas tree.
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 83 +++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6d5efeb..f969e68 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -679,6 +679,40 @@
status = "disabled";
};
+ scif0: serial@e6e6 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e6 0 64>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 207>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 206>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -694,6 +728,55 @@
status = "disabled";
};
+ scif3: serial@e6c5 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c5 0 64>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 204>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c4 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c4 0 64>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 203>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f3 {
+ compatible = "renesas,scif-r8a77990",
+"renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f3 0 64>;
+ interrupts = ;
+ clocks = <&cpg CPG_MOD 202>,
+<&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+<&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+
Re: [PATCH v2 5/8] pinctrl: sh-pfc: r8a77990: Add VIN pins, groups and functions
Hi Jacopo,
On Fri, Oct 19, 2018 at 6:55 PM jacopo mondi wrote:
>sorry to resurect this one, but while upporting VIN pin definition
> for R8A77965 I have noticed something in this patch.
>
> Please see below.
>
> On Tue, Oct 02, 2018 at 11:25:31AM +0200, Geert Uytterhoeven wrote:
> > Hi Jacopo,
>
> [snip]
>
> > > @@ -1889,6 +2077,32 @@ static const struct sh_pfc_pin_group
> > > pinmux_groups[] = {
> > > SH_PFC_PIN_GROUP(usb0_id),
> > > SH_PFC_PIN_GROUP(usb30),
> > > SH_PFC_PIN_GROUP(usb30_id),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 8),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 10),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 12),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 16),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 20),
> > > + VIN_DATA_PIN_GROUP(vin4_data_a, 24),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 8),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 10),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 12),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 16),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 20),
> > > + VIN_DATA_PIN_GROUP(vin4_data_b, 24),
>
> look here...
>
> [snip]
>
> > >
> > > +static const char * const vin4_groups[] = {
> > > + "vin4_data8_a",
> > > + "vin4_data10_a",
> > > + "vin4_data12_a",
> > > + "vin4_data16_a",
> > > + "vin4_data20_a",
> > > + "vin4_data24_a",
> > > + "vin4_data8_b",
> > > + "vin4_data10_b",
> > > + "vin4_data12_b",
> > > + "vin4_data16_b",
> > > + "vin4_data20_b",
> > > + "vin4_data24_b",
>
> Then here.
>
> VIN_DATA_PIN_GROUP() expands as:
>
> #define VIN_DATA_PIN_GROUP(n, s)\
> { \
> .name = #n#s, \
> .pins = n##_pins.data##s, \
> .mux = n##_mux.data##s, \
> .nr_pins = ARRAY_SIZE(n##_pins.data##s),\
> }
>
> So these groups should not be named
> "vin4_dataX_a" and
> "vin4_dataX_b"
>
> But instead
> "vin4_data_aX" and
> "vin4_data_bX"
>
> Am I wrong?
Nice catch!
For consistency with other groups, they should be named "vin4_dataX_a"
and "vin4_dataX_b".
> The only Gen3 SoC in mainline which uses the VIN data pins defined
> through this macro is D3, which fortunately does not have any 'a' or
> 'b' group.
>
> $ git grep vin\.*_data* arch/arm64/boot/dts/
> arch/arm64/boot/dts/renesas/r8a77995-draak.dts:groups =
> "vin4_data8", "vin4_sync", "vin4_clk";
>
> $ cat drivers/pinctrl/sh-pfc/pfc-r8a77995.c | grep "vin4_data, 8"
> VIN_DATA_PIN_GROUP(vin4_data, 8),
>
> Going forward we might see some user of vin data groups having to
> refer to "vin4_data_a8" and so on, which is not nice compared to
> "vin4_data8_a".
>
> What do you think?
> In any case, this patch is indeed wrong. Or we align the group names
> to what the macro produces, or change the macro, but I cannot tell how
> to do that in a sane way? (introduce a new one that wants a 'group'
> argument too?)
I only gave this a brief look, but it seems like we need more/better macros.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] i2c: rcar: cleanup DMA for all kinds of failure
On Fri, Oct 19, 2018 at 09:15:26PM +0200, Wolfram Sang wrote: > DMA needs to be cleaned up not only on timeout, but on all errors where > it has been setup before. > > Signed-off-by: Wolfram Sang Added fixes-tag and applied to for-current, thanks! signature.asc Description: PGP signature
