[PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC

[Biju Das]

Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.

Signed-off-by: Biju Das 
---
V1-->V2
* No change
V2-->V3
* No change
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts 
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 40b7f98..77d1824 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -84,12 +84,30 @@
clock-frequency = <2000>;
 };
 
+&i2c3 {
+   pinctrl-0 = <&i2c3_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+   clock-frequency = <40>;
+
+   rtc@51 {
+   compatible = "nxp,pcf85263";
+   reg = <0x51>;
+   };
+};
+
 &pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii_tx_rx";
function = "avb";
};
 
+   i2c3_pins: i2c3 {
+   groups = "i2c3_c";
+   function = "i2c3";
+   };
+
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
-- 
2.7.4

[PATCH v3 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock

[Biju Das]

The pcf85263 RTC is compatible with the pcf85363 RTC.

The difference between the pcf85263 and pcf85363 RTC is that the latter has
64 bytes more RAM. This renders them incompatible from a DT point of view.

Signed-off-by: Biju Das 
---
V1-->V2
* Incorporated Simon's review comment.
V2-->V3
* No Change
---
 Documentation/devicetree/bindings/rtc/pcf85363.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt 
b/Documentation/devicetree/bindings/rtc/pcf85363.txt
index 76fdabc..94adc1c 100644
--- a/Documentation/devicetree/bindings/rtc/pcf85363.txt
+++ b/Documentation/devicetree/bindings/rtc/pcf85363.txt
@@ -1,8 +1,8 @@
-NXP PCF85363 Real Time Clock
+NXP PCF85263/PCF85363 Real Time Clock
 
 
 Required properties:
-- compatible: Should contain "nxp,pcf85363".
+- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363".
 - reg: I2C address for chip.
 
 Optional properties:
-- 
2.7.4

[PATCH v3 3/4] ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig

[Biju Das]

The iWave RZ/G1C SBC supports RTC (NXP pcf85263). To increase hardware
support enable the driver in the shmobile_defconfig multiplatform
configuration.

Signed-off-by: Biju Das 
---
V1-->V2
* No change.
V2-->V3
* No change.
---
 arch/arm/configs/shmobile_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/shmobile_defconfig 
b/arch/arm/configs/shmobile_defconfig
index 9e5a5ad..fdac4e4 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -177,6 +177,7 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RS5C372=y
+CONFIG_RTC_DRV_PCF85363=y
 CONFIG_RTC_DRV_BQ32K=y
 CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_RX8581=y
-- 
2.7.4

[PATCH v3 0/4] Add NXP pcf85263 real-time clock support

[Biju Das]

This patch set aims to add support for NXP pcf85263 real-time clock.
pcf85263 rtc is compatible with pcf85363 rtc except that pcf85363 has
64 bytes additional RAM.

1 byte of nvmem is supported in pcf85263 and is exposed through sysfs.

The details of pcf85363 and pcf85263 can be found in the below data sheets.

https://www.nxp.com/docs/en/data-sheet/PCF85363A.pdf

https://www.nxp.com/docs/en/data-sheet/PCF85263A.pdf

This patch is tested against linux-next.

V1-->V2
   * Incorporated simon's review comment for binding patch.
   * Incorporated Geert and Alexandre's review comments.
V2-->V3
   * Incorporated Geert's review comments.

Biju Das (4):
  dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock
  rtc: pcf85363: Add support for NXP pcf85263 rtc
  ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig
  ARM: dts: iwg23s-sbc: Enable RTC

 Documentation/devicetree/bindings/rtc/pcf85363.txt |  4 +-
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts  | 18 +
 arch/arm/configs/shmobile_defconfig|  1 +
 drivers/rtc/rtc-pcf85363.c | 87 +-
 4 files changed, 90 insertions(+), 20 deletions(-)

-- 
2.7.4

[PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Biju Das]

Add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible
with pcf85363,except that pcf85363 has additional 64 bytes of RAM.

1 byte of nvmem is supported and exposed in sysfs (# is the instance
number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem

Signed-off-by: Biju Das 
---
V1-->V2
* Incorporated Alexandre and Geert's review comment.
V2-->V3
* Incorporated Geert's review comment.
---
 drivers/rtc/rtc-pcf85363.c | 87 --
 1 file changed, 69 insertions(+), 18 deletions(-)

diff --git a/drivers/rtc/rtc-pcf85363.c b/drivers/rtc/rtc-pcf85363.c
index c04a1ed..6a0a994 100644
--- a/drivers/rtc/rtc-pcf85363.c
+++ b/drivers/rtc/rtc-pcf85363.c
@@ -120,6 +120,11 @@ struct pcf85363 {
struct regmap   *regmap;
 };
 
+struct pcf85x63_config {
+   struct regmap_config regmap;
+   unsigned int num_nvram;
+};
+
 static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
 {
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
@@ -311,25 +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned int 
offset, void *val,
 val, bytes);
 }
 
-static const struct regmap_config regmap_config = {
-   .reg_bits = 8,
-   .val_bits = 8,
-   .max_register = 0x7f,
+static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
+  size_t bytes)
+{
+   struct pcf85363 *pcf85363 = priv;
+
+   return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
+}
+
+static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
+   size_t bytes)
+{
+   struct pcf85363 *pcf85363 = priv;
+
+   return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
+   *((unsigned int *)val));
+}
+
+static const struct pcf85x63_config pcf_85263_config = {
+   {
+   .reg_bits = 8,
+   .val_bits = 8,
+   .max_register = 0x2f,
+   },
+   1
+};
+
+static const struct pcf85x63_config pcf_85363_config = {
+   {
+   .reg_bits = 8,
+   .val_bits = 8,
+   .max_register = 0x7f,
+   },
+   2
 };
 
 static int pcf85363_probe(struct i2c_client *client,
  const struct i2c_device_id *id)
 {
struct pcf85363 *pcf85363;
-   struct nvmem_config nvmem_cfg = {
-   .name = "pcf85363-",
-   .word_size = 1,
-   .stride = 1,
-   .size = NVRAM_SIZE,
-   .reg_read = pcf85363_nvram_read,
-   .reg_write = pcf85363_nvram_write,
+   const struct pcf85x63_config *config = &pcf_85363_config;
+   const void *data = of_device_get_match_data(&client->dev);
+   static struct nvmem_config nvmem_cfg[] = {
+   {
+   .name = "pcf85x63-",
+   .word_size = 1,
+   .stride = 1,
+   .size = 1,
+   .reg_read = pcf85x63_nvram_read,
+   .reg_write = pcf85x63_nvram_write,
+   }, {
+   .name = "pcf85363-",
+   .word_size = 1,
+   .stride = 1,
+   .size = NVRAM_SIZE,
+   .reg_read = pcf85363_nvram_read,
+   .reg_write = pcf85363_nvram_write,
+   },
};
-   int ret;
+   int ret, i;
+
+   if (data)
+   config = data;
 
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
@@ -339,7 +387,7 @@ static int pcf85363_probe(struct i2c_client *client,
if (!pcf85363)
return -ENOMEM;
 
-   pcf85363->regmap = devm_regmap_init_i2c(client, ®map_config);
+   pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
if (IS_ERR(pcf85363->regmap)) {
dev_err(&client->dev, "regmap allocation failed\n");
return PTR_ERR(pcf85363->regmap);
@@ -370,15 +418,18 @@ static int pcf85363_probe(struct i2c_client *client,
 
ret = rtc_register_device(pcf85363->rtc);
 
-   nvmem_cfg.priv = pcf85363;
-   rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg);
+   for (i = 0; i < config->num_nvram; i++) {
+   nvmem_cfg[i].priv = pcf85363;
+   rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
+   }
 
return ret;
 }
 
 static const struct of_device_id dev_ids[] = {
-   { .compatible = "nxp,pcf85363" },
-   {}
+   { .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
+   { .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
+   { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dev_ids);
 
@@ -393,5 +444,5 @@ static struct i2c_driver pcf85363_driver = {
 module_i2c_driver(pcf85363_driver);
 
 MODULE_AUTHOR("Eric Nelson");
-MODULE_DESCRIPTION("pcf8536

Re: [PATCH v3 1/4] dt-bindings: rtc: pcf85363: Document pcf85263 real-time clock

[Geert Uytterhoeven]

On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> The pcf85263 RTC is compatible with the pcf85363 RTC.
>
> The difference between the pcf85263 and pcf85363 RTC is that the latter has
> 64 bytes more RAM. This renders them incompatible from a DT point of view.
>
> Signed-off-by: Biju Das 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Geert Uytterhoeven]

Hi Biju,

CC nvmem maintainer

On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> Add support for NXP pcf85263 real-time clock. pcf85263 rtc is compatible
> with pcf85363,except that pcf85363 has additional 64 bytes of RAM.
>
> 1 byte of nvmem is supported and exposed in sysfs (# is the instance
> number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
>
> Signed-off-by: Biju Das 
> ---
> V1-->V2
> * Incorporated Alexandre and Geert's review comment.
> V2-->V3
> * Incorporated Geert's review comment.

Thanks for the update!

> --- a/drivers/rtc/rtc-pcf85363.c
> +++ b/drivers/rtc/rtc-pcf85363.c
> @@ -120,6 +120,11 @@ struct pcf85363 {
> struct regmap   *regmap;
>  };
>
> +struct pcf85x63_config {
> +   struct regmap_config regmap;
> +   unsigned int num_nvram;
> +};
> +
>  static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
>  {
> struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
> @@ -311,25 +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned 
> int offset, void *val,
>  val, bytes);
>  }
>
> -static const struct regmap_config regmap_config = {
> -   .reg_bits = 8,
> -   .val_bits = 8,
> -   .max_register = 0x7f,
> +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
> +  size_t bytes)

Given bytes should be 1, val should be a pointer to a single byte...
What if bytes == 0?

> +{> +   struct pcf85363 *pcf85363 = priv;
> +
> +   return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);

However, regmap_read() has an unsigned int output parameter!
So it's writing too many bytes, and only writing the actual data byte to the
correct address on little-endian systems.
Hence you need to use an intermediate variable to convert from unsigned
int to byte.

> +}
> +
> +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
> +   size_t bytes)
> +{
> +   struct pcf85363 *pcf85363 = priv;
> +
> +   return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> +   *((unsigned int *)val));

Likewise for writing.

> +}

BTW, while the nvmem_device_{read,write}() public API is documented, the
nvmem_device.reg_{read,write}() driver API isn't.
And the behavior might be confusing.

E.g.
 * Return: length of successful bytes read on success and negative
 * error code on error.

The public API seems to assume the driver API returns zero on success,
and replaces the zero by the number of bytes requested.
If the requested number of bytes is too large, a zero success would be
converted to a value that's larger than the actual number of bytes
transferred!
However, the driver API can return a smaller (positive) number, which matches
"standard" read/write() APIs.

> +static const struct pcf85x63_config pcf_85263_config = {
> +   {
> +   .reg_bits = 8,
> +   .val_bits = 8,
> +   .max_register = 0x2f,
> +   },
> +   1

The "1" looks funny. Please use C99 initializers for all struct members.

> +};
> +
> +static const struct pcf85x63_config pcf_85363_config = {
> +   {
> +   .reg_bits = 8,
> +   .val_bits = 8,
> +   .max_register = 0x7f,
> +   },
> +   2

Likewise.

The rest looks good to me, so
Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3 3/4] ARM: shmobile: Enable NXP pcf85363 rtc in shmobile_defconfig

[Geert Uytterhoeven]

On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
>
> The iWave RZ/G1C SBC supports RTC (NXP pcf85263). To increase hardware
> support enable the driver in the shmobile_defconfig multiplatform
> configuration.
>
> Signed-off-by: Biju Das 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

RE: [RFC v3 1/2] pinctrl: core: Add pinctrl_mux_gpio_request_enable

[Fabrizio Castro]

Hello Linus,

Thank you for your feedback!

> From: Linus Walleij 
> Sent: 05 December 2018 21:46
> Subject: Re: [RFC v3 1/2] pinctrl: core: Add pinctrl_mux_gpio_request_enable
>
> On Tue, Nov 20, 2018 at 4:19 PM Fabrizio Castro
>  wrote:
>
> > Sometimes there is the need to change the muxing of a pin to make it
> > a GPIO without going through gpiolib.
> > This patch adds pinctrl_mux_gpio_request_enable to deal with this new
> > use case from code that has nothing to do with pinctrl.
>
> It has a lot to do with pinctrl I think, so I get confused by this
> commit message.

I can improve that

>
> >  extern int pinctrl_gpio_request(unsigned gpio);
> > +extern int pinctrl_mux_gpio_request_enable(unsigned gpio);
>
> What's wrong with just using the existing call
> pinctrl_gpio_request() right above your new one?
>
> It's not like we're reference counting or something, it's just
> a callback. Sprinkle some comments to show what's going
> on.

I tried that, and it was working for me, then something changed lately
in gpiolib that broke that solution, and Geert picked it up on his end.
Please see this:
https://patchwork.kernel.org/patch/10671325/

This patch was made to overcome the problems of the previous patch.

>
> If you for some reason need a new call for this specific
> use case, it needs to be named after the use case,
> like pinctrl_gpio_request_for_irq()
> so it is obvious what the function is doing.

I can do that, but I would like to hear from Geert first, no point in going
around in circle if this solution is not acceptable to him.

Geert, what do you think?

Thanks!
Fab

>
> Yours,
> Linus Walleij


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have 
decided to support Unicef with a donation. For further details click 
here to find out about the valuable work they do, 
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a 
prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC

[Geert Uytterhoeven]

Hi Biju,

On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
>
> Signed-off-by: Biju Das 

Reviewed-by: Geert Uytterhoeven 

> --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> @@ -84,12 +84,30 @@
> clock-frequency = <2000>;
>  };
>
> +&i2c3 {
> +   pinctrl-0 = <&i2c3_pins>;
> +   pinctrl-names = "default";
> +
> +   status = "okay";
> +   clock-frequency = <40>;
> +
> +   rtc@51 {
> +   compatible = "nxp,pcf85263";
> +   reg = <0x51>;

You might want to enable the optional interrupt:

interrupt-parent = <&gpio0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

> +   };


Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

RE: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC
>
> Hi Biju,
>
> On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> > Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
> >
> > Signed-off-by: Biju Das 
>
> Reviewed-by: Geert Uytterhoeven 
>
> > --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > @@ -84,12 +84,30 @@
> > clock-frequency = <2000>;
> >  };
> >
> > +&i2c3 {
> > +   pinctrl-0 = <&i2c3_pins>;
> > +   pinctrl-names = "default";
> > +
> > +   status = "okay";
> > +   clock-frequency = <40>;
> > +
> > +   rtc@51 {
> > +   compatible = "nxp,pcf85263";
> > +   reg = <0x51>;
>
> You might want to enable the optional interrupt:

I have enabled this but unfortunately it is generating 10 of gpio 
interrupts during boot.

The reason is, by default this pin is configured as function(Power on reset/at 
u-boot).
Currently there is no function available in kernel to convert a pin from 
function to gpio (Similar to the issue Fab is facing for display hot plug 
interrupt)

May be we can add optional interrupt at a later stage, once we have a solution 
for converting  pin from function to gpio.

Please share your opinion on this.

Regards,
Biju





[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have 
decided to support Unicef with a donation. For further details click 
here to find out about the valuable work they do, 
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a 
prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

phandles using absolute paths in DT overlays

[Geert Uytterhoeven]

Hi,

Some early revisions of SoCs may have hardware bugs that need to be
fixed up in DT.  Currently we are handling this by including DTS files
and fixing up nodes and properties, to create different DTB files for
different SoC revisons (see arch/arm64/boot/dts/renesas/*es1*).

As an alternative, I'm envisioning the use of DT overlays and the
fdtoverlay tool, in the hope of simplifying the generation of DTBs for
the various SoC/board combinations.

Ideally, such DTBs would not contain symbols, to avoid inflating DTB
size.  Hence if fixup overlays would not contain symbolic references,
there would be no need for symbols.

For anchors, the "&{/path/to/node@address}" syntax is working fine.
For phandles, while documented on
https://elinux.org/Device_Tree_Mysteries, and while working fine for the
non-overlay case, dtc seems to have issues interpreting the DTB:

$ scripts/dtc/dtc -I dtb -O dts my.dtb  | less
: ERROR (property_name_chars):
/__fixups__:/path/to/node@deadbeef: Bad character '/' in property
name
ERROR: Input tree has errors, aborting (use -f to force output)

With -f, the fixup generated seems to contain the expected value, though:

__fixups__ {
/path/to/node@deadbeef = "/fragment@0/__overlay__:power-domains:0";
};

When using ftdoverlay, the situation is worse:

Failed to apply my.dtb (-1)

Are these known issues?
Thanks for your comments!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC

[Geert Uytterhoeven]

Hi Biju,

On Thu, Dec 6, 2018 at 1:41 PM Biju Das  wrote:
> > Subject: Re: [PATCH v3 4/4] ARM: dts: iwg23s-sbc: Enable RTC

> > On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> > > Enable NXP pcf85263 real time clock for the iWave SBC based on RZ/G1C.
> > >
> > > Signed-off-by: Biju Das 
> >
> > Reviewed-by: Geert Uytterhoeven 
> >
> > > --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > > +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
> > > @@ -84,12 +84,30 @@
> > > clock-frequency = <2000>;
> > >  };
> > >
> > > +&i2c3 {
> > > +   pinctrl-0 = <&i2c3_pins>;
> > > +   pinctrl-names = "default";
> > > +
> > > +   status = "okay";
> > > +   clock-frequency = <40>;
> > > +
> > > +   rtc@51 {
> > > +   compatible = "nxp,pcf85263";
> > > +   reg = <0x51>;
> >
> > You might want to enable the optional interrupt:
>
> I have enabled this but unfortunately it is generating 10 of gpio 
> interrupts during boot.

Oh, the DT bindings claim interrupt support hasn't been implement yet ;-)

> The reason is, by default this pin is configured as function(Power on 
> reset/at u-boot).
> Currently there is no function available in kernel to convert a pin from 
> function to gpio (Similar to the issue Fab is facing for display hot plug 
> interrupt)
>
> May be we can add optional interrupt at a later stage, once we have a 
> solution for converting  pin from function to gpio.
>
> Please share your opinion on this.

IC. In that case, please postpone describing the interrupt until the issue is
fixed.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Biju Das]

Hi Geert,

Thanks for feedback.

> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> CC nvmem maintainer
>
> On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > compatible with pcf85363,except that pcf85363 has additional 64 bytes of
> RAM.
> >
> > 1 byte of nvmem is supported and exposed in sysfs (# is the instance
> > number,starting with 0): /sys/bus/nvmem/devices/pcf85x63-#/nvmem
> >
> > Signed-off-by: Biju Das 
> > ---
> > V1-->V2
> > * Incorporated Alexandre and Geert's review comment.
> > V2-->V3
> > * Incorporated Geert's review comment.
>
> Thanks for the update!
>
> > --- a/drivers/rtc/rtc-pcf85363.c
> > +++ b/drivers/rtc/rtc-pcf85363.c
> > @@ -120,6 +120,11 @@ struct pcf85363 {
> > struct regmap   *regmap;
> >  };
> >
> > +struct pcf85x63_config {
> > +   struct regmap_config regmap;
> > +   unsigned int num_nvram;
> > +};
> > +
> >  static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time
> > *tm)  {
> > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@ -311,25
> > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned int
> offset, void *val,
> >  val, bytes);  }
> >
> > -static const struct regmap_config regmap_config = {
> > -   .reg_bits = 8,
> > -   .val_bits = 8,
> > -   .max_register = 0x7f,
> > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
> > +  size_t bytes)
>
> Given bytes should be 1, val should be a pointer to a single byte...
> What if bytes == 0?

I doubt we get "bytes==0" because of the checks in " drivers/nvmem/core.c"
Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".


> > +{> +   struct pcf85363 *pcf85363 = priv;
> > +
> > +   return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
>
> However, regmap_read() has an unsigned int output parameter!
> So it's writing too many bytes, and only writing the actual data byte to the
> correct address on little-endian systems.
> Hence you need to use an intermediate variable to convert from unsigned int
> to byte.

OK. Will use an intermediate integer variable.

> > +}
> > +
> > +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
> > +   size_t bytes) {
> > +   struct pcf85363 *pcf85363 = priv;
> > +
> > +   return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> > +   *((unsigned int *)val));
>
> Likewise for writing.
>
> > +}
>
> BTW, while the nvmem_device_{read,write}() public API is documented, the
> nvmem_device.reg_{read,write}() driver API isn't.
> And the behavior might be confusing.
>
> E.g.
>  * Return: length of successful bytes read on success and negative
>  * error code on error.
>
> The public API seems to assume the driver API returns zero on success, and
> replaces the zero by the number of bytes requested.
> If the requested number of bytes is too large, a zero success would be
> converted to a value that's larger than the actual number of bytes
> transferred!
> However, the driver API can return a smaller (positive) number, which
> matches "standard" read/write() APIs.
>
> > +static const struct pcf85x63_config pcf_85263_config = {
> > +   {
> > +   .reg_bits = 8,
> > +   .val_bits = 8,
> > +   .max_register = 0x2f,
> > +   },
> > +   1
>
> The "1" looks funny. Please use C99 initializers for all struct members.

OK will fix this.
> > +};
> > +
> > +static const struct pcf85x63_config pcf_85363_config = {
> > +   {
> > +   .reg_bits = 8,
> > +   .val_bits = 8,
> > +   .max_register = 0x7f,
> > +   },
> > +   2
>
> Likewise.

 OK will fix this.

Regards,
Biju

> The rest looks good to me, so
> Reviewed-by: Geert Uytterhoeven 
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have 
decided to support Unicef with a donation. For further details click 
here to find out about the valuable work they do, 
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a 
prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Geert Uytterhoeven]

Hi Biju,

On Thu, Dec 6, 2018 at 4:24 PM Biju Das  wrote:
> > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
> > CC nvmem maintainer
> >
> > On Thu, Dec 6, 2018 at 10:04 AM Biju Das  wrote:
> > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > compatible with pcf85363,except that pcf85363 has additional 64 bytes of
> > RAM.

> > > --- a/drivers/rtc/rtc-pcf85363.c
> > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > @@ -120,6 +120,11 @@ struct pcf85363 {
> > > struct regmap   *regmap;
> > >  };
> > >
> > > +struct pcf85x63_config {
> > > +   struct regmap_config regmap;
> > > +   unsigned int num_nvram;
> > > +};
> > > +
> > >  static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time
> > > *tm)  {
> > > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@ -311,25
> > > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned int
> > offset, void *val,
> > >  val, bytes);  }
> > >
> > > -static const struct regmap_config regmap_config = {
> > > -   .reg_bits = 8,
> > > -   .val_bits = 8,
> > > -   .max_register = 0x7f,
> > > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void 
> > > *val,
> > > +  size_t bytes)
> >
> > Given bytes should be 1, val should be a pointer to a single byte...
> > What if bytes == 0?
>
> I doubt we get "bytes==0" because of the checks in " drivers/nvmem/core.c"
> Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".

Depends. There are other functions calling nvmem_reg_{read,write}(),
e.g. nvmem_device_{read,write}().

>
> > > +{> +   struct pcf85363 *pcf85363 = priv;
> > > +
> > > +   return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
> >
> > However, regmap_read() has an unsigned int output parameter!
> > So it's writing too many bytes, and only writing the actual data byte to the
> > correct address on little-endian systems.
> > Hence you need to use an intermediate variable to convert from unsigned int
> > to byte.
>
> OK. Will use an intermediate integer variable.
>
> > > +}
> > > +
> > > +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void 
> > > *val,
> > > +   size_t bytes) {
> > > +   struct pcf85363 *pcf85363 = priv;
> > > +
> > > +   return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> > > +   *((unsigned int *)val));
> >
> > Likewise for writing.
> >
> > > +}
> >
> > BTW, while the nvmem_device_{read,write}() public API is documented, the
> > nvmem_device.reg_{read,write}() driver API isn't.
> > And the behavior might be confusing.
> >
> > E.g.
> >  * Return: length of successful bytes read on success and negative
> >  * error code on error.
> >
> > The public API seems to assume the driver API returns zero on success, and
> > replaces the zero by the number of bytes requested.
> > If the requested number of bytes is too large, a zero success would be
> > converted to a value that's larger than the actual number of bytes
> > transferred!
> > However, the driver API can return a smaller (positive) number, which
> > matches "standard" read/write() APIs.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

RE: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
>
> Hi Biju,
>
> On Thu, Dec 6, 2018 at 4:24 PM Biju Das  wrote:
> > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > pcf85263 rtc CC nvmem maintainer
> > >
> > > On Thu, Dec 6, 2018 at 10:04 AM Biju Das 
> wrote:
> > > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > > compatible with pcf85363,except that pcf85363 has additional 64
> > > > bytes of
> > > RAM.
>
> > > > --- a/drivers/rtc/rtc-pcf85363.c
> > > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > > @@ -120,6 +120,11 @@ struct pcf85363 {
> > > > struct regmap   *regmap;
> > > >  };
> > > >
> > > > +struct pcf85x63_config {
> > > > +   struct regmap_config regmap;
> > > > +   unsigned int num_nvram;
> > > > +};
> > > > +
> > > >  static int pcf85363_rtc_read_time(struct device *dev, struct
> > > > rtc_time
> > > > *tm)  {
> > > > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@
> > > > -311,25
> > > > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned
> > > > +int
> > > offset, void *val,
> > > >  val, bytes);  }
> > > >
> > > > -static const struct regmap_config regmap_config = {
> > > > -   .reg_bits = 8,
> > > > -   .val_bits = 8,
> > > > -   .max_register = 0x7f,
> > > > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void
> *val,
> > > > +  size_t bytes)
> > >
> > > Given bytes should be 1, val should be a pointer to a single byte...
> > > What if bytes == 0?
> >
> > I doubt we get "bytes==0" because of the checks in "
> drivers/nvmem/core.c"
> > Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
>
> Depends. There are other functions calling nvmem_reg_{read,write}(), e.g.
> nvmem_device_{read,write}().

OK. In that case, I will return (-EINVAL)  for "bytes !=1"

> >
> > > > +{> +   struct pcf85363 *pcf85363 = priv;
> > > > +
> > > > +   return regmap_read(pcf85363->regmap, CTRL_RAMBYTE, val);
> > >
> > > However, regmap_read() has an unsigned int output parameter!
> > > So it's writing too many bytes, and only writing the actual data
> > > byte to the correct address on little-endian systems.
> > > Hence you need to use an intermediate variable to convert from
> > > unsigned int to byte.
> >
> > OK. Will use an intermediate integer variable.
> >
> > > > +}
> > > > +
> > > > +static int pcf85x63_nvram_write(void *priv, unsigned int offset, void
> *val,
> > > > +   size_t bytes) {
> > > > +   struct pcf85363 *pcf85363 = priv;
> > > > +
> > > > +   return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
> > > > +   *((unsigned int *)val));
> > >
> > > Likewise for writing.
> > >
> > > > +}
> > >
> > > BTW, while the nvmem_device_{read,write}() public API is documented,
> > > the
> > > nvmem_device.reg_{read,write}() driver API isn't.
> > > And the behavior might be confusing.
> > >
> > > E.g.
> > >  * Return: length of successful bytes read on success and negative
> > >  * error code on error.
> > >
> > > The public API seems to assume the driver API returns zero on
> > > success, and replaces the zero by the number of bytes requested.
> > > If the requested number of bytes is too large, a zero success would
> > > be converted to a value that's larger than the actual number of
> > > bytes transferred!
> > > However, the driver API can return a smaller (positive) number,
> > > which matches "standard" read/write() APIs.

Regards,
Biju


[https://www2.renesas.eu/media/email/unicef.jpg]

This Christmas, instead of sending out cards, Renesas Electronics Europe have 
decided to support Unicef with a donation. For further details click 
here to find out about the valuable work they do, 
helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a 
prosperous New Year.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc

[Alexandre Belloni]

On 06/12/2018 15:49:57+, Biju Das wrote:
> Hi Geert,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP pcf85263 rtc
> >
> > Hi Biju,
> >
> > On Thu, Dec 6, 2018 at 4:24 PM Biju Das  wrote:
> > > > Subject: Re: [PATCH v3 2/4] rtc: pcf85363: Add support for NXP
> > > > pcf85263 rtc CC nvmem maintainer
> > > >
> > > > On Thu, Dec 6, 2018 at 10:04 AM Biju Das 
> > wrote:
> > > > > Add support for NXP pcf85263 real-time clock. pcf85263 rtc is
> > > > > compatible with pcf85363,except that pcf85363 has additional 64
> > > > > bytes of
> > > > RAM.
> >
> > > > > --- a/drivers/rtc/rtc-pcf85363.c
> > > > > +++ b/drivers/rtc/rtc-pcf85363.c
> > > > > @@ -120,6 +120,11 @@ struct pcf85363 {
> > > > > struct regmap   *regmap;
> > > > >  };
> > > > >
> > > > > +struct pcf85x63_config {
> > > > > +   struct regmap_config regmap;
> > > > > +   unsigned int num_nvram;
> > > > > +};
> > > > > +
> > > > >  static int pcf85363_rtc_read_time(struct device *dev, struct
> > > > > rtc_time
> > > > > *tm)  {
> > > > > struct pcf85363 *pcf85363 = dev_get_drvdata(dev); @@
> > > > > -311,25
> > > > > +316,68 @@ static int pcf85363_nvram_write(void *priv, unsigned
> > > > > +int
> > > > offset, void *val,
> > > > >  val, bytes);  }
> > > > >
> > > > > -static const struct regmap_config regmap_config = {
> > > > > -   .reg_bits = 8,
> > > > > -   .val_bits = 8,
> > > > > -   .max_register = 0x7f,
> > > > > +static int pcf85x63_nvram_read(void *priv, unsigned int offset, void
> > *val,
> > > > > +  size_t bytes)
> > > >
> > > > Given bytes should be 1, val should be a pointer to a single byte...
> > > > What if bytes == 0?
> > >
> > > I doubt we get "bytes==0" because of the checks in "
> > drivers/nvmem/core.c"
> > > Function " bin_attr_nvmem_read/ bin_attr_nvmem_write".
> >
> > Depends. There are other functions calling nvmem_reg_{read,write}(), e.g.
> > nvmem_device_{read,write}().
> 
> OK. In that case, I will return (-EINVAL)  for "bytes !=1"
> 

I think it is probably better to ensure the nvmem core never passes an
invalid number of bytes. All the ther RTC drivers make that assumption.


-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH 3/3] arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE

[Simon Horman]

From: Geert Uytterhoeven 

Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function
on the Renesas Condor board.

Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Marek Vasut 
Signed-off-by: Simon Horman 
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9d0b42d96f03..77f98a7e860b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -657,6 +657,7 @@ CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
 CONFIG_PHY_QCOM_QMP=m
 CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_RCAR_GEN3_PCIE=y
 CONFIG_PHY_RCAR_GEN3_USB2=y
 CONFIG_PHY_RCAR_GEN3_USB3=m
 CONFIG_PHY_ROCKCHIP_EMMC=y
-- 
2.11.0

[PATCH 1/3] arm64: defconfig: Enable R-Car thermal driver

[Simon Horman]

Enable the R-Car thermal driver as a module.

This driver is used in conjunction with the R-Car V3M (r8a77970),
E3 (r8a77990) and D3 (r8a77995) SoCs.

Signed-off-by: Simon Horman 
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a57d11330b..f88190463481 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -377,6 +377,7 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_CPU_THERMAL=y
 CONFIG_THERMAL_EMULATION=y
 CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_RCAR_THERMAL=m
 CONFIG_RCAR_GEN3_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
 CONFIG_BRCMSTB_THERMAL=m
-- 
2.11.0

[PATCH 2/3] arm64: defconfig: Enable scu-simple-card driver

[Simon Horman]

Enable the scu-simple-card which is used by
the R-Car E3 (r8a77990) based Ebisu board.

Signed-off-by: Simon Horman 
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f88190463481..9d0b42d96f03 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -491,6 +491,7 @@ CONFIG_SND_SOC_RT5514=m
 CONFIG_SND_SOC_RT5514_SPI=m
 CONFIG_SND_SOC_RT5645=m
 CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_SCU_CARD=y
 CONFIG_SND_AUDIO_GRAPH_CARD=m
 CONFIG_I2C_HID=m
 CONFIG_USB=y
-- 
2.11.0

[GIT PULL] Renesas ARM64 Based SoC Defconfig Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM64 based SoC defconfig updates for v4.21.


The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm64-defconfig-for-v4.21

for you to fetch changes up to fe16bcd6d44f1a2bccc4618119463d9d23a6ae92:

  arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE (2018-11-16 06:56:49 -0800)


Renesas ARM64 Based SoC Defconfig Updates for v4.21

* Enable in arm64 defconfig:
  - Renesas R-Car Gen3 PCIe PHY driver
  - Renesas R-Car thermal driver
  - ASoC simple SCU sound card support


Geert Uytterhoeven (1):
  arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE

Simon Horman (2):
  arm64: defconfig: Enable R-Car thermal driver
  arm64: defconfig: Enable scu-simple-card driver

 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

[GIT PULL] Renesas ARM Based SoC Defconfig Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC defconfig updates for v4.21.


The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm-defconfig-for-v4.21

for you to fetch changes up to 65a8c17a39f62fd646950fa43efcced0d6fe029c:

  ARM: shmobile: defconfig: Enable SII902X (2018-11-05 12:41:09 +0100)


Renesas ARM Based SoC Defconfig Updates for v4.21

* Enable SII902X in shmobile defconfig


Fabrizio Castro (1):
  ARM: shmobile: defconfig: Enable SII902X

 arch/arm/configs/shmobile_defconfig | 1 +
 1 file changed, 1 insertion(+)

[GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these second round of Renesas ARM64 based SoC DT updates
for v4.21.

This pull request is based on the previous round of
such requests, tagged as renesas-arm64-dt-for-v4.21,
which you have already pulled.


The following changes since commit 275e4eb3f21a09b6b8bd4a353b9a01e500240385:

  arm64: dts: renesas: Add all CPUs in cooling maps (2018-11-26 09:11:44 +0100)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm64-dt2-for-v4.21

for you to fetch changes up to 4fbd4158fe8967e9296516ebae2cfaf7a1c7a214:

  arm64: dts: renesas: r8a77995: draak: Add backlight (2018-12-05 11:45:44 
-0800)


Second Round of Renesas ARM64 Based SoC DT Updates for v4.21

* R-Car D3 (r8a77995) SoC based Draak board
  - Add the backlight device for the LVDS1 output

* R-Car H3 (r8a7795) ES1.0 SoC
  - Add missing power domains to IPMMU nodes

* R-Car M3-N (r8a77965) SoC
  - Remove non-existent IPMMU-IR


Geert Uytterhoeven (2):
  arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR
  arm64: dts: renesas: r8a7795-es1: Add missing power domains to IPMMU nodes

Laurent Pinchart (1):
  arm64: dts: renesas: r8a77995: draak: Add backlight

 arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi   |  2 ++
 arch/arm64/boot/dts/renesas/r8a77965.dtsi  |  8 
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 20 
 3 files changed, 22 insertions(+), 8 deletions(-)

[PATCH 2/3] arm64: dts: renesas: r8a7795-es1: Add missing power domains to IPMMU nodes

[Simon Horman]

From: Geert Uytterhoeven 

While commit 3b7e7848f0e88b36 ("arm64: dts: renesas: r8a7795: Add IPMMU
device nodes") for R-Car H3 ES2.0 did include power-domains properties,
they were forgotten in the counterpart for older R-Car H3 ES1.x SoCs.

Fixes: e4b9a493df45075b ("arm64: dts: renesas: r8a7795-es1: Add IPMMU device 
nodes")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 0fb84c219b2f..40d10daca852 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -28,6 +28,7 @@
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec68 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
+   power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
 
@@ -35,6 +36,7 @@
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe773 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
+   power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
 
-- 
2.11.0

[PATCH 1/1] ARM: shmobile: defconfig: Enable SII902X

[Simon Horman]

From: Fabrizio Castro 

The iwg23s board comes with the SiI9022ACNU HDMI transmitter,
this patch makes sure the corresponding driver gets built.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm/configs/shmobile_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/shmobile_defconfig 
b/arch/arm/configs/shmobile_defconfig
index d090022ca975..9e5a5ade6cab 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -142,6 +142,7 @@ CONFIG_DRM=y
 CONFIG_DRM_RCAR_DU=y
 CONFIG_DRM_RCAR_LVDS=y
 CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_SII902X=y
 CONFIG_DRM_I2C_ADV7511=y
 CONFIG_DRM_I2C_ADV7511_AUDIO=y
 CONFIG_FB_SH_MOBILE_LCDC=y
-- 
2.11.0

[PATCH 3/3] arm64: dts: renesas: r8a77995: draak: Add backlight

[Simon Horman]

From: Laurent Pinchart 

Add the backlight device for the LVDS1 output, in preparation for panel
support.

Signed-off-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 48bb1d77744f..52d044b9f3f2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -24,6 +24,17 @@
stdout-path = "serial0:115200n8";
};
 
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = <&pwm1 0 5>;
+
+   brightness-levels = <256 128 64 16 8 4 0>;
+   default-brightness-level = <6>;
+
+   power-supply = <®_12p0v>;
+   enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+   };
+
composite-in {
compatible = "composite-video-connector";
 
@@ -104,6 +115,15 @@
regulator-always-on;
};
 
+   reg_12p0v: regulator1 {
+   compatible = "regulator-fixed";
+   regulator-name = "D12.0V";
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
vga {
compatible = "vga-connector";
 
-- 
2.11.0

[PATCH 1/3] arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Aug 24, 2018)
removed the IPMMU-IR IOMMU instance on R-Car M3-N, as this SoC does not
have an Image Processing Unit (IMP-X5) nor the A3IR power domain.

Fixes: 55697cbb44e4f7ea ("arm64: dts: renesas: r8a779{65,80,90}: Add IPMMU 
devices nodes")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 1c86e6f4dc71..6dc9b1fef830 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -795,14 +795,6 @@
#iommu-cells = <1>;
};
 
-   ipmmu_ir: mmu@ff8b {
-   compatible = "renesas,ipmmu-r8a77965";
-   reg = <0 0xff8b 0 0x1000>;
-   renesas,ipmmu-main = <&ipmmu_mm 3>;
-   power-domains = <&sysc R8A77965_PD_A3IR>;
-   #iommu-cells = <1>;
-   };
-
ipmmu_mm: mmu@e67b {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe67b 0 0x1000>;
-- 
2.11.0

[PATCH 01/34] ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibility

[Simon Horman]

From: Geert Uytterhoeven 

The thermal hardware description for the RZ/G1M SoC was added to its DTS
after the introduction of support for thermal zones, and included a
thermal-zones node from the beginning.

Hence there is no need to claim compatibility with
"renesas,rcar-thermal", which would be needed only for backwards
compatibility with kernels predating thermal zone support.

Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7743.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 24715f74ae08..3cc33f7ff7fe 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -348,8 +348,7 @@
 
thermal: thermal@e61f {
compatible = "renesas,thermal-r8a7743",
-"renesas,rcar-gen2-thermal",
-"renesas,rcar-thermal";
+"renesas,rcar-gen2-thermal";
reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
interrupts = ;
clocks = <&cpg CPG_MOD 522>;
-- 
2.11.0

[GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these second round of Renesas ARM based SoC DT updates for 
v4.21.

This pull request is based on the previous round of
such requests, tagged as renesas-arm-dt-for-v4.21,
which you have already pulled.


The following changes since commit 673df60a880f060e3e94920c7b5f7a9ed8aa65f2:

  ARM: dts: r9a06g032: Correct the GIC DT node name (2018-11-28 13:55:30 +0100)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm-dt2-for-v4.21

for you to fetch changes up to e259e04748e2798a747d9c363ded50514b15a7b9:

  ARM: dts: r8a7744-iwg20m: Add SPI NOR support (2018-12-05 11:52:46 -0800)


Second Round of Renesas ARM Based SoC DT Updates for v4.21

* RZ/G1N (r8a7744) SoC
  - Describe in DT: SYS-DMAC, GPIO, Ethernet AVB, SMP, [H]SCIF{A|B},
I2C, USB 2.0 and 3.0 hosts, USB-DMAC, HSUSB, RWDT, Audio, CAN, IRQC,
thermal, CMT, VIN, VSP, IPMMU, PMU, TPU, QSPI MSIOF, and PCIE
  - iWave G20D-Q7 board
- Initial support
- Enable eMMC, SDHI and SPIO NOR support
  - Add camera daughterboard

* RZ/G1M (r8a7743) SoC
  - Remove legacy "renesas,rcar-thermal" compatibility


Biju Das (33):
  ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
  ARM: dts: r8a7744: Initial SoC device tree
  ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on 
RZ/G1N
  ARM: dts: r8a7744: Add SYS-DMAC support
  ARM: dts: r8a7744: Add GPIO support
  ARM: dts: r8a7744: Add Ethernet AVB support
  ARM: dts: r8a7744: Add SMP support
  ARM: dts: r8a7744: Add [H]SCIF{A|B} support
  ARM: dts: r8a7744: Add I2C and IIC support
  ARM: dts: r8a7744: Add SDHI nodes
  ARM: dts: r8a7744: Add MMC node
  ARM: dts: r8a7744-iwg20m: Add eMMC support
  ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller
  ARM: dts: r8a7744: USB 2.0 host support
  ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
  ARM: dts: r8a7744: Add RWDT node
  ARM: dts: r8a7744: Add audio support
  ARM: dts: r8a7744: Add CAN support
  ARM: dts: r8a7744: Add IRQC support
  ARM: dts: r8a7744: Add thermal device to DT
  ARM: dts: r8a7744: Add CMT SoC specific support
  ARM: dts: r8a7744: add VIN dt support
  ARM: dts: r8a7744: Add VSP support
  ARM: dts: r8a7744: Add IPMMU DT nodes
  ARM: dts: r8a7744: Add PWM SoC support
  ARM: dts: r8a7744: Add TPU support
  ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB
  ARM: dts: r8a7744: Add QSPI support
  ARM: dts: r8a7744: Add MSIOF[012] support
  ARM: dts: r8a7744: Add xhci support
  ARM: dts: r8a7744: Add PCIe Controller device node
  ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM
  ARM: dts: r8a7744-iwg20m: Add SPI NOR support

Geert Uytterhoeven (1):
  ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibility

 arch/arm/boot/dts/Makefile  |2 +
 arch/arm/boot/dts/iwg20d-q7-common.dtsi |9 +
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi   |9 -
 arch/arm/boot/dts/r8a7743.dtsi  |3 +-
 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts |   17 +
 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts |   15 +
 arch/arm/boot/dts/r8a7744-iwg20m.dtsi   |   90 ++
 arch/arm/boot/dts/r8a7744.dtsi  | 1741 +++
 8 files changed, 1875 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
 create mode 100644 arch/arm/boot/dts/r8a7744.dtsi

[PATCH 09/34] ARM: dts: r8a7744: Add [H]SCIF{A|B} support

[Simon Horman]

From: Biju Das 

Describe [H]SCIF{|A|B} ports in the R8A7744 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 257 -
 1 file changed, 254 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 2cb6d8fa2fa0..1fe694d0215b 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -414,9 +414,139 @@
status = "disabled";
};
 
+   scifa0: serial@e6c4 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c4 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 204>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+  <&dmac1 0x21>, <&dmac1 0x22>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 204>;
+   status = "disabled";
+   };
+
+   scifa1: serial@e6c5 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c5 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 203>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+  <&dmac1 0x25>, <&dmac1 0x26>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 203>;
+   status = "disabled";
+   };
+
+   scifa2: serial@e6c6 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c6 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 202>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+  <&dmac1 0x27>, <&dmac1 0x28>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 202>;
+   status = "disabled";
+   };
+
+   scifa3: serial@e6c7 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c7 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 1106>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+  <&dmac1 0x1b>, <&dmac1 0x1c>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 1106>;
+   status = "disabled";
+   };
+
+   scifa4: serial@e6c78000 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c78000 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 1107>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+  <&dmac1 0x1f>, <&dmac1 0x20>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 1107>;
+   status = "disabled";
+   };
+
+   scifa5: serial@e6c8 {
+   compatible = "renesas,scifa-r8a7744",
+"renesas,rcar-gen2-scifa", "renesas,scifa";
+   reg = <0 0xe6c8 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 1108>;
+   clock-names = "fck";
+   dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+  <&dmac1 0x23>, <&dmac1 0x24>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 1108>;
+   status = "disabled";
+

[PATCH 16/34] ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes

[Simon Horman]

From: Biju Das 

Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 42 +-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 1d4cb5e447cd..cf05ce05bba1 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -449,8 +449,20 @@
};
 
hsusb: usb@e659 {
+   compatible = "renesas,usbhs-r8a7744",
+"renesas,rcar-gen2-usbhs";
reg = <0 0xe659 0 0x100>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 704>;
+   dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+  <&usb_dmac1 0>, <&usb_dmac1 1>;
+   dma-names = "ch0", "ch1", "ch2", "ch3";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 704>;
+   renesas,buswait = <4>;
+   phys = <&usb0 1>;
+   phy-names = "usb";
+   status = "disabled";
};
 
usbphy: usb-phy@e6590100 {
@@ -475,6 +487,34 @@
};
};
 
+   usb_dmac0: dma-controller@e65a {
+   compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+   reg = <0 0xe65a 0 0x100>;
+   interrupts = ;
+   interrupt-names = "ch0", "ch1";
+   clocks = <&cpg CPG_MOD 330>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 330>;
+   #dma-cells = <1>;
+   dma-channels = <2>;
+   };
+
+   usb_dmac1: dma-controller@e65b {
+   compatible = "renesas,r8a7744-usb-dmac",
+"renesas,usb-dmac";
+   reg = <0 0xe65b 0 0x100>;
+   interrupts = ;
+   interrupt-names = "ch0", "ch1";
+   clocks = <&cpg CPG_MOD 331>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 331>;
+   #dma-cells = <1>;
+   dma-channels = <2>;
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a7744",
 "renesas,rcar-dmac";
-- 
2.11.0

[PATCH 0/8] Remove CLK_IS_BASIC usage from clk drivers

[Stephen Boyd]

A collection of patches to remove CLK_IS_BASIC from drivers
that don't look to have any need for it. There are some files
outside of drivers/clk/ that aren't include here because I'll
send those patches to respective maintainers.

Cc: Anders Berg 
Cc: Geert Uytterhoeven 
Cc: Jiancheng Xue 
Cc: Jianguo Sun 
Cc: Krzysztof Kozlowski 
Cc: Kukjin Kim 
Cc: Leo Yan 
Cc: Linus Walleij 
Cc: 
Cc: Sylwester Nawrocki 
Cc: 
Cc: Wei Yongjun 
Cc: Yoshinori Sato 

Stephen Boyd (8):
  clk: renesas: Remove usage of CLK_IS_BASIC
  clk: st: Remove usage of CLK_IS_BASIC
  clk: axm5516: Remove usage of CLK_IS_BASIC
  clk: h8300: Remove usage of CLK_IS_BASIC
  clk: hisilicon: Remove usage of CLK_IS_BASIC
  clk: versatile: sp810: Remove usage of CLK_IS_BASIC
  clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC
  clk: Loongson1: Remove usage of CLK_IS_BASIC

 drivers/clk/clk-axm5516.c | 2 --
 drivers/clk/h8300/clk-h8s2678.c   | 2 +-
 drivers/clk/hisilicon/clk-hi3620.c| 2 +-
 drivers/clk/hisilicon/clk-hisi-phase.c| 2 +-
 drivers/clk/hisilicon/clk-hix5hd2.c   | 2 +-
 drivers/clk/hisilicon/clkgate-separated.c | 2 +-
 drivers/clk/loongson1/clk.c   | 8 +---
 drivers/clk/renesas/clk-div6.c| 2 +-
 drivers/clk/renesas/clk-mstp.c| 2 +-
 drivers/clk/renesas/r9a06g032-clocks.c| 8 
 drivers/clk/renesas/rcar-gen3-cpg.c   | 2 +-
 drivers/clk/renesas/renesas-cpg-mssr.c| 2 +-
 drivers/clk/samsung/clk-s3c2410-dclk.c| 2 +-
 drivers/clk/st/clk-flexgen.c  | 2 +-
 drivers/clk/st/clkgen-fsyn.c  | 4 ++--
 drivers/clk/st/clkgen-pll.c   | 2 +-
 drivers/clk/versatile/clk-sp810.c | 2 +-
 17 files changed, 24 insertions(+), 24 deletions(-)

-- 
Sent by a computer through tubes

[PATCH 11/34] ARM: dts: r8a7744: Add SDHI nodes

[Simon Horman]

From: Biju Das 

Add SDHI nodes to the DT of the r8a7744 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 39 +--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 57e0be34b989..97b417c1b5f9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -866,14 +866,49 @@
/* placeholder */
};
 
+   sdhi0: sd@ee10 {
+   compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
+   reg = <0 0xee10 0 0x328>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 314>;
+   dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+  <&dmac1 0xcd>, <&dmac1 0xce>;
+   dma-names = "tx", "rx", "tx", "rx";
+   max-frequency = <19500>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 314>;
+   status = "disabled";
+   };
+
sdhi1: sd@ee14 {
+   compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee14 0 0x100>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 312>;
+   dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+  <&dmac1 0xc1>, <&dmac1 0xc2>;
+   dma-names = "tx", "rx", "tx", "rx";
+   max-frequency = <9750>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 312>;
+   status = "disabled";
};
 
sdhi2: sd@ee16 {
+   compatible = "renesas,sdhi-r8a7744",
+"renesas,rcar-gen2-sdhi";
reg = <0 0xee16 0 0x100>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 311>;
+   dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+  <&dmac1 0xd3>, <&dmac1 0xd4>;
+   dma-names = "tx", "rx", "tx", "rx";
+   max-frequency = <9750>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 311>;
+   status = "disabled";
};
 
gic: interrupt-controller@f1001000 {
-- 
2.11.0

[PATCH 04/34] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N

[Simon Horman]

From: Biju Das 

Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +++
 2 files changed, 16 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d625b9..aba5a25b7eac 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -829,6 +829,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
+   r8a7744-iwg20d-q7.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts 
b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
new file mode 100644
index ..1fdac528f274
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1N Qseven board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+
+/ {
+   model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N";
+   compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
-- 
2.11.0

[PATCH 03/34] ARM: dts: r8a7744: Initial SoC device tree

[Simon Horman]

From: Biju Das 

Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders
to avoid compilation error with the common platform code.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 369 +
 1 file changed, 369 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7744.dtsi

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
new file mode 100644
index ..f4d0abde3f56
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7744 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a7744";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+   audio_clk_a: audio_clk_a {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_b: audio_clk_b {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_c: audio_clk_c {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   /* External CAN clock */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board. */
+   clock-frequency = <0>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a15";
+   reg = <0>;
+   clock-frequency = <15>;
+   clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
+   clock-latency = <30>; /* 300 us */
+   power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
+   next-level-cache = <&L2_CA15>;
+
+   /* kHz - uV - OPPs unknown yet */
+   operating-points = <150 100>,
+  <1312500 100>,
+  <1125000 100>,
+  < 937500 100>,
+  < 75 100>,
+  < 375000 100>;
+   };
+
+   L2_CA15: cache-controller-0 {
+   compatible = "cache";
+   cache-unified;
+   cache-level = <2>;
+   power-domains = <&sysc R8A7744_PD_CA15_SCU>;
+   };
+   };
+
+   /* External root clock */
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board. */
+   clock-frequency = <0>;
+   };
+
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   pmu {
+   compatible = "arm,cortex-a15-pmu";
+   interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <&cpu0>;
+   };
+
+   /* External SCIF clock */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board. */
+   clock-frequency = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <&gic>;
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   gpio0: gpio@e605 {
+   reg = <0 0xe605 0 0x50>;
+   #gpio-cells = <2>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   /* placeholder */
+   };
+
+   gpio1: gpio@e6051000 {
+   reg = <0 0xe6051000 0 0x50>;
+   #gpio-cells = <2>;
+   /* placeholder */
+   };
+
+   gpio2: gpio@e6052000 {
+   reg = <0 0xe6052000 0 0x50>;
+   #gpio-cells = <2>;
+  

[PATCH 12/34] ARM: dts: r8a7744: Add MMC node

[Simon Horman]

From: Biju Das 

Add MMC node to the DT of the r8a7744 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 97b417c1b5f9..3f7674b2aac5 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -911,6 +911,22 @@
status = "disabled";
};
 
+   mmcif0: mmc@ee20 {
+   compatible = "renesas,mmcif-r8a7744",
+"renesas,sh-mmcif";
+   reg = <0 0xee20 0 0x80>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 315>;
+   dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+  <&dmac1 0xd1>, <&dmac1 0xd2>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 315>;
+   reg-io-width = <4>;
+   max-frequency = <9750>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0

[PATCH 14/34] ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller

[Simon Horman]

From: Biju Das 

Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 1e57b1f9baed..503583e2c852 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -35,6 +35,12 @@
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
+
+   sdhi0_pins: sd0 {
+   groups = "sdhi0_data4", "sdhi0_ctrl";
+   function = "sdhi0";
+   power-source = <3300>;
+   };
 };
 
 &mmcif0 {
@@ -46,3 +52,13 @@
non-removable;
status = "okay";
 };
+
+&sdhi0 {
+   pinctrl-0 = <&sdhi0_pins>;
+   pinctrl-names = "default";
+
+   vmmc-supply = <®_3p3v>;
+   vqmmc-supply = <®_3p3v>;
+   cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
-- 
2.11.0

[PATCH 05/34] ARM: dts: r8a7744: Add SYS-DMAC support

[Simon Horman]

From: Biju Das 

Describe SYS-DMAC0/1 in the R8A7744 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 66 ++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index f4d0abde3f56..732c5d71191c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -215,6 +215,72 @@
/* placeholder */
};
 
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a7744",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+   clocks = <&cpg CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 219>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
+
+   dmac1: dma-controller@e672 {
+   compatible = "renesas,dmac-r8a7744",
+"renesas,rcar-dmac";
+   reg = <0 0xe672 0 0x2>;
+   interrupts = ;
+   interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+   clocks = <&cpg CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 218>;
+   #dma-cells = <1>;
+   dma-channels = <15>;
+   };
+
avb: ethernet@e680 {
reg = <0 0xe680 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
-- 
2.11.0

[PATCH 07/34] ARM: dts: r8a7744: Add Ethernet AVB support

[Simon Horman]

From: Biju Das 

Add Ethernet AVB support for R8A7744 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Simon Horman 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index ea1a78288707..4d4ddbaba456 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -376,10 +376,16 @@
};
 
avb: ethernet@e680 {
+   compatible = "renesas,etheravb-r8a7744",
+"renesas,etheravb-rcar-gen2";
reg = <0 0xe680 0 0x800>, <0 0xee0e8000 0 0x4000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 812>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
-   /* placeholder */
+   status = "disabled";
};
 
scifb1: serial@e6c3 {
-- 
2.11.0

[PATCH 13/34] ARM: dts: r8a7744-iwg20m: Add eMMC support

[Simon Horman]

From: Biju Das 

Add eMMC support for iWave RZ/G1N Qseven System On Module.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 6166ae053060..1e57b1f9baed 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -29,3 +29,20 @@
 &extal_clk {
clock-frequency = <2000>;
 };
+
+&pfc {
+   mmcif0_pins: mmc {
+   groups = "mmc_data8_b", "mmc_ctrl";
+   function = "mmc";
+   };
+};
+
+&mmcif0 {
+   pinctrl-0 = <&mmcif0_pins>;
+   pinctrl-names = "default";
+
+   vmmc-supply = <®_3p3v>;
+   bus-width = <8>;
+   non-removable;
+   status = "okay";
+};
-- 
2.11.0

[PATCH 08/34] ARM: dts: r8a7744: Add SMP support

[Simon Horman]

From: Biju Das 

Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Also add cpu1 phandle node to the PMU interrupt-affinity property.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 38 --
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 4d4ddbaba456..2cb6d8fa2fa0 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,6 +49,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+   enable-method = "renesas,apmu";
 
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,25 @@
   < 375000 100>;
};
 
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a15";
+   reg = <1>;
+   clock-frequency = <15>;
+   clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
+   clock-latency = <30>; /* 300 us */
+   power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+   next-level-cache = <&L2_CA15>;
+
+   /* kHz - uV - OPPs unknown yet */
+   operating-points = <150 100>,
+  <1312500 100>,
+  <1125000 100>,
+  < 937500 100>,
+  < 75 100>,
+  < 375000 100>;
+   };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -96,7 +116,7 @@
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-   interrupt-affinity = <&cpu0>;
+   interrupt-affinity = <&cpu0>, <&cpu1>;
};
 
/* External SCIF clock */
@@ -250,6 +270,12 @@
#reset-cells = <1>;
};
 
+   apmu@e6152000 {
+   compatible = "renesas,r8a7744-apmu", "renesas,apmu";
+   reg = <0 0xe6152000 0 0x188>;
+   cpus = <&cpu0 &cpu1>;
+   };
+
rst: reset-controller@e616 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe616 0 0x100>;
@@ -483,7 +509,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
  <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
-   interrupts = ;
+   interrupts = ;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -520,10 +546,10 @@
 
timer {
compatible = "arm,armv7-timer";
-   interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) 
| IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) 
| IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) 
| IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) 
| IRQ_TYPE_LEVEL_LOW)>;
+   interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>;
};
 
/* External USB clock - can be overridden by the board */
-- 
2.11.0

[PATCH 02/34] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM

[Simon Horman]

From: Biju Das 

Add support for iWave RZ/G1N Qseven System On Module.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++
 1 file changed, 31 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi

diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
new file mode 100644
index ..6166ae053060
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1N Qseven SOM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a7744.dtsi"
+#include 
+
+/ {
+   compatible = "iwave,g20m", "renesas,r8a7744";
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x4000>;
+   };
+
+   reg_3p3v: 3p3v {
+   compatible = "regulator-fixed";
+   regulator-name = "3P3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+};
+
+&extal_clk {
+   clock-frequency = <2000>;
+};
-- 
2.11.0

[PATCH 20/34] ARM: dts: r8a7744: Add IRQC support

[Simon Horman]

From: Biju Das 

Describe the IRQC interrupt controller in the r8a7744 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 87187f266066..91096c36dcac 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -297,6 +297,26 @@
#power-domain-cells = <1>;
};
 
+   irqc: interrupt-controller@e61c {
+   compatible = "renesas,irqc-r8a7744", "renesas,irqc";
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   reg = <0 0xe61c 0 0x200>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   clocks = <&cpg CPG_MOD 407>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 407>;
+   };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
-- 
2.11.0

[PATCH 22/34] ARM: dts: r8a7744: Add CMT SoC specific support

[Simon Horman]

From: Biju Das 

Add CMT[01] support to SoC DT.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 937c800b2415..8f43fb41ec91 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1360,6 +1360,38 @@
compatible = "renesas,prr";
reg = <0 0xff44 0 4>;
};
+
+   cmt0: timer@ffca {
+   compatible = "renesas,r8a7744-cmt0",
+"renesas,rcar-gen2-cmt0";
+   reg = <0 0xffca 0 0x1004>;
+   interrupts = ,
+;
+   clocks = <&cpg CPG_MOD 124>;
+   clock-names = "fck";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 124>;
+   status = "disabled";
+   };
+
+   cmt1: timer@e613 {
+   compatible = "renesas,r8a7744-cmt1",
+"renesas,rcar-gen2-cmt1";
+   reg = <0 0xe613 0 0x1004>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   clocks = <&cpg CPG_MOD 329>;
+   clock-names = "fck";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 329>;
+   status = "disabled";
+   };
};
 
thermal-zones {
-- 
2.11.0

[PATCH 10/34] ARM: dts: r8a7744: Add I2C and IIC support

[Simon Horman]

From: Biju Das 

Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 127 -
 1 file changed, 125 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 1fe694d0215b..57e0be34b989 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -310,19 +310,142 @@
reg = <0 0xe630 0 0x4>;
};
 
+   /* The memory map in the User's Manual maps the cores to
+* bus numbers
+*/
+   i2c0: i2c@e6508000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+   reg = <0 0xe6508000 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 931>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 931>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@e6518000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+   reg = <0 0xe6518000 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 930>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 930>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
i2c2: i2c@e653 {
#address-cells = <1>;
#size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe653 0 0x40>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 929>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 929>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@e654 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+   reg = <0 0xe654 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 928>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 928>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c4: i2c@e652 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
+   reg = <0 0xe652 0 0x40>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 927>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 927>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
};
 
i2c5: i2c@e6528000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
+   compatible = "renesas,i2c-r8a7744",
+"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 925>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 925>;
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   iic0: i2c@e650 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,iic-r8a7744",
+"renesas,rcar-gen2-iic",
+"renesas,rmobile-iic";
+   reg = <0 0xe650

[PATCH 15/34] ARM: dts: r8a7744: USB 2.0 host support

[Simon Horman]

From: Biju Das 

Describe internal PCI bridge devices, USB phy device and
link PCI USB devices to USB phy.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 77 +++---
 1 file changed, 72 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 3f7674b2aac5..1d4cb5e447cd 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -454,8 +454,25 @@
};
 
usbphy: usb-phy@e6590100 {
+   compatible = "renesas,usb-phy-r8a7744",
+"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
-   /* placeholder */
+   #address-cells = <1>;
+   #size-cells = <0>;
+   clocks = <&cpg CPG_MOD 704>;
+   clock-names = "usbhs";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 704>;
+   status = "disabled";
+
+   usb0: usb-channel@0 {
+   reg = <0>;
+   #phy-cells = <1>;
+   };
+   usb2: usb-channel@2 {
+   reg = <2>;
+   #phy-cells = <1>;
+   };
};
 
dmac0: dma-controller@e670 {
@@ -847,23 +864,73 @@
};
 
pci0: pci@ee09 {
-   reg = <0 0xee09 0 0xc00>;
+   compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+   device_type = "pci";
+   reg = <0 0xee09 0 0xc00>,
+ <0 0xee08 0 0x1100>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 703>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 703>;
+   status = "disabled";
 
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
-   /* placeholder */
+   ranges = <0x0200 0 0xee08 0 0xee08 0 
0x0001>;
+   interrupt-map-mask = <0xff00 0 0 0x7>;
+   interrupt-map = <0x 0 0 1 &gic GIC_SPI 108 
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 &gic GIC_SPI 108 
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 &gic GIC_SPI 108 
IRQ_TYPE_LEVEL_HIGH>;
+
+   usb@1,0 {
+   reg = <0x800 0 0 0 0>;
+   phys = <&usb0 0>;
+   phy-names = "usb";
+   };
+
+   usb@2,0 {
+   reg = <0x1000 0 0 0 0>;
+   phys = <&usb0 0>;
+   phy-names = "usb";
+   };
};
 
pci1: pci@ee0d {
-   reg = <0 0xee0d 0 0xc00>;
+   compatible = "renesas,pci-r8a7744",
+"renesas,pci-rcar-gen2";
+   device_type = "pci";
+   reg = <0 0xee0d 0 0xc00>,
+ <0 0xee0c 0 0x1100>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 703>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 703>;
+   status = "disabled";
 
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
-   /* placeholder */
+   ranges = <0x0200 0 0xee0c 0 0xee0c 0 
0x0001>;
+   interrupt-map-mask = <0xff00 0 0 0x7>;
+   interrupt-map = <0x 0 0 1 &gic GIC_SPI 113 
IRQ_TYPE_LEVEL_HIGH
+0x0800 0 0 1 &gic GIC_SPI 113 
IRQ_TYPE_LEVEL_HIGH
+0x1000 0 0 2 &gic GIC_SPI 113 
IRQ_TYPE_LEVEL_HIGH>;
+
+   usb@1,0 {
+   reg = <0x10800 0 0 0 0>;
+   phys = <&usb2 0>;
+   phy-names = "usb";
+   };
+
+   usb@2,0 {
+   reg = <0x11000 0 0 0 0>;
+   phys = <&usb2 0>;
+

[PATCH 27/34] ARM: dts: r8a7744: Add TPU support

[Simon Horman]

From: Biju Das 

Add TPU support to SoC DT.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 181aa0732ce1..bab78d43b5db 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -270,6 +270,16 @@
reg = <0 0xe606 0 0x250>;
};
 
+   tpu: pwm@e60f {
+   compatible = "renesas,tpu-r8a7744", "renesas,tpu";
+   reg = <0 0xe60f 0 0x148>;
+   clocks = <&cpg CPG_MOD 304>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 304>;
+   #pwm-cells = <3>;
+   status = "disabled";
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a7744-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
-- 
2.11.0

[PATCH 26/34] ARM: dts: r8a7744: Add PWM SoC support

[Simon Horman]

From: Biju Das 

Add the definitions for pwm[0123456] to the SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 70 ++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 06952f5a1e9f..181aa0732ce1 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -972,6 +972,76 @@
status = "disabled";
};
 
+   pwm0: pwm@e6e3 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e3 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm1: pwm@e6e31000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e31000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm2: pwm@e6e32000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e32000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm3: pwm@e6e33000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e33000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm4: pwm@e6e34000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e34000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm5: pwm@e6e35000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e35000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm6: pwm@e6e36000 {
+   compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
+   reg = <0 0xe6e36000 0 0x8>;
+   clocks = <&cpg CPG_MOD 523>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7744",
 "renesas,rcar-gen2-can";
-- 
2.11.0

[PATCH 17/34] ARM: dts: r8a7744: Add RWDT node

[Simon Horman]

From: Biju Das 

Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G1N (r8a7744) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cf05ce05bba1..fabc7f990952 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -135,6 +135,16 @@
#size-cells = <2>;
ranges;
 
+   rwdt: watchdog@e602 {
+   compatible = "renesas,r8a7744-wdt",
+"renesas,rcar-gen2-wdt";
+   reg = <0 0xe602 0 0x0c>;
+   clocks = <&cpg CPG_MOD 402>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 402>;
+   status = "disabled";
+   };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a7744",
 "renesas,rcar-gen2-gpio";
-- 
2.11.0

[PATCH 23/34] ARM: dts: r8a7744: add VIN dt support

[Simon Horman]

From: Biju Das 

Add VIN[012] support to SoC dt.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 8f43fb41ec91..094e1c4107e9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -942,6 +942,39 @@
status = "disabled";
};
 
+   vin0: video@e6ef {
+   compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+   reg = <0 0xe6ef 0 0x1000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 811>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 811>;
+   status = "disabled";
+   };
+
+   vin1: video@e6ef1000 {
+   compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+   reg = <0 0xe6ef1000 0 0x1000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 810>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 810>;
+   status = "disabled";
+   };
+
+   vin2: video@e6ef2000 {
+   compatible = "renesas,vin-r8a7744",
+"renesas,rcar-gen2-vin";
+   reg = <0 0xe6ef2000 0 0x1000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 809>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 809>;
+   status = "disabled";
+   };
+
rcar_sound: sound@ec50 {
/*
 * #sound-dai-cells is required
-- 
2.11.0

[PATCH 19/34] ARM: dts: r8a7744: Add CAN support

[Simon Horman]

From: Biju Das 

Add the definitions for can0 and can1 to the r8a7744 SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index cb6dfb5af218..87187f266066 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -884,13 +884,31 @@
};
 
can0: can@e6e8 {
+   compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e8 0 0x1000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 916>,
+<&cpg CPG_CORE R8A7744_CLK_RCAN>,
+<&can_clk>;
+   clock-names = "clkp1", "clkp2", "can_clk";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 916>;
+   status = "disabled";
};
 
can1: can@e6e88000 {
+   compatible = "renesas,can-r8a7744",
+"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
-   /* placeholder */
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 915>,
+<&cpg CPG_CORE R8A7744_CLK_RCAN>,
+<&can_clk>;
+   clock-names = "clkp1", "clkp2", "can_clk";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 915>;
+   status = "disabled";
};
 
rcar_sound: sound@ec50 {
-- 
2.11.0

[PATCH 28/34] ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB

[Simon Horman]

From: Biju Das 

This patch adds support for the camera daughter board which is
connected to iWave's RZ/G1N Qseven carrier board.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 +
 2 files changed, 18 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index aba5a25b7eac..9cf6fdfd1f3a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -830,6 +830,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7744-iwg20d-q7.dtb \
+   r8a7744-iwg20d-q7-dbcm-ca.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts 
b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
new file mode 100644
index ..3e58c2e92e03
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave Systems RZ/G1N Qseven board development
+ * platform with camera daughter board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+#include "iwg20d-q7-dbcm-ca.dtsi"
+
+/ {
+   model = "iWave Systems RZ/G1N Qseven development platform with camera 
add-on";
+   compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
-- 
2.11.0

[PATCH 06/34] ARM: dts: r8a7744: Add GPIO support

[Simon Horman]

From: Biju Das 

Describe GPIO blocks in the R8A7744 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 102 +++--
 1 file changed, 98 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 732c5d71191c..ea1a78288707 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -116,29 +116,123 @@
ranges;
 
gpio0: gpio@e605 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe605 0 0x50>;
+   interrupts = ;
#gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
-   /* placeholder */
+   clocks = <&cpg CPG_MOD 912>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 912>;
};
 
gpio1: gpio@e6051000 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
+   interrupts = ;
#gpio-cells = <2>;
-   /* placeholder */
+   gpio-controller;
+   gpio-ranges = <&pfc 0 32 26>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = <&cpg CPG_MOD 911>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 911>;
};
 
gpio2: gpio@e6052000 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
+   interrupts = ;
#gpio-cells = <2>;
-   /* placeholder */
+   gpio-controller;
+   gpio-ranges = <&pfc 0 64 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = <&cpg CPG_MOD 910>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 910>;
+   };
+
+   gpio3: gpio@e6053000 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6053000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = <&pfc 0 96 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = <&cpg CPG_MOD 909>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 909>;
+   };
+
+   gpio4: gpio@e6054000 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6054000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = <&pfc 0 128 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = <&cpg CPG_MOD 908>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 908>;
+   };
+
+   gpio5: gpio@e6055000 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6055000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = <&pfc 0 160 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = <&cpg CPG_MOD 907>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 907>;
};
 
gpio6: gpio@e6055400 {
+   compatible = "renesas,gpio-r8a7744",
+"renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
+   interrupts = ;
#gpio-ce

[PATCH 32/34] ARM: dts: r8a7744: Add PCIe Controller device node

[Simon Horman]

From: Biju Das 

Add a device node for the PCIe controller on the Renesas
RZ/G1N (r8a7744) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 33e15c5f21c9..04148d608fc4 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1616,6 +1616,34 @@
resets = <&cpg 127>;
};
 
+   pciec: pcie@fe00 {
+   compatible = "renesas,pcie-r8a7744",
+"renesas,pcie-rcar-gen2";
+   reg = <0 0xfe00 0 0x8>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <0x0100 0 0x 0 0xfe10 0 
0x0010
+ 0x0200 0 0xfe20 0 0xfe20 0 
0x0020
+ 0x0200 0 0x3000 0 0x3000 0 
0x0800
+ 0x4200 0 0x3800 0 0x3800 0 
0x0800>;
+   /* Map all possible DDR as inbound ranges */
+   dma-ranges = <0x4200 0 0x4000 0 0x4000 0 
0x8000
+ 0x4300 2 0x 2 0x 1 
0x>;
+   interrupts = ,
+,
+;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &gic GIC_SPI 116 
IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 319>;
+   status = "disabled";
+   };
+
du: display@feb0 {
reg = <0 0xfeb0 0 0x4>,
  <0 0xfeb9 0 0x1c>;
-- 
2.11.0

[PATCH 21/34] ARM: dts: r8a7744: Add thermal device to DT

[Simon Horman]

From: Biju Das 

This patch instantiates the thermal sensor module with thermal-zone
support.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 91096c36dcac..937c800b2415 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -317,6 +317,17 @@
resets = <&cpg 407>;
};
 
+   thermal: thermal@e61f {
+   compatible = "renesas,thermal-r8a7744",
+"renesas,rcar-gen2-thermal";
+   reg = <0 0xe61f 0 0x10>, <0 0xe61f0100 0 0x38>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 522>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 522>;
+   #thermal-sensor-cells = <0>;
+   };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
@@ -1351,6 +1362,26 @@
};
};
 
+   thermal-zones {
+   cpu_thermal: cpu-thermal {
+   polling-delay-passive = <0>;
+   polling-delay = <0>;
+
+   thermal-sensors = <&thermal>;
+
+   trips {
+   cpu-crit {
+   temperature = <95000>;
+   hysteresis = <0>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   };
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
-- 
2.11.0

[PATCH 34/34] ARM: dts: r8a7744-iwg20m: Add SPI NOR support

[Simon Horman]

From: Biju Das 

Add support for the SPI NOR device used to boot up the system
to the iWave RZ/G1N Qseven System On Module DT.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
index 503583e2c852..82ee3c1140ef 100644
--- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -36,6 +36,11 @@
function = "mmc";
};
 
+   qspi_pins: qspi {
+   groups = "qspi_ctrl", "qspi_data2";
+   function = "qspi";
+   };
+
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@@ -53,6 +58,27 @@
status = "okay";
 };
 
+&qspi {
+   pinctrl-0 = <&qspi_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+
+   /* WARNING - This device contains the bootloader. Handle with care. */
+   flash: flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <2>;
+   spi-rx-bus-width = <2>;
+   m25p,fast-read;
+   spi-cpol;
+   spi-cpha;
+   };
+};
+
 &sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH 25/34] ARM: dts: r8a7744: Add IPMMU DT nodes

[Simon Horman]

From: Biju Das 

Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 58 ++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index be84400c08ad..06952f5a1e9f 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -328,6 +328,64 @@
#thermal-sensor-cells = <0>;
};
 
+   ipmmu_sy0: mmu@e628 {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xe628 0 0x1000>;
+   interrupts = ,
+;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
+   ipmmu_sy1: mmu@e629 {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xe629 0 0x1000>;
+   interrupts = ;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
+   ipmmu_ds: mmu@e674 {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xe674 0 0x1000>;
+   interrupts = ,
+;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
+   ipmmu_mp: mmu@ec68 {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xec68 0 0x1000>;
+   interrupts = ;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
+   ipmmu_mx: mmu@fe951000 {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xfe951000 0 0x1000>;
+   interrupts = ,
+;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
+   ipmmu_gp: mmu@e62a {
+   compatible = "renesas,ipmmu-r8a7744",
+"renesas,ipmmu-vmsa";
+   reg = <0 0xe62a 0 0x1000>;
+   interrupts = ,
+;
+   #iommu-cells = <1>;
+   status = "disabled";
+   };
+
icram0: sram@e63a {
compatible = "mmio-sram";
reg = <0 0xe63a 0 0x12000>;
-- 
2.11.0

[PATCH 33/34] ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM

[Simon Horman]

From: Biju Das 

The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules
are SoC specific and should be part of board dts rather than SoM dtsi. By
moving these nodes to the common dtsi it allows cmt and rwdt to be enabled
on both of these boards with less lines of code.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi | 9 +
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi   | 9 -
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi 
b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index ca9154dd8052..e2b1ab9b56e5 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -116,6 +116,10 @@
status = "okay";
 };
 
+&cmt0 {
+   status = "okay";
+};
+
 &hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
@@ -230,6 +234,11 @@
};
 };
 
+&rwdt {
+   timeout-sec = <60>;
+   status = "okay";
+};
+
 &scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 0e2e033cc849..b3fee1d61c87 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -31,10 +31,6 @@
};
 };
 
-&cmt0 {
-   status = "okay";
-};
-
 &extal_clk {
clock-frequency = <2000>;
 };
@@ -88,11 +84,6 @@
};
 };
 
-&rwdt {
-   timeout-sec = <60>;
-   status = "okay";
-};
-
 &sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH 1/3] dt-bindings: arm: renesas: Document iWave RZ/G1N SOM

[Simon Horman]

From: Biju Das 

Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings,
listing it as a supported system on module.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index f5e0f82fd503..4cfb56787a90 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -101,6 +101,8 @@ Boards:
 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
   - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
 compatible = "iwave,g20m", "renesas,r8a7743"
+  - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
+compatible = "iwave,g20m", "renesas,r8a7744"
   - Kingfisher (SBEV-RCAR-KF-M03)
 compatible = "shimafuji,kingfisher"
   - Koelsch (RTP0RC7791SEB00010S)
-- 
2.11.0

[PATCH 7/9] soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers

[Simon Horman]

From: Geert Uytterhoeven 

Until commit 7e8a50df26f4e700 ("soc: renesas: rcar-sysc: Drop legacy
handling"), the rcar_sysc_power_{down,up}() helpers were public, as they
were called by the legacy (pre-DT) CPU power management code on R-Car H1
and R-Car Gen2 before.

As they are just one-line wrappers around rcar_sysc_power(), it makes
sense to just remove them.

This also avoids a bool/helper/bool conversion in rcar_sysc_power_cpu(),
where a bool is checked to call one of two helper functions, which
just call rcar_sysc_power() with hardcoded boolean values again.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/rcar-sysc.c | 19 ---
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index af53363eda03..73fae6a9728d 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -146,16 +146,6 @@ static int rcar_sysc_power(const struct rcar_sysc_ch 
*sysc_ch, bool on)
return ret;
 }
 
-static int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
-{
-   return rcar_sysc_power(sysc_ch, false);
-}
-
-static int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
-{
-   return rcar_sysc_power(sysc_ch, true);
-}
-
 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
 {
unsigned int st;
@@ -184,7 +174,7 @@ static int rcar_sysc_pd_power_off(struct generic_pm_domain 
*genpd)
struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
 
pr_debug("%s: %s\n", __func__, genpd->name);
-   return rcar_sysc_power_down(&pd->ch);
+   return rcar_sysc_power(&pd->ch, false);
 }
 
 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
@@ -192,7 +182,7 @@ static int rcar_sysc_pd_power_on(struct generic_pm_domain 
*genpd)
struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
 
pr_debug("%s: %s\n", __func__, genpd->name);
-   return rcar_sysc_power_up(&pd->ch);
+   return rcar_sysc_power(&pd->ch, true);
 }
 
 static bool has_cpg_mstp;
@@ -252,7 +242,7 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd 
*pd)
goto finalize;
}
 
-   rcar_sysc_power_up(&pd->ch);
+   rcar_sysc_power(&pd->ch, true);
 
 finalize:
error = pm_genpd_init(genpd, gov, false);
@@ -478,8 +468,7 @@ static int rcar_sysc_power_cpu(unsigned int idx, bool on)
if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
continue;
 
-   return on ? rcar_sysc_power_up(&pd->ch)
- : rcar_sysc_power_down(&pd->ch);
+   return rcar_sysc_power(&pd->ch, on);
}
 
return -ENOENT;
-- 
2.11.0

[GIT PULL] Renesas ARM Based SoC Drivers Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC drivers updates for v4.21.


The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-drivers-for-v4.21

for you to fetch changes up to 7fc4650cc2417d7a2907a000f6f88240baa42018:

  soc: renesas: rcar-sysc: Fix power domain control after system resume 
(2018-12-06 12:10:10 -0800)


Renesas ARM Based SoC Drivers Updates for v4.21

SYSC Driver:
* Common
  - Fix power domain control after system resume
  - Merge PM Domain registration and linking
  - Remove rcar_sysc_power_{down,up}() helpers
* R-Car E3 (r8a77990) SoC
  - Fix initialization order of 3DG-{A,B}
* R-Car V3H (r8a77980) SoC
  - Correct A3VIP[012] power domain hierarchy
  - Correct names of A2DP[01] power domains
* R-Car V3M (r8a77970) SoC
  - Correct names of A2DP/A2CN power domains
  - emove non-existent CR7 power domain
* R-Car M3-N (r8a77965) SoC
  - Remove non-existent A3IR power domain


Geert Uytterhoeven (9):
  soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domain
  soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain
  soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains
  soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains
  soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy
  soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B}
  soc: renesas: rcar-sysc: Remove rcar_sysc_power_{down,up}() helpers
  soc: renesas: rcar-sysc: Merge PM Domain registration and linking
  soc: renesas: rcar-sysc: Fix power domain control after system resume

 drivers/soc/renesas/r8a77965-sysc.c   |  1 -
 drivers/soc/renesas/r8a77970-sysc.c   |  5 +--
 drivers/soc/renesas/r8a77980-sysc.c   | 10 ++---
 drivers/soc/renesas/r8a77990-sysc.c   | 23 ++-
 drivers/soc/renesas/rcar-sysc.c   | 65 +--
 include/dt-bindings/power/r8a77970-sysc.h |  7 ++--
 include/dt-bindings/power/r8a77980-sysc.h |  6 +--
 7 files changed, 35 insertions(+), 82 deletions(-)

[PATCH 3/3] dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc

[Simon Horman]

From: Rob Herring 

In preparation to convert board-level bindings to json-schema, move
various misc SoC bindings out to their own file.

Signed-off-by: Rob Herring 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 .../devicetree/bindings/arm/renesas,prr.txt  | 20 
 Documentation/devicetree/bindings/arm/shmobile.txt   | 18 --
 2 files changed, 20 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt

diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt 
b/Documentation/devicetree/bindings/arm/renesas,prr.txt
new file mode 100644
index ..08e482e953ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt
@@ -0,0 +1,20 @@
+Renesas Product Register
+
+Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
+allows to retrieve SoC product and revision information.  If present, a device
+node for this register should be added.
+
+Required properties:
+  - compatible: Must be one of:
+"renesas,prr"
+"renesas,bsid"
+  - reg: Base address and length of the register block.
+
+
+Examples
+
+
+   prr: chipid@ff44 {
+   compatible = "renesas,prr";
+   reg = <0 0xff44 0 4>;
+   };
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 144f045a9f4b..92cda17870d3 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -153,21 +153,3 @@ Boards:
 compatible = "renesas,v3msk", "renesas,r8a77970"
   - Wheat (RTP0RC7792ASKBJE)
 compatible = "renesas,wheat", "renesas,r8a7792"
-
-
-Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
-allows to retrieve SoC product and revision information.  If present, a device
-node for this register should be added.
-
-Required properties:
-  - compatible: Must be "renesas,prr" or "renesas,bsid"
-  - reg: Base address and length of the register block.
-
-
-Examples
-
-
-   prr: chipid@ff44 {
-   compatible = "renesas,prr";
-   reg = <0 0xff44 0 4>;
-   };
-- 
2.11.0

[PATCH 5/9] soc: renesas: r8a77980-sysc: Correct A3VIP[012] power domain hierarchy

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
renamed the A3VIP power domain on R-Car V3H to A3VIP0, and clarified the
power domain hierarchy for the A3VIP[012] power domains.

As the definition for the A3VIP0 domain is not yet used from DT, it can
just be renamed.

Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain 
definitions")
Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77980-sysc.c   | 6 +++---
 include/dt-bindings/power/r8a77980-sysc.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/renesas/r8a77980-sysc.c 
b/drivers/soc/renesas/r8a77980-sysc.c
index dbb2621ce4e3..a8dbe55e8ba8 100644
--- a/drivers/soc/renesas/r8a77980-sysc.c
+++ b/drivers/soc/renesas/r8a77980-sysc.c
@@ -41,9 +41,9 @@ static const struct rcar_sysc_area r8a77980_areas[] 
__initconst = {
{ "a2dp0",  0x400, 11, R8A77980_PD_A2DP0,   R8A77980_PD_A3IR },
{ "a2dp1",  0x400, 12, R8A77980_PD_A2DP1,   R8A77980_PD_A3IR },
{ "a2cn",   0x400, 13, R8A77980_PD_A2CN,R8A77980_PD_A3IR },
-   { "a3vip",  0x2c0, 0, R8A77980_PD_A3VIP,R8A77980_PD_ALWAYS_ON },
-   { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1,   R8A77980_PD_A3VIP },
-   { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2,   R8A77980_PD_A3VIP },
+   { "a3vip0", 0x2c0, 0, R8A77980_PD_A3VIP0,   R8A77980_PD_ALWAYS_ON },
+   { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1,   R8A77980_PD_ALWAYS_ON },
+   { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2,   R8A77980_PD_ALWAYS_ON },
 };
 
 const struct rcar_sysc_info r8a77980_sysc_info __initconst = {
diff --git a/include/dt-bindings/power/r8a77980-sysc.h 
b/include/dt-bindings/power/r8a77980-sysc.h
index 7bebe7e8dbdb..e12c8587b87e 100644
--- a/include/dt-bindings/power/r8a77980-sysc.h
+++ b/include/dt-bindings/power/r8a77980-sysc.h
@@ -22,7 +22,7 @@
 #define R8A77980_PD_CA53_CPU2  7
 #define R8A77980_PD_CA53_CPU3  8
 #define R8A77980_PD_A2CN   10
-#define R8A77980_PD_A3VIP  11
+#define R8A77980_PD_A3VIP0 11
 #define R8A77980_PD_A2IR5  12
 #define R8A77980_PD_CR713
 #define R8A77980_PD_A2IR4  15
-- 
2.11.0

[PATCH 9/9] soc: renesas: rcar-sysc: Fix power domain control after system resume

[Simon Horman]

From: Geert Uytterhoeven 

To control power to a power domain, the System Controller (SYSC) needs
the corresponding interrupt source to be enabled, but masked, to prevent
the CPU from receiving it.

Currently this is handled in the driver's probe() routine, and set up
for every domain present, even if it will not be controlled directly by
SYSC (CPU domains are powered through the APMU on R-Car Gen2 and later).

On R-Car Gen3, PSCI powers down the SoC during system suspend, thus
losing any configured interrupt state.  Hence after system resume, power
domains not controlled through the APMU (e.g. A3IR, A3VC, A3VP) fail to
power up.

Fix this by replacing the global interrupt setup in the probe() routine
by a domain-specific interrupt setup in rcar_sysc_power(), where the
domain's power is actually controlled.  This brings the code more in
line with the flowchart in the Hardware User's Manual.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/rcar-sysc.c | 28 +---
 1 file changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 123e553510e8..0c80fab4f8de 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -105,6 +105,15 @@ static int rcar_sysc_power(const struct rcar_sysc_ch 
*sysc_ch, bool on)
 
spin_lock_irqsave(&rcar_sysc_lock, flags);
 
+   /*
+* The interrupt source needs to be enabled, but masked, to prevent the
+* CPU from receiving it.
+*/
+   iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
+ rcar_sysc_base + SYSCIMR);
+   iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
+ rcar_sysc_base + SYSCIER);
+
iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
 
/* Submit power shutoff or resume request until it was accepted */
@@ -324,7 +333,6 @@ static int __init rcar_sysc_pd_init(void)
const struct of_device_id *match;
struct rcar_pm_domains *domains;
struct device_node *np;
-   u32 syscier, syscimr;
void __iomem *base;
unsigned int i;
int error;
@@ -363,24 +371,6 @@ static int __init rcar_sysc_pd_init(void)
domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
rcar_sysc_onecell_data = &domains->onecell_data;
 
-   for (i = 0, syscier = 0; i < info->num_areas; i++)
-   syscier |= BIT(info->areas[i].isr_bit);
-
-   /*
-* Mask all interrupt sources to prevent the CPU from receiving them.
-* Make sure not to clear reserved bits that were set before.
-*/
-   syscimr = ioread32(base + SYSCIMR);
-   syscimr |= syscier;
-   pr_debug("%pOF: syscimr = 0x%08x\n", np, syscimr);
-   iowrite32(syscimr, base + SYSCIMR);
-
-   /*
-* SYSC needs all interrupt sources enabled to control power.
-*/
-   pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
-   iowrite32(syscier, base + SYSCIER);
-
for (i = 0; i < info->num_areas; i++) {
const struct rcar_sysc_area *area = &info->areas[i];
struct rcar_sysc_pd *pd;
-- 
2.11.0

[PATCH 31/34] ARM: dts: r8a7744: Add xhci support

[Simon Horman]

From: Biju Das 

Add a device node for the xhci controller on the Renesas
RZ/G1N (r8a7744) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 992d622b5393..33e15c5f21c9 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1424,6 +1424,26 @@
dma-channels = <13>;
};
 
+   /*
+* pci1 and xhci share the same phy, therefore only one of them
+* can be active at any one time. If both of them are enabled,
+* a race condition will determine who'll control the phy.
+* A firmware file is needed by the xhci driver in order for
+* USB 3.0 to work properly.
+*/
+   xhci: usb@ee00 {
+   compatible = "renesas,xhci-r8a7744",
+"renesas,rcar-gen2-xhci";
+   reg = <0 0xee00 0 0xc00>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 328>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 328>;
+   phys = <&usb2 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
pci0: pci@ee09 {
compatible = "renesas,pci-r8a7744",
 "renesas,pci-rcar-gen2";
-- 
2.11.0

[PATCH 2/3] dt-bindings: arm: renesas: Document iW-RainboW-G20D-Qseven-RZG1N board

[Simon Horman]

From: Biju Das 

Document the iW-RainboW-G20D-Qseven-RZG1N device tree bindings,
listing it as a supported board.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
Signed-off-by: Simon Horman 
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 4cfb56787a90..144f045a9f4b 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -101,6 +101,8 @@ Boards:
 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
   - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
 compatible = "iwave,g20m", "renesas,r8a7743"
+  - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
+compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"
   - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
 compatible = "iwave,g20m", "renesas,r8a7744"
   - Kingfisher (SBEV-RCAR-KF-M03)
-- 
2.11.0

[PATCH 8/9] soc: renesas: rcar-sysc: Merge PM Domain registration and linking

[Simon Horman]

From: Geert Uytterhoeven 

Commit 977d5ba4507dfe5b ("soc: renesas: rcar-sysc: Make PM domain
initialization more robust") split PM Domain registration and the
linking of children to their parents, to accommodate PM Domain tables
that list child domains before their parents.

However, this failed to realize that parent power domains must be
powered up before their children anyway, and that this thus must be
reflected by the order in the PM Domain tables.

Revert the split, as it did not help anyway.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/rcar-sysc.c | 18 +-
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 73fae6a9728d..123e553510e8 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -381,9 +381,6 @@ static int __init rcar_sysc_pd_init(void)
pr_debug("%pOF: syscier = 0x%08x\n", np, syscier);
iowrite32(syscier, base + SYSCIER);
 
-   /*
-* First, create all PM domains
-*/
for (i = 0; i < info->num_areas; i++) {
const struct rcar_sysc_area *area = &info->areas[i];
struct rcar_sysc_pd *pd;
@@ -411,22 +408,17 @@ static int __init rcar_sysc_pd_init(void)
goto out_put;
 
domains->domains[area->isr_bit] = &pd->genpd;
-   }
 
-   /*
-* Second, link all PM domains to their parents
-*/
-   for (i = 0; i < info->num_areas; i++) {
-   const struct rcar_sysc_area *area = &info->areas[i];
-
-   if (!area->name || area->parent < 0)
+   if (area->parent < 0)
continue;
 
error = pm_genpd_add_subdomain(domains->domains[area->parent],
-  domains->domains[area->isr_bit]);
-   if (error)
+  &pd->genpd);
+   if (error) {
pr_warn("Failed to add PM subdomain %s to parent %u\n",
area->name, area->parent);
+   goto out_put;
+   }
}
 
error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
-- 
2.11.0

[GIT PULL] Renesas ARM Based SoC DT Bindings Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC DT bindings updates for v4.21.


The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-dt-bindings-for-v4.21

for you to fetch changes up to 74791d15fd7c405511e3cc097c2f043171ecbdb0:

  dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc 
(2018-12-06 11:33:22 -0800)


Renesas ARM Based SoC DT Bindings Updates for v4.21

* Move 'renesas,prr' binding to its own document
  - Prepration for converting board-level bindings to json-schema

* Document iW-RainboW-G20D-Qseven-RZG1N board and iWave RZ/G1N SOM


Biju Das (2):
  dt-bindings: arm: renesas: Document iWave RZ/G1N SOM
  dt-bindings: arm: renesas: Document iW-RainboW-G20D-Qseven-RZG1N board

Rob Herring (1):
  dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc

 .../devicetree/bindings/arm/renesas,prr.txt| 20 
 Documentation/devicetree/bindings/arm/shmobile.txt | 22 --
 2 files changed, 24 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt

[PATCH 18/34] ARM: dts: r8a7744: Add audio support

[Simon Horman]

From: Biju Das 

Add sound support for the RZ/G1N SoC (a.k.a. R8A7744).

This work is based on similar work done on the R8A7743 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 243 +++--
 1 file changed, 235 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index fabc7f990952..cb6dfb5af218 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -894,23 +894,250 @@
};
 
rcar_sound: sound@ec50 {
-   reg = <0 0xec50 0 0x1000>;
+   /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; 
<&rcar_sound>;
+* Multi  DAI : #sound-dai-cells = <1>; 
<&rcar_sound N>;
+*/
+   compatible = "renesas,rcar_sound-r8a7744",
+"renesas,rcar_sound-gen2";
+   reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>,  /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>,  /* SSI */
+ <0 0xec74 0 0x200>;  /* Audio DMAC peri peri*/
+   reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+   clocks = <&cpg CPG_MOD 1005>,
+<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+<&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+<&cpg CPG_CORE R8A7744_CLK_M2>;
+   clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", 
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", 
"ssi.0",
+ "src.9", "src.8", "src.7", "src.6", 
"src.5",
+ "src.4", "src.3", "src.2", "src.1", 
"src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 1005>,
+<&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 
1009>,
+<&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 
1013>,
+<&cpg 1014>, <&cpg 1015>;
+   reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6", 
"ssi.5",
+ "ssi.4", "ssi.3", "ssi.2", "ssi.1", 
"ssi.0";
+   status = "disabled";
 
rcar_sound,dvc {
-   dvc0: dvc-0 {};
-   dvc1: dvc-1 {};
+   dvc0: dvc-0 {
+   dmas = <&audma1 0xbc>;
+   dma-names = "tx";
+   };
+   dvc1: dvc-1 {
+   dmas = <&audma1 0xbe>;
+   dma-names = "tx";
+   };
+   };
+
+   rcar_sound,mix {
+   mix0: mix-0 { };
+   mix1: mix-1 { };
+   };
+
+   rcar_sound,ctu {
+   ctu00: ctu-0 { };
+   ctu01: ctu-1 { };
+   ctu02: ctu-2 { };
+   ctu03: ctu-3 { };
+   ctu10: ctu-4 { }

[PATCH 24/34] ARM: dts: r8a7744: Add VSP support

[Simon Horman]

From: Biju Das 

Add VSP support to SoC DT.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 094e1c4107e9..be84400c08ad 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1367,6 +1367,33 @@
resets = <&cpg 408>;
};
 
+   vsp@fe928000 {
+   compatible = "renesas,vsp1";
+   reg = <0 0xfe928000 0 0x8000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 131>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 131>;
+   };
+
+   vsp@fe93 {
+   compatible = "renesas,vsp1";
+   reg = <0 0xfe93 0 0x8000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 128>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 128>;
+   };
+
+   vsp@fe938000 {
+   compatible = "renesas,vsp1";
+   reg = <0 0xfe938000 0 0x8000>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 127>;
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   resets = <&cpg 127>;
+   };
+
du: display@feb0 {
reg = <0 0xfeb0 0 0x4>,
  <0 0xfeb9 0 0x1c>;
-- 
2.11.0

[PATCH 3/9] soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
renamed the A2IR2 and A2IR3 power domains on R-Car V3M to A2DP resp.
A2CN.

As these definitions are not yet used from DT, they can just be renamed.

While at it, fix the indentation of the A3IR definition.

Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain 
definitions")
Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77970-sysc.c   | 4 ++--
 include/dt-bindings/power/r8a77970-sysc.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/renesas/r8a77970-sysc.c 
b/drivers/soc/renesas/r8a77970-sysc.c
index 2c6d76490ca0..280c48b80f24 100644
--- a/drivers/soc/renesas/r8a77970-sysc.c
+++ b/drivers/soc/renesas/r8a77970-sysc.c
@@ -23,8 +23,8 @@ static const struct rcar_sysc_area r8a77970_areas[] 
__initconst = {
{ "a3ir",   0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
{ "a2ir0",  0x400, 0, R8A77970_PD_A2IR0,R8A77970_PD_A3IR },
{ "a2ir1",  0x400, 1, R8A77970_PD_A2IR1,R8A77970_PD_A3IR },
-   { "a2ir2",  0x400, 2, R8A77970_PD_A2IR2,R8A77970_PD_A3IR },
-   { "a2ir3",  0x400, 3, R8A77970_PD_A2IR3,R8A77970_PD_A3IR },
+   { "a2dp",   0x400, 2, R8A77970_PD_A2DP, R8A77970_PD_A3IR },
+   { "a2cn",   0x400, 3, R8A77970_PD_A2CN, R8A77970_PD_A3IR },
{ "a2sc0",  0x400, 4, R8A77970_PD_A2SC0,R8A77970_PD_A3IR },
{ "a2sc1",  0x400, 5, R8A77970_PD_A2SC1,R8A77970_PD_A3IR },
 };
diff --git a/include/dt-bindings/power/r8a77970-sysc.h 
b/include/dt-bindings/power/r8a77970-sysc.h
index 5c1ef1398b70..85cc5f23cf9f 100644
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ b/include/dt-bindings/power/r8a77970-sysc.h
@@ -18,10 +18,10 @@
 #define R8A77970_PD_CA53_CPU1   6
 #define R8A77970_PD_CA53_SCU   21
 #define R8A77970_PD_A2IR0  23
-#define R8A77970_PD_A3IR   24
+#define R8A77970_PD_A3IR   24
 #define R8A77970_PD_A2IR1  27
-#define R8A77970_PD_A2IR2  28
-#define R8A77970_PD_A2IR3  29
+#define R8A77970_PD_A2DP   28
+#define R8A77970_PD_A2CN   29
 #define R8A77970_PD_A2SC0  30
 #define R8A77970_PD_A2SC1  31
 
-- 
2.11.0

[PATCH 1/9] soc: renesas: r8a77965-sysc: Remove non-existent A3IR power domain

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
removed the A3IR power domain on R-Car M3-N, as this SoC does not have
an Image Processing Unit (IMP-X5).

The definition in the DT bindings header cannot be removed yet, until
its (incorrect) user has been removed.

Fixes: a527709b78b3c997 ("soc: renesas: rcar-sysc: Add R-Car M3-N support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77965-sysc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/soc/renesas/r8a77965-sysc.c 
b/drivers/soc/renesas/r8a77965-sysc.c
index d7f7928e3c07..e0533beb50fd 100644
--- a/drivers/soc/renesas/r8a77965-sysc.c
+++ b/drivers/soc/renesas/r8a77965-sysc.c
@@ -28,7 +28,6 @@ static const struct rcar_sysc_area r8a77965_areas[] 
__initconst = {
{ "a2vc1",  0x3c0, 1, R8A77965_PD_A2VC1,R8A77965_PD_A3VC },
{ "3dg-a",  0x100, 0, R8A77965_PD_3DG_A,R8A77965_PD_ALWAYS_ON },
{ "3dg-b",  0x100, 1, R8A77965_PD_3DG_B,R8A77965_PD_3DG_A },
-   { "a3ir",   0x180, 0, R8A77965_PD_A3IR, R8A77965_PD_ALWAYS_ON },
 };
 
 const struct rcar_sysc_info r8a77965_sysc_info __initconst = {
-- 
2.11.0

[PATCH 30/34] ARM: dts: r8a7744: Add MSIOF[012] support

[Simon Horman]

From: Biju Das 

Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 48 ++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 28fea2aaa0cf..992d622b5393 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1068,6 +1068,54 @@
status = "disabled";
};
 
+   msiof0: spi@e6e2 {
+   compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+   reg = <0 0xe6e2 0 0x0064>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 000>;
+   dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+  <&dmac1 0x51>, <&dmac1 0x52>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   resets = <&cpg 000>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6e1 {
+   compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+   reg = <0 0xe6e1 0 0x0064>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 208>;
+   dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+  <&dmac1 0x55>, <&dmac1 0x56>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   resets = <&cpg 208>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6e0 {
+   compatible = "renesas,msiof-r8a7744",
+"renesas,rcar-gen2-msiof";
+   reg = <0 0xe6e0 0 0x0064>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 205>;
+   dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+  <&dmac1 0x41>, <&dmac1 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   resets = <&cpg 205>;
+   status = "disabled";
+   };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7744",
 "renesas,rcar-gen2-can";
-- 
2.11.0

[PATCH 2/9] soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
removed the CR7 power domain on R-Car V3M, as this SoC does not have an
ARM Cortex-R7 Realtime Core.

As this definition was never used from DT, it can just be removed.

Fixes: 833bdb47c826a1a6 ("dt-bindings: power: add R8A77970 SYSC power domain 
definitions")
Fixes: bab9b2a74fe9da96 ("soc: renesas: rcar-sysc: add R8A77970 support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77970-sysc.c   | 1 -
 include/dt-bindings/power/r8a77970-sysc.h | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/soc/renesas/r8a77970-sysc.c 
b/drivers/soc/renesas/r8a77970-sysc.c
index 35b30d6a8958..2c6d76490ca0 100644
--- a/drivers/soc/renesas/r8a77970-sysc.c
+++ b/drivers/soc/renesas/r8a77970-sysc.c
@@ -20,7 +20,6 @@ static const struct rcar_sysc_area r8a77970_areas[] 
__initconst = {
  PD_CPU_NOCR },
{ "ca53-cpu1",  0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
  PD_CPU_NOCR },
-   { "cr7",0x240, 0, R8A77970_PD_CR7,  R8A77970_PD_ALWAYS_ON },
{ "a3ir",   0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
{ "a2ir0",  0x400, 0, R8A77970_PD_A2IR0,R8A77970_PD_A3IR },
{ "a2ir1",  0x400, 1, R8A77970_PD_A2IR1,R8A77970_PD_A3IR },
diff --git a/include/dt-bindings/power/r8a77970-sysc.h 
b/include/dt-bindings/power/r8a77970-sysc.h
index bf54779d1625..5c1ef1398b70 100644
--- a/include/dt-bindings/power/r8a77970-sysc.h
+++ b/include/dt-bindings/power/r8a77970-sysc.h
@@ -16,7 +16,6 @@
 
 #define R8A77970_PD_CA53_CPU0   5
 #define R8A77970_PD_CA53_CPU1   6
-#define R8A77970_PD_CR713
 #define R8A77970_PD_CA53_SCU   21
 #define R8A77970_PD_A2IR0  23
 #define R8A77970_PD_A3IR   24
-- 
2.11.0

[PATCH 6/9] soc: renesas: r8a77990-sysc: Fix initialization order of 3DG-{A,B}

[Simon Horman]

From: Geert Uytterhoeven 

The workaround for the wrong hierarchy of the 3DG-{A,B} power
domains on R-Car E3 ES1.0 corrected the parent domains.
However, the 3DG-{A,B} power domains were still initialized and powered
in the wrong order, causing 3DG operation to fail.

Fix this by changing the order in the table at runtime, when running on
an affected SoC.

Fixes: 086b399965a7ee7e ("soc: renesas: r8a77990-sysc: Add workaround for 
3DG-{A,B}")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77990-sysc.c | 23 ---
 1 file changed, 4 insertions(+), 19 deletions(-)

diff --git a/drivers/soc/renesas/r8a77990-sysc.c 
b/drivers/soc/renesas/r8a77990-sysc.c
index 15579ebc5ed2..664b244eb1dd 100644
--- a/drivers/soc/renesas/r8a77990-sysc.c
+++ b/drivers/soc/renesas/r8a77990-sysc.c
@@ -28,19 +28,6 @@ static struct rcar_sysc_area r8a77990_areas[] __initdata = {
{ "3dg-b",  0x100, 1, R8A77990_PD_3DG_B,R8A77990_PD_3DG_A },
 };
 
-static void __init rcar_sysc_fix_parent(struct rcar_sysc_area *areas,
-   unsigned int num_areas, u8 id,
-   int new_parent)
-{
-   unsigned int i;
-
-   for (i = 0; i < num_areas; i++)
-   if (areas[i].isr_bit == id) {
-   areas[i].parent = new_parent;
-   return;
-   }
-}
-
 /* Fixups for R-Car E3 ES1.0 revision */
 static const struct soc_device_attribute r8a77990[] __initconst = {
{ .soc_id = "r8a77990", .revision = "ES1.0" },
@@ -50,12 +37,10 @@ static const struct soc_device_attribute r8a77990[] 
__initconst = {
 static int __init r8a77990_sysc_init(void)
 {
if (soc_device_match(r8a77990)) {
-   rcar_sysc_fix_parent(r8a77990_areas,
-ARRAY_SIZE(r8a77990_areas),
-R8A77990_PD_3DG_A, R8A77990_PD_3DG_B);
-   rcar_sysc_fix_parent(r8a77990_areas,
-ARRAY_SIZE(r8a77990_areas),
-R8A77990_PD_3DG_B, R8A77990_PD_ALWAYS_ON);
+   /* Fix incorrect 3DG hierarchy */
+   swap(r8a77990_areas[7], r8a77990_areas[8]);
+   r8a77990_areas[7].parent = R8A77990_PD_ALWAYS_ON;
+   r8a77990_areas[8].parent = R8A77990_PD_3DG_B;
}
 
return 0;
-- 
2.11.0

[PATCH 29/34] ARM: dts: r8a7744: Add QSPI support

[Simon Horman]

From: Biju Das 

Add the DT node for the QSPI interface to the SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7744.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index bab78d43b5db..28fea2aaa0cf 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -703,6 +703,22 @@
status = "disabled";
};
 
+   qspi: spi@e6b1 {
+   compatible = "renesas,qspi-r8a7744", "renesas,qspi";
+   reg = <0 0xe6b1 0 0x2c>;
+   interrupts = ;
+   clocks = <&cpg CPG_MOD 917>;
+   dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+  <&dmac1 0x17>, <&dmac1 0x18>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+   num-cs = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   resets = <&cpg 917>;
+   status = "disabled";
+   };
+
scifa0: serial@e6c4 {
compatible = "renesas,scifa-r8a7744",
 "renesas,rcar-gen2-scifa", "renesas,scifa";
-- 
2.11.0

[PATCH 4/9] soc: renesas: r8a77980-sysc: Correct names of A2DP[01] power domains

[Simon Horman]

From: Geert Uytterhoeven 

The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018)
renamed the A2PD0 and A2DP0 power domains on R-Car V3H to A2DP0 resp.
A2DP1.

As these definitions are not yet used from DT, they can just be renamed.

Fixes: 7755b40d07a8dba7 ("dt-bindings: power: add R8A77980 SYSC power domain 
definitions")
Fixes: 41d6d8bd8ae94ca9 ("soc: renesas: rcar-sysc: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 drivers/soc/renesas/r8a77980-sysc.c   | 4 ++--
 include/dt-bindings/power/r8a77980-sysc.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/renesas/r8a77980-sysc.c 
b/drivers/soc/renesas/r8a77980-sysc.c
index 9265fb525ef3..dbb2621ce4e3 100644
--- a/drivers/soc/renesas/r8a77980-sysc.c
+++ b/drivers/soc/renesas/r8a77980-sysc.c
@@ -38,8 +38,8 @@ static const struct rcar_sysc_area r8a77980_areas[] 
__initconst = {
{ "a2sc2",  0x400, 8, R8A77980_PD_A2SC2,R8A77980_PD_A3IR },
{ "a2sc3",  0x400, 9, R8A77980_PD_A2SC3,R8A77980_PD_A3IR },
{ "a2sc4",  0x400, 10, R8A77980_PD_A2SC4,   R8A77980_PD_A3IR },
-   { "a2pd0",  0x400, 11, R8A77980_PD_A2PD0,   R8A77980_PD_A3IR },
-   { "a2pd1",  0x400, 12, R8A77980_PD_A2PD1,   R8A77980_PD_A3IR },
+   { "a2dp0",  0x400, 11, R8A77980_PD_A2DP0,   R8A77980_PD_A3IR },
+   { "a2dp1",  0x400, 12, R8A77980_PD_A2DP1,   R8A77980_PD_A3IR },
{ "a2cn",   0x400, 13, R8A77980_PD_A2CN,R8A77980_PD_A3IR },
{ "a3vip",  0x2c0, 0, R8A77980_PD_A3VIP,R8A77980_PD_ALWAYS_ON },
{ "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1,   R8A77980_PD_A3VIP },
diff --git a/include/dt-bindings/power/r8a77980-sysc.h 
b/include/dt-bindings/power/r8a77980-sysc.h
index 2c90c1237725..7bebe7e8dbdb 100644
--- a/include/dt-bindings/power/r8a77980-sysc.h
+++ b/include/dt-bindings/power/r8a77980-sysc.h
@@ -15,8 +15,8 @@
 #define R8A77980_PD_A2SC2  0
 #define R8A77980_PD_A2SC3  1
 #define R8A77980_PD_A2SC4  2
-#define R8A77980_PD_A2PD0  3
-#define R8A77980_PD_A2PD1  4
+#define R8A77980_PD_A2DP0  3
+#define R8A77980_PD_A2DP1  4
 #define R8A77980_PD_CA53_CPU0  5
 #define R8A77980_PD_CA53_CPU1  6
 #define R8A77980_PD_CA53_CPU2  7
-- 
2.11.0

[PATCH 4/9] ARM: shmobile: sh73a0: Remove obsolete inclusion of

[Simon Horman]

From: Geert Uytterhoeven 

As of commit 9a9863987bf7307f ("ARM: shmobile: Remove legacy SoC code
for SH-Mobile AG5"), this header file is no longer used.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/smp-sh73a0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c 
b/arch/arm/mach-shmobile/smp-sh73a0.c
index 9bc543faba96..0403aa8629dd 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -12,7 +12,6 @@
 #include 
 
 #include 
-#include 
 
 #include "common.h"
 #include "sh73a0.h"
-- 
2.11.0

[PATCH 1/9] arm64: renesas: Enable GPIOLIB to allow GPIO driver selection

[Simon Horman]

From: Takeshi Kihara 

The R-Car GPIO driver cannot be enabled when Renesas SoC's ARCH configs
(ARCH_RENESAS, ARCH_R8A7795, ARCH_R8A7796 and ARCH_R8A77965) are enabled
only.

As GPIOs are a critical resource for proper operation on Renesas
platforms, this patch selects GPIOLIB, just like is done for other SoC
vendors, and on Renesas arm32 SoCs.

Reported-by: Alexandru Gheorghe 
Signed-off-by: Takeshi Kihara 
[geert: Improve patch description]
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479334a4..2eb02734ae45 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -157,6 +157,7 @@ config ARCH_REALTEK
 
 config ARCH_RENESAS
bool "Renesas SoC Platforms"
+   select GPIOLIB
select PINCTRL
select PM
select PM_GENERIC_DOMAINS
-- 
2.11.0

[PATCH 7/9] ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/

[Simon Horman]

From: Geert Uytterhoeven 

For consistency with arm64, where vendors have a single Kconfig symbol
in arch/arm64/Kconfig.platforms.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/Kconfig | 126 ---
 drivers/soc/renesas/Kconfig| 148 ++---
 2 files changed, 139 insertions(+), 135 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 70c6f557f8cd..9b798c9dffe4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,31 +4,6 @@ config PM_RMOBILE
select PM
select PM_GENERIC_DOMAINS
 
-config ARCH_RCAR_GEN1
-   bool
-   select PM
-   select PM_GENERIC_DOMAINS
-   select RENESAS_INTC_IRQPIN
-   select SYS_SUPPORTS_SH_TMU
-
-config ARCH_RCAR_GEN2
-   bool
-   select HAVE_ARM_ARCH_TIMER
-   select PM
-   select PM_GENERIC_DOMAINS
-   select RENESAS_IRQC
-   select SYS_SUPPORTS_SH_CMT
-
-config ARCH_RMOBILE
-   bool
-   select PM_RMOBILE
-   select SYS_SUPPORTS_SH_CMT
-   select SYS_SUPPORTS_SH_TMU
-
-config ARCH_RZN1
-   bool
-   select ARM_AMBA
-
 menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
@@ -38,104 +13,3 @@ menuconfig ARCH_RENESAS
select PINCTRL
select SOC_BUS
select ZONE_DMA if ARM_LPAE
-
-if ARCH_RENESAS
-
-#comment "Renesas ARM SoCs System Type"
-
-config ARCH_EMEV2
-   bool "Emma Mobile EV2"
-   select HAVE_ARM_SCU if SMP
-   select SYS_SUPPORTS_EM_STI
-
-config ARCH_R7S72100
-   bool "RZ/A1H (R7S72100)"
-   select PM
-   select PM_GENERIC_DOMAINS
-   select SYS_SUPPORTS_SH_MTU2
-   select RENESAS_OSTM
-
-config ARCH_R7S9210
-   bool "RZ/A2 (R7S9210)"
-   select PM
-   select PM_GENERIC_DOMAINS
-   select RENESAS_OSTM
-
-config ARCH_R8A73A4
-   bool "R-Mobile APE6 (R8A73A40)"
-   select ARCH_RMOBILE
-   select ARM_ERRATA_798181 if SMP
-   select HAVE_ARM_ARCH_TIMER
-   select RENESAS_IRQC
-
-config ARCH_R8A7740
-   bool "R-Mobile A1 (R8A77400)"
-   select ARCH_RMOBILE
-   select RENESAS_INTC_IRQPIN
-
-config ARCH_R8A7743
-   bool "RZ/G1M (R8A77430)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7744
-   bool "RZ/G1N (R8A77440)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7745
-   bool "RZ/G1E (R8A77450)"
-   select ARCH_RCAR_GEN2
-
-config ARCH_R8A77470
-   bool "RZ/G1C (R8A77470)"
-   select ARCH_RCAR_GEN2
-
-config ARCH_R8A7778
-   bool "R-Car M1A (R8A77781)"
-   select ARCH_RCAR_GEN1
-
-config ARCH_R8A7779
-   bool "R-Car H1 (R8A77790)"
-   select HAVE_ARM_SCU if SMP
-   select HAVE_ARM_TWD if SMP
-   select ARCH_RCAR_GEN1
-
-config ARCH_R8A7790
-   bool "R-Car H2 (R8A77900)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-   select I2C
-
-config ARCH_R8A7791
-   bool "R-Car M2-W (R8A77910)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-   select I2C
-
-config ARCH_R8A7792
-   bool "R-Car V2H (R8A77920)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-
-config ARCH_R8A7793
-   bool "R-Car M2-N (R8A7793)"
-   select ARCH_RCAR_GEN2
-   select ARM_ERRATA_798181 if SMP
-   select I2C
-
-config ARCH_R8A7794
-   bool "R-Car E2 (R8A77940)"
-   select ARCH_RCAR_GEN2
-
-config ARCH_R9A06G032
-   bool "RZ/N1D (R9A06G032)"
-   select ARCH_RZN1
-
-config ARCH_SH73A0
-   bool "SH-Mobile AG5 (R8A73A00)"
-   select ARCH_RMOBILE
-   select HAVE_ARM_SCU if SMP
-   select HAVE_ARM_TWD if SMP
-   select RENESAS_INTC_IRQPIN
-endif
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 2f5bc5a6ae2b..fe7f58616cdd 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,18 +3,26 @@ config SOC_RENESAS
bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
-   select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2
-   select SYSC_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
-   select SYSC_R8A7745 if ARCH_R8A7745
-   select SYSC_R8A77470 if ARCH_R8A77470
-   select SYSC_R8A7779 if ARCH_R8A7779
-   select SYSC_R8A7790 if ARCH_R8A7790
-   select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
-   select SYSC_R8A7792 if ARCH_R8A7792
-   select SYSC_R8A7794 if ARCH_R8A7794
 
 if SOC_RENESAS
 
+config ARCH_RCAR_GEN1
+   bool
+   select PM
+   select PM_GENERIC_DOMAINS
+   select RENESAS_INTC_IRQPIN
+   select RST_RCAR
+   select SYS_SUPPORTS_SH_TMU
+
+config ARCH_RCAR_GEN2
+   bool
+   select HAVE_ARM_ARCH_TIMER
+   select PM
+   select PM_GENERIC_DOMAINS
+

[GIT PULL] Renesas ARM Based SoC Updates for v4.21

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC updates for v4.21.


Usually I separate SoC changes for ARM and arm64 into separate branches.
On this occasion I have applied them to a single branch and pull request.
The reason for this is that moving SoC Konfig symbols for both ARM and
arm64 creates a dependency and a combined branch is a clean way to resolve
this.

If separate branches are required then I propose deferring the movement
of ARM (but not arm64) SoC Kconfig symbols to v4.22.


The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:

  Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-soc-for-v4.21

for you to fetch changes up to 2ed29e15e4b2500ae78de658a18f4482e7ac288b:

  ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/ (2018-11-30 
11:29:11 +0100)


Renesas ARM Based SoC Updates for v4.21

* pm-rmobile driver
  - Move to drivers/soc/renesas/
  - Clean up struct rmobile_pm_domain
* Renesas SoC Kconfig Symbols
  - Move symbols for ARM and SoCs to drivers/soc/renesas/
  - Hide ARCH_RZN1 to improve consistency
* SH-Mobile AG5 (sh73a0) SoC: Remove obsolete inclusion of 
* Restrict TWD and SCU to Renesas ARM based SoCs where they are present
* Enable GPIOLIB on Renesas arm64 based SoCs to allow GPIO driver selection


Geert Uytterhoeven (8):
  ARM: shmobile: Restrict SCU support to SoCs that have it
  ARM: shmobile: Restrict TWD support to SoCs that have it
  ARM: shmobile: sh73a0: Remove obsolete inclusion of 
  ARM: shmobile: Hide ARCH_RZN1 to improve consistency
  arm64: renesas: Move SoC Kconfig symbols to drivers/soc/renesas/
  ARM: shmobile: Move SoC Kconfig symbols to drivers/soc/renesas/
  ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domain
  ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/

Takeshi Kihara (1):
  arm64: renesas: Enable GPIOLIB to allow GPIO driver selection

 arch/arm/mach-shmobile/Kconfig | 129 ---
 arch/arm/mach-shmobile/Makefile|   1 -
 arch/arm/mach-shmobile/pm-rmobile.h|  22 --
 arch/arm/mach-shmobile/smp-sh73a0.c|   1 -
 arch/arm64/Kconfig.platforms   |  60 +
 drivers/soc/renesas/Kconfig| 241 +++--
 drivers/soc/renesas/Makefile   |   1 +
 .../soc/renesas/rmobile-sysc.c |  37 ++--
 8 files changed, 240 insertions(+), 252 deletions(-)
 delete mode 100644 arch/arm/mach-shmobile/pm-rmobile.h
 rename arch/arm/mach-shmobile/pm-rmobile.c => 
drivers/soc/renesas/rmobile-sysc.c (93%)

[PATCH 2/9] ARM: shmobile: Restrict SCU support to SoCs that have it

[Simon Horman]

From: Geert Uytterhoeven 

Currently support for the ARM Cortex-A9 Snoop Control Unit is included
unconditionally, while only Renesas multicore Cortex-A9 SoCs have this
kind of SCU.

This decreases kernel image size by ca. 300 bytes on SoCs without such
an SCU.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index b100c26a858f..32f8297d993a 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -30,7 +30,6 @@ menuconfig ARCH_RENESAS
depends on ARCH_MULTI_V7 && MMU
select ARM_GIC
select GPIOLIB
-   select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
@@ -43,6 +42,7 @@ if ARCH_RENESAS
 
 config ARCH_EMEV2
bool "Emma Mobile EV2"
+   select HAVE_ARM_SCU if SMP
select SYS_SUPPORTS_EM_STI
 
 config ARCH_R7S72100
@@ -94,6 +94,7 @@ config ARCH_R8A7778
 
 config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
+   select HAVE_ARM_SCU if SMP
select ARCH_RCAR_GEN1
 
 config ARCH_R8A7790
@@ -135,5 +136,6 @@ config ARCH_RZN1
 config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
+   select HAVE_ARM_SCU if SMP
select RENESAS_INTC_IRQPIN
 endif
-- 
2.11.0

[PATCH 8/9] ARM: shmobile: R-Mobile: Clean up struct rmobile_pm_domain

[Simon Horman]

From: Geert Uytterhoeven 

Commit 59b89af1d5551c12 ("ARM: shmobile: sh7372: Remove Legacy C
SoC code") removed the last user of the rmobile_pm_domain.resume()
callback.

Commit 44d88c754e57a6d9 ("ARM: shmobile: Remove legacy SoC code
for R-Mobile A1") removed the last user of the rmobile_pm_domain.no_debug
flag and of the "pm-rmobile.h" header file (outside the actual driver).

Hence remove no longer used rmobile_pm_domain members, and absorb the
header file into the driver.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/pm-rmobile.c | 37 ++---
 arch/arm/mach-shmobile/pm-rmobile.h | 22 --
 2 files changed, 18 insertions(+), 41 deletions(-)
 delete mode 100644 arch/arm/mach-shmobile/pm-rmobile.h

diff --git a/arch/arm/mach-shmobile/pm-rmobile.c 
b/arch/arm/mach-shmobile/pm-rmobile.c
index c6a11b5ec6db..421ae1c887d8 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -18,12 +18,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
 
-#include "pm-rmobile.h"
-
 /* SYSC */
 #define SPDCR  0x08/* SYS Power Down Control Register */
 #define SWUCR  0x14/* SYS Wakeup Control Register */
@@ -32,6 +31,14 @@
 #define PSTR_RETRIES   100
 #define PSTR_DELAY_US  10
 
+struct rmobile_pm_domain {
+   struct generic_pm_domain genpd;
+   struct dev_power_governor *gov;
+   int (*suspend)(void);
+   void __iomem *base;
+   unsigned int bit_shift;
+};
+
 static inline
 struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
 {
@@ -65,16 +72,13 @@ static int rmobile_pd_power_down(struct generic_pm_domain 
*genpd)
}
}
 
-   if (!rmobile_pd->no_debug)
-   pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
-genpd->name, mask,
-__raw_readl(rmobile_pd->base + PSTR));
+   pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask,
+__raw_readl(rmobile_pd->base + PSTR));
 
return 0;
 }
 
-static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
-bool do_resume)
+static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd)
 {
unsigned int mask;
unsigned int retry_count;
@@ -85,7 +89,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain 
*rmobile_pd,
 
mask = BIT(rmobile_pd->bit_shift);
if (__raw_readl(rmobile_pd->base + PSTR) & mask)
-   goto out;
+   return ret;
 
__raw_writel(mask, rmobile_pd->base + SWUCR);
 
@@ -100,21 +104,16 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain 
*rmobile_pd,
if (!retry_count)
ret = -EIO;
 
-   if (!rmobile_pd->no_debug)
-   pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
-rmobile_pd->genpd.name, mask,
-__raw_readl(rmobile_pd->base + PSTR));
-
-out:
-   if (ret == 0 && rmobile_pd->resume && do_resume)
-   rmobile_pd->resume();
+   pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
+rmobile_pd->genpd.name, mask,
+__raw_readl(rmobile_pd->base + PSTR));
 
return ret;
 }
 
 static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
 {
-   return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
+   return __rmobile_pd_power_up(to_rmobile_pd(genpd));
 }
 
 static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
@@ -127,7 +126,7 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain 
*rmobile_pd)
genpd->power_on = rmobile_pd_power_up;
genpd->attach_dev   = cpg_mstp_attach_dev;
genpd->detach_dev   = cpg_mstp_detach_dev;
-   __rmobile_pd_power_up(rmobile_pd, false);
+   __rmobile_pd_power_up(rmobile_pd);
pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
 }
 
diff --git a/arch/arm/mach-shmobile/pm-rmobile.h 
b/arch/arm/mach-shmobile/pm-rmobile.h
deleted file mode 100644
index 69f839259b09..
--- a/arch/arm/mach-shmobile/pm-rmobile.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * Kuninori Morimoto 
- */
-#ifndef PM_RMOBILE_H
-#define PM_RMOBILE_H
-
-#include 
-
-struct rmobile_pm_domain {
-   struct generic_pm_domain genpd;
-   struct dev_power_governor *gov;
-   int (*suspend)(void);
-   void (*resume)(void);
-   void __iomem *base;
-   unsigned int bit_shift;
-   bool no_debug;
-};
-
-#endif /* PM_RMOBILE_H */
-- 
2.11.0

[PATCH 9/9] ARM: shmobile: R-Mobile: Move pm-rmobile to drivers/soc/renesas/

[Simon Horman]

From: Geert Uytterhoeven 

The pm-rmobile driver is really a driver for the System Controller
(SYSC) found in R-Mobile SoCs.  An equivalent driver for R-Car SoCs is
already located under drivers/soc/renesas/.

Hence move the pm-rmobile driver from arch/arm/mach-shmobile/ to
drivers/soc/renesas/, and rename it to rmobile-sysc.

Enable compile-testing on non-ARM and non-R-Mobile SoCs.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/Kconfig | 5 -
 arch/arm/mach-shmobile/Makefile| 1 -
 drivers/soc/renesas/Kconfig| 7 ++-
 drivers/soc/renesas/Makefile   | 1 +
 .../pm-rmobile.c => drivers/soc/renesas/rmobile-sysc.c | 0
 5 files changed, 7 insertions(+), 7 deletions(-)
 rename arch/arm/mach-shmobile/pm-rmobile.c => 
drivers/soc/renesas/rmobile-sysc.c (100%)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9b798c9dffe4..3683d6f10973 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,9 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
-config PM_RMOBILE
-   bool
-   select PM
-   select PM_GENERIC_DOMAINS
-
 menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5591646cb9bb..f7bf17b7abae 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -35,7 +35,6 @@ smp-$(CONFIG_ARCH_EMEV2)  += smp-emev2.o headsmp-scu.o 
platsmp-scu.o
 
 # PM objects
 obj-$(CONFIG_SUSPEND)  += suspend.o
-obj-$(CONFIG_PM_RMOBILE)   += pm-rmobile.o
 obj-$(CONFIG_ARCH_RCAR_GEN2)   += pm-rcar-gen2.o
 
 # Framework support
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fe7f58616cdd..4d8012e1205c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -34,9 +34,11 @@ config ARCH_RCAR_GEN3
 
 config ARCH_RMOBILE
bool
-   select PM_RMOBILE
+   select PM
+   select PM_GENERIC_DOMAINS
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
+   select SYSC_RMOBILE
 
 config ARCH_RZN1
bool
@@ -297,4 +299,7 @@ config RST_RCAR
 config SYSC_RCAR
bool "R-Car System Controller support" if COMPILE_TEST
 
+config SYSC_RMOBILE
+   bool "R-Mobile System Controller support" if COMPILE_TEST
+
 endif # SOC_RENESAS
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 3bdd7dbc38a9..00764d5a60b3 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -27,3 +27,4 @@ endif
 # Family
 obj-$(CONFIG_RST_RCAR) += rcar-rst.o
 obj-$(CONFIG_SYSC_RCAR)+= rcar-sysc.o
+obj-$(CONFIG_SYSC_RMOBILE) += rmobile-sysc.o
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c 
b/drivers/soc/renesas/rmobile-sysc.c
similarity index 100%
rename from arch/arm/mach-shmobile/pm-rmobile.c
rename to drivers/soc/renesas/rmobile-sysc.c
-- 
2.11.0

[PATCH 6/9] arm64: renesas: Move SoC Kconfig symbols to drivers/soc/renesas/

[Simon Horman]

From: Geert Uytterhoeven 

arch/arm64/Kconfig.platforms has SoC-specific Kconfig symbols for
Renesas SoCs, while other vendors have only a single Kconfig symbol.

Increase consistency with other vendors by moving the SoC-specific
Kconfig symbols to drivers/soc/renesas/Kconfig.

Increase consistency with R-Car Gen1 and Gen2 SoCs on arm32 by
introducing a family-specific Kconfig symbol for R-Car Gen3
(ARCH_RCAR_GEN3), which enables family-specific hardware features.
While so far only a single family (R-Car Gen3 and derivatives) of
Renesas arm64 SoCs is supported by Linux, this will make it easier
to add support for other SoC families later.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/Kconfig.platforms | 59 -
 drivers/soc/renesas/Kconfig  | 90 +---
 2 files changed, 77 insertions(+), 72 deletions(-)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2eb02734ae45..28f052185eb6 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -159,69 +159,10 @@ config ARCH_RENESAS
bool "Renesas SoC Platforms"
select GPIOLIB
select PINCTRL
-   select PM
-   select PM_GENERIC_DOMAINS
-   select RENESAS_IRQC
select SOC_BUS
-   select SYS_SUPPORTS_SH_CMT
-   select SYS_SUPPORTS_SH_TMU
help
  This enables support for the ARMv8 based Renesas SoCs.
 
-config ARCH_R8A774A1
-   bool "Renesas RZ/G2M SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas RZ/G2M SoC.
-
-config ARCH_R8A774C0
-   bool "Renesas RZ/G2E SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas RZ/G2E SoC.
-
-config ARCH_R8A7795
-   bool "Renesas R-Car H3 SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car H3 SoC.
-
-config ARCH_R8A7796
-   bool "Renesas R-Car M3-W SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car M3-W SoC.
-
-config ARCH_R8A77965
-   bool "Renesas R-Car M3-N SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car M3-N SoC.
-
-config ARCH_R8A77970
-   bool "Renesas R-Car V3M SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car V3M SoC.
-
-config ARCH_R8A77980
-   bool "Renesas R-Car V3H SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car V3H SoC.
-
-config ARCH_R8A77990
-   bool "Renesas R-Car E3 SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car E3 SoC.
-
-config ARCH_R8A77995
-   bool "Renesas R-Car D3 SoC Platform"
-   depends on ARCH_RENESAS
-   help
- This enables support for the Renesas R-Car D3 SoC.
-
 config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 407f02c80e8b..2f5bc5a6ae2b 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -3,30 +3,94 @@ config SOC_RENESAS
bool "Renesas SoC driver support" if COMPILE_TEST && !ARCH_RENESAS
default y if ARCH_RENESAS
select SOC_BUS
-   select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \
-  ARCH_R8A774A1 || ARCH_R8A774C0 || ARCH_R8A7795 || \
-  ARCH_R8A7796 || ARCH_R8A77965 || ARCH_R8A77970 || \
-  ARCH_R8A77980 || ARCH_R8A77990 || ARCH_R8A77995
+   select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2
select SYSC_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
select SYSC_R8A7745 if ARCH_R8A7745
select SYSC_R8A77470 if ARCH_R8A77470
-   select SYSC_R8A774A1 if ARCH_R8A774A1
-   select SYSC_R8A774C0 if ARCH_R8A774C0
select SYSC_R8A7779 if ARCH_R8A7779
select SYSC_R8A7790 if ARCH_R8A7790
select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
select SYSC_R8A7792 if ARCH_R8A7792
select SYSC_R8A7794 if ARCH_R8A7794
-   select SYSC_R8A7795 if ARCH_R8A7795
-   select SYSC_R8A7796 if ARCH_R8A7796
-   select SYSC_R8A77965 if ARCH_R8A77965
-   select SYSC_R8A77970 if ARCH_R8A77970
-   select SYSC_R8A77980 if ARCH_R8A77980
-   select SYSC_R8A77990 if ARCH_R8A77990
-   select SYSC_R8A77995 if ARCH_R8A77995
 
 if SOC_RENESAS
 
+config ARCH_RCAR_GEN3
+   bool
+   select PM
+   select PM_GENERIC_DOMAINS
+   select RENESAS_IRQC
+   select RST_RCAR
+   select SYS_SUPPORTS_SH_CMT
+   select SYS_SUPPORTS_SH_TMU
+
+if ARM64
+
+config ARCH_R8A774A1
+   bool "Renesas RZ/G2M SoC Platform"
+   select ARCH_RCAR_GEN3
+   s

[PATCH 5/9] ARM: shmobile: Hide ARCH_RZN1 to improve consistency

[Simon Horman]

From: Geert Uytterhoeven 

Unlike all other family-specific Kconfig symbols for Renesas ARM SoCs,
ARCH_RZN1 is user-visible.  As this symbol is already selected by the
SoC-specific ARCH_R9A06G032 symbol, there is no need for that.

Hide ARCH_RZN1 from the user, and move it up, where all other
family-specific Kconfig symbols live.  Drop the select of CPU_V7, as
this is already implied by the dependency of ARCH_RENESAS on
ARCH_MULTI_V7.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/Kconfig | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a35eb5913dfd..70c6f557f8cd 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -25,6 +25,10 @@ config ARCH_RMOBILE
select SYS_SUPPORTS_SH_CMT
select SYS_SUPPORTS_SH_TMU
 
+config ARCH_RZN1
+   bool
+   select ARM_AMBA
+
 menuconfig ARCH_RENESAS
bool "Renesas ARM SoCs"
depends on ARCH_MULTI_V7 && MMU
@@ -128,11 +132,6 @@ config ARCH_R9A06G032
bool "RZ/N1D (R9A06G032)"
select ARCH_RZN1
 
-config ARCH_RZN1
-   bool "RZ/N1 (R9A06G0xx) Family"
-   select ARM_AMBA
-   select CPU_V7
-
 config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
-- 
2.11.0

[PATCH 3/9] ARM: shmobile: Restrict TWD support to SoCs that have it

[Simon Horman]

From: Geert Uytterhoeven 

Currently support for the ARM Timer and Watchdog Unit is included
unconditionally, while only some Renesas multicore Cortex-A9 SoCs have
a TWD.

This decreases kernel image size by ca. 2 KiB on SoCs without a TWD.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/mach-shmobile/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 32f8297d993a..a35eb5913dfd 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -30,7 +30,6 @@ menuconfig ARCH_RENESAS
depends on ARCH_MULTI_V7 && MMU
select ARM_GIC
select GPIOLIB
-   select HAVE_ARM_TWD if SMP
select NO_IOPORT_MAP
select PINCTRL
select SOC_BUS
@@ -95,6 +94,7 @@ config ARCH_R8A7778
 config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
select HAVE_ARM_SCU if SMP
+   select HAVE_ARM_TWD if SMP
select ARCH_RCAR_GEN1
 
 config ARCH_R8A7790
@@ -137,5 +137,6 @@ config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select HAVE_ARM_SCU if SMP
+   select HAVE_ARM_TWD if SMP
select RENESAS_INTC_IRQPIN
 endif
-- 
2.11.0

Re: phandles using absolute paths in DT overlays

[David Gibson]

On Thu, Dec 06, 2018 at 01:56:45PM +0100, Geert Uytterhoeven wrote:
> Hi,
> 
> Some early revisions of SoCs may have hardware bugs that need to be
> fixed up in DT.  Currently we are handling this by including DTS files
> and fixing up nodes and properties, to create different DTB files for
> different SoC revisons (see arch/arm64/boot/dts/renesas/*es1*).
> 
> As an alternative, I'm envisioning the use of DT overlays and the
> fdtoverlay tool, in the hope of simplifying the generation of DTBs for
> the various SoC/board combinations.
> 
> Ideally, such DTBs would not contain symbols, to avoid inflating DTB
> size.  Hence if fixup overlays would not contain symbolic references,
> there would be no need for symbols.
> 
> For anchors, the "&{/path/to/node@address}" syntax is working fine.
> For phandles, while documented on
> https://elinux.org/Device_Tree_Mysteries, and while working fine for the
> non-overlay case, dtc seems to have issues interpreting the DTB:
> 
> $ scripts/dtc/dtc -I dtb -O dts my.dtb  | less
> : ERROR (property_name_chars):
> /__fixups__:/path/to/node@deadbeef: Bad character '/' in property
> name
> ERROR: Input tree has errors, aborting (use -f to force output)
> 
> With -f, the fixup generated seems to contain the expected value, though:
> 
> __fixups__ {
> /path/to/node@deadbeef = "/fragment@0/__overlay__:power-domains:0";
> };
> 
> When using ftdoverlay, the situation is worse:
> 
> Failed to apply my.dtb (-1)
> 
> Are these known issues?

Unfortunately, this can't work with the current overlay format.  We
have a specific syntax to allow the target of an overlay fragment to
specified as a path, but phandle references by path won't work.

The problem is that the encoding of the fixups node has the fixup
target as a property name, and as the error says '/' is an illegal
character in property names - for a bunch of good reasons, so we can't
just go and remove that restriction.

So to allow this we'd need to come up with a different encoding for
path-targeted fixups and add support for it in the various pieces of
the chain.

One way to do that would be to entirely rework the overlay format to
something more sensible, which would have a number of other benefits.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


signature.asc
Description: PGP signature

Re: [PATCH 4/4] soc: renesas: rcar-sysc: Fix power domain control after system resume

[Geert Uytterhoeven]

Hi Simon,

On Wed, Dec 5, 2018 at 10:21 PM Simon Horman  wrote:
> On Wed, Dec 05, 2018 at 04:39:45PM +0100, Geert Uytterhoeven wrote:
> > To control power to a power domain, the System Controller (SYSC) needs
> > the corresponding interrupt source to be enabled, but masked, to prevent
> > the CPU from receiving it.
> >
> > Currently this is handled in the driver's probe() routine, and set up
> > for every domain present, even if it will not be controlled directly by
> > SYSC (CPU domains are powered through the APMU on R-Car Gen2 and later).
> >
> > On R-Car Gen3, PSCI powers down the SoC during system suspend, thus
> > loosing any configured interrupt state.  Hence after system resume, power
> > domains not controlled through the APMU (e.g. A3IR, A3VC, A3VP) fail to
> > power up.
>
> I corrected the spelling of losing when applying this patch.

Checkpatch complained about that as well, so I did some investigation, and
decided to keep it... Was I wrong?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

[Marek Vasut]

On 12/06/2018 06:56 AM, masonccy...@mxic.com.tw wrote:
> Hi Geert,
> 
>> "Geert Uytterhoeven" 
>> 2018/12/05 下午 05:06
>>
>> To
>>
>> masonccy...@mxic.com.tw,
>>
>> cc
>>
>> "Mark Brown" , "Marek Vasut"
>> , "Linux Kernel Mailing List" > ker...@vger.kernel.org>, "linux-spi" ,
>> "Boris Brezillon" , "Linux-Renesas"
>> , "Geert Uytterhoeven" > +rene...@glider.be>, julie...@mxic.com.tw, "Simon Horman"
>> , zhengxu...@mxic.com.tw
>>
>> Subject
>>
>> Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver
>>
>> Hi Mason,
>>
>> On Mon, Dec 3, 2018 at 10:19 AM Mason Yang 
> wrote:
>> > Add a driver for Renesas R-Car Gen3 RPC SPI controller.
>> >
>> > Signed-off-by: Mason Yang 
>>
>> Thanks for your patch!
>>
>> > --- a/drivers/spi/Kconfig
>> > +++ b/drivers/spi/Kconfig
>> > @@ -528,6 +528,12 @@ config SPI_RSPI
>> >         help
>> >           SPI driver for Renesas RSPI and QSPI blocks.
>> >
>> > +config SPI_RENESAS_RPC
>> > +       tristate "Renesas R-Car Gen3 RPC SPI controller"
>> > +       depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
>>
>> So this driver is intended for SuperH SoCs, too?
>> If not, please drop the dependency.
>>
> 
> okay, I will drop "SUPERH".
> 
>> > --- /dev/null
>> > +++ b/drivers/spi/spi-renesas-rpc.c
>>
>> > +#ifdef CONFIG_RESET_CONTROLLER
>> > +static int rpc_spi_do_reset(struct rpc_spi *rpc)
>>
>> What's the purpose of the reset routine?
> 
> in case RPC xfer is time-out due to something wrong in RPC module,
> as Marek comments.
> 
>> Given the #ifdef, is it optional or required?
>>
>> > +{
>> > +       int i, ret;
>> > +
>> > +       ret = reset_control_reset(rpc->rstc);
>> > +       if (ret)
>> > +               return ret;
>> > +
>> > +       for (i = 0; i < LOOP_TIMEOUT; i++) {
>> > +               ret = reset_control_status(rpc->rstc);
>> > +               if (ret == 0)
>> > +                       return 0;
>> > +               usleep_range(0, 1);
>> > +       }
>>
>> Why do you need this loop?
>> The delay in cpg_mssr_reset() should be sufficient.
>>
> 
> yup, I know there is already 35 us delay in cpg_mssr_reset().
> If you think reset_control_status()checking is not necessary,
> I will drop it.
> 
>> > +
>> > +       return -ETIMEDOUT;
>> > +}
>> > +#else
>> > +static int rpc_spi_do_reset(struct rpc_spi *rpc)
>> > +{
>> > +       return -ETIMEDOUT;
>> > +}
>> > +#endif
>>
>> > +static int rpc_spi_transfer_one_message(struct spi_master *master,
>> > +                                       struct spi_message *msg)
>> > +{
>> > +       struct rpc_spi *rpc = spi_master_get_devdata(master);
>> > +       struct spi_transfer *t;
>> > +       int ret;
>> > +
>> > +       rpc_spi_transfer_setup(rpc, msg);
>> > +
>> > +       list_for_each_entry(t, &msg->transfers, transfer_list) {
>> > +               if (!list_is_last(&t->transfer_list, &msg->transfers))
>> > +                       continue;
>> > +               ret = rpc_spi_xfer_message(rpc, t);
>>
>> rpc_spi_xfer_message() sounds like a bad name to me, given it operates
>> on a transfer, not on a message.
>>
> 
> Because RPC send a entire SPI message at one time, not separately,
> that is the 1'st transfer is for command, the 2'nd transfer is for
> address/data
> and so on.
> The reason is CS# pin control restriction in RPC HW module.
> 
> 
>> > +               if (ret)
>> > +                       goto out;
>> > +       }
>> > +
>> > +       msg->status = 0;
>> > +       msg->actual_length = rpc->totalxferlen;
>> > +out:
>> > +       spi_finalize_current_message(master);
>> > +       return 0;
>> > +}
>>
>>
>> > +static int rpc_spi_probe(struct platform_device *pdev)
>> > +{
>>
>> > +       rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
>> > +       if (IS_ERR(rpc->rstc))
>> > +               return PTR_ERR(rpc->rstc);
>>
>> This will return an error if CONFIG_RESET_CONTROLLER is not set, hence
>> the #ifdef above is moot.
>>
> 
> You are right.
> so, I should do
> Option 1: remove #CONFIG_RESET_CONTROLLER
> Option 2: add #CONFIG_RESET_CONTROLLER for
> devm_reset_control_get_exclusive()
> 
> please comments on it, thanks.
> 
> 
>> > +
>> > +       pm_runtime_enable(&pdev->dev);
>> > +       master->auto_runtime_pm = true;
>> > +
>> > +       master->num_chipselect = 1;
>> > +       master->mem_ops = &rpc_spi_mem_ops;
>> > +       master->transfer_one_message = rpc_spi_transfer_one_message;
>>
>> Is there any reason you cannot use the standard
>> spi_transfer_one_message, i.e. provide spi_controller.transfer_one()
>> instead of spi_controller.transfer_one_message()?
>>
> 
> It seems there is a RPC HW restriction in CS# pin control.
> Therefore, it can't send the 1'st spi-transfer for command and then
> keeping CS# pin goes low for the 2'nd spi-transfer for address/data and
> so on.

Isn't register DRCR bit SSLN/SSLE exactly for this purpose ?

-- 
Best regards,
Marek Vasut

Re: [PATCH 0/4] soc: renesas: rcar-sysc: Miscellaneous fixes and cleanups

[Geert Uytterhoeven]

On Wed, Dec 5, 2018 at 4:39 PM Geert Uytterhoeven
 wrote:
> This series (against renesas-devel-20181204-v4.20-rc5) contains
> miscellaneous fixes and cleanups for the R-Car SYSC driver.
>
> This has been tested on R-Car Gen2 (H2 and M2-W) and R-Car Gen3 (H3
> ES1.0, H3 ES2.0, M3-W, M3-N, D3, E3, and V3M) (without 3DG).
>
> This not been tested on R-Car H1 and R-Car V3H.

Now tested on R-Car H1 (Marzen), with no ill effects on secondary CPU
boot and CPU hotplug.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

[Marek Vasut]

On 12/06/2018 08:30 AM, masonccy...@mxic.com.tw wrote:
> Hi Marek,

Hi,

>> >> Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller
> driver
>> >>
>> >> On 12/03/2018 10:18 AM, Mason Yang wrote:
>> >> > Add a driver for Renesas R-Car Gen3 RPC SPI controller.
>> >> >
>> >> > Signed-off-by: Mason Yang 
>> >>
>> >> What changed in this V2 ?
>> >>
>> >> [...]
>> >
>> > see some description in [PATH v2 0/2]
>>
>> I don't see any V2: list there.
>>
> 
> including
> 1) remove RPC clock enable/dis-able control,
> 2) patch run time PM,
> 3) add RPC module software reset,
> 4) add regmap,
> 5) other coding style and so on.

Please include a detailed changelog in each subsequent patch series.

>> >> > +static int rpc_spi_io_xfer(struct rpc_spi *rpc,
>> >> > +            const void *tx_buf, void *rx_buf)
>> >> > +{
>> >> > +   u32 smenr, smcr, data, pos = 0;
>> >> > +   int ret = 0;
>> >> > +
>> >> > +   regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD |
> RPC_CMNCR_SFDE |
>> >> > +              RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
>> >> > +              RPC_CMNCR_BSZ(0));
>> >> > +   regmap_write(rpc->regmap, RPC_SMDRENR, 0x0);
>> >> > +   regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd);
>> >> > +   regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy);
>> >> > +   regmap_write(rpc->regmap, RPC_SMADR, rpc->addr);
>> >> > +
>> >> > +   if (tx_buf) {
>> >> > +      smenr = rpc->smenr;
>> >> > +
>> >> > +      while (pos < rpc->xferlen) {
>> >> > +         u32 nbytes = rpc->xferlen  - pos;
>> >> > +
>> >> > +         regmap_write(rpc->regmap, RPC_SMWDR0,
>> >> > +                 *(u32 *)(tx_buf + pos));
>> >>
>> >> *(u32 *) cast is probably not needed , fix casts globally.
>> >
>> > It must have it!
>>
>> Why ?
> 
> Get a compiler warning due to tx_bug is void *, as Geert replied.

The compiler warning is usually an indication that this is something to
check, not silence with a type cast.

> Using get_unaligned(), patched code would be
> -
> regmap_write(rpc->regmap, RPC_SMWDR0,
>                  get_unaligned((u32 *)(tx_buf + pos)));                
> 

Do you need the cast if you use get_unaligned() ?

>> >> > +         rpc->xferlen = *(u32 *)len;
>> >> > +         rpc->totalxferlen += *(u32 *)len;
>> >> > +      } else {
>> >> > +         rpc->smenr |= RPC_SMENR_SPIDE(rpc_bits_xfer
>> >> > +               (op->data.nbytes)) | RPC_SMENR_SPIDB
>> >> > +               (fls(op->data.buswidth >> 1));
>> >>
>> >> Drop parenthesis around fls()
>> >
>> > ?
>> > no way.
>>
>> I would really appreciate it if you could explain things instead.
>>
>> Geert already did so, by pointing out this is a confusing code
>> formatting problem and how it should be fixed, so no need to repeat
>> that. But I hope you understand how that sort of explanation is far more
>> valuable than "no way" kind of reply.
> 
> okay, understood.
> 
> 
>> >> > +
>> >> > +   xfercnt = xferpos;
>> >> > +   rpc->xferlen = xfer[--xferpos].len;
>> >> > +   rpc->cmd = RPC_SMCMR_CMD(((u8 *)xfer[0].tx_buf)[0]);
>> >>
>> >> Is the cast needed ?
>> >
>> > yes!
>>
>> Why ?
> 
> Get a compiler warning due to tx_bug is void *, as Geert replied.

> Using get_unaligned(), patched code would be
> ---
>  rpc->cmd = RPC_SMCMR_CMD(get_unaligned((u8 *)xfer[0].tx_buf));
> 

See above

>> >> > +   rpc->smenr = RPC_SMENR_CDE | RPC_SMENR_CDB(fls(xfer[0].tx_nbits
>> >>> 1));
>> >> > +   rpc->addr = 0;
>> >> > +
>> >> > +   if (xfercnt > 2 && xfer[1].len && xfer[1].tx_buf) {
>> >> > +      rpc->smenr |= RPC_SMENR_ADB(fls(xfer[1].tx_nbits >> 1));
>> >> > +      for (i = 0; i < xfer[1].len; i++)
>> >> > +         rpc->addr |= (u32)((u8 *)xfer[1].tx_buf)[i]
>> >> > +               << (8 * (xfer[1].len - i - 1));
>> >> > +
>> >> > +      if (xfer[1].len == 4)
>> >> > +         rpc->smenr |= RPC_SMENR_ADE(0xf);
>> >> > +      else
>> >> > +         rpc->smenr |= RPC_SMENR_ADE(0x7);
>> >> > +   }
>> >> > +
>> >> > +   switch (xfercnt) {
>> >> > +   case 2:
>> >> > +      if (xfer[1].rx_buf) {
>> >> > +         rpc->smenr |= RPC_SMENR_SPIDE(rpc_bits_xfer
>> >> > +                  (xfer[1].len)) | RPC_SMENR_SPIDB(fls
>> >> > +                  (xfer[1].rx_nbits >> 1));
>> >> > +      } else if (xfer[1].tx_buf) {
>> >> > +         rpc->smenr |= RPC_SMENR_SPIDE(rpc_bits_xfer
>> >> > +                  (xfer[1].len)) | RPC_SMENR_SPIDB(fls
>> >> > +                  (xfer[1].tx_nbits >> 1));
>> >> > +      }
>> >> > +      break;
>> >> > +
>> >> > +   case 3:
>> >> > +      if (xfer[2].len && xfer[2].rx_buf && !xfer[2].tx_buf) {
>> >> > +         rpc->smenr |= RPC_SMENR_SPIDE(rpc_bits_xfer
>> >> > +                  (xfer[2].len)) | RPC_SMENR_SPIDB(fls
>> >> > +                  (xfer[2].rx_nbits >> 1));
>> >>
>> >> It seems this SMENR pattern repeats i

Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

[Geert Uytterhoeven]

Hi Mason,

On Thu, Dec 6, 2018 at 8:31 AM  wrote:
> > >> Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver
> > >>
> > >> On 12/03/2018 10:18 AM, Mason Yang wrote:
> > >> > Add a driver for Renesas R-Car Gen3 RPC SPI controller.
> > >> >
> > >> > Signed-off-by: Mason Yang 

> > >> > +   xfercnt = xferpos;
> > >> > +   rpc->xferlen = xfer[--xferpos].len;
> > >> > +   rpc->cmd = RPC_SMCMR_CMD(((u8 *)xfer[0].tx_buf)[0]);
> > >>
> > >> Is the cast needed ?
> > >
> > > yes!
> >
> > Why ?
>
> Get a compiler warning due to tx_bug is void *, as Geert replied.
>
> Using get_unaligned(), patched code would be
> ---
>  rpc->cmd = RPC_SMCMR_CMD(get_unaligned((u8 *)xfer[0].tx_buf));
> 

Using get_unaligned(0 is a bit strange for accessing a single byte quantity.
Please keep the normal pointer dereference (including the cast).

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

[Marek Vasut]

On 12/06/2018 10:12 AM, Geert Uytterhoeven wrote:
> Hi Mason,
> 
> On Thu, Dec 6, 2018 at 8:31 AM  wrote:
> Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver
>
> On 12/03/2018 10:18 AM, Mason Yang wrote:
>> Add a driver for Renesas R-Car Gen3 RPC SPI controller.
>>
>> Signed-off-by: Mason Yang 
> 
>> +   xfercnt = xferpos;
>> +   rpc->xferlen = xfer[--xferpos].len;
>> +   rpc->cmd = RPC_SMCMR_CMD(((u8 *)xfer[0].tx_buf)[0]);
>
> Is the cast needed ?

 yes!
>>>
>>> Why ?
>>
>> Get a compiler warning due to tx_bug is void *, as Geert replied.
>>
>> Using get_unaligned(), patched code would be
>> ---
>>  rpc->cmd = RPC_SMCMR_CMD(get_unaligned((u8 *)xfer[0].tx_buf));
>> 
> 
> Using get_unaligned(0 is a bit strange for accessing a single byte quantity.
> Please keep the normal pointer dereference (including the cast).

Oh, right, for single bytes this is OK.

-- 
Best regards,
Marek Vasut

Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

[Marek Vasut]

On 12/06/2018 10:17 AM, masonccy...@mxic.com.tw wrote:
> Hi Marek,

Hi,

>> >> > +
>> >> > +       pm_runtime_enable(&pdev->dev);
>> >> > +       master->auto_runtime_pm = true;
>> >> > +
>> >> > +       master->num_chipselect = 1;
>> >> > +       master->mem_ops = &rpc_spi_mem_ops;
>> >> > +       master->transfer_one_message = rpc_spi_transfer_one_message;
>> >>
>> >> Is there any reason you cannot use the standard
>> >> spi_transfer_one_message, i.e. provide spi_controller.transfer_one()
>> >> instead of spi_controller.transfer_one_message()?
>> >>
>> >
>> > It seems there is a RPC HW restriction in CS# pin control.
>> > Therefore, it can't send the 1'st spi-transfer for command and then
>> > keeping CS# pin goes low for the 2'nd spi-transfer for address/data and
>> > so on.
>>
>> Isn't register DRCR bit SSLN/SSLE exactly for this purpose ?
>>
> 
> DRCR is for RPC module works in external space read mode, using memcpy( ).
> It is not for _spi_sync().
> 
> I only could use manual I/O mode by SMCR@bit-8 SSLKP and I found it has
> some
> restrictions in manual I/O mode to control CS# pin.

What restrictions are those ? I am aware of some, maybe there is more.

-- 
Best regards,
Marek Vasut

Re: [PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible

[Laurent Pinchart]

Hi Morimoto-san,

On Tuesday, 27 November 2018 02:44:58 EET Kuninori Morimoto wrote:
> Hi Laurent
> 
> Sorry for super late response.
> I got opinion from BSP team about this patch.

No worries. My reply is late too I'm afraid :-S

> > On selected SoCs, the DU can use the clock output by the LVDS encoder
> > PLL as its input dot clock. This feature is optional, but on the D3 and
> > E3 SoC it is often the only way to obtain a precise dot clock frequency,
> > as the other available clocks (CPG-generated clock and external clock)
> > usually have fixed rates.
> > 
> > Add a DU model information field to describe which DU channels can use
> > the LVDS PLL output clock as their input clock, and configure clock
> > routing accordingly.
> > 
> > This feature is available on H2, M2-W, M2-N, D3 and E3 SoCs, with D3 and
> > E3 being the primary targets. It is left disabled in this commit, and
> > will be enabled per-SoC after careful testing.
> > 
> > At the hardware level, clock routing is configured at runtime in two
> > steps, first selecting an internal dot clock between the LVDS PLL clock
> > and the external DOTCLKIN clock, and then selecting between the internal
> > dot clock and the CPG-generated clock. The first part requires stopping
> > the whole DU group in order for the change to take effect, thus causing
> > flickering on the screen. For this reason we currently hardcode the
> > clock source to the LVDS PLL clock if available, and allow flicker-free
> > selection of the external DOTCLKIN clock or CPG-generated clock
> > otherwise. A more dynamic clock selection process can be implemented
> > later if the need arises.
> > 
> > Signed-off-by: Laurent Pinchart
> > 
> > Tested-by: Jacopo Mondi 
> > ---
> 
> (snip)
> 
> > +   didsr = DIDSR_CODE;
> > +   for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
> > +   if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
> > +   didsr |= DIDSR_LCDS_LVDS0(i)
> > + |  DIDSR_PDCS_CLK(i, 0);
> > +   else
> > +   didsr |= DIDSR_LCDS_DCLKIN(i)
> > + |  DIDSR_PDCS_CLK(i, 0);
> > +   }
> 
> Here, this is for DU pin settings, and fixed for
> 
>   DU_DOTCLKIN0 -> DU0
>   DU_DOTCLKIN1 -> DU1
> 
> But on E3 (Ebisu) board, it has only DU_DOTCLKIN0.
> We might use like this
> 
>   DU_DOTCLKIN0 -> DU0
>   DU_DOTCLKIN0 -> DU1
> 
> It is possible to adjust to this situation ?
> DIDSR :: PDCSn allows only 0

I think this would make sense. I'm not sure how to implement that, but I'll 
give it a try. What is the priority ?

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 26/34] dt-bindings: arm: Convert Renesas board/soc bindings to json-schema

[Rob Herring]

On Wed, Dec 5, 2018 at 1:44 PM Simon Horman  wrote:
>
> On Tue, Dec 04, 2018 at 09:08:57AM -0600, Rob Herring wrote:
> > On Tue, Dec 4, 2018 at 8:57 AM Geert Uytterhoeven  
> > wrote:
> > >
> > > Hi Simon,
> > >
> > > On Tue, Dec 4, 2018 at 3:48 PM Simon Horman  wrote:
> > > > On Mon, Dec 03, 2018 at 03:32:15PM -0600, Rob Herring wrote:
> > > > > Convert Renesas SoC bindings to DT schema format using json-schema.
> > > > >
> > > > > Cc: Simon Horman 
> > > > > Cc: Magnus Damm 
> > > > > Cc: Mark Rutland 
> > > > > Cc: linux-renesas-soc@vger.kernel.org
> > > > > Cc: devicet...@vger.kernel.org
> > > > > Signed-off-by: Rob Herring 
> > > > > ---
> > > > >  .../devicetree/bindings/arm/shmobile.txt  | 151 
> > > > >  .../devicetree/bindings/arm/shmobile.yaml | 218 
> > > > > ++
> > > > >  2 files changed, 218 insertions(+), 151 deletions(-)
> > > > >  delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt
> > > > >  create mode 100644 
> > > > > Documentation/devicetree/bindings/arm/shmobile.yaml
> > > >
> > > > Hi Rob,
> > > >
> > > > what is this based on? I get a conflict when applying the .txt change
> > > > and if I knew the base for this patch it would be rather easy to work
> > > > out what has changed.
> >
> > 4.20-rc2
> >
> > > >
> > > > Also, should we do an s/shmobile.txt/shmobile.yaml/ in MAINTAINERS?
> >
> > Yes. Though it was pointed out that get_maintainers.pl can pull emails
> > out of this file. We'd need to get that to work by default though.
> >
> > > Probably even s/shmobile.yaml/renesas.yaml/, while at it?
> >
> > Sure, if that's what you all want.
>
> How about this?

LGTM

> From: Rob Herring 
> Subject: [PATCH v2.1] dt-bindings: arm: Convert Renesas board/soc bindings to
>  json-schema
>
> Convert Renesas SoC bindings to DT schema format using json-schema.
>
> v2.1 [Simon Horman]
> - rebased on renesas-devel-20181204-v4.20-rc5
>   + Added r8a7744 development platform and SoM
>   + Correct RZ/G2E part number
> - Update MAINTAINERS
>
> Signed-off-by: Rob Herring 
> Signed-off-by: Simon Horman 
> ---
>  Documentation/devicetree/bindings/arm/renesas.yaml | 228 
> +
>  Documentation/devicetree/bindings/arm/shmobile.txt | 155 --
>  MAINTAINERS|   4 +-
>  3 files changed, 230 insertions(+), 157 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/renesas.yaml
>  delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt

[PATCH 1/8] clk: renesas: Remove usage of CLK_IS_BASIC

[Stephen Boyd]

This flag doesn't look to be used by any code, just set in various clk
init structures and then never tested again. Remove it from these
drivers as it doesn't provide any benefit.

Cc: Geert Uytterhoeven 
Cc: 
Signed-off-by: Stephen Boyd 
---
 drivers/clk/renesas/clk-div6.c | 2 +-
 drivers/clk/renesas/clk-mstp.c | 2 +-
 drivers/clk/renesas/r9a06g032-clocks.c | 8 
 drivers/clk/renesas/rcar-gen3-cpg.c| 2 +-
 drivers/clk/renesas/renesas-cpg-mssr.c | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 57c934164306..e98a9f5b3c90 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -274,7 +274,7 @@ struct clk * __init cpg_div6_register(const char *name,
/* Register the clock. */
init.name = name;
init.ops = &cpg_div6_clock_ops;
-   init.flags = CLK_IS_BASIC;
+   init.flags = 0;
init.parent_names = parent_names;
init.num_parents = valid_parents;
 
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 1c1768c2cc82..2ba6105937e3 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -158,7 +158,7 @@ static struct clk * __init cpg_mstp_clock_register(const 
char *name,
 
init.name = name;
init.ops = &cpg_mstp_clock_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
/* INTC-SYS is the module clock of the GIC, and must not be disabled */
if (!strcmp(name, "intc-sys")) {
pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c 
b/drivers/clk/renesas/r9a06g032-clocks.c
index 6d2b56891559..658cb11b6f55 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -424,7 +424,7 @@ r9a06g032_register_gate(struct r9a06g032_priv *clocks,
 
init.name = desc->name;
init.ops = &r9a06g032_clk_gate_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
 
@@ -595,7 +595,7 @@ r9a06g032_register_div(struct r9a06g032_priv *clocks,
 
init.name = desc->name;
init.ops = &r9a06g032_clk_div_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
 
@@ -683,7 +683,7 @@ r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
 
init.name = desc->name;
init.ops = &clk_bitselect_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = names;
init.num_parents = 2;
 
@@ -777,7 +777,7 @@ r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
 
init.name = desc->name;
init.ops = &r9a06g032_clk_dualgate_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
g->hw.init = &init;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 4ba38f98cc7b..48e003c69cd1 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -368,7 +368,7 @@ static struct clk * __init cpg_sd_clk_register(const struct 
cpg_core_clk *core,
 
init.name = core->name;
init.ops = &cpg_sd_clock_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c 
b/drivers/clk/renesas/renesas-cpg-mssr.c
index f7bb817420b4..30df0dc853f0 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -412,7 +412,7 @@ static void __init cpg_mssr_register_mod_clk(const struct 
mssr_mod_clk *mod,
 
init.name = mod->name;
init.ops = &cpg_mstp_clock_ops;
-   init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+   init.flags = CLK_SET_RATE_PARENT;
for (i = 0; i < info->num_crit_mod_clks; i++)
if (id == info->crit_mod_clks[i]) {
dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
-- 
Sent by a computer through tubes

Re: [PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible

[Kuninori Morimoto]

Hi Laurent

> > > + didsr = DIDSR_CODE;
> > > + for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
> > > + if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
> > > + didsr |= DIDSR_LCDS_LVDS0(i)
> > > +   |  DIDSR_PDCS_CLK(i, 0);
> > > + else
> > > + didsr |= DIDSR_LCDS_DCLKIN(i)
> > > +   |  DIDSR_PDCS_CLK(i, 0);
> > > + }
> > 
> > Here, this is for DU pin settings, and fixed for
> > 
> > DU_DOTCLKIN0 -> DU0
> > DU_DOTCLKIN1 -> DU1
> > 
> > But on E3 (Ebisu) board, it has only DU_DOTCLKIN0.
> > We might use like this
> > 
> > DU_DOTCLKIN0 -> DU0
> > DU_DOTCLKIN0 -> DU1
> > 
> > It is possible to adjust to this situation ?
> > DIDSR :: PDCSn allows only 0
> 
> I think this would make sense. I'm not sure how to implement that, but I'll 
> give it a try. What is the priority ?

Normal priority is very OK, so far.
Thank you

Best regards
---
Kuninori Morimoto