RE: [PATCH v2 1/2] arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
Hi Geert-san, Thanks for your review. > -Original Message- > From: Geert Uytterhoeven > Sent: Wednesday, November 14, 2018 6:50 PM > To: Gaku Inami > Cc: Simon Horman ; Magnus Damm ; > Rob Herring ; Mark > Rutland ; Linux-Renesas > ; open list:OPEN FIRMWARE AND FLATTENED > DEVICE TREE BINDINGS > Subject: Re: [PATCH v2 1/2] arm64: dts: renesas: Add CPU topology on R-Car > Gen3 SoCs [snip] > Next time, please collect tags provided by reviewers on the previous > version. I am sorry that "reviewed-by" from you is lacked. I will add correct tags next time. Regards, Inami
[PATCH v2 2/2] arm64: dts: renesas: Add CPU capacity-dmips-mhz
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on
dhrystone. The average in 10 times of dhrystone result as follows:
r8a7795 SoC (A57x4 + A53x4)
CPU max-freq dhrystone
-
A57 1500 MHz 11470943 lps/s
A53 1200 MHz 4798583 lps/s
r8a7796 SoC (A57x2 + A53x4)
CPU max-freq dhrystone
-
A57 1500 MHz 11463526 lps/s
A53 1200 MHz 4793276 lps/s
Based on above, capacity-dmips-mhz values are calculated as follows:
r8a7795 SoC
A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024
A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535
r8a7796 SoC
A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024
A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535
However, since each CPUs have different max frequencies, the final
CPU capacities of A53 are scaled by this difference, the values are
as follows.
[r8a7795 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 < CPU capacity of A57
1024
1024
1024
428 < CPU capacity of A53
428
428
428
[r8a7796 SoC]
$ cat /sys/devices/system/cpu/cpu*/cpu_capacity
1024 < CPU capacity of A57
1024
428 < CPU capacity of A53
428
428
428
Signed-off-by: Gaku Inami
---
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
- Add the formula for capacity-dmips-mhz into description
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 63d5b61..94a4ab6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -157,6 +157,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -169,6 +170,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -181,6 +183,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -193,6 +196,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -205,6 +209,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_1: cpu@101 {
@@ -216,6 +221,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_2: cpu@102 {
@@ -227,6 +233,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
a53_3: cpu@103 {
@@ -238,6 +245,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <535>;
};
L2_CA57: cache-controller-0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index b12bf73..369d0bc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -162,6 +162,7 @@
enable-method = "psci";
clocks = < CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
[PATCH v2 0/2] Optimization with aware of cpu capacity for R-Car Gen3
The commit 05484e098448 ("sched/topology: Add SD_ASYM_CPUCAPACITY
flag detection") to automatically detect asymmetric CPU capacity
has been merged into v4.20-rc1, so I will post this patch series
as v2 again.
These add the scheduler information to be aware cpu capacity. Some
R-Car SoCs have big LITTLE architecture(e.g. CA57/CA53). It has a
difference performance/power consumption for each CPUs.
As the scheduler will be aware the capacity of CPU, the scheduler is
balancing so that the free capacity of each CPU is even. This means
that it aggressively migrates tasks to big CPUs(e.g. CA57) with large
capacity in case of the system load is low and middle, the performance
of user application is improved than before.
Since most users for IVI are using CPU with performance oriented than
power consumption, this change will benefit for their use-cases. Some
benchmark is improved as an example below.
UnixBench (1 parallel) on r8a7796 SoC (CA57x2 + CA53x4) :
before after
- Dhrystone 2 using register variables4777159 11353624 +58%
- Double-Precision Whetstone 866 1218 +29%
- Execl Throughput728920 +21%
- File Copy 1024 bufsize 2000 maxblocks 69405 115962 +40%
- File Copy 256 bufsize 500 maxblocks 21404 28685 +25%
- File Copy 4096 bufsize 8000 maxblocks102749 159978 +36%
- Pipe Throughput 93876 150848 +38%
- Pipe-based Context Switching 27257 25317-8%
- Process Creation 1885 2292 +18%
- Shell Scripts (1 concurrent)135137+1%
- Shell Scripts (8 concurrent) 35 34-3%
- System Call Overhead 99169 140146 +29%
- System Benchmarks Index Score 112152 +26%
UnixBench (8 parallel) on r8a7795 SoC (CA57x4 + CA53x4) :
before after
- Dhrystone 2 using register variables 64686060 64472624 0%
- Double-Precision Whetstone 8380 8423+1%
- Execl Throughput 5856 6147+5%
- File Copy 1024 bufsize 2000 maxblocks142923 164482 +13%
- File Copy 256 bufsize 500 maxblocks 46257 51344 +10%
- File Copy 4096 bufsize 8000 maxblocks360398 393339+8%
- Pipe Throughput 974106 972545 0%
- Pipe-based Context Switching 162455 146567 -11%
- Process Creation 10164 9659-5%
- Shell Scripts (1 concurrent)317317 0%
- Shell Scripts (8 concurrent) 30 31+3%
- System Call Overhead 897596 899274 0%
- System Benchmarks Index Score 523534+2%
based on renesas-devel-20181105-v4.20-rc1
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
- Add the formula for capacity-dmips-mhz into description
- Remove the static setting of SD_ASYM_CPUCAPACITY for R-Car
Gaku Inami (2):
arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
arm64: dts: renesas: Add CPU capacity-dmips-mhz
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 32 +
2 files changed, 72 insertions(+)
--
2.7.4
[PATCH v2 1/2] arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs
This patch adds the "cpu-map" into r8a7795/r8a7796 composed of
multi-cluster. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami
---
v1 -> v2:
- Consolidate two patches for r8a7795 and r8a7796 into one patch
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++
2 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 0b54c53..63d5b61 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -116,6 +116,38 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 3baee26..b12bf73 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -127,6 +127,32 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
--
2.7.4
RE: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz
Hi Geert-san, Simon-san, > -Original Message- > From: linux-renesas-soc-ow...@vger.kernel.org > [mailto:linux-renesas-soc-ow...@vger.kernel.org] On Behalf Of Simon > Horman > Sent: Wednesday, March 7, 2018 5:11 PM [snip] > > > > Documentation/devicetree/bindings/arm/cpu-capacity.txt: > > > > "capacity-dmips-mhz is an optional cpu node [1] property: u32 value > > representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, > > the > > maximum frequency available to the cpu is then used to calculate the > > capacity > > value internally used by the kernel." > > > > IIUIC, you should thus not use 15532585 and 6241541 directly, but > > scale them to the frequency. > > > > So the formula for CA53 becomes: > > > > 1024 / (15532585 / 1500) * (6241541 / 1200) = 514 > > > > > Considering cpufreq is available later, is it better to set the value(514) > > > for CA53 scaled by different maximum frequencies? > > > > DT describes the hardware, not software limitations, so IMHO 514 is the > > correct > > value. Sorry, I misunderstood the intention of definition in DT. Thanks for your detailed explanation. I understood it. > Yes agreed. Please refresh this patchset accordingly. I will update v2 patch. Regards, Inami
RE: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz
Hi Geert-san, > -Original Message- > From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com] On > Behalf Of Geert Uytterhoeven > Sent: Monday, March 5, 2018 7:24 PM [snip] > > 411 for the A53 cores sounds a bit low to me, though. > Documentation/devicetree/bindings/arm/cpu-capacity.txt uses 578. > > Perhaps you already took into account the maximum clock frequencies? > According to the binding document, you should not do that (cfr. > "final capacities are 1024 for cluster0 and 446 for cluster1" in the > bindings doc). Thanks for your review. I set 411 for CA53 based on dhrystone measurement and current implementation. The average in 10 times of measurement as follows: cpu max-freq dhrystone - A57 1500 MHz 15532585 lps/s A53 1200 MHz 6241541 lps/s With the value of CA57 is scaled at 1024, I end up with 411 for CA53. However, since cpufreq is not available on renesas-devel-20180212-v4.16-rc1, the final capacity is set by directly using capacity-dmips-mhz in dt as below. $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 411 411 411 411 Considering cpufreq is available later, is it better to set the value(514) for CA53 scaled by different maximum frequencies? Regards, Inami
RE: [PATCH 5/5] soc: renesas: rcar-topology: Add support to be aware cpu capacity
Hi Geert-san, > -Original Message- > From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com] On > Behalf Of Geert Uytterhoeven [snip] > None of the above seems R-Car specific to me. So please explain why this > can't just be added to arch/arm64/kernel/topology.c instead, and enabled > unconditionally. Thanks for your feedback. As you said, this code should not be R-Car specific. I will consider again that it enables SD_ASYM_CPUCAPACITY unconditionally. Regards, Inami
[PATCH 1/5] arm64: dts: renesas: r8a7795: Add multi-cluster definition
This patch adds the "cpu-map" for multi-cluster into r8a7795
device-tree. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami <gaku.inami...@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index ce85704..ffcc91e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -34,6 +34,38 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
--
2.7.4
[PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz
Set the capacity-dmips-mhz for r8a7795, that is based on dhrystone.
Expected cpu capacity:
Cortex-A57@1.5GHz: 1024, Cortex-A53@1.2GHz: 411
Signed-off-by: Gaku Inami <gaku.inami...@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index ffcc91e..be15864 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -75,6 +75,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -87,6 +88,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -99,6 +101,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -111,6 +114,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -123,6 +127,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_1: cpu@101 {
@@ -134,6 +139,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_2: cpu@102 {
@@ -145,6 +151,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_3: cpu@103 {
@@ -156,6 +163,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
L2_CA57: cache-controller-0 {
--
2.7.4
[PATCH 2/5] arm64: dts: renesas: r8a7796: Add multi-cluster definition
This patch adds the "cpu-map" for multi-cluster into r8a7796
device-tree. This definition is used to parse the cpu topology.
Signed-off-by: Gaku Inami <gaku.inami...@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f8e9313..154df9b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -64,6 +64,32 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <_0>;
+ };
+ core1 {
+ cpu = <_1>;
+ };
+ core2 {
+ cpu = <_2>;
+ };
+ core3 {
+ cpu = <_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
--
2.7.4
[PATCH 4/5] arm64: dts: renesas: r8a7796: Add cpu capacity-dmips-mhz
Set the capacity-dmips-mhz for r8a7796, that is based on dhrystone.
Expected cpu capacity:
Cortex-A57@1.5Ghz: 1024, Cortex-A53@1.2GHz: 411
Signed-off-by: Gaku Inami <gaku.inami...@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 154df9b..a776d29 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -99,6 +99,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -111,6 +112,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <1024>;
#cooling-cells = <2>;
};
@@ -123,6 +125,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_1: cpu@101 {
@@ -134,6 +137,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_2: cpu@102 {
@@ -145,6 +149,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
a53_3: cpu@103 {
@@ -156,6 +161,7 @@
enable-method = "psci";
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
+ capacity-dmips-mhz = <411>;
};
L2_CA57: cache-controller-0 {
--
2.7.4
[PATCH 5/5] soc: renesas: rcar-topology: Add support to be aware cpu capacity
Some R-Car SoCs support big LITTLE architecture produced by ARM, that
have different power/performance characteristics between each CPUs.
In order to aware such as difference, this patch changes the sched
domain flags that the tasks can be scheduled with capacity awareness.
If you use big LITTLE without this patch, the scheduler may make
unintended behaviors.
Signed-off-by: Gaku Inami <gaku.inami...@renesas.com>
---
drivers/soc/renesas/Kconfig | 4
drivers/soc/renesas/Makefile| 1 +
drivers/soc/renesas/rcar-topology.c | 36
3 files changed, 41 insertions(+)
create mode 100644 drivers/soc/renesas/rcar-topology.c
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 6efd7be..296bdee 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -16,6 +16,7 @@ config SOC_RENESAS
select SYSC_R8A7796 if ARCH_R8A7796
select SYSC_R8A77970 if ARCH_R8A77970
select SYSC_R8A77995 if ARCH_R8A77995
+ select RCAR_CPU_TOPOLOGY if ARCH_R8A7795 || ARCH_R8A7796
if SOC_RENESAS
@@ -71,4 +72,7 @@ config RST_RCAR
config SYSC_RCAR
bool "R-Car System Controller support" if COMPILE_TEST
+config RCAR_CPU_TOPOLOGY
+ bool "R-Car CPU Topology" if COMPILE_TEST
+
endif # SOC_RENESAS
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 845d62a..244f243 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
# Family
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
obj-$(CONFIG_SYSC_RCAR)+= rcar-sysc.o
+obj-$(CONFIG_RCAR_CPU_TOPOLOGY)+= rcar-topology.o
diff --git a/drivers/soc/renesas/rcar-topology.c
b/drivers/soc/renesas/rcar-topology.c
new file mode 100644
index 000..7e941cf
--- /dev/null
+++ b/drivers/soc/renesas/rcar-topology.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car CPU topology for ARM big.LITTLE platforms
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static int rcar_cpu_cpu_flags(void)
+{
+ return SD_ASYM_CPUCAPACITY;
+}
+
+static struct sched_domain_topology_level rcar_topology[] = {
+#ifdef CONFIG_SCHED_MC
+ { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
+#endif
+ { cpu_cpu_mask, rcar_cpu_cpu_flags, SD_INIT_NAME(DIE) },
+ { NULL, }
+};
+
+static int __init rcar_topology_init(void)
+{
+ if (of_machine_is_compatible("renesas,r8a7795") ||
+ of_machine_is_compatible("renesas,r8a7796"))
+ set_sched_topology(rcar_topology);
+
+ return 0;
+}
+early_initcall(rcar_topology_init);
--
2.7.4
RE: [PATCH 4/4] arm64: dts: r8a7796: Add DEVFREQ support for GSX
Hi Geert-san, Ulrich-san,
> Do they really all use the same voltage?
>
> And AFAIU, DVFS is shared between CPU and GPU.
We support the opp table of GPU with the same voltage for each in
R-Car H3/M3. As you know, DVFS is shared between CA57 and GPU.
We understand that arbitration control of the voltage from both
cores can't be realized with the current CPUFREQ and DEVFREQ
framework. Therefore, we have implemented as above now.
In our test with GPU team, it is fine except power consumption.
Regards,
Inami
-Original Message-
From: geert.uytterhoe...@gmail.com [mailto:geert.uytterhoe...@gmail.com] On
Behalf Of Geert Uytterhoeven
Sent: Monday, December 18, 2017 7:27 PM
To: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>; Laurent Pinchart
<laurent.pinch...@ideasonboard.com>; Magnus Damm <magnus.d...@gmail.com>; Gaku
Inami <gaku.inami...@bp.renesas.com>; TAKESHI KIHARA
<takeshi.kihara...@renesas.com>; Hien Dang <hien.dang...@renesas.com>
Subject: Re: [PATCH 4/4] arm64: dts: r8a7796: Add DEVFREQ support for GSX
Hi Uli,
On Fri, Dec 15, 2017 at 4:14 PM, Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
wrote:
> From: Gaku Inami <gaku.inami...@bp.renesas.com>
>
> This patch supports GSX frequency scaling using devfreq.
>
> Includes update of the OPP tables for GSX because the typical voltage
> of VDD_DVFS (power optimized) was updated to 0.83V by R-Car Gen3 EC
> Rev0.54E specification.
>
> Signed-off-by: Gaku Inami <gaku.inami...@bp.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
> Signed-off-by: Hien Dang <hien.dang...@renesas.com>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -166,6 +166,27 @@
> };
> };
>
> + gsx_opp_table: gsx_opp_table {
> + compatible = "operating-points-v2";
> +
> + opp@2 {
opp-2 (try "make dtbs W=1")
> + opp-hz = /bits/ 64 <2>;
> + opp-microvolt = <83>;
> + };
> + opp@3 {
> + opp-hz = /bits/ 64 <3>;
> + opp-microvolt = <83>;
> + };
> + opp@4 {
> + opp-hz = /bits/ 64 <4>;
> + opp-microvolt = <83>;
> + };
> + opp@6 {
> + opp-hz = /bits/ 64 <6>;
> + opp-microvolt = <83>;
Do they really all use the same voltage?
And AFAIU, DVFS is shared between CPU and GPU.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
