Re: [PATCH 02/14] pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E pin was selected

2017-07-13 Thread Geert Uytterhoeven 
Hi Kaneko-san,

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko  wrote:
> From: Takeshi Kihara 
>
> This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function
> is selected.
>
> This is a correction to the incorrect implementation of IPSR register
> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
> User's Manual Rev.0.51E or later.
>
> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Identical to "[PATCH 4/5] pinctrl: sh-pfc: r8a7796: Fix IPSR setting for
MSIOF3_SS1_E pin" I sent yesterday.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 02/14] pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E pin was selected

2017-07-12 Thread Yoshihiro Kaneko 
From: Takeshi Kihara 

This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function
is selected.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index b2fb66f..87f21d7b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -645,7 +645,7 @@ enum {
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B,  SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B,SEL_CANFD0_1),
-   PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E,   SEL_MSIOF3_4),
+   PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E,   SEL_MSIOF3_4),
 
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0,   IRQ2),
-- 
1.9.1