Re: [PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function definitions

[Geert Uytterhoeven]

On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko  wrote:
> From: Takeshi Kihara 
>
> This patch fixes the implementation incorrect of IPSR register value
> definitions for MSIOF3_{SS1,SS2}_E pins function.
>
> This is a correction to the incorrect implementation of IPSR register
> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
> User's Manual Rev.0.51E or later.
>
> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
> Signed-off-by: Takeshi Kihara 
> Signed-off-by: Yoshihiro Kaneko 

Identical to "[PATCH 3/5] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pin
 function definitions" I sent yesterday.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of IPSR register value
definitions for MSIOF3_{SS1,SS2}_E pins function.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 80007b9..866cbe4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -221,8 +221,8 @@
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   FM(A25) 
FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)
F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)  
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)FM(A24) 
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-- 
1.9.1