Re: [PATCH v12 31/33] rcar-vin: enable support for r8a7795
On 07/03/18 23:05, Niklas Söderlund wrote: > Add the SoC specific information for Renesas r8a7795 ES1.x and ES2.0. > > Signed-off-by: Niklas Söderlund > Reviewed-by: Laurent Pinchart Reviewed-by: Hans Verkuil Regards, Hans > --- > drivers/media/platform/rcar-vin/Kconfig | 2 +- > drivers/media/platform/rcar-vin/rcar-core.c | 120 > > 2 files changed, 121 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/rcar-vin/Kconfig > b/drivers/media/platform/rcar-vin/Kconfig > index af4c98b44d2e22cb..8fa7ee468c63afb9 100644 > --- a/drivers/media/platform/rcar-vin/Kconfig > +++ b/drivers/media/platform/rcar-vin/Kconfig > @@ -6,7 +6,7 @@ config VIDEO_RCAR_VIN > select V4L2_FWNODE > ---help--- > Support for Renesas R-Car Video Input (VIN) driver. > - Supports R-Car Gen2 SoCs. > + Supports R-Car Gen2 and Gen3 SoCs. > > To compile this driver as a module, choose M here: the > module will be called rcar-vin. > diff --git a/drivers/media/platform/rcar-vin/rcar-core.c > b/drivers/media/platform/rcar-vin/rcar-core.c > index a1c441c1a314feb7..bc116cc0181171e0 100644 > --- a/drivers/media/platform/rcar-vin/rcar-core.c > +++ b/drivers/media/platform/rcar-vin/rcar-core.c > @@ -21,6 +21,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -832,6 +833,104 @@ static const struct rvin_info rcar_info_gen2 = { > .max_height = 2048, > }; > > +static const struct rvin_group_route rcar_info_r8a7795_routes[] = { > + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, > + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, > + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, > + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, > + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, > + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, > + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, > + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, > + { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, > + { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, > + { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, > + { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, > + { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, > + { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, > + { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, > + { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, > + { /* Sentinel */ } > +}; > + > +static const struct rvin_info rcar_info_r8a7795 = { > + .model = RCAR_GEN3, > + .use_mc = true, > + .max_width = 4096, > + .max_height = 4096, > + .routes = rcar_info_r8a7795_routes, > +}; > + > +static const struct rvin_group_route rcar_info_r8a7795es1_routes[] = { > + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, > + { .csi = RVIN_CSI21, .channel = 0, .vin = 0, .mask = BIT(2) | BIT(5) }, > + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, > + { .csi = RVIN_CSI21, .channel = 0, .vin = 1, .mask = BIT(1) }, > + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, > + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, > + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, > + { .csi = RVIN_CSI21, .channel = 1, .vin = 1, .mask = BIT(5) }, > + { .csi = RVIN_CSI21, .channel = 0, .vin = 2, .mask = BIT(0) }, > + { .csi =
[PATCH v12 31/33] rcar-vin: enable support for r8a7795
Add the SoC specific information for Renesas r8a7795 ES1.x and ES2.0. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart --- drivers/media/platform/rcar-vin/Kconfig | 2 +- drivers/media/platform/rcar-vin/rcar-core.c | 120 2 files changed, 121 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rcar-vin/Kconfig b/drivers/media/platform/rcar-vin/Kconfig index af4c98b44d2e22cb..8fa7ee468c63afb9 100644 --- a/drivers/media/platform/rcar-vin/Kconfig +++ b/drivers/media/platform/rcar-vin/Kconfig @@ -6,7 +6,7 @@ config VIDEO_RCAR_VIN select V4L2_FWNODE ---help--- Support for Renesas R-Car Video Input (VIN) driver. - Supports R-Car Gen2 SoCs. + Supports R-Car Gen2 and Gen3 SoCs. To compile this driver as a module, choose M here: the module will be called rcar-vin. diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index a1c441c1a314feb7..bc116cc0181171e0 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -832,6 +833,104 @@ static const struct rvin_info rcar_info_gen2 = { .max_height = 2048, }; +static const struct rvin_group_route rcar_info_r8a7795_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, + { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, + { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, + { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, + { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, + { /* Sentinel */ } +}; + +static const struct rvin_info rcar_info_r8a7795 = { + .model = RCAR_GEN3, + .use_mc = true, + .max_width = 4096, + .max_height = 4096, + .routes = rcar_info_r8a7795_routes, +}; + +static const struct rvin_group_route rcar_info_r8a7795es1_routes[] = { + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, + { .csi = RVIN_CSI21, .channel = 0, .vin = 0, .mask = BIT(2) | BIT(5) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, + { .csi = RVIN_CSI21, .channel = 0, .vin = 1, .mask = BIT(1) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, + { .csi = RVIN_CSI21, .channel = 1, .vin = 1, .mask = BIT(5) }, + { .csi = RVIN_CSI21, .channel = 0, .vin = 2, .mask = BIT(0) }, + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, + { .csi = RVIN_CSI40, .channel = 2, .vin = 2,