Re: [PATCH v2 05/11] ARM: dts: r8a7792: initial SoC device tree

[Geert Uytterhoeven]

Hi Sergei,

On Fri, Jun 3, 2016 at 11:26 PM, Sergei Shtylyov
 wrote:
> The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC,
> and the required  clock descriptions.
>
> Signed-off-by: Sergei Shtylyov 
>
> ---
> Changes in version 2:

> - created  the "soc" subnode, moving the SoC  device  nodes there;
> - removed  the "clocks" node, moving its fixed clock  subnodes to the root and
>   the MSTP subnodes into the "soc" node.
>
>  arch/arm/boot/dts/r8a7792.dtsi |  171 
> +
>  1 file changed, 171 insertions(+)
>
> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
> ===
> --- /dev/null
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi

> +   /* Fixed factor clocks */
> +   zs_clk: zs {
> +   compatible = "fixed-factor-clock";
> +   clocks = <_clocks R8A7792_CLK_PLL1>;
> +   #clock-cells = <0>;
> +   clock-div = <6>;
> +   clock-mult = <1>;
> +   };
> +   p_clk: p {
> +   compatible = "fixed-factor-clock";
> +   clocks = <_clocks R8A7792_CLK_PLL1>;
> +   #clock-cells = <0>;
> +   clock-div = <24>;
> +   clock-mult = <1>;
> +   };
> +   cp_clk: cp {
> +   compatible = "fixed-factor-clock";
> +   clocks = <_clocks R8A7792_CLK_PLL1>;
> +   #clock-cells = <0>;
> +   clock-div = <3>;
> +   clock-mult = <1>;
> +   };

I think the above 3 fixed factor clocks should be children of the "soc" node,
as they're generated on-SoC.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 05/11] ARM: dts: r8a7792: initial SoC device tree

[Sergei Shtylyov]

The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC,
and the required  clock descriptions.

Signed-off-by: Sergei Shtylyov 

---
Changes in version 2:
- explicitly included the IRQ header;
- removed the CPU1 node;
- removed the audio and PCIe bus clocks;
- removed the SDH, SD0, and SD1 CPG clocks;
- added RCAN and ADSP CPG clocks;
- removed the PLL1/2, Z2, ZS, I, B, P, CL, M2, RCLK, OSCCLK, ZB3, ZB3D2, DDR,
  and MP fixed factor clocks;
- fixed up the parent and divisor for the CP fixed factor clock;
- swapped  the SYS-DMAC0/1 clocks;
- removed  all gated clocks except the [H]SCIF, IRQC, and SYS-DMAC ones;
- created  the "soc" subnode, moving the SoC  device  nodes there;
- removed  the "clocks" node, moving its fixed clock  subnodes to the root and
  the MSTP subnodes into the "soc" node.

 arch/arm/boot/dts/r8a7792.dtsi |  171 +
 1 file changed, 171 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a7792";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a15";
+   reg = <0>;
+   clock-frequency = <10>;
+   clocks = <_clocks R8A7792_CLK_Z>;
+   power-domains = < R8A7792_PD_CA15_CPU0>;
+   next-level-cache = <_CA15>;
+   };
+
+   L2_CA15: cache-controller@0 {
+   compatible = "cache";
+   reg = <0>;
+   cache-unified;
+   cache-level = <2>;
+   power-domains = < R8A7792_PD_CA15_SCU>;
+   };
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   gic: interrupt-controller@f1001000 {
+   compatible = "arm,gic-400";
+   #interrupt-cells = <3>;
+   interrupt-controller;
+   reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+   interrupts = ;
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   sysc: system-controller@e618 {
+   compatible = "renesas,r8a7792-sysc";
+   reg = <0 0xe618 0 0x0200>;
+   #power-domain-cells = <1>;
+   };
+
+   /* Special CPG clocks */
+   cpg_clocks: cpg_clocks@e615 {
+   compatible = "renesas,r8a7792-cpg-clocks",
+"renesas,rcar-gen2-cpg-clocks";
+   reg = <0 0xe615 0 0x1000>;
+   clocks = <_clk>;
+   #clock-cells = <1>;
+   clock-output-names = "main", "pll0", "pll1", "pll3",
+"lb", "qspi", "z", "rcan", "adsp";
+   #power-domain-cells = <0>;
+   };
+
+   /* Gate clocks */
+   mstp2_clks: mstp2_clks@e6150138 {
+   compatible = "renesas,r8a7792-mstp-clocks",
+"renesas,cpg-mstp-clocks";
+   reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+   clocks = <_clk>, <_clk>;
+   #clock-cells = <1>;
+   clock-indices = <
+   R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
+   >;
+   clock-output-names = "sys-dmac1", "sys-dmac0";
+   };
+   mstp4_clks: mstp4_clks@e6150140 {
+   compatible = "renesas,r8a7792-mstp-clocks",
+"renesas,cpg-mstp-clocks";
+