Re: [PATCH v3 1/2] pinctrl: rza1: add support for RZ/A1L

[Geert Uytterhoeven]

Hi Linus,

On Sat, Oct 7, 2017 at 1:19 PM, Linus Walleij  wrote:
> On Wed, Oct 4, 2017 at 11:07 PM, Chris Brandt  
> wrote:
>> Aspects like the number of ports and the location where peripherals are
>> brought out differ between the RZ/A1H and RZ/A1L.
>>
>> Signed-off-by: Chris Brandt 
>> Reviewed-by: Jacopo Mondi 
>> ---
>> v2:
>>  * added Reviewed-by
>
> Looks good, I expect Geert to queue this for me with a pull
> request like with other Renesas stuff.

Thank you, your wish my command.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3 1/2] pinctrl: rza1: add support for RZ/A1L

[Linus Walleij]

On Wed, Oct 4, 2017 at 11:07 PM, Chris Brandt  wrote:

> Aspects like the number of ports and the location where peripherals are
> brought out differ between the RZ/A1H and RZ/A1L.
>
> Signed-off-by: Chris Brandt 
> Reviewed-by: Jacopo Mondi 
> ---
> v2:
>  * added Reviewed-by

Looks good, I expect Geert to queue this for me with a pull
request like with other Renesas stuff.

Yours,
Linus Walleij

[PATCH v3 1/2] pinctrl: rza1: add support for RZ/A1L

[Chris Brandt]

Aspects like the number of ports and the location where peripherals are
brought out differ between the RZ/A1H and RZ/A1L.

Signed-off-by: Chris Brandt 
Reviewed-by: Jacopo Mondi 
---
v2:
 * added Reviewed-by
---
 drivers/pinctrl/pinctrl-rza1.c | 134 +
 1 file changed, 134 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
index 04d058706b80..717c0f4449a0 100644
--- a/drivers/pinctrl/pinctrl-rza1.c
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -302,6 +302,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = {
.swio_entries   = rza1h_swio_entries,
 };
 
+/* 
+ * RZ/A1L (r7s72102) pinmux flags
+ */
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
+   { .pin = 0, .func = 1 },
+   { .pin = 1, .func = 1 },
+   { .pin = 2, .func = 1 },
+   { .pin = 3, .func = 1 },
+   { .pin = 4, .func = 1 },
+   { .pin = 5, .func = 1 },
+   { .pin = 6, .func = 1 },
+   { .pin = 7, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
+   { .pin = 0, .func = 2 },
+   { .pin = 1, .func = 2 },
+   { .pin = 2, .func = 2 },
+   { .pin = 4, .func = 2 },
+   { .pin = 5, .func = 2 },
+   { .pin = 10, .func = 2 },
+   { .pin = 11, .func = 2 },
+   { .pin = 12, .func = 2 },
+   { .pin = 13, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
+   { .pin = 1, .func = 4 },
+   { .pin = 2, .func = 2 },
+   { .pin = 3, .func = 2 },
+   { .pin = 6, .func = 2 },
+   { .pin = 7, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
+   { .pin = 0, .func = 1 },
+   { .pin = 1, .func = 1 },
+   { .pin = 2, .func = 1 },
+   { .pin = 3, .func = 1 },
+   { .pin = 4, .func = 1 },
+   { .pin = 5, .func = 1 },
+   { .pin = 6, .func = 1 },
+   { .pin = 7, .func = 1 },
+   { .pin = 8, .func = 1 },
+   { .pin = 9, .func = 1 },
+   { .pin = 10, .func = 1 },
+   { .pin = 11, .func = 1 },
+   { .pin = 12, .func = 1 },
+   { .pin = 13, .func = 1 },
+   { .pin = 14, .func = 1 },
+   { .pin = 15, .func = 1 },
+   { .pin = 0, .func = 2 },
+   { .pin = 1, .func = 2 },
+   { .pin = 2, .func = 2 },
+   { .pin = 3, .func = 2 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
+   { .pin = 0, .func = 1 },
+   { .pin = 1, .func = 1 },
+   { .pin = 2, .func = 1 },
+   { .pin = 3, .func = 1 },
+   { .pin = 4, .func = 1 },
+   { .pin = 5, .func = 1 },
+   { .pin = 6, .func = 1 },
+   { .pin = 7, .func = 1 },
+   { .pin = 8, .func = 1 },
+   { .pin = 9, .func = 1 },
+   { .pin = 10, .func = 1 },
+   { .pin = 11, .func = 1 },
+   { .pin = 12, .func = 1 },
+   { .pin = 13, .func = 1 },
+   { .pin = 14, .func = 1 },
+   { .pin = 15, .func = 1 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
+   { .pin = 2, .func = 2 },
+   { .pin = 3, .func = 2 },
+   { .pin = 5, .func = 2 },
+   { .pin = 6, .func = 2 },
+   { .pin = 7, .func = 2 },
+   { .pin = 2, .func = 3 },
+   { .pin = 3, .func = 3 },
+   { .pin = 5, .func = 3 },
+   { .pin = 6, .func = 3 },
+   { .pin = 7, .func = 3 },
+};
+
+static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
+   { .pin = 1, .func = 2 },
+   { .pin = 0, .func = 3 },
+   { .pin = 1, .func = 3 },
+   { .pin = 3, .func = 3 },
+   { .pin = 4, .func = 3 },
+   { .pin = 5, .func = 3 },
+};
+
+static const struct rza1_swio_pin rza1l_swio_pins[] = {
+   { .port = 2, .pin = 8, .func = 2, .input = 0 },
+   { .port = 5, .pin = 6, .func = 3, .input = 0 },
+   { .port = 6, .pin = 6, .func = 3, .input = 0 },
+   { .port = 6, .pin = 10, .func = 3, .input = 0 },
+   { .port = 7, .pin = 10, .func = 2, .input = 0 },
+   { .port = 8, .pin = 2, .func = 3, .input = 0 },
+};
+
+static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
+   [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
+   [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
+   [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
+   [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
+   [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
+   [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
+   [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
+};
+
+static const struct rza1_swio_entry rza1l_swio_entries[] = {
+   [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
+};
+
+/* RZ/A1L (r7s72102x) pinmux flags table */
+static const struct rza1_pinmux_conf rza1l_pmx_conf = {
+   .bidir_entries  = rza1l_bidir_entries,
+   .swio_entries   =