Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[Linus Walleij]

On Wed, Mar 29, 2017 at 9:30 AM, Geert Uytterhoeven
 wrote:
> On Fri, Mar 24, 2017 at 4:42 PM, Linus Walleij  
> wrote:
>> On Fri, Mar 24, 2017 at 4:22 PM, Jacopo Mondi  
>> wrote:
>>
>> I assume Geert will queue this driver even if it is outside of sh-pfc?
>
> OK for me, thanks. I was actually wondering about that ;-)

Thanks Geert, much appreciated.

Yours,
Linus Walleij

Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[Geert Uytterhoeven]

Hi Linus,

On Fri, Mar 24, 2017 at 4:42 PM, Linus Walleij  wrote:
> On Fri, Mar 24, 2017 at 4:22 PM, Jacopo Mondi  
> wrote:
>
> I assume Geert will queue this driver even if it is outside of sh-pfc?

OK for me, thanks. I was actually wondering about that ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[Linus Walleij]

On Fri, Mar 24, 2017 at 5:45 PM, jacopo  wrote:

> I initially created a whole new sub-directory where all the Renesas
> devices with this kind of pin controller would have gone
> (drivers/pinctrl/rz-pfc) but since as of now the only available
> hardware of that type is RZ/A1 and some of its variants, we decided to go
> with a single driver supporting that platform only.
> If more will come, we'll think about supporting them through this
> driver if possible, or create a dedicated directory.
>
> Are you ok with this?

Yep it's OK. It's no big deal to move it into a new subdir if many
new drivers start popping in anyway.

Right now I see the use of renesas,pins as the only big blocker,
I would much like it to use just pins = <>;

Yours,
Linus Walleij

Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[jacopo]

Hi Linus,

On Fri, Mar 24, 2017 at 04:42:47PM +0100, Linus Walleij wrote:
> On Fri, Mar 24, 2017 at 4:22 PM, Jacopo Mondi  
> wrote:
> 
> I assume Geert will queue this driver even if it is outside of sh-pfc?
> 
> > Add combined gpio and pin controller driver for Renesas RZ/A1
> > r7s72100 SoC.
> >
> > Signed-off-by: Jacopo Mondi 
> > ---
> >  drivers/pinctrl/Kconfig|  10 +
> >  drivers/pinctrl/Makefile   |   1 +
> >  drivers/pinctrl/pinctrl-rza1.c | 961 
> > +
> 
> So this is very different from the SH-PFC family and should not
> be in drivers/pinctrl/sh-pfc?
> 

Correct. The pin controller hardware in RZ/A(1) devices configures pin
functions per-pin and not per-group as the SH/R-Car family does.

There has been an attempt to support this platforms with the existing
sh-pfc/ infrastructure in the past (https://lwn.net/Articles/573222/)
which I re-proposed for v4.9, but that driver simply does not fit
this hardware which is different from the one found in R-Car
devices.

More on the background of this series in this email thread:
https://marc.info/?l=linux-gpio=148536779917834=2

I initially created a whole new sub-directory where all the Renesas
devices with this kind of pin controller would have gone
(drivers/pinctrl/rz-pfc) but since as of now the only available
hardware of that type is RZ/A1 and some of its variants, we decided to go
with a single driver supporting that platform only.
If more will come, we'll think about supporting them through this
driver if possible, or create a dedicated directory.

Are you ok with this?

Thanks
  j

> > +config PINCTRL_RZA1
> > +   bool "Renesas RZ/A1 gpio and pinctrl driver"
> > +   depends on OF
> > +   depends on ARCH_R7S72100 || COMPILE_TEST
> > +   select GENERIC_PINCTRL_GROUPS
> > +   select GENERIC_PINMUX_FUNCTIONS
> > +   select GENERIC_PINCONF
> 
> If it is also a GPIO driver I guess it should
> select GPIOLIB as well.
> 
> This was not possible in the past, but it is possible nowadays.
> 
> > +struct gpio_chip rza1_gpiochip_template = {
> > +   .request= rza1_gpio_request,
> > +   .free   = rza1_gpio_free,
> > +   .get_direction  = rza1_gpio_get_direction,
> > +   .direction_input= rza1_gpio_direction_input,
> > +   .direction_output   = rza1_gpio_direction_output,
> > +   .get= rza1_gpio_get,
> > +   .set= rza1_gpio_set,
> > +};
> 
> We now also have .set_multiple() and more interestingly
> .set_config() which can be backed by pinctrl if you want
> to e.g. support debouncing and/or open drain/open source.
> 
> Maybe this is stuff your pin controller can do, but not needed
> in the initial submission for sure.
> 
> > +static int rza1_pinmux_set(struct pinctrl_dev *pctldev, unsigned int 
> > selector,
> > +  unsigned int group)
> 
> Please name it rza1_set_mux() to correspond with the ops field.
> 
> Yours,
> Linus Walleij

Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[Linus Walleij]

On Fri, Mar 24, 2017 at 4:22 PM, Jacopo Mondi  wrote:

I assume Geert will queue this driver even if it is outside of sh-pfc?

> Add combined gpio and pin controller driver for Renesas RZ/A1
> r7s72100 SoC.
>
> Signed-off-by: Jacopo Mondi 
> ---
>  drivers/pinctrl/Kconfig|  10 +
>  drivers/pinctrl/Makefile   |   1 +
>  drivers/pinctrl/pinctrl-rza1.c | 961 
> +

So this is very different from the SH-PFC family and should not
be in drivers/pinctrl/sh-pfc?

> +config PINCTRL_RZA1
> +   bool "Renesas RZ/A1 gpio and pinctrl driver"
> +   depends on OF
> +   depends on ARCH_R7S72100 || COMPILE_TEST
> +   select GENERIC_PINCTRL_GROUPS
> +   select GENERIC_PINMUX_FUNCTIONS
> +   select GENERIC_PINCONF

If it is also a GPIO driver I guess it should
select GPIOLIB as well.

This was not possible in the past, but it is possible nowadays.

> +struct gpio_chip rza1_gpiochip_template = {
> +   .request= rza1_gpio_request,
> +   .free   = rza1_gpio_free,
> +   .get_direction  = rza1_gpio_get_direction,
> +   .direction_input= rza1_gpio_direction_input,
> +   .direction_output   = rza1_gpio_direction_output,
> +   .get= rza1_gpio_get,
> +   .set= rza1_gpio_set,
> +};

We now also have .set_multiple() and more interestingly
.set_config() which can be backed by pinctrl if you want
to e.g. support debouncing and/or open drain/open source.

Maybe this is stuff your pin controller can do, but not needed
in the initial submission for sure.

> +static int rza1_pinmux_set(struct pinctrl_dev *pctldev, unsigned int 
> selector,
> +  unsigned int group)

Please name it rza1_set_mux() to correspond with the ops field.

Yours,
Linus Walleij

[PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller

[Jacopo Mondi]

Add combined gpio and pin controller driver for Renesas RZ/A1
r7s72100 SoC.

Signed-off-by: Jacopo Mondi 
---
 drivers/pinctrl/Kconfig|  10 +
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/pinctrl-rza1.c | 961 +
 3 files changed, 972 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-rza1.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f8c2af..c9b55b9 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,6 +163,16 @@ config PINCTRL_ROCKCHIP
select GENERIC_IRQ_CHIP
select MFD_SYSCON
 
+config PINCTRL_RZA1
+   bool "Renesas RZ/A1 gpio and pinctrl driver"
+   depends on OF
+   depends on ARCH_R7S72100 || COMPILE_TEST
+   select GENERIC_PINCTRL_GROUPS
+   select GENERIC_PINMUX_FUNCTIONS
+   select GENERIC_PINCONF
+   help
+ This selects pinctrl driver for Renesas RZ/A1 platforms.
+
 config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a251f43..0c2328d2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_PALMAS)  += pinctrl-palmas.o
 obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
 obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SIRF) += sirf/
 obj-$(CONFIG_PINCTRL_SX150X)   += pinctrl-sx150x.o
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
new file mode 100644
index 000..0a4fc41
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -0,0 +1,961 @@
+/*
+ * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
+ *
+ * Copyright (C) 2017 Jacopo Mondi
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * This pincontroller/gpio combined driver support Renesas devices of RZ/A1
+ * family.
+ * This includes SoCs which are sub- or super- sets of this particular line,
+ * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020) are.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "core.h"
+#include "devicetree.h"
+#include "pinmux.h"
+
+#define DRIVER_NAME"pinctrl-rza1"
+
+#define RZA1_PINMUX_OF_ARGS2
+
+#define P_REG  0x
+#define PPR_REG0x0200
+#define PM_REG 0x0300
+#define PMC_REG0x0400
+#define PFC_REG0x0500
+#define PFCE_REG   0x0600
+#define PFCEA_REG  0x0a00
+#define PIBC_REG   0x4000
+#define PBDC_REG   0x4100
+#define PIPC_REG   0x4200
+#define RZA1_ADDR(mem, reg, port)  ((mem) + (reg) + ((port) * 4))
+
+#define RZA1_NPORTS12
+#define RZA1_PINS_PER_PORT 16
+#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
+#define RZA1_PIN_TO_PORT(pin)  ((pin) / RZA1_PINS_PER_PORT)
+#define RZA1_PIN_TO_OFFSET(pin)((pin) % RZA1_PINS_PER_PORT)
+
+/*
+ * Be careful here: the pin configuration subnodes in device tree enumerate
+ * alternate functions from 1 to 8; subtract 1 before using macros so to match
+ * register configuration which expects numbers from 0 to 7 instead.
+ */
+#define MUX_FUNC_OFFS  3
+#define MUX_FUNC_MASK  (BIT(MUX_FUNC_OFFS) - 1)
+#define MUX_FUNC_PFC_MASK  BIT(0)
+#define MUX_FUNC_PFCE_MASK BIT(1)
+#define MUX_FUNC_PFCEA_MASKBIT(2)
+#define MUX_CONF_BIDIR BIT(0)
+#define MUX_CONF_SWIO_INPUTBIT(1)
+#define MUX_CONF_SWIO_OUTPUT   BIT(2)
+
+/**
+ * rza1_pin_conf - describes a pin position, id, mux config and output value
+ *
+ * @id: the pin identifier from 0 to RZA1_NPINS
+ * @port: the port where pin sits on
+ * @offset: pin offset in the port
+ * @mux: alternate function configuration settings
+ * @value: output value to set the pin to
+ */
+struct rza1_pin_conf {
+   u16 id;
+   u8 port;
+   u8 offset;
+   u8 mux_conf;
+   u8 value;
+};
+
+/**
+ * rza1_port - describes a pin port
+ *
+ * This is mostly useful to lock register writes per-bank and not globally.
+ *
+ * @lock: protect access to HW registers
+ * @id: port number
+ * @base: logical address base
+ * @pins: pins sitting on this port
+ */
+struct rza1_port {
+