Re: [PATCH v7 5/5] clk: renesas: Renesas R9A06G032 clock driver

[kbuild test robot]

Hi Michel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on renesas-drivers/clk-renesas]
[also build test WARNING on v4.17-rc6]
[cannot apply to robh/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Michel-Pollet/dt-bindings-Add-the-r9a06g032-sysctrl-h-file/20180526-154235
base:   
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git 
clk-renesas
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/clk/renesas/r9a06g032-clocks.c:430:22: sparse: cast removes address 
>> space of expression
>> drivers/clk/renesas/r9a06g032-clocks.c:431:30: sparse: incorrect type in 
>> argument 1 (different address spaces) @@expected unsigned int [noderef] 
>> [usertype] *reg @@got eref] [usertype] *reg @@
   drivers/clk/renesas/r9a06g032-clocks.c:431:30:expected unsigned int 
[noderef] [usertype] *reg
   drivers/clk/renesas/r9a06g032-clocks.c:431:30:got unsigned int 
[usertype] *reg
   drivers/clk/renesas/r9a06g032-clocks.c:516:22: sparse: cast removes address 
space of expression
   drivers/clk/renesas/r9a06g032-clocks.c:528:38: sparse: incorrect type in 
argument 2 (different address spaces) @@expected unsigned int [noderef] 
[usertype] *reg @@got eref] [usertype] *reg @@
   drivers/clk/renesas/r9a06g032-clocks.c:528:38:expected unsigned int 
[noderef] [usertype] *reg
   drivers/clk/renesas/r9a06g032-clocks.c:528:38:got unsigned int 
[usertype] *reg

vim +430 drivers/clk/renesas/r9a06g032-clocks.c

   421  
   422  #define to_r9a06g032_divider(_hw) \
   423  container_of(_hw, struct r9a06g032_clk_div, hw)
   424  
   425  static unsigned long r9a06g032_divider_recalc_rate(
   426  struct clk_hw *hw,
   427  unsigned long parent_rate)
   428  {
   429  struct r9a06g032_clk_div *clk = to_r9a06g032_divider(hw);
 > 430  u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg;
 > 431  long div = clk_readl(reg);
   432  
   433  if (div < clk->min)
   434  div = clk->min;
   435  else if (div > clk->max)
   436  div = clk->max;
   437  return DIV_ROUND_UP(parent_rate, div);
   438  }
   439  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

[PATCH v7 5/5] clk: renesas: Renesas R9A06G032 clock driver

[Michel Pollet]

This provides a clock driver for the Renesas R09A06G032.
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.

Signed-off-by: Michel Pollet 
---
 drivers/clk/renesas/Kconfig|   6 +
 drivers/clk/renesas/Makefile   |   1 +
 drivers/clk/renesas/r9a06g032-clocks.c | 812 +
 3 files changed, 819 insertions(+)
 create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f9ba71311..9022bbe 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,6 +21,7 @@ config CLK_RENESAS
select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
+   select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -125,6 +126,11 @@ config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
 
+config CLK_R9A06G032
+   bool "Renesas R9A06G032 clock driver"
+   help
+ This is a driver for R9A06G032 clocks
+
 config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index fe5bac9..e4aa3d6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_CLK_R8A77970)+= r8a77970-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032)+= r9a06g032-clocks.o
 obj-$(CONFIG_CLK_SH73A0)   += clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c 
b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 000..ad61cda
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A09G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet , 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct r9a06g032_gate {
+   uint16_t gate, reset, ready, midle,
+   scon, mirack, mistat;
+};
+
+/* This is used to describe a clock for instantiation */
+struct r9a06g032_clkdesc {
+   const char *name;
+   uint32_t type: 3;
+   uint32_t index: 8;
+   uint32_t source : 8; /* source index + 1 (0 == none) */
+   /* these are used to populate the bitsel struct */
+   union {
+   struct r9a06g032_gate gate;
+   /* for dividers */
+   struct {
+   unsigned int div_min : 10, div_max : 10, reg: 10;
+   uint16_t div_table[4];
+   };
+   /* For fixed-factor ones */
+   uint16_t div;
+   unsigned int factor;
+   unsigned int frequency;
+   /* for dual gate */
+   struct {
+   uint16_t group : 1, index: 3;
+   uint16_t sel, g1, r1, g2, r2;
+   } dual;
+   };
+} __packed;
+
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
+   { .gate = _clk, .reset = _rst, \
+   .ready = _rdy, .midle = _midle, \
+   .scon = _scon, .mirack = _mirack, .mistat = _mistat }
+#define D_GATE(_idx, _n, _src, ...) \
+   { .type = K_GATE, .index = R9A06G032_##_idx, \
+   .source = 1 + R9A06G032_##_src, .name = _n, \
+   .gate = I_GATE(__VA_ARGS__), }
+#define D_FC(_idx, _n, _freq) \
+   { .type = K_FC, .index = R9A06G032_##_idx, .name = _n, .frequency = 
_freq, }
+#define D_FFC(_idx, _n, _src, _div) \
+   { .type = K_FFC, .index = R9A06G032_##_idx, \
+   .source = 1 + R9A06G032_##_src, .name = _n, \
+   .div = _div, }
+#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
+   { .type = K_DIV, .index = R9A06G032_##_idx, \
+   .source = 1 + R9A06G032_##_src, .name = _n, \
+   .reg = _reg, .div_min = _min, .div_max = _max, \
+   .div_table = { __VA_ARGS__ } }
+#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
+   { .type = K_DUALGATE, .index = R9A06G032_##_idx, \
+   .source = 1 + R9A06G032_##_src, .name = _n, \
+   .dual = { .group = _g, .index = _gi, \
+   .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
+
+enum { K_GATE = 0, K_FFC, K_FC, K_DIV, K_BITSEL, K_DUALGATE };
+
+static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = {
+   D_FC(CLKOUT, "clkout", 10),
+   D_FC(CLK_PLL_USB, "clk_pll_usb", 4800),
+   D_FFC(CLKOUT_D10, "clkout_d1