RE: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for the review!

> From: Geert Uytterhoeven, Sent: Thursday, April 12, 2018 9:23 PM
> 
> Hi Shimoda-san,
> 
> On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
>  wrote:

> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
> > @@ -0,0 +1,63 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> > +
> > +#include 
> > +
> > +/* r8a77990 CPG Core Clocks */
> 
> [...]
> 
> > +#define R8A77990_CLK_CSI0  47
> 
> Note that CSI0 is not listed in Table 8.2g ("R-Car E3").
> Probably it does exist, given:
>   - Table 8.11 ("Register Configuration") says CSI0CKCR exists on R-Car E3,
>   - Figure 25.6 ("CSI2 Block Diagram (R-Car E3)") shows CSI0.

I think so. I'm asking HW team about missing CSI0 in Table 8.2g now.

> > +#define R8A77990_CLK_POST3 48
> 
> I noticed these POSTx clocks have been added to all R-Car Gen3 clock tables.
> It doesn't look like we will ever need to refer them from DT, so I think we
> can treat them as internal clocks, and omit them from the DT bindings.
> 
> What do you think?

I agree with you. So, I will omit POSTx clocks from the DT bindings in v2 patch.

Best regards,
Yoshihiro Shimoda

Re: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda
 wrote:
> From: Takeshi Kihara 
>
> This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
>
> Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included,
> as they are used as internal clock sources only, and never referenced
> from DT.
>
> Signed-off-by: Takeshi Kihara 
> [shimoda: add SPDX-License-Identifier]
> Signed-off-by: Yoshihiro Shimoda 

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
> +
> +#include 
> +
> +/* r8a77990 CPG Core Clocks */

[...]

> +#define R8A77990_CLK_CSI0  47

Note that CSI0 is not listed in Table 8.2g ("R-Car E3").
Probably it does exist, given:
  - Table 8.11 ("Register Configuration") says CSI0CKCR exists on R-Car E3,
  - Figure 25.6 ("CSI2 Block Diagram (R-Car E3)") shows CSI0.

> +#define R8A77990_CLK_POST3 48

I noticed these POSTx clocks have been added to all R-Car Gen3 clock tables.
It doesn't look like we will ever need to refer them from DT, so I think we
can treat them as internal clocks, and omit them from the DT bindings.

What do you think?
Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds