[PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread Padmavathi Venna 
This patchset does the following:

1. Move duplicated code to common place
[PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
SPI platform devices are defined in respective machine folder of
Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
So all SPI platform devices are moved to a common place.

[PATCH 2/7] ARM: SAMSUNG: Define common macro for SPI physical address

[PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs
Each SoC has it's own set of clock sources for SPI.So they are defined in
respective machine folder.

[PATCH 4/7] ARM: SAMSUNG: Create SPI device setup files in
respective machine folder

[PATCH 5/7] ARM: SAMSUNG: Add SPI platform specific code
As SPI platform devices are moved to common place some platform specific
code need to be initialized in the respective machine file.

[PATCH 6/7] SPI: S5PC100: Enable the SPI driver for S5PC100

[PATCH 7/7] SPI: S5PV210: Enable the SPI driver for S5PV210

 arch/arm/mach-s3c64xx/Kconfig|   14 ++
 arch/arm/mach-s3c64xx/Makefile   |3 +-
 arch/arm/mach-s3c64xx/dev-spi.c  |  177 -
 arch/arm/mach-s3c64xx/include/mach/map.h |2 +
 arch/arm/mach-s3c64xx/include/mach/spi-clocks.h  |6 +
 arch/arm/mach-s3c64xx/mach-smdk6410.c|   11 +
 arch/arm/mach-s3c64xx/setup-spi0.c   |   21 ++
 arch/arm/mach-s3c64xx/setup-spi1.c   |   21 ++
 arch/arm/mach-s5p64x0/Kconfig|   20 ++-
 arch/arm/mach-s5p64x0/Makefile   |3 +-
 arch/arm/mach-s5p64x0/dev-spi.c  |  222 -
 arch/arm/mach-s5p64x0/include/mach/map.h |2 +
 arch/arm/mach-s5p64x0/include/mach/spi-clocks.h  |5 +
 arch/arm/mach-s5p64x0/mach-smdk6440.c|   11 +
 arch/arm/mach-s5p64x0/mach-smdk6450.c|   11 +
 arch/arm/mach-s5p64x0/setup-spi0.c   |   31 +++
 arch/arm/mach-s5p64x0/setup-spi1.c   |   31 +++
 arch/arm/mach-s5pc100/Kconfig|   21 ++
 arch/arm/mach-s5pc100/Makefile   |4 +-
 arch/arm/mach-s5pc100/dev-spi.c  |  223 --
 arch/arm/mach-s5pc100/include/mach/map.h |3 +
 arch/arm/mach-s5pc100/include/mach/spi-clocks.h  |6 +
 arch/arm/mach-s5pc100/mach-smdkc100.c|   19 ++
 arch/arm/mach-s5pc100/setup-spi0.c   |   21 ++
 arch/arm/mach-s5pc100/setup-spi1.c   |   21 ++
 arch/arm/mach-s5pc100/setup-spi2.c   |   23 +++
 arch/arm/mach-s5pv210/Kconfig|   14 ++
 arch/arm/mach-s5pv210/Makefile   |3 +-
 arch/arm/mach-s5pv210/dev-spi.c  |  173 -
 arch/arm/mach-s5pv210/include/mach/map.h |2 +
 arch/arm/mach-s5pv210/include/mach/spi-clocks.h  |5 +
 arch/arm/mach-s5pv210/mach-smdkv210.c|   12 ++
 arch/arm/mach-s5pv210/setup-spi0.c   |   23 +++
 arch/arm/mach-s5pv210/setup-spi1.c   |   23 +++
 arch/arm/plat-samsung/Kconfig|   15 ++-
 arch/arm/plat-samsung/Makefile   |3 +
 arch/arm/plat-samsung/dev-spi0.c |   87 +
 arch/arm/plat-samsung/dev-spi1.c |   87 +
 arch/arm/plat-samsung/dev-spi2.c |   87 +
 arch/arm/plat-samsung/include/plat/devs.h|   12 +-
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   18 ++-
 drivers/spi/Kconfig  |3 +-
 42 files changed, 677 insertions(+), 822 deletions(-)
 delete mode 100644 arch/arm/mach-s3c64xx/dev-spi.c
 create mode 100644 arch/arm/mach-s3c64xx/setup-spi0.c
 create mode 100644 arch/arm/mach-s3c64xx/setup-spi1.c
 delete mode 100644 arch/arm/mach-s5p64x0/dev-spi.c
 create mode 100644 arch/arm/mach-s5p64x0/setup-spi0.c
 create mode 100644 arch/arm/mach-s5p64x0/setup-spi1.c
 delete mode 100644 arch/arm/mach-s5pc100/dev-spi.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi0.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi1.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi2.c
 delete mode 100644 arch/arm/mach-s5pv210/dev-spi.c
 create mode 100644 arch/arm/mach-s5pv210/setup-spi0.c
 create mode 100644 arch/arm/mach-s5pv210/setup-spi1.c
 create mode 100644 arch/arm/plat-samsung/dev-spi0.c
 create mode 100644 arch/arm/plat-samsung/dev-spi1.c
 create mode 100644 arch/arm/plat-samsung/dev-spi2.c

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[PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung

2011-06-30 Thread Padmavathi Venna 
Move all SPI platform device definitions from respective machine
folder to plat-samsung

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 arch/arm/mach-s3c64xx/dev-spi.c  |  177 -
 arch/arm/mach-s5p64x0/dev-spi.c  |  222 -
 arch/arm/mach-s5pc100/dev-spi.c  |  223 --
 arch/arm/mach-s5pv210/dev-spi.c  |  173 -
 arch/arm/plat-samsung/Kconfig|   15 ++-
 arch/arm/plat-samsung/Makefile   |3 +
 arch/arm/plat-samsung/dev-spi0.c |   87 +
 arch/arm/plat-samsung/dev-spi1.c |   87 +
 arch/arm/plat-samsung/dev-spi2.c |   87 +
 arch/arm/plat-samsung/include/plat/devs.h|   12 +-
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   18 ++-
 11 files changed, 289 insertions(+), 815 deletions(-)
 delete mode 100644 arch/arm/mach-s3c64xx/dev-spi.c
 delete mode 100644 arch/arm/mach-s5p64x0/dev-spi.c
 delete mode 100644 arch/arm/mach-s5pc100/dev-spi.c
 delete mode 100644 arch/arm/mach-s5pv210/dev-spi.c
 create mode 100644 arch/arm/plat-samsung/dev-spi0.c
 create mode 100644 arch/arm/plat-samsung/dev-spi1.c
 create mode 100644 arch/arm/plat-samsung/dev-spi2.c

diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 82db072..000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/dev-spi.c
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- * Jaswinder Singh jassi.b...@samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include linux/kernel.h
-#include linux/string.h
-#include linux/platform_device.h
-#include linux/dma-mapping.h
-#include linux/gpio.h
-
-#include mach/dma.h
-#include mach/map.h
-#include mach/spi-clocks.h
-#include mach/irqs.h
-
-#include plat/s3c64xx-spi.h
-#include plat/gpio-cfg.h
-#include plat/devs.h
-
-static char *spi_src_clks[] = {
-   [S3C64XX_SPI_SRCCLK_PCLK] = pclk,
-   [S3C64XX_SPI_SRCCLK_SPIBUS] = spi-bus,
-   [S3C64XX_SPI_SRCCLK_48M] = spi_48m,
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
-{
-   unsigned int base;
-
-   switch (pdev-id) {
-   case 0:
-   base = S3C64XX_GPC(0);
-   break;
-
-   case 1:
-   base = S3C64XX_GPC(4);
-   break;
-
-   default:
-   dev_err(pdev-dev, Invalid SPI Controller number!);
-   return -EINVAL;
-   }
-
-   s3c_gpio_cfgall_range(base, 3,
- S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-
-   return 0;
-}
-
-static struct resource s3c64xx_spi0_resource[] = {
-   [0] = {
-   .start = S3C64XX_PA_SPI0,
-   .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
-   .flags = IORESOURCE_MEM,
-   },
-   [1] = {
-   .start = DMACH_SPI0_TX,
-   .end   = DMACH_SPI0_TX,
-   .flags = IORESOURCE_DMA,
-   },
-   [2] = {
-   .start = DMACH_SPI0_RX,
-   .end   = DMACH_SPI0_RX,
-   .flags = IORESOURCE_DMA,
-   },
-   [3] = {
-   .start = IRQ_SPI0,
-   .end   = IRQ_SPI0,
-   .flags = IORESOURCE_IRQ,
-   },
-};
-
-static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-   .cfg_gpio = s3c64xx_spi_cfg_gpio,
-   .fifo_lvl_mask = 0x7f,
-   .rx_lvl_offset = 13,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s3c64xx_device_spi0 = {
-   .name = s3c64xx-spi,
-   .id   = 0,
-   .num_resources= ARRAY_SIZE(s3c64xx_spi0_resource),
-   .resource = s3c64xx_spi0_resource,
-   .dev = {
-   .dma_mask   = spi_dmamask,
-   .coherent_dma_mask  = DMA_BIT_MASK(32),
-   .platform_data = s3c64xx_spi0_pdata,
-   },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi0);
-
-static struct resource s3c64xx_spi1_resource[] = {
-   [0] = {
-   .start = S3C64XX_PA_SPI1,
-   .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
-   .flags = IORESOURCE_MEM,
-   },
-   [1] = {
-   .start = DMACH_SPI1_TX,
-   .end   = DMACH_SPI1_TX,
-   .flags = IORESOURCE_DMA,
-   },
-   [2] = {
-   .start = DMACH_SPI1_RX,
-

[PATCH 2/7] ARM: SAMSUNG: Define common macro for SPI physical address

2011-06-30 Thread Padmavathi Venna 
A common macro has been defined for SPI physical address as
SPI has been made common across all the S3C64xx and S5P series.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 arch/arm/mach-s3c64xx/include/mach/map.h |2 ++
 arch/arm/mach-s5p64x0/include/mach/map.h |2 ++
 arch/arm/mach-s5pc100/include/mach/map.h |3 +++
 arch/arm/mach-s5pv210/include/mach/map.h |2 ++
 4 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h 
b/arch/arm/mach-s3c64xx/include/mach/map.h
index a1f13f0..1082e2e 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -122,6 +122,8 @@
 #define S3C_VA_USB_HSPHY   S3C64XX_VA_USB_HSPHY
 #define S3C_PA_RTC S3C64XX_PA_RTC
 #define S3C_PA_WDT S3C64XX_PA_WATCHDOG
+#define S3C_PA_SPI0S3C64XX_PA_SPI0
+#define S3C_PA_SPI1S3C64XX_PA_SPI1
 
 #define SAMSUNG_PA_ADC S3C64XX_PA_ADC
 #define SAMSUNG_PA_CFCON   S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h 
b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c9125..13f453c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -64,6 +64,8 @@
 #define S3C_PA_IIC1S5P6440_PA_IIC1
 #define S3C_PA_RTC S5P64X0_PA_RTC
 #define S3C_PA_WDT S5P64X0_PA_WDT
+#define S3C_PA_SPI0S5P64X0_PA_SPI0
+#define S3C_PA_SPI1S5P64X0_PA_SPI1
 
 #define S5P_PA_CHIPID  S5P64X0_PA_CHIPID
 #define S5P_PA_SROMC   S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h 
b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b7..54bc4f8 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
 #define S3C_PA_USB_HSOTG   S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY   S5PC100_PA_USB_HSPHY
 #define S3C_PA_WDT S5PC100_PA_WATCHDOG
+#define S3C_PA_SPI0S5PC100_PA_SPI0
+#define S3C_PA_SPI1S5PC100_PA_SPI1
+#define S3C_PA_SPI2S5PC100_PA_SPI2
 
 #define S5P_PA_CHIPID  S5PC100_PA_CHIPID
 #define S5P_PA_FIMC0   S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h 
b/arch/arm/mach-s5pv210/include/mach/map.h
index 1dd5883..3fdacfa 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -101,6 +101,8 @@
 #define S3C_PA_RTC S5PV210_PA_RTC
 #define S3C_PA_USB_HSOTG   S5PV210_PA_HSOTG
 #define S3C_PA_WDT S5PV210_PA_WATCHDOG
+#define S3C_PA_SPI0S5PV210_PA_SPI0
+#define S3C_PA_SPI1S5PV210_PA_SPI1
 
 #define S5P_PA_CHIPID  S5PV210_PA_CHIPID
 #define S5P_PA_FIMC0   S5PV210_PA_FIMC0
-- 
1.7.0.4

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[PATCH 4/7] ARM: SAMSUNG: Create SPI device setup files in respective machine folder

2011-06-30 Thread Padmavathi Venna 
SPI device specific setup files are created for S3C64XX,S5P64X0,S5PC100
and S5PV210 to configure the GPIO pins corresponding to specific SoC.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 arch/arm/mach-s3c64xx/Kconfig  |   14 ++
 arch/arm/mach-s3c64xx/Makefile |3 ++-
 arch/arm/mach-s3c64xx/setup-spi0.c |   21 +
 arch/arm/mach-s3c64xx/setup-spi1.c |   21 +
 arch/arm/mach-s5p64x0/Kconfig  |   20 ++--
 arch/arm/mach-s5p64x0/Makefile |3 ++-
 arch/arm/mach-s5p64x0/setup-spi0.c |   31 +++
 arch/arm/mach-s5p64x0/setup-spi1.c |   31 +++
 arch/arm/mach-s5pc100/Kconfig  |   21 +
 arch/arm/mach-s5pc100/Makefile |4 +++-
 arch/arm/mach-s5pc100/setup-spi0.c |   21 +
 arch/arm/mach-s5pc100/setup-spi1.c |   21 +
 arch/arm/mach-s5pc100/setup-spi2.c |   23 +++
 arch/arm/mach-s5pv210/Kconfig  |   14 ++
 arch/arm/mach-s5pv210/Makefile |3 ++-
 arch/arm/mach-s5pv210/setup-spi0.c |   23 +++
 arch/arm/mach-s5pv210/setup-spi1.c |   23 +++
 17 files changed, 291 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/setup-spi0.c
 create mode 100644 arch/arm/mach-s3c64xx/setup-spi1.c
 create mode 100644 arch/arm/mach-s5p64x0/setup-spi0.c
 create mode 100644 arch/arm/mach-s5p64x0/setup-spi1.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi0.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi1.c
 create mode 100644 arch/arm/mach-s5pc100/setup-spi2.c
 create mode 100644 arch/arm/mach-s5pv210/setup-spi0.c
 create mode 100644 arch/arm/mach-s5pv210/setup-spi1.c

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 4e2c371..d2acce0 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -77,6 +77,16 @@ config S3C64XX_SETUP_SDHCI_GPIO
help
  Common setup code for S3C64XX SDHCI GPIO configurations
 
+config S3C64XX_SETUP_SPI0
+   bool
+   help
+ Common setup code for SPI channel 0
+
+config S3C64XX_SETUP_SPI1
+   bool
+   help
+ Common setup code for SPI channel 1
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -142,6 +152,8 @@ config MACH_SMDK6410
select S3C_DEV_USB_HOST
select S3C_DEV_USB_HSOTG
select S3C_DEV_WDT
+   select SAMSUNG_DEV_SPI0
+   select SAMSUNG_DEV_SPI1
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -150,6 +162,8 @@ config MACH_SMDK6410
select S3C64XX_SETUP_IDE
select S3C64XX_SETUP_FB_24BPP
select S3C64XX_SETUP_KEYPAD
+   select S3C64XX_SETUP_SPI0
+   select S3C64XX_SETUP_SPI1
help
  Machine support for the Samsung SMDK6410
 
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 88d7fd2..f3d2f81 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -40,6 +40,8 @@ obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI0) += setup-spi0.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI1) += setup-spi1.o
 
 # PM
 
@@ -65,6 +67,5 @@ obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
 
 obj-y  += dev-uart.o
 obj-y  += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)  += dev-spi.o
 obj-$(CONFIG_S3C64XX_DEV_TS)   += dev-ts.o
 obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o
diff --git a/arch/arm/mach-s3c64xx/setup-spi0.c 
b/arch/arm/mach-s3c64xx/setup-spi0.c
new file mode 100644
index 000..bdf881d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi0.c
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-s3c64xx/setup-spi0.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/gpio.h
+#include linux/platform_device.h
+
+#include plat/gpio-cfg.h
+
+int s3c_spi0_cfg_gpio(struct platform_device *dev)
+{
+   s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
+   S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+   return 0;
+}
diff --git a/arch/arm/mach-s3c64xx/setup-spi1.c 
b/arch/arm/mach-s3c64xx/setup-spi1.c
new file mode 100644
index 000..3d8acad
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi1.c
@@ -0,0 +1,21 @@
+/* linux/arch/arm/mach-s3c64xx/setup-spi1.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ * http://www.samsung.com/
+ *
+ * This program is free software; you

[PATCH 7/7] SPI: S5PV210: Enable the SPI driver for S5PV210

2011-06-30 Thread Padmavathi Venna 
The SPI module on S5PV210 is similar to the earlier Samsung SoCs like
S3C64XX. Enable the existing SPI driver for use on S5PV210.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 drivers/spi/Kconfig |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 91d607b..ed1ebea 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -340,7 +340,8 @@ config SPI_S3C24XX_GPIO
 
 config SPI_S3C64XX
tristate Samsung S3C64XX series type SPI
-   depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_S5PC100)
+   depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_S5PC100 \
+   || ARCH_S5PV210)
select S3C64XX_DMA if ARCH_S3C64XX
help
  SPI driver for Samsung S3C64XX and newer SoCs.
-- 
1.7.0.4

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[PATCH 1/2] ARM: SAMSUNG: Added tx_st_done variable in the platform data of SPI

2011-06-30 Thread Padmavathi Venna 
tx_st_done is required for checking the transmission status of SPI
channels with different fifo levels

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 arch/arm/mach-s3c64xx/mach-smdk6410.c|2 ++
 arch/arm/mach-s5p64x0/mach-smdk6440.c|2 ++
 arch/arm/mach-s5p64x0/mach-smdk6450.c|2 ++
 arch/arm/mach-s5pc100/mach-smdkc100.c|3 +++
 arch/arm/mach-s5pv210/mach-smdkv210.c|2 ++
 arch/arm/plat-samsung/dev-spi0.c |1 +
 arch/arm/plat-samsung/dev-spi1.c |1 +
 arch/arm/plat-samsung/dev-spi2.c |1 +
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |2 ++
 9 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c 
b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ff31a3d..dce89aa 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -212,11 +212,13 @@ static struct platform_device smdk6410_smsc911x = {
 static struct s3c64xx_spi_info s3c_spi0_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 13,
+   .tx_st_done = 21,
 };
 
 static struct s3c64xx_spi_info s3c_spi1_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 13,
+   .tx_st_done = 21,
 };
 
 #ifdef CONFIG_REGULATOR
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c 
b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 03469bc..7488feb 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -134,11 +134,13 @@ static struct platform_device smdk6440_backlight_device = 
{
 static struct s3c64xx_spi_info s3c_spi0_pdata __initdata = {
.fifo_lvl_mask  = 0x1ff,
.rx_lvl_offset  = 15,
+   .tx_st_done = 25,
 };
 
 static struct s3c64xx_spi_info s3c_spi1_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 15,
+   .tx_st_done = 25,
 };
 
 static struct platform_device *smdk6440_devices[] __initdata = {
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c 
b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 4048447..e7b2560 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -152,11 +152,13 @@ static struct platform_device smdk6450_backlight_device = 
{
 static struct s3c64xx_spi_info s3c_spi0_pdata __initdata = {
.fifo_lvl_mask  = 0x1ff,
.rx_lvl_offset  = 15,
+   .tx_st_done = 25,
 };
 
 static struct s3c64xx_spi_info s3c_spi1_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 15,
+   .tx_st_done = 25,
 };
 
 static struct platform_device *smdk6450_devices[] __initdata = {
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c 
b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 127f7b6..4e87530 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -223,18 +223,21 @@ static struct s3c64xx_spi_info s3c_spi0_pdata __initdata 
= {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 13,
.high_speed = 1,
+   .tx_st_done = 21,
 };
 
 static struct s3c64xx_spi_info s3c_spi1_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 13,
.high_speed = 1,
+   .tx_st_done = 21,
 };
 
 static struct s3c64xx_spi_info s3c_spi2_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 13,
.high_speed = 1,
+   .tx_st_done = 21,
 };
 
 static struct platform_device *smdkc100_devices[] __initdata = {
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c 
b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 8978757..71af473 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -254,12 +254,14 @@ static struct s3c64xx_spi_info s3c_spi0_pdata __initdata 
= {
.fifo_lvl_mask  = 0x1ff,
.rx_lvl_offset  = 15,
.high_speed = 1,
+   .tx_st_done = 25,
 };
 
 static struct s3c64xx_spi_info s3c_spi1_pdata __initdata = {
.fifo_lvl_mask  = 0x7f,
.rx_lvl_offset  = 15,
.high_speed = 1,
+   .tx_st_done = 25,
 };
 static struct platform_device *smdkv210_devices[] __initdata = {
s3c_device_adc,
diff --git a/arch/arm/plat-samsung/dev-spi0.c b/arch/arm/plat-samsung/dev-spi0.c
index 3d2c8bf..18f379e 100644
--- a/arch/arm/plat-samsung/dev-spi0.c
+++ b/arch/arm/plat-samsung/dev-spi0.c
@@ -71,6 +71,7 @@ void __init s3c_spi0_set_info(struct s3c64xx_spi_info *pd,
}
spi_info-fifo_lvl_mask = pd-fifo_lvl_mask;
spi_info-rx_lvl_offset = pd-rx_lvl_offset;
+   spi_info-tx_st_done = pd-tx_st_done;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr  0
|| src_clk_nr  ARRAY_SIZE(spi_src_clks)) {
diff --git a/arch/arm/plat-samsung/dev-spi1.c b/arch/arm/plat-samsung/dev-spi1.c
index 2aaa251..2a80c5d 100644
---

[PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread Padmavathi Venna 
Fixed the bug in transmission status check for 64 bytes FIFO
level.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 drivers/spi/spi_s3c64xx.c |4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c
index 795828b..8945e20 100644
--- a/drivers/spi/spi_s3c64xx.c
+++ b/drivers/spi/spi_s3c64xx.c
@@ -116,9 +116,7 @@
(((i)-fifo_lvl_mask + 1))) \
? 1 : 0)
 
-#define S3C64XX_SPI_ST_TX_DONE(v, i) v)  (i)-rx_lvl_offset)  \
-   (((i)-fifo_lvl_mask + 1)  1)) \
-   ? 1 : 0)
+#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v)  (1  (i)-tx_st_done)) ? 1 : 0)
 #define TX_FIFO_LVL(v, i) (((v)  6)  (i)-fifo_lvl_mask)
 #define RX_FIFO_LVL(v, i) (((v)  (i)-rx_lvl_offset)  (i)-fifo_lvl_mask)
 
-- 
1.7.0.4

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[PATCH] ARM: EXYNOS4: Add SPI support

2011-06-30 Thread Padmavathi Venna 
Add SPI Support
Add SPI setup files for GPIO configurations
Define SPI source clocks
Add SPI platform specific code
Enable the existing SPI driver

Signed-off-by: Padmavathi Venna padm...@samsung.com
---
 arch/arm/mach-exynos4/Kconfig   |   21 +++
 arch/arm/mach-exynos4/Makefile  |4 +++
 arch/arm/mach-exynos4/include/mach/irqs.h   |4 +++
 arch/arm/mach-exynos4/include/mach/map.h|7 ++
 arch/arm/mach-exynos4/include/mach/spi-clocks.h |   21 +++
 arch/arm/mach-exynos4/mach-smdkv310.c   |   25 +++
 arch/arm/mach-exynos4/setup-spi0.c  |   23 +
 arch/arm/mach-exynos4/setup-spi1.c  |   23 +
 arch/arm/mach-exynos4/setup-spi2.c  |   23 +
 drivers/spi/Kconfig |2 +-
 10 files changed, 152 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/include/mach/spi-clocks.h
 create mode 100644 arch/arm/mach-exynos4/setup-spi0.c
 create mode 100644 arch/arm/mach-exynos4/setup-spi1.c
 create mode 100644 arch/arm/mach-exynos4/setup-spi2.c

diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1413778..953eec2 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -96,6 +96,21 @@ config EXYNOS4_SETUP_USB_PHY
help
  Common setup code for USB PHY controller
 
+config EXYNOS4_SETUP_SPI0
+   bool
+   help
+ Common setup code for SPI channel 0
+
+config EXYNOS4_SETUP_SPI1
+   bool
+   help
+ Common setup code for SPI channel 1
+
+config EXYNOS4_SETUP_SPI2
+   bool
+   help
+ Common setup code for SPI channel 2
+
 # machine support
 
 menu EXYNOS4 Machines
@@ -128,11 +143,17 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select SAMSUNG_DEV_KEYPAD
+   select SAMSUNG_DEV_SPI0
+   select SAMSUNG_DEV_SPI1
+   select SAMSUNG_DEV_SPI2
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
+   select EXYNOS4_SETUP_SPI0
+   select EXYNOS4_SETUP_SPI1
+   select EXYNOS4_SETUP_SPI2
help
  Machine support for Samsung SMDKV310
 
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..ccbd8fa 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -57,3 +57,7 @@ obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
 
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)+= setup-usb-phy.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI0)+= setup-spi0.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI1)+= setup-spi1.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI2)+= setup-spi2.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI0)+= setup-spi0.o
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d03730..edffb30 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -103,6 +103,10 @@
 #define IRQ_IIC6   COMBINER_IRQ(27, 6)
 #define IRQ_IIC7   COMBINER_IRQ(27, 7)
 
+#define IRQ_SPI0   COMBINER_IRQ(28, 0)
+#define IRQ_SPI1   COMBINER_IRQ(28, 1)
+#define IRQ_SPI2   COMBINER_IRQ(28, 2)
+
 #define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
 #define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
 #define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h 
b/arch/arm/mach-exynos4/include/mach/map.h
index 57d8074..8de8952 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -110,6 +110,10 @@
 
 #define EXYNOS4_PA_IIC(x)  (0x1386 + ((x) * 0x1))
 
+#define EXYNOS4_PA_SPI00x1392
+#define EXYNOS4_PA_SPI10x1393
+#define EXYNOS4_PA_SPI20x1394
+
 #define EXYNOS4_PA_AC970x139A
 
 #define EXYNOS4_PA_SPDIF   0x139B
@@ -134,6 +138,9 @@
 #define S3C_PA_IIC7EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC EXYNOS4_PA_RTC
 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
+#define S3C_PA_SPI0EXYNOS4_PA_SPI0
+#define S3C_PA_SPI1EXYNOS4_PA_SPI1
+#define S3C_PA_SPI2EXYNOS4_PA_SPI2
 
 #define S5P_PA_CHIPID  EXYNOS4_PA_CHIPID
 #define S5P_PA_FIMC0   EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos4/include/mach/spi-clocks.h 
b/arch/arm/mach-exynos4/include/mach/spi-clocks.h
new file mode 100644
index 000..7af25a6
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/spi-clocks.h
@@ -0,0

Re: [PATCH 1/7] ARM: EXYNOS4: Add external GIC io memory mapping

2011-06-30 Thread MyungJoo Ham 
On Mon, Jun 20, 2011 at 4:34 PM, Changhwan Youn chaos.y...@samsung.com wrote:
 This patch adds external GIC io memory mapping
 to support external GIC on EXYNOS4.

 Signed-off-by: Changhwan Youn chaos.y...@samsung.com
 ---
  arch/arm/mach-exynos4/cpu.c              |   10 ++
  arch/arm/mach-exynos4/include/mach/map.h |    5 +++--
  arch/arm/plat-s5p/include/plat/map-s5p.h |    5 +++--
  3 files changed, 16 insertions(+), 4 deletions(-)

 diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
 index 1196f39..6a1ed74 100644
 --- a/arch/arm/mach-exynos4/cpu.c
 +++ b/arch/arm/mach-exynos4/cpu.c
 @@ -107,6 +107,16 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(EXYNOS4_PA_AUDSS),
                .length         = SZ_1K,
                .type           = MT_DEVICE,
 +       }, {
 +               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 +               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 +               .length         = SZ_64K,
 +               .type           = MT_DEVICE,
 +       }, {
 +               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 +               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 +               .length         = SZ_64K,
 +               .type           = MT_DEVICE,
        },
  };

 diff --git a/arch/arm/mach-exynos4/include/mach/map.h 
 b/arch/arm/mach-exynos4/include/mach/map.h
 index 57d8074..9d5d797 100644
 --- a/arch/arm/mach-exynos4/include/mach/map.h
 +++ b/arch/arm/mach-exynos4/include/mach/map.h
 @@ -61,10 +61,11 @@

  #define EXYNOS4_PA_COMBINER            0x10448000

Isn't this 0x1044 if we are going to use External GIC?

The user manual says it's 0x1044 for Ext-GIC and 0x10448000 for
Internal-GIC.


-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 6:08 PM, Padmavathi Venna padm...@samsung.com wrote:
 Fixed the bug in transmission status check for 64 bytes FIFO
 level.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  drivers/spi/spi_s3c64xx.c |    4 +---
  1 files changed, 1 insertions(+), 3 deletions(-)

 diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c
 index 795828b..8945e20 100644
 --- a/drivers/spi/spi_s3c64xx.c
 +++ b/drivers/spi/spi_s3c64xx.c
 @@ -116,9 +116,7 @@
                                        (((i)-fifo_lvl_mask + 1))) \
                                        ? 1 : 0)

 -#define S3C64XX_SPI_ST_TX_DONE(v, i) v)  (i)-rx_lvl_offset)  \
 -                                       (((i)-fifo_lvl_mask + 1)  1)) \
 -                                       ? 1 : 0)
 +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v)  (1  (i)-tx_st_done)) ? 1 : 0)

IIRC the macro is already designed to deduct tx-done levels from other fields.
Could you please _explain_ with one example where it fails ? It is
difficult to see without
numbers.

Thanks,
-Jassi
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Re: [PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 5:55 PM, Padmavathi Venna padm...@samsung.com wrote:
 This patchset does the following:

 1. Move duplicated code to common place
 [PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
 SPI platform devices are defined in respective machine folder of
 Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
 So all SPI platform devices are moved to a common place.

The machine specific code is put in machine specific location for some reason.
And the code is not duplicated, it's mostly data structures
initialized with machine
specific values.

Have you considered if it would still be possible to build kernel
image supporting
more than 1 soc after your changes ?
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[PATCH v3 0/6] Update Samsung-SoC ADC to support recent CPUs

2011-06-30 Thread MyungJoo Ham 
Patch 1/6: Add regulator support in ADC driver.
If CONFIG_REGULATOR is enabled, vdd regulator for the ADC driver
(e.g., s5p-adc) should exist for the adc driver.

Patch 2/6: Channel selection method for S5PC110 and Exynos4
Recent Samsung SoCs have different register addresses for
channel selection. Use s5p-adc to support such chips.

Patch 3/6: Bugfix for suspend/resume of ADC driver.

Patch 4/6: Support ADC at Exynos4
Define register addresses and device name for Exynos4

Patch 5/6: Support ADC at S5PC110/S5PV210
Correct ADC device name for S5PC110/S5PV210

Patch 6/6: Header file correction (plat/devs.h)
The long-overdue bugfix for compiler errors. ADC for Exynos4 fails to
be compiled without this patch.


MyungJoo Ham (6):
  Samsung SoC ADC: use regulator (VDD for ADC).
  Samsung SoC ADC: Channel selection for S5PV210, S5PC110, and Exynos4
  Samsung SoC ADC: Revise PM for 12-bit ADC operations
  ARM: EXYNOS4: Support ADC
  ARM: S5PC110/S5PV210: Support ADC
  Samsung SoC: header file revised to prevent declaring duplicated.

 arch/arm/mach-exynos4/Kconfig |1 +
 arch/arm/mach-exynos4/cpu.c   |4 +
 arch/arm/mach-exynos4/include/mach/irqs.h |3 +
 arch/arm/mach-exynos4/include/mach/map.h  |5 ++
 arch/arm/mach-s5pv210/cpu.c   |2 +-
 arch/arm/plat-samsung/adc.c   |   84 +++--
 arch/arm/plat-samsung/include/plat/devs.h |5 ++
 arch/arm/plat-samsung/include/plat/regs-adc.h |1 +
 8 files changed, 84 insertions(+), 21 deletions(-)

-- 
1.7.4.1

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[PATCH v3 2/6] Samsung SoC ADC: Channel selection for S5PV210, S5PC110, and Exynos4

2011-06-30 Thread MyungJoo Ham 
In S5PV210/S5PC110/Exynos4, ADCMUX channel selection uses ADCMUX
register, not ADCCON register. This patch corrects the behavior of
Samsung-ADC for such cpus.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
updates from v2
- Renamed internal device names.
---
 arch/arm/plat-samsung/adc.c   |   29 
 arch/arm/plat-samsung/include/plat/regs-adc.h |1 +
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 2224128..45cc7e6 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -40,8 +40,9 @@
  */
 
 enum s3c_cpu_type {
-   TYPE_S3C24XX,
-   TYPE_S3C64XX
+   TYPE_ADCV1, /* S3C24XX */
+   TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
+   TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
 };
 
 struct s3c_adc_client {
@@ -93,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
  struct s3c_adc_client *client)
 {
unsigned con = readl(adc-regs + S3C2410_ADCCON);
+   enum s3c_cpu_type cpu = platform_get_device_id(adc-pdev)-driver_data;
 
client-select_cb(client, 1);
 
@@ -100,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
con = ~S3C2410_ADCCON_STDBM;
con = ~S3C2410_ADCCON_STARTMASK;
 
-   if (!client-is_ts)
-   con |= S3C2410_ADCCON_SELMUX(client-channel);
+   if (!client-is_ts) {
+   if (cpu == TYPE_ADCV3)
+   writel(client-channel  0xf, adc-regs + S5P_ADCMUX);
+   else
+   con |= S3C2410_ADCCON_SELMUX(client-channel);
+   }
 
writel(con, adc-regs + S3C2410_ADCCON);
 }
@@ -287,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
 
client-nr_samples--;
 
-   if (cpu == TYPE_S3C64XX) {
-   /* S3C64XX ADC resolution is 12-bit */
+   if (cpu != TYPE_ADCV1) {
+   /* S3C64XX/S5P ADC resolution is 12-bit */
data0 = 0xfff;
data1 = 0xfff;
} else {
@@ -314,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
}
 
 exit:
-   if (cpu == TYPE_S3C64XX) {
+   if (cpu != TYPE_ADCV1) {
/* Clear ADC interrupt */
writel(0, adc-regs + S3C64XX_ADCCLRINT);
}
@@ -388,7 +394,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
clk_enable(adc-clk);
 
tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
-   if (platform_get_device_id(pdev)-driver_data == TYPE_S3C64XX) {
+   if (platform_get_device_id(pdev)-driver_data != TYPE_ADCV1) {
/* Enable 12-bit ADC resolution */
tmp |= S3C64XX_ADCCON_RESSEL;
}
@@ -476,10 +482,13 @@ static int s3c_adc_resume(struct platform_device *pdev)
 static struct platform_device_id s3c_adc_driver_ids[] = {
{
.name   = s3c24xx-adc,
-   .driver_data= TYPE_S3C24XX,
+   .driver_data= TYPE_ADCV1,
}, {
.name   = s3c64xx-adc,
-   .driver_data= TYPE_S3C64XX,
+   .driver_data= TYPE_ADCV2,
+   }, {
+   .name   = samsung-adc-v3,
+   .driver_data= TYPE_ADCV3,
},
{ }
 };
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h 
b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4f..035e8c3 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,6 +21,7 @@
 #define S3C2410_ADCDAT1   S3C2410_ADCREG(0x10)
 #define S3C64XX_ADCUPDNS3C2410_ADCREG(0x14)
 #define S3C64XX_ADCCLRINT  S3C2410_ADCREG(0x18)
+#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
 #define S3C64XX_ADCCLRINTPNDNUPS3C2410_ADCREG(0x20)
 
 
-- 
1.7.4.1

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[PATCH v3 1/6] Samsung SoC ADC: use regulator (VDD for ADC).

2011-06-30 Thread MyungJoo Ham 
This patch allows the Samsung ADC driver to enable VDD regulator at
probe and resume and to disable at exit and suspend.
In a platform where ADC's VDD regulator is not always-on, this control
is required although this patch does not provide fine-grained power
control (turning on the regulator only when being accessed).

However, if VDD regulator (vdd for the adc device) is not provided,
the regulator control will not be activated because there are platforms
that do not provide regulator for ADC device.

arch_initcall has been modified to module_init in order to allow
regulators to be available at probe.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com

--
changed from v2 with valuable comments from Mark Brown.
- Bugfix on error handling
- Faster escape when error at resume function
changes from v1
- Removed macro defining the name of regulator.
- Handle error from regulator_enable.
- Do not allow not to have the regulator if CONFIG_REGULATOR.
- Seperate a patch dealing with arch_initcall-module_init
---
 arch/arm/plat-samsung/adc.c |   31 +++
 1 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index e8f2be2..2224128 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -21,6 +21,7 @@
 #include linux/clk.h
 #include linux/interrupt.h
 #include linux/io.h
+#include linux/regulator/consumer.h
 
 #include plat/regs-adc.h
 #include plat/adc.h
@@ -71,6 +72,7 @@ struct adc_device {
unsigned int prescale;
 
int  irq;
+   struct regulator*vdd;
 };
 
 static struct adc_device *adc_dev;
@@ -338,17 +340,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
adc-pdev = pdev;
adc-prescale = S3C2410_ADCCON_PRSCVL(49);
 
+   adc-vdd = regulator_get(dev, vdd);
+   if (IS_ERR(adc-vdd)) {
+   dev_err(dev, operating without regulator \vdd\ .\n);
+   ret = PTR_ERR(adc-vdd);
+   goto err_alloc;
+   }
+
adc-irq = platform_get_irq(pdev, 1);
if (adc-irq = 0) {
dev_err(dev, failed to get adc irq\n);
ret = -ENOENT;
-   goto err_alloc;
+   goto err_reg;
}
 
ret = request_irq(adc-irq, s3c_adc_irq, 0, dev_name(dev), adc);
if (ret  0) {
dev_err(dev, failed to attach adc irq\n);
-   goto err_alloc;
+   goto err_reg;
}
 
adc-clk = clk_get(dev, adc);
@@ -372,6 +381,10 @@ static int s3c_adc_probe(struct platform_device *pdev)
goto err_clk;
}
 
+   ret = regulator_enable(adc-vdd);
+   if (ret)
+   goto err_ioremap;
+
clk_enable(adc-clk);
 
tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
@@ -388,12 +401,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
 
return 0;
 
+ err_ioremap:
+   iounmap(adc-regs);
  err_clk:
clk_put(adc-clk);
 
  err_irq:
free_irq(adc-irq, adc);
-
+ err_reg:
+   regulator_put(adc-vdd);
  err_alloc:
kfree(adc);
return ret;
@@ -406,6 +422,8 @@ static int __devexit s3c_adc_remove(struct platform_device 
*pdev)
iounmap(adc-regs);
free_irq(adc-irq, adc);
clk_disable(adc-clk);
+   regulator_disable(adc-vdd);
+   regulator_put(adc-vdd);
clk_put(adc-clk);
kfree(adc);
 
@@ -428,6 +446,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, 
pm_message_t state)
disable_irq(adc-irq);
spin_unlock_irqrestore(adc-lock, flags);
clk_disable(adc-clk);
+   regulator_disable(adc-vdd);
 
return 0;
 }
@@ -435,7 +454,11 @@ static int s3c_adc_suspend(struct platform_device *pdev, 
pm_message_t state)
 static int s3c_adc_resume(struct platform_device *pdev)
 {
struct adc_device *adc = platform_get_drvdata(pdev);
+   int ret;
 
+   ret = regulator_enable(adc-vdd);
+   if (ret)
+   return ret;
clk_enable(adc-clk);
enable_irq(adc-irq);
 
@@ -485,4 +508,4 @@ static int __init adc_init(void)
return ret;
 }
 
-arch_initcall(adc_init);
+module_init(adc_init);
-- 
1.7.4.1

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[PATCH v3 4/6] ARM: EXYNOS4: Support ADC

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
Updates from v2
- Based on EXT_GIC patches from Changhwan Youn (ARM: EXYNOS4: Adds
  External GIC)
---
 arch/arm/mach-exynos4/Kconfig |1 +
 arch/arm/mach-exynos4/cpu.c   |4 
 arch/arm/mach-exynos4/include/mach/irqs.h |3 +++
 arch/arm/mach-exynos4/include/mach/map.h  |5 +
 4 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0aca083..80f4fbe 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -184,6 +184,7 @@ config MACH_NURI
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
+   select SAMSUNG_DEV_ADC
help
  Machine support for Samsung Mobile NURI Board.
 
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 5423ed8..7ffa81d 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -21,7 +21,9 @@
 
 #include plat/cpu.h
 #include plat/clock.h
+#include plat/devs.h
 #include plat/exynos4.h
+#include plat/adc-core.h
 #include plat/sdhci.h
 #include plat/devs.h
 #include plat/fimc-core.h
@@ -141,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
 
+   s3c_adc_setname(samsung-adc-v3);
+
s3c_fimc_setname(0, exynos4-fimc);
s3c_fimc_setname(1, exynos4-fimc);
s3c_fimc_setname(2, exynos4-fimc);
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index 250427f..31f6bed 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -139,6 +139,9 @@
 
 #define MAX_COMBINER_NR16
 
+#define IRQ_ADCIRQ_ADC0
+#define IRQ_TC IRQ_PEN0
+
 #define S5P_IRQ_EINT_BASE  COMBINER_IRQ(MAX_COMBINER_NR, 0)
 
 #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h 
b/arch/arm/mach-exynos4/include/mach/map.h
index e4b5c79..e03e820 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -110,6 +110,9 @@
 
 #define EXYNOS4_PA_IIC(x)  (0x1386 + ((x) * 0x1))
 
+#define EXYNOS4_PA_ADC 0x1391
+#define EXYNOS4_PA_ADC10x13911000
+
 #define EXYNOS4_PA_AC970x139A
 
 #define EXYNOS4_PA_SPDIF   0x139B
@@ -132,6 +135,8 @@
 #define S3C_PA_IIC5EXYNOS4_PA_IIC(5)
 #define S3C_PA_IIC6EXYNOS4_PA_IIC(6)
 #define S3C_PA_IIC7EXYNOS4_PA_IIC(7)
+#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1EXYNOS4_PA_ADC1
 #define S3C_PA_RTC EXYNOS4_PA_RTC
 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
 
-- 
1.7.4.1

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[PATCH v3 3/6] Samsung SoC ADC: Revise PM for 12-bit ADC operations

2011-06-30 Thread MyungJoo Ham 
- Fixed: 12bit precision is lost at suspend/resume
- Updated: use pm_dev_ops

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/plat-samsung/adc.c |   24 ++--
 1 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 45cc7e6..ee8deef 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -437,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device 
*pdev)
 }
 
 #ifdef CONFIG_PM
-static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_adc_suspend(struct device *dev)
 {
+   struct platform_device *pdev = container_of(dev,
+   struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
unsigned long flags;
u32 con;
@@ -457,10 +459,13 @@ static int s3c_adc_suspend(struct platform_device *pdev, 
pm_message_t state)
return 0;
 }
 
-static int s3c_adc_resume(struct platform_device *pdev)
+static int s3c_adc_resume(struct device *dev)
 {
+   struct platform_device *pdev = container_of(dev,
+   struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
int ret;
+   unsigned long tmp;
 
ret = regulator_enable(adc-vdd);
if (ret)
@@ -468,8 +473,11 @@ static int s3c_adc_resume(struct platform_device *pdev)
clk_enable(adc-clk);
enable_irq(adc-irq);
 
-   writel(adc-prescale | S3C2410_ADCCON_PRSCEN,
-  adc-regs + S3C2410_ADCCON);
+   tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
+   /* Enable 12-bit ADC resolution */
+   if (platform_get_device_id(pdev)-driver_data != TYPE_ADCV1)
+   tmp |= S3C64XX_ADCCON_RESSEL;
+   writel(tmp, adc-regs + S3C2410_ADCCON);
 
return 0;
 }
@@ -494,16 +502,20 @@ static struct platform_device_id s3c_adc_driver_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
 
+static const struct dev_pm_ops adc_pm_ops = {
+   .suspend= s3c_adc_suspend,
+   .resume = s3c_adc_resume,
+};
+
 static struct platform_driver s3c_adc_driver = {
.id_table   = s3c_adc_driver_ids,
.driver = {
.name   = s3c-adc,
.owner  = THIS_MODULE,
+   .pm = adc_pm_ops,
},
.probe  = s3c_adc_probe,
.remove = __devexit_p(s3c_adc_remove),
-   .suspend= s3c_adc_suspend,
-   .resume = s3c_adc_resume,
 };
 
 static int __init adc_init(void)
-- 
1.7.4.1

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[PATCH v3 5/6] ARM: S5PC110/S5PV210: Support ADC

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-s5pv210/cpu.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24..79907ec 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
s5pv210_default_sdhci2();
s5pv210_default_sdhci3();
 
-   s3c_adc_setname(s3c64xx-adc);
+   s3c_adc_setname(samsung-adc-v3);
 
s3c_cfcon_setname(s5pv210-pata);
 
-- 
1.7.4.1

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[PATCH v3 6/6] Samsung SoC: header file revised to prevent declaring duplicated.

2011-06-30 Thread MyungJoo Ham 
There has been no #ifndef - #define - #endif protection for this header
file. The patch adds it for Exynos4-ADC support

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
---
 arch/arm/plat-samsung/include/plat/devs.h |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/devs.h 
b/arch/arm/plat-samsung/include/plat/devs.h
index 4af108f..3c87779 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -12,6 +12,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+#ifndef __PLAT_DEVS_H
+#define __PLAT_DEVS_H __FILE__
+
 #include linux/platform_device.h
 
 struct s3c24xx_uart_resources {
@@ -159,3 +162,5 @@ extern struct platform_device s3c_device_ac97;
  */
 extern void *s3c_set_platdata(void *pd, size_t pdsize,
  struct platform_device *pdev);
+
+#endif /* __PLAT_DEVS_H */
-- 
1.7.4.1

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Re: [PATCH v2 2/5] Samsung SoC ADC: Channel selection for S5PV210, S5PC110, and Exynos4

2011-06-30 Thread MyungJoo Ham 
On Wed, Jun 29, 2011 at 10:42 PM, Kukjin Kim kgene@samsung.com wrote:
 MyungJoo Ham wrote:

 In S5PV210/S5PC110/Exynos4, ADCMUX channel selection uses ADCMUX
 register, not ADCCON register. This patch corrects the behavior of
 Samsung-ADC for such cpus.

 Signed-off-by: MyungJoo Ham myungjoo@samsung.com
 Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
 --
 v2: No changes from v1. Resubmitted as a series of patches
 ---
[]

  enum s3c_cpu_type {
       TYPE_S3C24XX,
 -     TYPE_S3C64XX
 +     TYPE_S3C64XX,
 +     TYPE_S5P,
  };

 How about S5PC100? Following is better for next if we cannot distinguish it
 by CPU.

 -enum s3c_cpu_type {
 -       TYPE_S3C24XX,
 -       TYPE_S3C64XX
 +enum samsung_adc_type {
 +       TYPE_ADC24,      /* S3C24XX */
 +       TYPE_ADC64,      /* S3C64XX, S5P64X0, S5PC100 */
 +       TYPE_ADCV3      /* S5PV210, EXYNOS4210 */
  };
 ...

 TYPE_ADCV1 and V2?...
 Of course, the name can be changed...

I don't mind about these names as they are just internal values of adc.c.
Anyway, I prefer the last suggestion and I'll use TYPE_ADCV1/V2/V3.

Thanks.

-- 
MyungJoo Ham (함명주), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
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[PATCH v3 6/6] Exynos4 NURI: configure rtc-s3c.

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 0c9401c..bdf7a5c 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -1098,6 +1098,7 @@ static struct platform_device *nuri_devices[] __initdata 
= {
s3c_device_i2c3,
i2c9_gpio,
s3c_device_adc,
+   s3c_device_rtc,
 
/* NURI Devices */
nuri_gpio_keys,
-- 
1.7.4.1

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[PATCH v3 0/6] ARM: EXYNOS4: NURI Board Configuration Update

2011-06-30 Thread MyungJoo Ham 
1/6: Increase NR_IRQS for MAX8997
2/6: Add MAX8997 PMIC
3/6: Add MAX17042 Fuel Gauge
4/6: Add ADC
5/6: Add MAX8903 Secondary Charger
6/6: Add RTC-S3C

ps. Tushar, I didn't seperated MAX8997 support code out of mach-nuri.c, yet 
because I still have no idea about how similar the Origen board is with NURI 
board.

MyungJoo Ham (6):
  ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs
  Exynos4 NURI: configure regulators and PMIC (MAX8997)
  Exynos4 NURI: configure MAX17042 fuel gauge
  Exynos4 NURI: configure ADC.
  Exynos4 NURI: configure MAX8903 secondary charger
  Exynos4 NURI: configure rtc-s3c.

 arch/arm/mach-exynos4/include/mach/irqs.h |2 +-
 arch/arm/mach-exynos4/mach-nuri.c |  739 -
 2 files changed, 739 insertions(+), 2 deletions(-)

-- 
1.7.4.1

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[PATCH v3 1/6] ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs

2011-06-30 Thread MyungJoo Ham 
MAX8997/17042, which are used by Exynos4-NURI, use additional IRQ
numbers after GPIO's IRQs. The patch creates some room for those
devices.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/include/mach/irqs.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h 
b/arch/arm/mach-exynos4/include/mach/irqs.h
index 31f6bed..51b5db5 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -154,6 +154,6 @@
 #define IRQ_GPIO_END   (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
 /* Set the default NR_IRQS */
-#define NR_IRQS(IRQ_GPIO_END)
+#define NR_IRQS(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */
-- 
1.7.4.1

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[PATCH v3 2/6] Exynos4 NURI: configure regulators and PMIC (MAX8997)

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com

--
Changes from v3
- Updated init function name to include other power related devices.
Changes from v2
- Add more __initdata entries
- Moved and renamed pmic init function
- Rearranged init point of PMIC
Changes from v1
- Removed unnecessary initialization data
- Add __initdata where necessary
- Corrected a regulator name for ADC
---
 arch/arm/mach-exynos4/mach-nuri.c |  625 -
 1 files changed, 624 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 642702b..ec51f5c 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -17,6 +17,7 @@
 #include linux/gpio.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
+#include linux/mfd/max8997.h
 #include linux/mmc/host.h
 #include linux/fb.h
 #include linux/pwm_backlight.h
@@ -344,11 +345,629 @@ static void __init nuri_tsp_init(void)
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
 }
 
+static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
+   REGULATOR_SUPPLY(vdd, s5p-adc), /* Used by CPU's ADC drv */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
+   REGULATOR_SUPPLY(vdd11, s5p-mipi-csis.0), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
+   REGULATOR_SUPPLY(vdd18, s5p-mipi-csis.0), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
+   REGULATOR_SUPPLY(vhsic, modemctl), /* MODEM */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
+   REGULATOR_SUPPLY(dig_18, 0-001f), /* HCD803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
+   REGULATOR_SUPPLY(vusb_d, NULL), /* Used by CPU */
+   REGULATOR_SUPPLY(vdac, NULL), /* Used by CPU */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
+   REGULATOR_SUPPLY(vcc, platform-lcd), /* U804 LVDS */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
+   REGULATOR_SUPPLY(vddio, 6-003c), /* HDC802 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
+   REGULATOR_SUPPLY(vmmc, s3c-sdhci.2), /* TFLASH */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
+   REGULATOR_SUPPLY(inmotor, max8997-haptic),
+};
+static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
+   REGULATOR_SUPPLY(avdd, 3-004a), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
+   REGULATOR_SUPPLY(d_sensor, 0-001f), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
+   REGULATOR_SUPPLY(vdd, 3-004a), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
+   REGULATOR_SUPPLY(vdd_arm, NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
+   REGULATOR_SUPPLY(vdd_int, NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
+   REGULATOR_SUPPLY(vdd, mali_dev.0), /* G3D of Exynos 4 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
+   REGULATOR_SUPPLY(core, 0-001f), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
+   REGULATOR_SUPPLY(dig_28, 0-001f), /* pin 7 of HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
+   REGULATOR_SUPPLY(usb_vbus, NULL), /* CPU's USB OTG */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
+   REGULATOR_SUPPLY(usb_vbus, modemctl), /* VBUS of Modem */
+};
+
+static struct regulator_consumer_supply __initdata max8997_charger_[] = {
+   REGULATOR_SUPPLY(vinchg1, charger-manager.0),
+};
+static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
+   REGULATOR_SUPPLY(vinchg_stop, NULL), /* for jack interrupt handlers */
+};
+
+static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
+   REGULATOR_SUPPLY(gps_clk, bcm4751),
+   REGULATOR_SUPPLY(bt_clk, bcm4330-b1),
+   REGULATOR_SUPPLY(wifi_clk, bcm433-b1),
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+   .constraints= {
+   .name   = VADC_3.3V_C210,
+   .min_uV = 330,
+   .max_uV = 330,
+   .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+   .apply_uV   = 1,
+   .state_mem  = {
+   .disabled   = 1,
+   },
+   },
+   .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
+   .consumer_supplies  = max8997_ldo1_,
+};
+
+static struct regulator_init_data

[PATCH v3 4/6] Exynos4 NURI: configure ADC.

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index 2467a2a..e81e8ca 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -29,6 +29,7 @@
 #include asm/mach/arch.h
 #include asm/mach-types.h
 
+#include plat/adc.h
 #include plat/regs-serial.h
 #include plat/exynos4.h
 #include plat/cpu.h
@@ -1020,6 +1021,7 @@ static struct platform_device *nuri_devices[] __initdata 
= {
s5p_device_ehci,
s3c_device_i2c3,
i2c9_gpio,
+   s3c_device_adc,
 
/* NURI Devices */
nuri_gpio_keys,
-- 
1.7.4.1

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[PATCH v3 5/6] Exynos4 NURI: configure MAX8903 secondary charger

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |   78 +
 1 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index e81e8ca..0c9401c 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -16,6 +16,7 @@
 #include linux/i2c-gpio.h
 #include linux/gpio_keys.h
 #include linux/gpio.h
+#include linux/power/max8903_charger.h
 #include linux/power/max17042_battery.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
@@ -58,6 +59,7 @@
 
 enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
+   FIXED_REG_ID_MAX8903,
 };
 
 static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -980,10 +982,70 @@ static struct i2c_board_info i2c9_devs[] __initdata = {
},
 };
 
+/* MAX8903 Secondary Charger */
+static struct regulator_consumer_supply supplies_max8903[] = {
+   REGULATOR_SUPPLY(vinchg2, charger-manager.0),
+};
+
+static struct regulator_init_data max8903_charger_en_data = {
+   .constraints = {
+   .name   = VOUT_CHARGER,
+   .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+   .boot_on= 1,
+   },
+   .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
+   .consumer_supplies = supplies_max8903,
+};
+
+static struct fixed_voltage_config max8903_charger_en = {
+   .supply_name = VOUT_CHARGER,
+   .microvolts = 500, /* Assume 5VDC */
+   .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
+   .enable_high = 0, /* Enable = Low */
+   .enabled_at_boot = 1,
+   .init_data = max8903_charger_en_data,
+};
+
+static struct platform_device max8903_fixed_reg_dev = {
+   .name = reg-fixed-voltage,
+   .id = FIXED_REG_ID_MAX8903,
+   .dev = { .platform_data = max8903_charger_en },
+};
+
+static struct max8903_pdata nuri_max8903 = {
+   /*
+* cen: don't control with the driver, let it be
+* controlled by regulator above
+*/
+   .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
+   /* uok, usus: not connected */
+   .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+   /* flt: vcc_1.8V_pda */
+   .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
+
+   .dc_valid = true,
+   .usb_valid = false, /* USB is not wired to MAX8903 */
+};
+
+static struct platform_device nuri_max8903_device = {
+   .name   = max8903-charger,
+   .dev= {
+   .platform_data  = nuri_max8903,
+   },
+};
+
+static struct device *nuri_cm_devices[] = {
+   s3c_device_i2c5.dev,
+   s3c_device_adc.dev,
+   NULL, /* Reserved for UART */
+   NULL,
+};
+
 static void __init nuri_power_init(void)
 {
int gpio;
int irq_base = IRQ_GPIO_END + 1;
+   int ta_en = 0;
 
nuri_max8997_pdata.irq_base = irq_base;
irq_base += MAX8997_IRQ_NR;
@@ -997,6 +1059,20 @@ static void __init nuri_power_init(void)
gpio_request(gpio, FUEL_ALERT);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+   gpio = nuri_max8903.dok;
+   gpio_request(gpio, TA_nCONNECTED);
+   s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+   s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+   ta_en = gpio_get_value(gpio) ? 0 : 1;
+
+   gpio = nuri_max8903.chg;
+   gpio_request(gpio, TA_nCHG);
+   gpio_direction_input(gpio);
+
+   gpio = nuri_max8903.dcm;
+   gpio_request(gpio, CURR_ADJ);
+   gpio_direction_output(gpio, ta_en);
 }
 
 /* USB EHCI */
@@ -1027,6 +1103,8 @@ static struct platform_device *nuri_devices[] __initdata 
= {
nuri_gpio_keys,
nuri_lcd_device,
nuri_backlight_device,
+   max8903_fixed_reg_dev,
+   nuri_max8903_device,
 };
 
 static void __init nuri_map_io(void)
-- 
1.7.4.1

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[PATCH v3 3/6] Exynos4 NURI: configure MAX17042 fuel gauge

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
--
changed from v2
- Moved locations
---
 arch/arm/mach-exynos4/mach-nuri.c |   33 +
 1 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index ec51f5c..2467a2a 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,8 +13,10 @@
 #include linux/input.h
 #include linux/i2c.h
 #include linux/i2c/atmel_mxt_ts.h
+#include linux/i2c-gpio.h
 #include linux/gpio_keys.h
 #include linux/gpio.h
+#include linux/power/max17042_battery.h
 #include linux/regulator/machine.h
 #include linux/regulator/fixed.h
 #include linux/mfd/max8997.h
@@ -954,6 +956,29 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
},
 };
 
+static struct max17042_platform_data nuri_battery_platform_data = {
+};
+
+/* GPIO I2C 9 (Fuel Gauge) */
+static struct i2c_gpio_platform_data i2c9_gpio_data = {
+   .sda_pin= EXYNOS4_GPY4(0),  /* XM0ADDR_8 */
+   .scl_pin= EXYNOS4_GPY4(1),  /* XM0ADDR_9 */
+};
+static struct platform_device i2c9_gpio = {
+   .name   = i2c-gpio,
+   .id = 9,
+   .dev= {
+   .platform_data  = i2c9_gpio_data,
+   },
+};
+enum { I2C9_MAX17042};
+static struct i2c_board_info i2c9_devs[] __initdata = {
+   [I2C9_MAX17042] = {
+   I2C_BOARD_INFO(max17042, 0x36),
+   .platform_data = nuri_battery_platform_data,
+   },
+};
+
 static void __init nuri_power_init(void)
 {
int gpio;
@@ -966,6 +991,11 @@ static void __init nuri_power_init(void)
gpio_request(gpio, AP_PMIC_IRQ);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+   gpio = EXYNOS4_GPX2(3);
+   gpio_request(gpio, FUEL_ALERT);
+   s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+   s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 }
 
 /* USB EHCI */
@@ -989,6 +1019,7 @@ static struct platform_device *nuri_devices[] __initdata = 
{
s3c_device_timer[0],
s5p_device_ehci,
s3c_device_i2c3,
+   i2c9_gpio,
 
/* NURI Devices */
nuri_gpio_keys,
@@ -1015,6 +1046,8 @@ static void __init nuri_machine_init(void)
s3c_i2c5_set_platdata(NULL);
i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+   i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
+   i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 
nuri_ehci_init();
clk_xusbxti.rate = 2400;
-- 
1.7.4.1

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Re: [PATCH v3 1/6] Samsung SoC ADC: use regulator (VDD for ADC).

2011-06-30 Thread Vasily Khoruzhick 
On Thursday 30 June 2011 10:49:30 MyungJoo Ham wrote:
 This patch allows the Samsung ADC driver to enable VDD regulator at
 probe and resume and to disable at exit and suspend.
 In a platform where ADC's VDD regulator is not always-on, this control
 is required although this patch does not provide fine-grained power
 control (turning on the regulator only when being accessed).
 
 However, if VDD regulator (vdd for the adc device) is not provided,
 the regulator control will not be activated because there are platforms
 that do not provide regulator for ADC device.
 
 arch_initcall has been modified to module_init in order to allow
 regulators to be available at probe.
 
 Signed-off-by: MyungJoo Ham myungjoo@samsung.com
 Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com


 --
 changed from v2 with valuable comments from Mark Brown.
 - Bugfix on error handling
 - Faster escape when error at resume function
 changes from v1
 - Removed macro defining the name of regulator.
 - Handle error from regulator_enable.
 - Do not allow not to have the regulator if CONFIG_REGULATOR.
 - Seperate a patch dealing with arch_initcall-module_init
 ---
  arch/arm/plat-samsung/adc.c |   31 +++
  1 files changed, 27 insertions(+), 4 deletions(-)
 
 diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
 index e8f2be2..2224128 100644
 --- a/arch/arm/plat-samsung/adc.c
 +++ b/arch/arm/plat-samsung/adc.c
 @@ -21,6 +21,7 @@
  #include linux/clk.h
  #include linux/interrupt.h
  #include linux/io.h
 +#include linux/regulator/consumer.h
 
  #include plat/regs-adc.h
  #include plat/adc.h
 @@ -71,6 +72,7 @@ struct adc_device {
   unsigned int prescale;
 
   int  irq;
 + struct regulator*vdd;
  };
 
  static struct adc_device *adc_dev;
 @@ -338,17 +340,24 @@ static int s3c_adc_probe(struct platform_device
 *pdev) adc-pdev = pdev;
   adc-prescale = S3C2410_ADCCON_PRSCVL(49);
 
 + adc-vdd = regulator_get(dev, vdd);
 + if (IS_ERR(adc-vdd)) {
 + dev_err(dev, operating without regulator \vdd\ .\n);
 + ret = PTR_ERR(adc-vdd);
 + goto err_alloc;
 + }
 +

NACK. Make it optional, otherwise it breaks s3c24xx.

   adc-irq = platform_get_irq(pdev, 1);
   if (adc-irq = 0) {
   dev_err(dev, failed to get adc irq\n);
   ret = -ENOENT;
 - goto err_alloc;
 + goto err_reg;
   }
 
   ret = request_irq(adc-irq, s3c_adc_irq, 0, dev_name(dev), adc);
   if (ret  0) {
   dev_err(dev, failed to attach adc irq\n);
 - goto err_alloc;
 + goto err_reg;
   }
 
   adc-clk = clk_get(dev, adc);
 @@ -372,6 +381,10 @@ static int s3c_adc_probe(struct platform_device *pdev)
   goto err_clk;
   }
 
 + ret = regulator_enable(adc-vdd);
 + if (ret)
 + goto err_ioremap;
 +
   clk_enable(adc-clk);
 
   tmp = adc-prescale | S3C2410_ADCCON_PRSCEN;
 @@ -388,12 +401,15 @@ static int s3c_adc_probe(struct platform_device
 *pdev)
 
   return 0;
 
 + err_ioremap:
 + iounmap(adc-regs);
   err_clk:
   clk_put(adc-clk);
 
   err_irq:
   free_irq(adc-irq, adc);
 -
 + err_reg:
 + regulator_put(adc-vdd);
   err_alloc:
   kfree(adc);
   return ret;
 @@ -406,6 +422,8 @@ static int __devexit s3c_adc_remove(struct
 platform_device *pdev) iounmap(adc-regs);
   free_irq(adc-irq, adc);
   clk_disable(adc-clk);
 + regulator_disable(adc-vdd);
 + regulator_put(adc-vdd);
   clk_put(adc-clk);
   kfree(adc);
 
 @@ -428,6 +446,7 @@ static int s3c_adc_suspend(struct platform_device
 *pdev, pm_message_t state) disable_irq(adc-irq);
   spin_unlock_irqrestore(adc-lock, flags);
   clk_disable(adc-clk);
 + regulator_disable(adc-vdd);
 
   return 0;
  }
 @@ -435,7 +454,11 @@ static int s3c_adc_suspend(struct platform_device
 *pdev, pm_message_t state) static int s3c_adc_resume(struct
 platform_device *pdev)
  {
   struct adc_device *adc = platform_get_drvdata(pdev);
 + int ret;
 
 + ret = regulator_enable(adc-vdd);
 + if (ret)
 + return ret;
   clk_enable(adc-clk);
   enable_irq(adc-irq);
 
 @@ -485,4 +508,4 @@ static int __init adc_init(void)
   return ret;
  }
 
 -arch_initcall(adc_init);
 +module_init(adc_init);
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[PATCH 2/3] Samsung SoC: ready to use NTC value inside kernel

2011-06-30 Thread MyungJoo Ham 
This patch allows kernel codes to use values from NTC LM-Sensor
driver, which allows SYSFS access only.

Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/plat-samsung/dev-adc.c  |   62 ++
 arch/arm/plat-samsung/include/plat/adc-ntc.h |   19 
 2 files changed, 81 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/adc-ntc.h

diff --git a/arch/arm/plat-samsung/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c
index 622972c..526097a 100644
--- a/arch/arm/plat-samsung/dev-adc.c
+++ b/arch/arm/plat-samsung/dev-adc.c
@@ -22,6 +22,8 @@
 #include plat/devs.h
 #include plat/cpu.h
 
+#include ../../../fs/sysfs/sysfs.h
+
 static struct resource s3c_adc_resource[] = {
[0] = {
.start = SAMSUNG_PA_ADC,
@@ -101,3 +103,63 @@ struct platform_device s3c_device_adc_ntc_thermistor = {
.platform_data = ntc_adc_pdata,
},
 };
+
+static struct device_attribute *ntc_attr;
+
+static int init_s3c_adc_ntc_read(void)
+{
+   struct kobject *ntc;
+   struct sysfs_dirent *ntc_d;
+
+   ntc = s3c_device_adc_ntc_thermistor.dev.kobj;
+   ntc_d = sysfs_get_dirent(ntc-sd, get_ktype(ntc)-namespace(ntc),
+temp1_input);
+   if (!ntc_d || sysfs_type(ntc_d) != SYSFS_KOBJ_ATTR) {
+   dev_err(s3c_device_adc_ntc_thermistor.dev,
+   Cannot initialize thermistor dirent info.\n);
+   if (ntc_d)
+   sysfs_put(ntc_d);
+   return -ENODEV;
+   }
+   ntc_attr = container_of(ntc_d-s_attr.attr, struct device_attribute,
+   attr);
+
+   sysfs_put(ntc_d);
+   if (IS_ERR(ntc_attr)) {
+   dev_err(s3c_device_adc_ntc_thermistor.dev,
+   Cannot access NTC thermistor.\n);
+   return PTR_ERR(ntc_attr);
+   }
+
+   return 0;
+}
+
+/* A helper function to read values from NTC, in 1/1000 Centigrade */
+int read_s3c_adc_ntc(int *mC)
+{
+   char buf[32];
+   int ret;
+
+   /* init should be done after ADC and NTC are probed */
+   if (ntc_attr == NULL) {
+   ret = init_s3c_adc_ntc_read();
+   if (ret) {
+   if (ntc_attr == NULL)
+   ntc_attr = ERR_PTR(ret);
+   return ret;
+   }
+   }
+
+   if (IS_ERR(ntc_attr))
+   return -ENODEV;
+
+   if (!ntc_attr-show)
+   return -EINVAL;
+
+   ret = ntc_attr-show(s3c_device_adc_ntc_thermistor.dev, ntc_attr, buf);
+   if (ret  0)
+   return ret;
+   sscanf(buf, %d, mC);
+
+   return 0;
+}
diff --git a/arch/arm/plat-samsung/include/plat/adc-ntc.h 
b/arch/arm/plat-samsung/include/plat/adc-ntc.h
new file mode 100644
index 000..3d74118
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/adc-ntc.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/plat-samsung/include/plat/adc-ntc.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * NTC Thermistor attached to Samsung ADC Controller driver information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_ADC_NTC_H
+#define __PLAT_ADC_NTC_H __FILE__
+
+extern void s3c_adc_ntc_init(int port);
+extern int read_s3c_adc_ntc(int *mC);
+
+#endif /* __PLAT_ADC_NTC_H */
-- 
1.7.4.1

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[PATCH 0/3] ARM: EXYNOS4: NURI Support NTC

2011-06-30 Thread MyungJoo Ham 
This series of patches require NTC thermistor support.
NTC thermistor support patch is submitted and told to be applied (lm-sensors) 
although it is not being found in -next branches just yet.
You can find the patch at:
http://comments.gmane.org/gmane.linux.drivers.sensors/26475

MyungJoo Ham (3):
  Samsung SoC: NTC Thermistor attached to S3C-ADC.
  Samsung SoC: ready to use NTC value inside kernel
  Exynos4 NURI: support for NTC thermistor

 arch/arm/mach-exynos4/mach-nuri.c|4 +
 arch/arm/plat-samsung/dev-adc.c  |  119 ++
 arch/arm/plat-samsung/include/plat/adc-ntc.h |   19 
 arch/arm/plat-samsung/include/plat/devs.h|1 +
 4 files changed, 143 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/adc-ntc.h

-- 
1.7.4.1

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[PATCH 3/3] Exynos4 NURI: support for NTC thermistor

2011-06-30 Thread MyungJoo Ham 
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
 arch/arm/mach-exynos4/mach-nuri.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/mach-nuri.c 
b/arch/arm/mach-exynos4/mach-nuri.c
index bdf7a5c..cd8bc06 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -40,6 +40,7 @@
 #include plat/clock.h
 #include plat/gpio-cfg.h
 #include plat/iic.h
+#include plat/adc-ntc.h
 
 #include mach/map.h
 
@@ -1098,6 +1099,7 @@ static struct platform_device *nuri_devices[] __initdata 
= {
s3c_device_i2c3,
i2c9_gpio,
s3c_device_adc,
+   s3c_device_adc_ntc_thermistor,
s3c_device_rtc,
 
/* NURI Devices */
@@ -1133,6 +1135,8 @@ static void __init nuri_machine_init(void)
nuri_ehci_init();
clk_xusbxti.rate = 2400;
 
+   s3c_adc_ntc_init(6); /* NTC Thermistor uses ADC port 6 */
+
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
 }
-- 
1.7.4.1

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Re: [PATCH 2/3] Samsung SoC: ready to use NTC value inside kernel

2011-06-30 Thread Russell King - ARM Linux 
On Thu, Jun 30, 2011 at 05:26:26PM +0900, MyungJoo Ham wrote:
 diff --git a/arch/arm/plat-samsung/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c
 index 622972c..526097a 100644
 --- a/arch/arm/plat-samsung/dev-adc.c
 +++ b/arch/arm/plat-samsung/dev-adc.c
 @@ -22,6 +22,8 @@
  #include plat/devs.h
  #include plat/cpu.h
  
 +#include ../../../fs/sysfs/sysfs.h

That is a big hint that you're doing something wrong.

 @@ -101,3 +103,63 @@ struct platform_device s3c_device_adc_ntc_thermistor = {
   .platform_data = ntc_adc_pdata,
   },
  };
 +
 +static struct device_attribute *ntc_attr;
 +
 +static int init_s3c_adc_ntc_read(void)
 +{
 + struct kobject *ntc;
 + struct sysfs_dirent *ntc_d;
 +
 + ntc = s3c_device_adc_ntc_thermistor.dev.kobj;
 + ntc_d = sysfs_get_dirent(ntc-sd, get_ktype(ntc)-namespace(ntc),
 +  temp1_input);
 + if (!ntc_d || sysfs_type(ntc_d) != SYSFS_KOBJ_ATTR) {
 + dev_err(s3c_device_adc_ntc_thermistor.dev,
 + Cannot initialize thermistor dirent info.\n);
 + if (ntc_d)
 + sysfs_put(ntc_d);
 + return -ENODEV;
 + }
 + ntc_attr = container_of(ntc_d-s_attr.attr, struct device_attribute,
 + attr);
 +
 + sysfs_put(ntc_d);
 + if (IS_ERR(ntc_attr)) {
 + dev_err(s3c_device_adc_ntc_thermistor.dev,
 + Cannot access NTC thermistor.\n);
 + return PTR_ERR(ntc_attr);
 + }
 +
 + return 0;
 +}
 +
 +/* A helper function to read values from NTC, in 1/1000 Centigrade */
 +int read_s3c_adc_ntc(int *mC)
 +{
 + char buf[32];
 + int ret;
 +
 + /* init should be done after ADC and NTC are probed */
 + if (ntc_attr == NULL) {
 + ret = init_s3c_adc_ntc_read();
 + if (ret) {
 + if (ntc_attr == NULL)
 + ntc_attr = ERR_PTR(ret);
 + return ret;
 + }
 + }
 +
 + if (IS_ERR(ntc_attr))
 + return -ENODEV;
 +
 + if (!ntc_attr-show)
 + return -EINVAL;
 +
 + ret = ntc_attr-show(s3c_device_adc_ntc_thermistor.dev, ntc_attr, buf);
 + if (ret  0)
 + return ret;
 + sscanf(buf, %d, mC);
 +
 + return 0;
 +}

This is wrong on just about every level.  It needs to be rewritten to
avoid poking about in subsystem internal data structures, and you really
should not be sprint-ing a value to only sscanf it later.

Plus, container_of doesn't return a pointer-error code.

You need to come up with a far better way of doing this altogether.
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Re: [PATCH v3 1/6] Samsung SoC ADC: use regulator (VDD for ADC).

2011-06-30 Thread MyungJoo Ham 
On Thu, Jun 30, 2011 at 5:22 PM, Vasily Khoruzhick anars...@gmail.com wrote:
 On Thursday 30 June 2011 10:49:30 MyungJoo Ham wrote:
 This patch allows the Samsung ADC driver to enable VDD regulator at
 probe and resume and to disable at exit and suspend.
 In a platform where ADC's VDD regulator is not always-on, this control
 is required although this patch does not provide fine-grained power
 control (turning on the regulator only when being accessed).

 However, if VDD regulator (vdd for the adc device) is not provided,
 the regulator control will not be activated because there are platforms
 that do not provide regulator for ADC device.

 arch_initcall has been modified to module_init in order to allow
 regulators to be available at probe.

 Signed-off-by: MyungJoo Ham myungjoo@samsung.com
 Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
[]
 +     adc-vdd = regulator_get(dev, vdd);
 +     if (IS_ERR(adc-vdd)) {
 +             dev_err(dev, operating without regulator \vdd\ .\n);
 +             ret = PTR_ERR(adc-vdd);
 +             goto err_alloc;
 +     }
 +

 NACK. Make it optional, otherwise it breaks s3c24xx.


Ok. Now, I've got the issue I've worried in the previous patch revision.

Anyway, Mark once stated:
--- quote starts ---
On Sun, Jun 19, 2011 at 12:06 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
 + if (IS_ERR_OR_NULL(adc-vdd)) {
 + dev_dbg(dev, operating without regulator %s.\n, 
 S3C_ADC_REGULATOR_NAME);
 + adc-vdd = NULL; /* Do not control regulator */
 + }
 +

 No, don't do this.  Just unconditionally assume the regulator is present
 if power is essential for use of the device.  The regulator API will
 stub out correctly if it's not in use to allow things to proceed and if
 vdd is genuinely not hooked up then the driver can't function.
--- quote ends ---

Then, how about unconditionally using ADC VDD for TYPE_ADCV3
(S5PC110/S5PV210/Exynos4210) and forget VDD for older ADC types?


Thanks.

- MyungJoo
-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread padma venkat 
Hi,

On Thu, Jun 30, 2011 at 12:38 PM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Thu, Jun 30, 2011 at 6:08 PM, Padmavathi Venna padm...@samsung.com wrote:
 Fixed the bug in transmission status check for 64 bytes FIFO
 level.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  drivers/spi/spi_s3c64xx.c |    4 +---
  1 files changed, 1 insertions(+), 3 deletions(-)

 diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.hc
 index 795828b..8945e20 100644
 --- a/drivers/spi/spi_s3c64xx.c
 +++ b/drivers/spi/spi_s3c64xx.c
 @@ -116,9 +116,7 @@
                                        (((i)-fifo_lvl_mask + 1))) \
                                        ? 1 : 0)

 -#define S3C64XX_SPI_ST_TX_DONE(v, i) v)  (i)-rx_lvl_offset)  \
 -                                       (((i)-fifo_lvl_mask + 1)  1)) \
 -                                       ? 1 : 0)
 +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v)  (1  (i)-tx_st_done)) ? 1 : 
 0)

 IIRC the macro is already designed to deduct tx-done levels from other fields.
 Could you please _explain_ with one example where it fails ? It is
 difficult to see without
 numbers.
The existing macro fails for following scenarios.
1) S5P64X0 channel 1
2) S5PV210 channel 1
3) S5PV310 channel 1 and channel 2

The FIFO data level supported in the above SoCs either 64 or 256
bytes depending on the channel. Because of this the TX_DONE
is the 25 bit in the status register.

The existing macro works for the following scenarios
1) S3C6410 all channels
2) S5PC100 all channels

The FIFO data level supported in the above SoCs 64 bytes
on all the channels. Because of this the TX_DONE is the 21 bit
in the status register.

So when we use the existing macro for the non-working SoCs
it is not anding with the TX_DONE bit but it is only anding the bits
earlier to TX_DONE bit.


 Thanks,
 -Jassi
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RE: [PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread Marek Szyprowski 
Hello,

On Thursday, June 30, 2011 2:25 PM Padmavathi Venna wrote:

 This patchset does the following:
 
 1. Move duplicated code to common place
 [PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
 SPI platform devices are defined in respective machine folder of
 Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
 So all SPI platform devices are moved to a common place.
 
 [PATCH 2/7] ARM: SAMSUNG: Define common macro for SPI physical address
 
 [PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs
 Each SoC has it's own set of clock sources for SPI.So they are defined in
 respective machine folder.
 
 [PATCH 4/7] ARM: SAMSUNG: Create SPI device setup files in
 respective machine folder
 
 [PATCH 5/7] ARM: SAMSUNG: Add SPI platform specific code
 As SPI platform devices are moved to common place some platform specific
 code need to be initialized in the respective machine file.
 
 [PATCH 6/7] SPI: S5PC100: Enable the SPI driver for S5PC100
 
 [PATCH 7/7] SPI: S5PV210: Enable the SPI driver for S5PV210

These patch set improves a bit platform part of SPI driver, but I really
wonder if we really need to pass so many SoC version specific data 
with platform data. Are all these data (clock list, fifo parameters)
specific to SoC version or particular board configuration/implementation?

Maybe it will be much easier to convert the SPI driver to use driver id 
feature and use different platform id's for each SoC version? (please 
refer to drivers/video/s3c-fb.c and plat-samsung/include/plat/fb-core.h
for more information). This will remove the need for SoC specific
parameters in platform data and will group all version dependent 
information in the driver.

Best regards
-- 
Marek Szyprowski
Samsung Poland RD Center



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Re: [PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread padma venkat 
Hi,

On Thu, Jun 30, 2011 at 1:01 PM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Thu, Jun 30, 2011 at 5:55 PM, Padmavathi Venna padm...@samsung.com wrote:
 This patchset does the following:

 1. Move duplicated code to common place
 [PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
 SPI platform devices are defined in respective machine folder of
 Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
 So all SPI platform devices are moved to a common place.

 The machine specific code is put in machine specific location for some reason.
 And the code is not duplicated, it's mostly data structures
 initialized with machine
 specific values.

 Have you considered if it would still be possible to build kernel
 image supporting
 more than 1 soc after your changes ?
I didn't consider the single image scenario. Because as far as I know,
the existing Samsung code doesn't have support for building a single kernel
image for multiple SoCs.

The intention behind my changes were
1) To reuse the dev-spi files for all the SoCs, as this reduces the code size.
Also future SoCs with SPI can use the same file.
2) To be in line with other IPs like i2c,sdhci etc

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ThanksRegards
Padma
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Re: [PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs

2011-06-30 Thread Russell King - ARM Linux 
On Thu, Jun 30, 2011 at 08:25:19AM -0400, Padmavathi Venna wrote:
 SPI Clocks were defined in dev-spi.c of machine specific folder.
 To make SPI devices common across all SoCs,dev-spi.c is moved
 from machine specific folder to plat-samsung. So SPI clock
 definitions has been moved from dev-spi.c to SoC specific machine
 folder for S3C64XX,S5P64X0,S5PC100 and S5PV210

This just shows how sick the Samsung code is by abusing the clk API.
If it stopped that abuse and switched over to clkdev none of this would
be necessary.

So I'm going to NAK this until the Samsung clk code moves over to clkdev.
Sorry, I've made enough requests of Samsung people to do this, and its
time for more effective persuasion by standing in the way of other patches
to make it happen.
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Re: [PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 3:00 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
 On Thu, Jun 30, 2011 at 08:25:19AM -0400, Padmavathi Venna wrote:
 SPI Clocks were defined in dev-spi.c of machine specific folder.
 To make SPI devices common across all SoCs,dev-spi.c is moved
 from machine specific folder to plat-samsung. So SPI clock
 definitions has been moved from dev-spi.c to SoC specific machine
 folder for S3C64XX,S5P64X0,S5PC100 and S5PV210

 This just shows how sick the Samsung code is by abusing the clk API.
 If it stopped that abuse and switched over to clkdev none of this would
 be necessary.
I am anyways not for the patch set.
Though this 'sickness' predates clkdev, and I agree it should be changed now.
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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 2:35 PM, padma venkat padma@gmail.com wrote:
 Hi,

 On Thu, Jun 30, 2011 at 12:38 PM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Thu, Jun 30, 2011 at 6:08 PM, Padmavathi Venna padm...@samsung.com 
 wrote:
 Fixed the bug in transmission status check for 64 bytes FIFO
 level.

 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  drivers/spi/spi_s3c64xx.c |    4 +---
  1 files changed, 1 insertions(+), 3 deletions(-)

 diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.hc
 index 795828b..8945e20 100644
 --- a/drivers/spi/spi_s3c64xx.c
 +++ b/drivers/spi/spi_s3c64xx.c
 @@ -116,9 +116,7 @@
                                        (((i)-fifo_lvl_mask + 1))) \
                                        ? 1 : 0)

 -#define S3C64XX_SPI_ST_TX_DONE(v, i) v)  (i)-rx_lvl_offset)  \
 -                                       (((i)-fifo_lvl_mask + 1)  1)) \
 -                                       ? 1 : 0)
 +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v)  (1  (i)-tx_st_done)) ? 1 : 
 0)

 IIRC the macro is already designed to deduct tx-done levels from other 
 fields.
 Could you please _explain_ with one example where it fails ? It is
 difficult to see without
 numbers.
 The existing macro fails for following scenarios.
 1) S5P64X0 channel 1
 2) S5PV210 channel 1
 3) S5PV310 channel 1 and channel 2

 The FIFO data level supported in the above SoCs either 64 or 256
 bytes depending on the channel. Because of this the TX_DONE
 is the 25 bit in the status register.

 The existing macro works for the following scenarios
 1) S3C6410 all channels
 2) S5PC100 all channels

 The FIFO data level supported in the above SoCs 64 bytes
 on all the channels. Because of this the TX_DONE is the 21 bit
 in the status register.

 So when we use the existing macro for the non-working SoCs
 it is not anding with the TX_DONE bit but it is only anding the bits
 earlier to TX_DONE bit.


I see.
I don't have access to post s3c64xx datasheets. Please confirm if TX_DONE
bit at same offset for all channels of an SoC. If so, I am OK with
these 2 patches.

Thanks,
Jassi
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Re: [PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 2:57 PM, padma venkat padma@gmail.com wrote:
 Hi,

 On Thu, Jun 30, 2011 at 1:01 PM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Thu, Jun 30, 2011 at 5:55 PM, Padmavathi Venna padm...@samsung.com 
 wrote:
 This patchset does the following:

 1. Move duplicated code to common place
 [PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
 SPI platform devices are defined in respective machine folder of
 Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
 So all SPI platform devices are moved to a common place.

 The machine specific code is put in machine specific location for some 
 reason.
 And the code is not duplicated, it's mostly data structures
 initialized with machine
 specific values.

 Have you considered if it would still be possible to build kernel
 image supporting
 more than 1 soc after your changes ?
 I didn't consider the single image scenario. Because as far as I know,
 the existing Samsung code doesn't have support for building a single kernel
 image for multiple SoCs.

Samsung did use to support during 24xx days. Unfortunately not much with
new generation SoCs.
This patch-set only takes us further away from having multiple SoCs
supported in a single kernel image some day.


 The intention behind my changes were
 1) To reuse the dev-spi files for all the SoCs, as this reduces the code size.
I already decided in favor of being able to support multiple SoCs in
single image.

 Also future SoCs with SPI can use the same file.
Only if they have _exactly_ same SPI block. Then most probably they'll have most
other blocks identical too (not sure if I can name such examples in public) and
can be supported under the same SoC name.
Otherwise different SoCs spanning last 5yrs are already supported by
the same SPI
driver. We must provide SoC specific bits to the driver either via one
place or the other.

-j
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[PATCH] ARM:SAMSUNG: DMA Cleanup as per sparse

2011-06-30 Thread Sangwook Lee 
Function declaration differs between file:s3c-pl330.c and file:dma.h
and SPARSE (Documentation/sparse.txt) gives error messages

Signed-off-by: Sangwook Lee sangwook@linaro.org
---
 arch/arm/plat-samsung/include/plat/dma.h |   16 
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/dma.h 
b/arch/arm/plat-samsung/include/plat/dma.h
index 2e8f8c6..7365f46 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -62,7 +62,7 @@ typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
  * request a dma channel exclusivley
 */
 
-extern int s3c2410_dma_request(unsigned int channel,
+extern int s3c2410_dma_request(enum dma_ch id,
   struct s3c2410_dma_client *, void *dev);
 
 
@@ -71,14 +71,14 @@ extern int s3c2410_dma_request(unsigned int channel,
  * change the state of the dma channel
 */
 
-extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
+extern int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op);
 
 /* s3c2410_dma_setflags
  *
  * set the channel's flags to a given state
 */
 
-extern int s3c2410_dma_setflags(unsigned int channel,
+extern int s3c2410_dma_setflags(enum dma_ch id,
unsigned int flags);
 
 /* s3c2410_dma_free
@@ -86,7 +86,7 @@ extern int s3c2410_dma_setflags(unsigned int channel,
  * free the dma channel (will also abort any outstanding operations)
 */
 
-extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
+extern int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *);
 
 /* s3c2410_dma_enqueue
  *
@@ -95,7 +95,7 @@ extern int s3c2410_dma_free(unsigned int channel, struct 
s3c2410_dma_client *);
  * drained before the buffer is given to the DMA system.
 */
 
-extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
+extern int s3c2410_dma_enqueue(enum dma_ch idx, void *id,
   dma_addr_t data, int size);
 
 /* s3c2410_dma_config
@@ -103,14 +103,14 @@ extern int s3c2410_dma_enqueue(unsigned int channel, void 
*id,
  * configure the dma channel
 */
 
-extern int s3c2410_dma_config(unsigned int channel, int xferunit);
+extern int s3c2410_dma_config(enum dma_ch id, int xferunit);
 
 /* s3c2410_dma_devconfig
  *
  * configure the device we're talking to
 */
 
-extern int s3c2410_dma_devconfig(unsigned int channel,
+extern int s3c2410_dma_devconfig(enum dma_ch id,
enum s3c2410_dmasrc source, unsigned long devaddr);
 
 /* s3c2410_dma_getposition
@@ -118,7 +118,7 @@ extern int s3c2410_dma_devconfig(unsigned int channel,
  * get the position that the dma transfer is currently at
 */
 
-extern int s3c2410_dma_getposition(unsigned int channel,
+extern int s3c2410_dma_getposition(enum dma_ch id,
   dma_addr_t *src, dma_addr_t *dest);
 
 extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
-- 
1.7.4.1

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Re: [PATCH] ARM:SAMSUNG: DMA Cleanup as per sparse

2011-06-30 Thread Jassi Brar 
On Thu, Jun 30, 2011 at 3:46 PM, Sangwook Lee sangwook@linaro.org wrote:
 Function declaration differs between file:s3c-pl330.c and file:dma.h
 and SPARSE (Documentation/sparse.txt) gives error messages

 Signed-off-by: Sangwook Lee sangwook@linaro.org

Acked-by: Jassi Brar jassisinghb...@gmail.com

 ---
  arch/arm/plat-samsung/include/plat/dma.h |   16 
  1 files changed, 8 insertions(+), 8 deletions(-)

 diff --git a/arch/arm/plat-samsung/include/plat/dma.h 
 b/arch/arm/plat-samsung/include/plat/dma.h
 index 2e8f8c6..7365f46 100644
 --- a/arch/arm/plat-samsung/include/plat/dma.h
 +++ b/arch/arm/plat-samsung/include/plat/dma.h
 @@ -62,7 +62,7 @@ typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan 
 *,
  * request a dma channel exclusivley
  */

 -extern int s3c2410_dma_request(unsigned int channel,
 +extern int s3c2410_dma_request(enum dma_ch id,
                               struct s3c2410_dma_client *, void *dev);


 @@ -71,14 +71,14 @@ extern int s3c2410_dma_request(unsigned int channel,
  * change the state of the dma channel
  */

 -extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
 +extern int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op);

  /* s3c2410_dma_setflags
  *
  * set the channel's flags to a given state
  */

 -extern int s3c2410_dma_setflags(unsigned int channel,
 +extern int s3c2410_dma_setflags(enum dma_ch id,
                                unsigned int flags);

  /* s3c2410_dma_free
 @@ -86,7 +86,7 @@ extern int s3c2410_dma_setflags(unsigned int channel,
  * free the dma channel (will also abort any outstanding operations)
  */

 -extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client 
 *);
 +extern int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *);

  /* s3c2410_dma_enqueue
  *
 @@ -95,7 +95,7 @@ extern int s3c2410_dma_free(unsigned int channel, struct 
 s3c2410_dma_client *);
  * drained before the buffer is given to the DMA system.
  */

 -extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
 +extern int s3c2410_dma_enqueue(enum dma_ch idx, void *id,
                               dma_addr_t data, int size);

  /* s3c2410_dma_config
 @@ -103,14 +103,14 @@ extern int s3c2410_dma_enqueue(unsigned int channel, 
 void *id,
  * configure the dma channel
  */

 -extern int s3c2410_dma_config(unsigned int channel, int xferunit);
 +extern int s3c2410_dma_config(enum dma_ch id, int xferunit);

  /* s3c2410_dma_devconfig
  *
  * configure the device we're talking to
  */

 -extern int s3c2410_dma_devconfig(unsigned int channel,
 +extern int s3c2410_dma_devconfig(enum dma_ch id,
                enum s3c2410_dmasrc source, unsigned long devaddr);

  /* s3c2410_dma_getposition
 @@ -118,7 +118,7 @@ extern int s3c2410_dma_devconfig(unsigned int channel,
  * get the position that the dma transfer is currently at
  */

 -extern int s3c2410_dma_getposition(unsigned int channel,
 +extern int s3c2410_dma_getposition(enum dma_ch id,
                                   dma_addr_t *src, dma_addr_t *dest);

  extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
 --
 1.7.4.1


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Re: [PATCH] arm: platsmp: Allow secondary cpu hotplug with maxcpus=1

2011-06-30 Thread Russell King - ARM Linux 
On Wed, Jun 29, 2011 at 11:31:39AM -0700, Stephen Boyd wrote:
  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  {
 - int i;
 -
   /*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
 - for (i = 0; i  max_cpus; i++)
 - set_cpu_present(i, true);
 + init_cpu_present(cpu_possible_map);

Ok, if we're now doing this in every platform, it might as well go into
arch/arm/kernel/smp.c - platforms can re-initialize the present map
in this callback if they need to do something different.
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Re: [PATCH v3 1/6] Samsung SoC ADC: use regulator (VDD for ADC).

2011-06-30 Thread Mark Brown 
On Thu, Jun 30, 2011 at 11:22:50AM +0300, Vasily Khoruzhick wrote:
 On Thursday 30 June 2011 10:49:30 MyungJoo Ham wrote:

  +   adc-vdd = regulator_get(dev, vdd);
  +   if (IS_ERR(adc-vdd)) {
  +   dev_err(dev, operating without regulator \vdd\ .\n);
  +   ret = PTR_ERR(adc-vdd);
  +   goto err_alloc;
  +   }
  +

 NACK. Make it optional, otherwise it breaks s3c24xx.

No, the above code is how the regulator API should be used.  The API
will stub itself out if not in use so unless the s3c24xx platforms are
using regulators and there's a couple of options in the regulator API
for handling partially defined hookups of regulators on the board.

If there isn't a separate supply for the regulators on S3C24xx devices
then I guess the best option is to provide that supply as a dummy
regulator in the s3c24xx core code.
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Re: [PATCH] arm: platsmp: Allow secondary cpu hotplug with maxcpus=1

2011-06-30 Thread Stephen Boyd 
On 6/30/2011 6:11 AM, Russell King - ARM Linux wrote:
 On Wed, Jun 29, 2011 at 11:31:39AM -0700, Stephen Boyd wrote:
  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  {
 -int i;
 -
  /*
   * Initialise the present map, which describes the set of CPUs
   * actually populated at the present time.
   */
 -for (i = 0; i  max_cpus; i++)
 -set_cpu_present(i, true);
 +init_cpu_present(cpu_possible_map);
 Ok, if we're now doing this in every platform, it might as well go into
 arch/arm/kernel/smp.c - platforms can re-initialize the present map
 in this callback if they need to do something different.

That sounds better. V2 coming soon.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

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Re: [PATCH 2/3] Samsung SoC: ready to use NTC value inside kernel

2011-06-30 Thread MyungJoo Ham 
On Thu, Jun 30, 2011 at 6:00 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
 On Thu, Jun 30, 2011 at 05:26:26PM +0900, MyungJoo Ham wrote:
 diff --git a/arch/arm/plat-samsung/dev-adc.c 
 b/arch/arm/plat-samsung/dev-adc.c
 index 622972c..526097a 100644
 --- a/arch/arm/plat-samsung/dev-adc.c
 +++ b/arch/arm/plat-samsung/dev-adc.c
 @@ -22,6 +22,8 @@
  #include plat/devs.h
  #include plat/cpu.h

 +#include ../../../fs/sysfs/sysfs.h

 That is a big hint that you're doing something wrong.

[]

 This is wrong on just about every level.  It needs to be rewritten to
 avoid poking about in subsystem internal data structures, and you really
 should not be sprint-ing a value to only sscanf it later.

 Plus, container_of doesn't return a pointer-error code.

 You need to come up with a far better way of doing this altogether.


Um.. is there any clean and nice way to read values that are exported to sysfs?

Or if the values are only exported through sysfs (HWMON), is the only
clean way to read such values (w/o extending HWMON itself) to seperate
the HWMON device driver into two pieces: a platform driver that
provide values to somewhere sharable in kernel and a HWMON driver that
reads the values and exports them to sysfs?



Thanks.

- MyungJoo

-- 
MyungJoo Ham (함명주), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
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RE: [PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

2011-06-30 Thread Kukjin Kim 
Russell King - ARM Linux wrote:
 
 On Fri, Jun 24, 2011 at 10:37:50AM +0100, Russell King - ARM Linux wrote:
  On Fri, Jun 24, 2011 at 04:42:26PM +0900, Kukjin Kim wrote:
   Russell King - ARM Linux wrote:
  

(snip)

 
 Here's an updated patch for it against the v3 set of patches.
 
  arch/arm/include/asm/suspend.h |9 +
  arch/arm/kernel/sleep.S|   11 +--
  2 files changed, 14 insertions(+), 6 deletions(-)
 
 diff --git a/arch/arm/include/asm/suspend.h
b/arch/arm/include/asm/suspend.h
 index f8db9d0..54821b5 100644
 --- a/arch/arm/include/asm/suspend.h
 +++ b/arch/arm/include/asm/suspend.h
 @@ -10,12 +10,13 @@ extern void cpu_resume(void);
   * Hide the first two arguments to __cpu_suspend - these are an
implementation
   * detail which platform code shouldn't have to know about.
   */
 -static inline void cpu_suspend(unsigned long arg, void (*fn)(unsigned
long))
 +static inline int cpu_suspend(unsigned long arg, void (*fn)(unsigned
long))
  {
 - extern void __cpu_suspend(int, long, unsigned long,
 -   void (*)(unsigned long));
 - __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
 + extern int __cpu_suspend(int, long, unsigned long,
 +  void (*)(unsigned long));
 + int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
   flush_tlb_all();
 + return ret;
  }
 
  #endif
 diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
 index c156d0e..dc902f2 100644
 --- a/arch/arm/kernel/sleep.S
 +++ b/arch/arm/kernel/sleep.S
 @@ -12,7 +12,6 @@
   *  r1 = v:p offset
   *  r2 = suspend function arg0
   *  r3 = suspend function
 - * Note: does not return until system resumes
   */
  ENTRY(__cpu_suspend)
   stmfd   sp!, {r4 - r11, lr}
 @@ -26,7 +25,7 @@ ENTRY(__cpu_suspend)
  #endif
   mov r6, sp  @ current virtual SP
   sub sp, sp, r5  @ allocate CPU state on stack
 - mov r0, sp  @ save pointer
 + mov r0, sp  @ save pointer to CPU save block
   add ip, ip, r1  @ convert resume fn to phys
   stmfd   sp!, {r1, r6, ip}   @ save v:p, virt SP, phys resume fn
   ldr r5, =sleep_save_sp
 @@ -55,10 +54,17 @@ ENTRY(__cpu_suspend)
  #else
   bl  __cpuc_flush_kern_all
  #endif
 + adr lr, BSYM(cpu_suspend_abort)
   ldmfd   sp!, {r0, pc}   @ call suspend fn
  ENDPROC(__cpu_suspend)
   .ltorg
 
 +cpu_suspend_abort:
 + ldmia   sp!, {r1 - r3}  @ pop v:p, virt SP, phys resume fn
 + mov sp, r2

Russell thanks.

How do you think to add following for handling failure of cpu_suspend?

+   mov r0, #-1

Thanks.

Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

 + ldmfd   sp!, {r4 - r11, pc}
 +ENDPROC(cpu_suspend_abort)
 +
  /*
   * r0 = control register value
   * r1 = v:p offset (preserved by cpu_do_resume)
 @@ -89,6 +95,7 @@ cpu_resume_after_mmu:
   str r5, [r2, r4, lsl #2]@ restore old mapping
   mcr p15, 0, r0, c1, c0, 0   @ turn on D-cache
   bl  cpu_init@ restore the und/abt/irq banked
regs
 + mov r0, #0  @ return zero on success
   ldmfd   sp!, {r4 - r11, pc}
  ENDPROC(cpu_resume_after_mmu)
 

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[PATCH V2 0/8] ARM: EXYNOS4: Update PM

2011-06-30 Thread Kukjin Kim 
This patch updates EXYNOS4 PM based on Russell's suspend consolidation patches.

NOTE: Depends on external GIC patches which are from Changhwan Youn.

Changes since V1:
- address comments from Russell King

[PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration
[PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM
[PATCH V2 3/8] ARM: EXYNOS4: Add support PM with external GIC
[PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode
[PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode
[PATCH V2 6/8] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM
[PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers
[PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL
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[PATCH V2 4/8] ARM: SAMSUNG: Add support for failure of sleep mode

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/plat-samsung/pm.c |7 ++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 69d6b04..df12645 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -299,7 +299,10 @@ static int s3c_pm_enter(suspend_state_t state)
 * we resume as it saves its own register state and restores it
 * during the resume.  */
 
-   cpu_suspend(0, pm_cpu_sleep);
+   /* If entering sleep mode is failed, non-zero value is returned */
+
+   if (cpu_suspend(0, pm_cpu_sleep));
+   goto exit;
 
/* restore the system state */
 
@@ -323,6 +326,8 @@ static int s3c_pm_enter(suspend_state_t state)
/* ok, let's return from sleep */
 
S3C_PMDBG(S3C PM Resume (post-restore)\n);
+
+exit:
return 0;
 }
 
-- 
1.7.1

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[PATCH V2 1/8] ARM: EXYNOS4: Support system level power down configuration

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

EXYNOS4 supports 3 different system level power down mode by PMU (Power
Management Unit). Each power down mode need to configure many PMU registers
with different value. This patch supports function to configure PMU registers
with pre-defined values in PMU code. This function may be used by PM code and
AFTR/LPA support driver.

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/mach-exynos4/Makefile   |2 +-
 arch/arm/mach-exynos4/include/mach/pmu.h |   25 +
 arch/arm/mach-exynos4/pmu.c  |  175 ++
 3 files changed, 201 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/include/mach/pmu.h
 create mode 100644 arch/arm/mach-exynos4/pmu.c

diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..880f902 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,7 +13,7 @@ obj-  :=
 # Core support for EXYNOS4 system
 
 obj-$(CONFIG_CPU_EXYNOS4210)   += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)   += setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210)   += setup-i2c0.o irq-eint.o dma.o pmu.o
 obj-$(CONFIG_PM)   += pm.o sleep.o
 obj-$(CONFIG_CPU_FREQ) += cpufreq.o
 obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h 
b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000..a952904
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+   SYS_AFTR,
+   SYS_LPA,
+   SYS_SLEEP,
+   NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 000..7ea9eb2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+
+#include mach/regs-clock.h
+#include mach/pmu.h
+
+static void __iomem *sys_powerdown_reg[] = {
+   S5P_ARM_CORE0_LOWPWR,
+   S5P_DIS_IRQ_CORE0,
+   S5P_DIS_IRQ_CENTRAL0,
+   S5P_ARM_CORE1_LOWPWR,
+   S5P_DIS_IRQ_CORE1,
+   S5P_DIS_IRQ_CENTRAL1,
+   S5P_ARM_COMMON_LOWPWR,
+   S5P_L2_0_LOWPWR,
+   S5P_L2_1_LOWPWR,
+   S5P_CMU_ACLKSTOP_LOWPWR,
+   S5P_CMU_SCLKSTOP_LOWPWR,
+   S5P_CMU_RESET_LOWPWR,
+   S5P_APLL_SYSCLK_LOWPWR,
+   S5P_MPLL_SYSCLK_LOWPWR,
+   S5P_VPLL_SYSCLK_LOWPWR,
+   S5P_EPLL_SYSCLK_LOWPWR,
+   S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+   S5P_CMU_RESET_GPSALIVE_LOWPWR,
+   S5P_CMU_CLKSTOP_CAM_LOWPWR,
+   S5P_CMU_CLKSTOP_TV_LOWPWR,
+   S5P_CMU_CLKSTOP_MFC_LOWPWR,
+   S5P_CMU_CLKSTOP_G3D_LOWPWR,
+   S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+   S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+   S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+   S5P_CMU_CLKSTOP_GPS_LOWPWR,
+   S5P_CMU_RESET_CAM_LOWPWR,
+   S5P_CMU_RESET_TV_LOWPWR,
+   S5P_CMU_RESET_MFC_LOWPWR,
+   S5P_CMU_RESET_G3D_LOWPWR,
+   S5P_CMU_RESET_LCD0_LOWPWR,
+   S5P_CMU_RESET_LCD1_LOWPWR,
+   S5P_CMU_RESET_MAUDIO_LOWPWR,
+   S5P_CMU_RESET_GPS_LOWPWR,
+   S5P_TOP_BUS_LOWPWR,
+   S5P_TOP_RETENTION_LOWPWR,
+   S5P_TOP_PWR_LOWPWR,
+   S5P_LOGIC_RESET_LOWPWR,
+   S5P_ONENAND_MEM_LOWPWR,
+   S5P_MODIMIF_MEM_LOWPWR,
+   S5P_G2D_ACP_MEM_LOWPWR,
+   S5P_USBOTG_MEM_LOWPWR,
+   S5P_HSMMC_MEM_LOWPWR,
+   S5P_CSSYS_MEM_LOWPWR,
+   S5P_SECSS_MEM_LOWPWR,
+   S5P_PCIE_MEM_LOWPWR,
+   S5P_SATA_MEM_LOWPWR,
+   S5P_PAD_RETENTION_DRAM_LOWPWR,
+   S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+   S5P_PAD_RETENTION_GPIO_LOWPWR,
+   S5P_PAD_RETENTION_UART_LOWPWR,
+   S5P_PAD_RETENTION_MMCA_LOWPWR,
+   S5P_PAD_RETENTION_MMCB_LOWPWR,
+   S5P_PAD_RETENTION_EBIA_LOWPWR,
+   S5P_PAD_RETENTION_EBIB_LOWPWR,
+   S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+   S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+

[PATCH V2 7/8] ARM: EXYNOS4: Add save/restore for other ARM registers

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

This patch adds save/restore values for Power Control Register and
Diagnostic Register for PM.

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/mach-exynos4/pm.c |   24 
 1 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index a658318..4130e5a 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -238,6 +238,9 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
 };
 
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
 void exynos4_cpu_suspend(unsigned long arg)
 {
outer_flush_all();
@@ -329,6 +332,16 @@ static int exynos4_pm_suspend(void)
tmp = ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
+   /* Save Power control register */
+   asm (mrc p15, 0, %0, c15, c0, 0
+: =r (tmp) : : cc);
+   save_arm_register[0] = tmp;
+
+   /* Save Diagnostic register */
+   asm (mrc p15, 0, %0, c15, c0, 1
+: =r (tmp) : : cc);
+   save_arm_register[1] = tmp;
+
return 0;
 }
 
@@ -349,6 +362,17 @@ static void exynos4_pm_resume(void)
/* No need to perform below restore code */
goto early_wakeup;
}
+   /* Restore Power control register */
+   tmp = save_arm_register[0];
+   asm volatile (mcr p15, 0, %0, c15, c0, 0
+ : : r (tmp)
+ : cc);
+
+   /* Restore Diagnostic register */
+   tmp = save_arm_register[1];
+   asm volatile (mcr p15, 0, %0, c15, c0, 1
+ : : r (tmp)
+ : cc);
 
/* For release retention */
 
-- 
1.7.1

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[PATCH V2 5/8] ARM: EXYNOS4: Support early wakeup entering sleep mode

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

Since early wakeup can be handled in pm so we don't need masking
interrupts of external GIC. When the early wakeup interrupt happens,
PMU(Power Management Unit) ignores WFI instruction. This means that
PC(Program Counter) passed without any changes. This patch can handle
that case by early wakeup interrupt.

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/mach-exynos4/pm.c |   43 +++
 1 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 9b5f3a5..17d43c2 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -241,7 +241,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
 void exynos4_cpu_suspend(unsigned long arg)
 {
unsigned long tmp;
-   unsigned long mask = 0x;
 
/* Setting Central Sequence Register for power down mode */
 
@@ -249,33 +248,10 @@ void exynos4_cpu_suspend(unsigned long arg)
tmp = ~(S5P_CENTRAL_LOWPWR_CFG);
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-   /* Setting Central Sequence option Register */
-
-   tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-   tmp = ~(S5P_USE_MASK);
-   tmp |= S5P_USE_STANDBY_WFI0;
-   __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
-   /* Clear all interrupt pending to avoid early wakeup */
-
-   __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
-   __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
-   __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
-   /* Disable all interrupt */
-
-   __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
-   __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
-   __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
-   __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
outer_flush_all();
 
/* issue the standby signal into the pm unit. */
cpu_do_idle();
-
-   /* we should never get past here */
-   panic(sleep resumed to originator?);
 }
 
 static void exynos4_pm_prepare(void)
@@ -353,6 +329,22 @@ arch_initcall(exynos4_pm_drvinit);
 
 static void exynos4_pm_resume(void)
 {
+   unsigned long tmp;
+
+   /*
+* If PMU failed while entering sleep mode, WFI will be
+* ignored by PMU and then exiting cpu_do_idle().
+* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+* in this situation.
+*/
+   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+   if (!(tmp  S5P_CENTRAL_LOWPWR_CFG)) {
+   tmp |= S5P_CENTRAL_LOWPWR_CFG;
+   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+   /* No need to perform below restore code */
+   goto early_wakeup;
+   }
+
/* For release retention */
 
__raw_writel((1  28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -373,6 +365,9 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
 #endif
+
+early_wakeup:
+   return;
 }
 
 static struct syscore_ops exynos4_pm_syscore_ops = {
-- 
1.7.1

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[PATCH V2 2/8] ARM: EXYNOS4: Remove PMU configuration for S2RAM

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed
and using function which provided by PMU support code to configure
PMU register.

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/mach-exynos4/pm.c |   77 +--
 1 files changed, 2 insertions(+), 75 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 5c01c60..4d9ee97 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -30,80 +30,7 @@
 #include mach/regs-clock.h
 #include mach/regs-pmu.h
 #include mach/pm-core.h
-
-static struct sleep_save exynos4_sleep[] = {
-   { .reg = S5P_ARM_CORE0_LOWPWR   , .val = 0x2, },
-   { .reg = S5P_DIS_IRQ_CORE0  , .val = 0x0, },
-   { .reg = S5P_DIS_IRQ_CENTRAL0   , .val = 0x0, },
-   { .reg = S5P_ARM_CORE1_LOWPWR   , .val = 0x2, },
-   { .reg = S5P_DIS_IRQ_CORE1  , .val = 0x0, },
-   { .reg = S5P_DIS_IRQ_CENTRAL1   , .val = 0x0, },
-   { .reg = S5P_ARM_COMMON_LOWPWR  , .val = 0x2, },
-   { .reg = S5P_L2_0_LOWPWR, .val = 0x3, },
-   { .reg = S5P_L2_1_LOWPWR, .val = 0x3, },
-   { .reg = S5P_CMU_ACLKSTOP_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_SCLKSTOP_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_RESET_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
-   { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
-   { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
-   { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_CAM_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_TV_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_RESET_MFC_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_G3D_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_LCD0_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_LCD1_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR, .val = 0x0, },
-   { .reg = S5P_CMU_RESET_GPS_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
-   { .reg = S5P_TOP_RETENTION_LOWPWR   , .val = 0x1, },
-   { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
-   { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
-   { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
-   { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
-   { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
-   { .reg = S5P_USBOTG_MEM_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_HSMMC_MEM_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_CSSYS_MEM_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_SECSS_MEM_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_PCIE_MEM_LOWPWR, .val = 0x0, },
-   { .reg = S5P_SATA_MEM_LOWPWR, .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR, .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_UART_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR  , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
-   { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR   , .val = 0x0, },
-   { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
-   { .reg = S5P_XXTI_LOWPWR

[PATCH V2 8/8] ARM: EXYNOS4: Add save/restore function for PLL

2011-06-30 Thread Kukjin Kim 
From: Jaecheol Lee jc@samsung.com

The PLL restore routine supports waiting pll locking. If PLL is
enabled in restoring sequence, it should wait until PLL is locked.

Signed-off-by: Jaecheol Lee jc@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
 arch/arm/mach-exynos4/include/mach/regs-clock.h |9 ++
 arch/arm/mach-exynos4/pm.c  |   96 ++-
 2 files changed, 101 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h 
b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..64bdd24 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
 #define S5P_CLKDIV_STAT_RIGHTBUS   S5P_CLKREG(0x08600)
 #define S5P_CLKGATE_IP_RIGHTBUSS5P_CLKREG(0x08800)
 
+#define S5P_EPLL_LOCK  S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK  S5P_CLKREG(0x0C020)
+
 #define S5P_EPLL_CON0  S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1  S5P_CLKREG(0x0C114)
 #define S5P_VPLL_CON0  S5P_CLKREG(0x0C120)
@@ -120,6 +123,12 @@
 #define S5P_APLL_VAL_1000  ((250  16) | (6  8) | 1)
 #define S5P_APLL_VAL_800   ((200  16) | (6  8) | 1)
 
+#define S5P_EPLLCON0_ENABLE_SHIFT  (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT  (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT  (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT  (29)
+
 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT   (16)
 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK(0x7  
S5P_CLKSRC_CPU_MUXCORE_SHIFT)
 
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 4130e5a..e3d4147 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,12 +18,15 @@
 #include linux/suspend.h
 #include linux/syscore_ops.h
 #include linux/io.h
+#include linux/err.h
+#include linux/clk.h
 
 #include asm/cacheflush.h
 #include asm/hardware/cache-l2x0.h
 
 #include plat/cpu.h
 #include plat/pm.h
+#include plat/pll.h
 
 #include mach/regs-irq.h
 #include mach/regs-gpio.h
@@ -45,16 +48,22 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC, .val = 0x0001, },
 };
 
+static struct sleep_save exynos4_epll_save[] = {
+   SAVE_ITEM(S5P_EPLL_CON0),
+   SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+   SAVE_ITEM(S5P_VPLL_CON0),
+   SAVE_ITEM(S5P_VPLL_CON1),
+};
+
 static struct sleep_save exynos4_core_save[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-   SAVE_ITEM(S5P_EPLL_CON0),
-   SAVE_ITEM(S5P_EPLL_CON1),
-   SAVE_ITEM(S5P_VPLL_CON0),
-   SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
@@ -255,6 +264,8 @@ static void exynos4_pm_prepare(void)
 
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+   s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+   s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
tmp = __raw_readl(S5P_INFORM1);
 
@@ -302,12 +313,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all();
 }
 
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+   unsigned long pll_con, locktime, lockcnt;
+   unsigned long pll_in_rate;
+   unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+   if (pll_base_rate == 0)
+   return;
+
+   pll_in_rate = pll_base_rate;
+
+   /* EPLL */
+   pll_con = exynos4_epll_save[0].val;
+
+   if (pll_con  (1  31)) {
+   pll_con = (PLL46XX_PDIV_MASK  PLL46XX_PDIV_SHIFT);
+   p_div = (pll_con  PLL46XX_PDIV_SHIFT);
+
+   pll_in_rate /= 100;
+
+   locktime = (3000 / pll_in_rate) * p_div;
+   lockcnt = locktime * 1 / (1 / pll_in_rate);
+
+   __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+   s3c_pm_do_restore_core(exynos4_epll_save,
+   ARRAY_SIZE(exynos4_epll_save));
+   epll_wait = 1;
+   }
+
+   pll_in_rate = pll_base_rate;
+
+   /* VPLL */
+   pll_con = exynos4_vpll_save[0].val;
+
+   if (pll_con  (1  31)) {
+   pll_in_rate /= 100;
+   /* 750us */
+   locktime = 750;
+   lockcnt = locktime * 1 / (1 / pll_in_rate);
+
+   __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+   s3c_pm_do_restore_core(exynos4_vpll_save,
+   ARRAY_SIZE(exynos4_vpll_save));
+   vpll_wait = 1;
+   }
+
+   /*

Re: [PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs

2011-06-30 Thread padma venkat 
Hi Russell,Jassi

On Thu, Jun 30, 2011 at 3:13 PM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Thu, Jun 30, 2011 at 3:00 PM, Russell King - ARM Linux
 li...@arm.linux.org.uk wrote:
 On Thu, Jun 30, 2011 at 08:25:19AM -0400, Padmavathi Venna wrote:
 SPI Clocks were defined in dev-spi.c of machine specific folder.
 To make SPI devices common across all SoCs,dev-spi.c is moved
 from machine specific folder to plat-samsung. So SPI clock
 definitions has been moved from dev-spi.c to SoC specific machine
 folder for S3C64XX,S5P64X0,S5PC100 and S5PV210

 This just shows how sick the Samsung code is by abusing the clk API.
 If it stopped that abuse and switched over to clkdev none of this would
 be necessary.
 I am anyways not for the patch set.
 Though this 'sickness' predates clkdev, and I agree it should be changed now.

I will prepare new set of patches based on clkdev code and send for review.

ThanksRegards
Padma

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Re: [PATCH 0/7] ARM: SAMSUNG: Cleanup SPI platform specific code

2011-06-30 Thread padma venkat 
Hi Marek,

On Thu, Jun 30, 2011 at 2:55 PM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
 Hello,

 On Thursday, June 30, 2011 2:25 PM Padmavathi Venna wrote:

 This patchset does the following:

 1. Move duplicated code to common place
 [PATCH 1/7] ARM: SAMSUNG: Move SPI device definitions to plat-samsung
 SPI platform devices are defined in respective machine folder of
 Samsung S3C64XX and S5P series SoCs.This is duplicated for every SoC.
 So all SPI platform devices are moved to a common place.

 [PATCH 2/7] ARM: SAMSUNG: Define common macro for SPI physical address

 [PATCH 3/7] ARM: SAMSUNG: Add SPI clock definitions for SAMSUNG SoCs
 Each SoC has it's own set of clock sources for SPI.So they are defined in
 respective machine folder.

 [PATCH 4/7] ARM: SAMSUNG: Create SPI device setup files in
 respective machine folder

 [PATCH 5/7] ARM: SAMSUNG: Add SPI platform specific code
 As SPI platform devices are moved to common place some platform specific
 code need to be initialized in the respective machine file.

 [PATCH 6/7] SPI: S5PC100: Enable the SPI driver for S5PC100

 [PATCH 7/7] SPI: S5PV210: Enable the SPI driver for S5PV210

 These patch set improves a bit platform part of SPI driver, but I really
 wonder if we really need to pass so many SoC version specific data
 with platform data. Are all these data (clock list, fifo parameters)
 specific to SoC version or particular board configuration/implementation?

 Maybe it will be much easier to convert the SPI driver to use driver id
 feature and use different platform id's for each SoC version? (please
 refer to drivers/video/s3c-fb.c and plat-samsung/include/plat/fb-core.h
 for more information). This will remove the need for SoC specific
 parameters in platform data and will group all version dependent
 information in the driver.

Thanks for your suggestion. I will consider your comments for the
next patch set based on clkdev code.

ThanksRegards
Padma

 Best regards
 --
 Marek Szyprowski
 Samsung Poland RD Center



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[PATCH] ARM: EXYNOS4: Add support Core1 Power On/Off with hotplug in/out

2011-06-30 Thread JungHi Min 
To insert the code for power on/off with pmu control to support hotplug in/out 
core1
As for hotplug.c, the codes for core1 to be hotplug in/out is inserted.
As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined.
As for platsmp.c, the codes for core1 to be powered on is inserted.

Signed-off-by: JungHi Min junghi@samsung.com
---
 arch/arm/mach-exynos4/hotplug.c   |   13 ++
 arch/arm/mach-exynos4/include/mach/regs-pmu.h |1 +
 arch/arm/mach-exynos4/platsmp.c   |   33 +++-
 3 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 2b5909e..7490789 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -13,9 +13,12 @@
 #include linux/kernel.h
 #include linux/errno.h
 #include linux/smp.h
+#include linux/io.h
 
 #include asm/cacheflush.h
 
+#include mach/regs-pmu.h
+
 extern volatile int pen_release;
 
 static inline void cpu_enter_lowpower(void)
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
-   /*
-* there is no power-control hardware on this platform, so all
-* we can do is put the core into WFI; this is safe as the calling
-* code will have already disabled interrupts
-*/
for (;;) {
+
+   /* make cpu1 to be turned off at next WFI command */
+   if (cpu == 1)
+   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+
/*
 * here's the WFI
 */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h 
b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a964337..96de0e7 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
 #define S5P_PMU_GPS_CONF   S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN0x1
+#define S5P_CORE_LOCAL_PWR_EN  0x3
 #define S5P_INT_LOCAL_PWR_EN   0x7

 define S5P_CHECK_SLEEP 0x0BAD
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index c5e65a0..15aa2c0 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
 
 #include mach/hardware.h
 #include mach/regs-clock.h
+#include mach/regs-pmu.h
 
 extern void exynos4_secondary_startup(void);
 
+#define CPU1_BOOT_REG S5P_VA_SYSRAM
+
 /*
  * control for which core is the next to come out of the secondary
  * boot holding pen
@@ -100,16 +103,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(cpu);
 
+   if (!(__raw_readl(S5P_ARM_CORE1_STATUS)  S5P_CORE_LOCAL_PWR_EN)) {
+   __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+S5P_ARM_CORE1_CONFIGURATION);
+
+   timeout = 10;
+
+   /* wait max 10 ms until cpu1 is on */
+   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+   if (timeout-- == 0)
+   break;
+
+   mdelay(1);
+   }
+
+   if (timeout == 0) {
+   printk(KERN_ERR cpu1 power enable failed);
+   spin_unlock(boot_lock);
+   return -ETIMEDOUT;
+   }
+   }
/*
 * Send the secondary CPU a soft interrupt, thereby causing
 * the boot monitor to read the system wide flags register,
 * and branch to the address found there.
 */
-   gic_raise_softirq(cpumask_of(cpu), 1);
 
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
+
+   __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+   CPU1_BOOT_REG);
+   gic_raise_softirq(cpumask_of(cpu), 1);
+
if (pen_release == -1)
break;
 
-- 
1.7.1

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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread padma venkat 
Hi Tony,

On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal ton...@gmail.com wrote:
 Hi Padma,
 With regards to your patch, even though one can check the tx done status
 using the TX_DONE bit, the present macro itself would work perfectly fine if
 the 'fifo_lvl_mask' is set properly.
 For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff (for 9bits,
 15:23), while even in your patch, it is wrongly set as 0x7f(only 7bits).

 Thus, if this fifo_lvl_mask was defined correctly, the existing macro would
 itself have worked.
Thanks for your comment.
I considered changing to the fifo_lvl_mask to 1ff as you mentioned.
But I  think that the fifo_lvl_mask reflects the actual FIFO capacity
in the SPI driver.
For the failing channels the FIFO trigger level is 64 bytes and so i
retained that value.
In the driver it polls till the FIFO capacity level otherwise it goes
for DMA.So if we keep
the FIFO level as 1ff when the actual capacity is 7f then it fails.

Jassi what do you think about this?

ThanksRegards
Padma

 Thanks,
 Tony

 On Thu, Jun 30, 2011 at 3:22 PM, Jassi Brar jassisinghb...@gmail.com
 wrote:

 On Thu, Jun 30, 2011 at 2:35 PM, padma venkat padma@gmail.com wrote:
  Hi,
 
  On Thu, Jun 30, 2011 at 12:38 PM, Jassi Brar jassisinghb...@gmail.com
  wrote:
  On Thu, Jun 30, 2011 at 6:08 PM, Padmavathi Venna padm...@samsung.com
  wrote:
  Fixed the bug in transmission status check for 64 bytes FIFO
  level.
 
  Signed-off-by: Padmavathi Venna padm...@samsung.com
  ---
   drivers/spi/spi_s3c64xx.c |    4 +---
   1 files changed, 1 insertions(+), 3 deletions(-)
 
  diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.hc
  index 795828b..8945e20 100644
  --- a/drivers/spi/spi_s3c64xx.c
  +++ b/drivers/spi/spi_s3c64xx.c
  @@ -116,9 +116,7 @@
                                         (((i)-fifo_lvl_mask + 1))) \
                                         ? 1 : 0)
 
  -#define S3C64XX_SPI_ST_TX_DONE(v, i) v)  (i)-rx_lvl_offset) 
  \
  -                                       (((i)-fifo_lvl_mask + 1) 
  1)) \
  -                                       ? 1 : 0)
  +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v)  (1  (i)-tx_st_done))
  ? 1 : 0)
 
  IIRC the macro is already designed to deduct tx-done levels from other
  fields.
  Could you please _explain_ with one example where it fails ? It is
  difficult to see without
  numbers.
  The existing macro fails for following scenarios.
  1) S5P64X0 channel 1
  2) S5PV210 channel 1
  3) S5PV310 channel 1 and channel 2
 
  The FIFO data level supported in the above SoCs either 64 or 256
  bytes depending on the channel. Because of this the TX_DONE
  is the 25 bit in the status register.
 
  The existing macro works for the following scenarios
  1) S3C6410 all channels
  2) S5PC100 all channels
 
  The FIFO data level supported in the above SoCs 64 bytes
  on all the channels. Because of this the TX_DONE is the 21 bit
  in the status register.
 
  So when we use the existing macro for the non-working SoCs
  it is not anding with the TX_DONE bit but it is only anding the bits
  earlier to TX_DONE bit.
 

 I see.
 I don't have access to post s3c64xx datasheets. Please confirm if TX_DONE
 bit at same offset for all channels of an SoC. If so, I am OK with
 these 2 patches.

 Thanks,
 Jassi
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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread Jassi Brar 
On Fri, Jul 1, 2011 at 11:16 AM, padma venkat padma@gmail.com wrote:
 Hi Tony,

 On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal ton...@gmail.com wrote:
 Hi Padma,
 With regards to your patch, even though one can check the tx done status
 using the TX_DONE bit, the present macro itself would work perfectly fine if
 the 'fifo_lvl_mask' is set properly.
 For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff (for 9bits,
 15:23), while even in your patch, it is wrongly set as 0x7f(only 7bits).

 Thus, if this fifo_lvl_mask was defined correctly, the existing macro would
 itself have worked.
 Thanks for your comment.
 I considered changing to the fifo_lvl_mask to 1ff as you mentioned.
 But I  think that the fifo_lvl_mask reflects the actual FIFO capacity
 in the SPI driver.
 For the failing channels the FIFO trigger level is 64 bytes and so i
 retained that value.
 In the driver it polls till the FIFO capacity level otherwise it goes
 for DMA.So if we keep
 the FIFO level as 1ff when the actual capacity is 7f then it fails.

 Jassi what do you think about this?


'fifo_lvl_mask' is h/w specific and can't be set for convenience.

I don't have access to post-s3c64xx datasheets.
Please check and reply if TX_DONE bit is at same offset for all
channels of an SoC, because
I suspect it's otherwise.
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Re: [PATCH 2/2] SPI: SAMSUNG: Bug fix for SPI with different FIFO level

2011-06-30 Thread padma venkat 
Hi Jassi,

On Fri, Jul 1, 2011 at 11:22 AM, Jassi Brar jassisinghb...@gmail.com wrote:
 On Fri, Jul 1, 2011 at 11:16 AM, padma venkat padma@gmail.com wrote:
 Hi Tony,

 On Thu, Jun 30, 2011 at 4:30 PM, Tony Nadackal ton...@gmail.com wrote:
 Hi Padma,
 With regards to your patch, even though one can check the tx done status
 using the TX_DONE bit, the present macro itself would work perfectly fine if
 the 'fifo_lvl_mask' is set properly.
 For example in 6450 channel 1, the fifo_lvl_mask should be 0x1ff (for 9bits,
 15:23), while even in your patch, it is wrongly set as 0x7f(only 7bits).

 Thus, if this fifo_lvl_mask was defined correctly, the existing macro would
 itself have worked.
 Thanks for your comment.
 I considered changing to the fifo_lvl_mask to 1ff as you mentioned.
 But I  think that the fifo_lvl_mask reflects the actual FIFO capacity
 in the SPI driver.
 For the failing channels the FIFO trigger level is 64 bytes and so i
 retained that value.
 In the driver it polls till the FIFO capacity level otherwise it goes
 for DMA.So if we keep
 the FIFO level as 1ff when the actual capacity is 7f then it fails.

 Jassi what do you think about this?


 'fifo_lvl_mask' is h/w specific and can't be set for convenience.

 I don't have access to post-s3c64xx datasheets.
 Please check and reply if TX_DONE bit is at same offset for all
 channels of an SoC, because
 I suspect it's otherwise.

Yes. The TX_DONE bit is at the same offset for all the channels of an SoC.
in S5P64X0,S5PV210 and S5PV310 it is at offset 25.
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