date:20120204

Re: [PATCH 4/4] [SCSI] ufshcd: SCSI error handling

2012-02-04 Thread Namjae Jeon

> +
> +/**
> + * ufshcd_abort - abort a specific command
> + * @cmd: SCSI command pointer
> + *
> + * Returns 0 on success, non-zero value on failure
> + */
> +static int ufshcd_abort(struct scsi_cmnd *cmd)
> +{
> +       struct Scsi_Host *host;
> +       struct ufs_hba *hba;
> +       unsigned long flags;
> +       unsigned int tag;
> +       unsigned int pos;
> +       int err;
> +
> +       host = cmd->device->host;
> +       hba = (struct ufs_hba *) host->hostdata;
> +       tag = cmd->request->tag;
> +
> +       spin_lock_irqsave(host->host_lock, flags);
> +       pos = (1 << tag);
> +
> +       /* check if command is still pending */
> +       if (!(hba->outstanding_reqs & pos)) {
> +               err = -1;
> +               spin_unlock_irqrestore(host->host_lock, flags);
> +               goto out;
> +       }
> +
> +       err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK);
Hi.
You called spin_lock_irqsave in ufshcd_issue_tm_cmd() without
spin_unlock_irqrestore.

> +       if (!err) {
> +               spin_lock_irqsave(host->host_lock, flags);
This case is same also.
Thanks.
> +               scsi_dma_unmap(cmd);
> +
> +               /* clear the respective UTRLCLR bit */
> +               writel(~pos,
> +                       (UFSHCD_MMIO_BASE +
> +                        REG_UTP_TRANSFER_REQ_LIST_CLEAR));
> +               hba->outstanding_reqs &= ~pos;
> +               hba->lrb[tag].cmd = NULL;
> +               spin_unlock_irqrestore(host->host_lock, flags);
> +       }
> +out:
> +       return err;
> +}
> +
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Re: [PATCH 0/4] [SCSI] ufshcd: UFS Host Controller Driver

2012-02-04 Thread Namjae Jeon

2012/2/2 Vinayak Holikatti :
> From: Santosh Yaraganavi 
>
> UFS is designed to be the most advanced specification for
> both embedded and removable flash memory-based storage in mobile devices
> such as smart phones and tablet computers.  The UFS standard represents
> an evolutionary progression of JEDEC standards in this field, and has been
> specifically tailored for mobile applications and computing systems requiring
> high performance and low power consumption.  The initial data throughput for
> UFS will be ~300 megabytes per second (MB/s), and the standard also supports
> command queuing features to raise random read/write speeds.
>
> To achieve the highest performance and most power efficient data
> transport, UFS uses the leading industry interface standards to form its
> Interconnect Layer: MIPI® Alliance’s M-PHY and UniProSM  specifications.
> UniPro is a comprehensive specification meant to act as a universal
> chip-to-chip protocol, providing a common tunnel for other protocols.
> The M-PHY interface is designed as the primary physical interface (PHY layer)
> for the UniPro specification, and is a high speed serial interface targeting
> up to 2.9 gigabits per second (Gbps) per lane with up-scalability to 5.8Gbps
> per lane.
>
> MIPI’s M-PHY and UniPro specifications are optimized for mobile applications,
> and are designed from the ground up for efficient power management in mobile
> devices, including enabling efficient transitions between the active and power
> save modes. Combined with a low active power level and a near-zero idle power
> level, UFS offers the promise for significant reductions in device power
> consumption.
>
> The UFS standard adopts the well-known SCSI Architecture Model and command
> protocols supporting multiple commands with command queuing features and
> enabling a multi-thread programming paradigm. This differs from conventional
> flash-based memory cards and embedded flash solutions which process one
> command at a time, limiting random read/write access performance.
> In addition, a forthcoming complementary UFS Host Controller Interface (HCI)
> specification will allow system designers greater flexibility by simplifying
> the involvement of the host processor in the operation of the flash storage
> subsystem. The UFS HCI specification and the adoption of SCSI will provide
> a well-known software programming model and enable wider market adoption.
>
> This patchset contains PCIe based UFS host controller driver which complies
> to UFSHCI 1.0 and 1.1. The driver is based on Linux SCSI framework.
> The driver is tested with UFS Host controller(FPGA) and UFS device(FPGA).
>
> This patch set is successfully applied on kernel version 3.3-rc2.
>
> Santosh Yaraganavi (4):
>  [SCSI] ufshcd: UFS Host controller driver
>  [SCSI] ufshcd: UFS UTP Transfer requests handling
>  [SCSI] ufshcd: UFSHCI error handling
>  [SCSI] ufshcd: SCSI error handling
>
>  drivers/scsi/Kconfig      |    1 +
>  drivers/scsi/Makefile     |    1 +
>  drivers/scsi/ufs/Kconfig  |   49 ++
>  drivers/scsi/ufs/Makefile |    2 +
>  drivers/scsi/ufs/ufs.h    |  203 +
>  drivers/scsi/ufs/ufshcd.c | 1954 
> +
>  drivers/scsi/ufs/ufshci.h |  360 +
>  7 files changed, 2570 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/scsi/ufs/Kconfig
>  create mode 100644 drivers/scsi/ufs/Makefile
>  create mode 100644 drivers/scsi/ufs/ufs.h
>  create mode 100644 drivers/scsi/ufs/ufshcd.c
>  create mode 100644 drivers/scsi/ufs/ufshci.h
>
> --
> 1.7.5.4
Hi.
I have been waiting for ufs contribution.
Unfortunately I don't have real target supported ufs(maybe only you
have it). I can not debug and run this code, So just review only code
with specification.
>
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Re: [PATCH] mmc: core: Fix PowerOff Notify suspend/resume

2012-02-04 Thread Chris Ball

Hi,

On Tue, Jan 31 2012, Girish K S wrote:
> Modified the mmc_poweroff to resume before sending the
> poweroff notification command. In sleep mode only AWAKE
> and RESET commands are allowed, so before sending the
> poweroff notification command resume from sleep mode and
> then send the notification command.
>
> POwerOff Notify is tested on a Synopsis Designware Host
> Controller(eMMC 4.5). The suspend to RAM and resume works fine.
>
> This patch is successfully applied on the Chris's mmc-next
> branch
>
> cc: Chris Ball 
> Signed-off-by: Girish K S 
> Tested-by: Girish K S 

Thanks, pushed to mmc-next for 3.3 with Saugata's Reviewed-by.

- Chris.
-- 
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One Laptop Per Child
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Re: [PATCH] mmc: core: Fix Low speed mmc card detection failure

2012-02-04 Thread Chris Ball

Hi,

On Wed, Jan 18 2012, Girish K S wrote:
> This patch fixes the failure of low speed mmc card detection
>
> Signed-off-by: Girish K S 
> ---
>  drivers/mmc/core/mmc.c |5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index dc03291..2bc586b 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1020,7 +1020,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>   err = mmc_select_hs200(card);
>   else if (host->caps & MMC_CAP_MMC_HIGHSPEED)
>   err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> -  EXT_CSD_HS_TIMING, 1, 0);
> +  EXT_CSD_HS_TIMING, 1,
> +  card->ext_csd.generic_cmd6_time);
>  
>   if (err && err != -EBADMSG)
>   goto free_card;
> @@ -1130,7 +1131,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>* Activate wide bus and DDR (if supported).
>*/
>   if (!mmc_card_hs200(card) &&
> - (card->csd.mmca_vsn >= CSD_SPEC_VER_3) &&
> + (card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
>   (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) {
>   static unsigned ext_csd_bits[][2] = {
>   { EXT_CSD_BUS_WIDTH_8, EXT_CSD_DDR_BUS_WIDTH_8 },

Thanks, pushed to mmc-next for 3.3.

- Chris.
-- 
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One Laptop Per Child
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Re: [PATCH 1/2] ARM: EXYNOS: Add files about definition of C2C

2012-02-04 Thread Russell King - ARM Linux

On Sat, Feb 04, 2012 at 05:13:00PM +0900, Kisang Lee wrote:
> Cc: Arnd Bergmann  arndb.de>
> Cc: Greg Kroah-Hartman  kroah.com>
> 
> Following files are added for C2C driver
> c2c.h : Definition of C2C platform data and mode
> regs-c2c.h : Definition of C2C registers
> 
> Signed-off-by: Kisang Lee 
> ---
>  arch/arm/mach-exynos/include/mach/c2c.h  |   65 +++
>  arch/arm/mach-exynos/include/mach/regs-c2c.h |   71 
> ++

Does anything other than these two files (in your second patch):

 drivers/misc/c2c/samsung-c2c.c |  500 
 drivers/misc/c2c/samsung-c2c.h |  300 

use the regs-c2c.h file?  If not, it should be placed next to the
drivers itself, and not in some random include directory far
away from the drivers.
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Re: [PATCH 2/2] misc: c2c: Add C2C(Chip to Chip) device driver for EXYNOS

2012-02-04 Thread Russell King - ARM Linux

On Sat, Feb 04, 2012 at 05:15:03PM +0900, Kisang Lee wrote:
> Cc: Arnd Bergmann  arndb.de>
> Cc: Greg Kroah-Hartman  kroah.com>
> 
> Signed-off-by: Kisang Lee 

What follows is a quick review of this driver.  I think there's quite
a number of issues which need to be fixed before this driver is ready,
some of them are rather serious.  Please take a look and try to address
as many of these comments as possible.

Thanks.

> ---
>  drivers/misc/Kconfig   |1 +
>  drivers/misc/Makefile  |1 +
>  drivers/misc/c2c/Kconfig   |   10 +
>  drivers/misc/c2c/Makefile  |5 +
>  drivers/misc/c2c/samsung-c2c.c |  500 
> 
>  drivers/misc/c2c/samsung-c2c.h |  300 
>  6 files changed, 817 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/misc/c2c/Kconfig
>  create mode 100644 drivers/misc/c2c/Makefile
>  create mode 100644 drivers/misc/c2c/samsung-c2c.c
>  create mode 100644 drivers/misc/c2c/samsung-c2c.h
> 
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 6a1a092..2ec3f48 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -516,5 +516,6 @@ source "drivers/misc/ti-st/Kconfig"
>  source "drivers/misc/lis3lv02d/Kconfig"
>  source "drivers/misc/carma/Kconfig"
>  source "drivers/misc/altera-stapl/Kconfig"
> +source "drivers/misc/c2c/Kconfig"
>  
>  endif # MISC_DEVICES
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 3e1d801..bd96ed7 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -49,3 +49,4 @@ obj-y   += carma/
>  obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
>  obj-$(CONFIG_ALTERA_STAPL)   +=altera-stapl/
>  obj-$(CONFIG_MAX8997_MUIC)   += max8997-muic.o
> +obj-$(CONFIG_SAMSUNG_C2C)+= c2c/
> diff --git a/drivers/misc/c2c/Kconfig b/drivers/misc/c2c/Kconfig
> new file mode 100644
> index 000..cd13078
> --- /dev/null
> +++ b/drivers/misc/c2c/Kconfig
> @@ -0,0 +1,10 @@
> +#
> +# C2C(Chip to Chip) Device
> +#
> +
> +config SAMSUNG_C2C
> + tristate "C2C Support"
> + depends on SOC_EXYNOS4212 || SOC_EXYNOS5250
> + default n
> + help
> +   It is for supporting C2C driver.
> diff --git a/drivers/misc/c2c/Makefile b/drivers/misc/c2c/Makefile
> new file mode 100644
> index 000..1af7d3a
> --- /dev/null
> +++ b/drivers/misc/c2c/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for C2C(Chip to Chip) device
> +#
> +
> +obj-$(CONFIG_SAMSUNG_C2C)+= samsung-c2c.o
> diff --git a/drivers/misc/c2c/samsung-c2c.c b/drivers/misc/c2c/samsung-c2c.c
> new file mode 100644
> index 000..ee08ac6
> --- /dev/null
> +++ b/drivers/misc/c2c/samsung-c2c.c
> @@ -0,0 +1,500 @@
> +/*
> + * Samsung C2C driver
> + *
> + * Copyright (C) 2011 Samsung Electronics Co.Ltd
> + * Author: Kisang Lee 
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 

I can find nothing related to the input layer in this file - is this
header required?

> +#include 
> +#include 
> +#include 
> +#include 

I can find nothing which declares a misc_device in this file - is this
header required?

> +#include 
> +#include 
> +#include 
> +#include 

You appear to use nothing from this header, please remove it.  Drivers
should not depend on the type of platform they're running on.

> +
> +#include 
> +#include 
> +#include 

Is plat/cpu.h necessary?

> +
> +#include "samsung-c2c.h"
> +
> +void c2c_reset_ops(void)
> +{
> + u32 set_clk = 0;
> +
> + if (c2c_con.opp_mode == C2C_OPP100)
> + set_clk = c2c_con.clk_opp100;
> + else if (c2c_con.opp_mode == C2C_OPP50)
> + set_clk = c2c_con.clk_opp50;
> + else if (c2c_con.opp_mode == C2C_OPP25)
> + set_clk = c2c_con.clk_opp25;
> +
> + dev_info(c2c_con.c2c_dev, "c2c_reset_ops()\n");
> + clk_set_rate(c2c_con.c2c_sclk, (set_clk + 1) * MHZ);
> + c2c_set_func_clk(set_clk);
> +
> + /* C2C block reset */
> + c2c_set_reset(C2C_CLEAR);
> + c2c_set_reset(C2C_SET);
> +
> + c2c_set_clock_gating(C2C_CLEAR);
> + c2c_writel(c2c_con.retention_reg, EXYNOS_C2C_IRQ_EN_SET1);
> + c2c_writel(set_clk, EXYNOS_C2C_FCLK_FREQ);
> + c2c_writel(set_clk, EXYNOS_C2C_RX_MAX_FREQ);
> + c2c_set_clock_gating(C2C_SET);
> +}
> +
> +static ssize_t c2c_ctrl_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + int ret = 0;
> + ret = sprintf(buf, "C2C State");
> + ret += sprintf(&buf[ret], "SysReg : 0x%x\n",
> + readl(c2c_con.c2c_sysreg));
> + ret += sprintf(&buf[ret], "Port Config : 0x%x\n",
> + c2c_readl(EXYNOS_C2C_PORTCONFIG));
> + ret += sprintf(&buf[ret], "FCLK_FR

Re: [PATCH 1/2] ARM: EXYNOS: add support GPIO for EXYNOS5250

2012-02-04 Thread Sylwester Nawrocki

On 02/02/2012 07:22 PM, Grant Likely wrote:
>>>   /* the end of the EXYNOS4 specific gpios */
>>>   #define EXYNOS4_GPIO_END  (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
>>> -#define S3C_GPIO_END   EXYNOS4_GPIO_END
>>>
>>> -/* define the number of gpios we need to the one after the GPZ() range */
>>> -#define ARCH_NR_GPIOS  (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +   
>>> \
>>> -CONFIG_SAMSUNG_GPIO_EXTRA + 1)
>>> +/* EXYNOS5 serise */
>>> +/* GPIO bank sizes */
>>> +#define EXYNOS5_GPIO_A0_NR (8)
>>
>> nit: It's been always a mystery to me, what are the parentheses around the
>> numbers helpful for ? IMHO even if there is more things like this in
>> the file it might be better to skip extra parentheses here.
> 
> It protects against the preprocessor combining a macro with other code in
> unpredictable ways.  For example:
> 
> #define SIZE  10 + 20
> int i = SIZE * 5;
> 
> Without the parenthesis the result of i is 110, when the programmer would
> expect 150.

Right, I guess it's a fundamental requirement most people are aware about. 
Nevertheless my point were only single integers.

> For single integers like these, the parenthesis aren't actually necessary, but
> I given that for every other #define it is good practice, I don't object to
> seeing them on single integers also.

I respect that but I have a different opinion. :-) Those parentheses have 
always been bugging me, they decrease readability for virtually no benefit. 
They're more an aesthetic issue though so I wouldn't argue more about it. 
Just will try to get used, and I'll avoid them where possible. :-)

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Sylwester
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Re: [PATCH 1/2] ARM: EXYNOS: Add files about definition of C2C

2012-02-04 Thread Sylwester Nawrocki

Hi,

On 02/04/2012 09:13 AM, Kisang Lee wrote:
> Cc: Arnd Bergmann  arndb.de>
> Cc: Greg Kroah-Hartman  kroah.com>
> 
> Following files are added for C2C driver
> c2c.h : Definition of C2C platform data and mode
> regs-c2c.h : Definition of C2C registers
>
> Signed-off-by: Kisang Lee
> ---
>   arch/arm/mach-exynos/include/mach/c2c.h  |   65 +++
>   arch/arm/mach-exynos/include/mach/regs-c2c.h |   71 
> ++
>   2 files changed, 136 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/mach-exynos/include/mach/c2c.h
>   create mode 100644 arch/arm/mach-exynos/include/mach/regs-c2c.h
> 
...
> diff --git a/arch/arm/mach-exynos/include/mach/regs-c2c.h 
> b/arch/arm/mach-exynos/include/mach/regs-c2c.h
> new file mode 100644
> index 000..0c3d005
> --- /dev/null
> +++ b/arch/arm/mach-exynos/include/mach/regs-c2c.h
> @@ -0,0 +1,71 @@
> +/* linux/arch/arm/mach-exynos/include/mach/regs-c2c.h
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.

2012 ?

> + * http://www.samsung.com/
> + *
> + * Register definition file for Samsung C2C
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#ifndef __ASM_ARM_REGS_S5P_C2C_H
> +#define __ASM_ARM_REGS_S5P_C2C_H
> +
> +/***/
> +/* C2C Registers part*/
> +/***/
> +#define EXYNOS_C2C_REVISION  0x0
> +#define EXYNOS_C2C_SYSCONFIG 0x4
> +#define EXYNOS_C2C_SYSSTATUS 0x8
> +#define EXYNOS_C2C_PORTCONFIG0xc
> +#define EXYNOS_C2C_MIRRORMODE0x10
> +#define EXYNOS_C2C_IRQ_RAW_STAT0 0x14
> +#define EXYNOS_C2C_IRQ_RAW_STAT1 0x18
> +#define EXYNOS_C2C_IRQ_EN_STAT0  0x1c
> +#define EXYNOS_C2C_IRQ_EN_STAT1  0x20
> +#define EXYNOS_C2C_IRQ_EN_SET0   0x24
> +#define EXYNOS_C2C_IRQ_EN_SET1   0x28
> +#define EXYNOS_C2C_IRQ_EN_CLEAR0 0x2c
> +#define EXYNOS_C2C_IRQ_EN_CLEAR1 0x30
> +#define EXYNOS_C2C_IRQ_EOI   0x34
> +
> +#define EXYNOS_C2C_FCLK_FREQ 0x40
> +#define EXYNOS_C2C_RX_MAX_FREQ   0x44
> +#define EXYNOS_C2C_TX_MAX_FREQ   0x48
> +#define EXYNOS_C2C_RX_MAX_FREQ_ACK   0x4c
> +#define EXYNOS_C2C_WAKE_REQ  0x50
> +#define EXYNOS_C2C_WAKE_ACK  0x54
> +#define EXYNOS_C2C_STANDBY   0x60
> +#define EXYNOS_C2C_STANDBY_IN0x64
> +#define EXYNOS_C2C_WAIT  0x68
> +#define EXYNOS_C2C_GENI_CONTROL  0x70
> +#define EXYNOS_C2C_GENI_MASK 0x74
> +#define EXYNOS_C2C_GENO_STATUS   0x80
> +
> +#define EXYNOS_C2C_GENO_INT  0x84
> +#define EXYNOS_C2C_GENO_LEVEL0x88
> +
> +/***/
> +/* C2C Bit definition part   */
> +/***/
> +/* SYSREG Bit definition */
> +#define C2C_SYSREG_CG(31) /* C2C Clock Gating [31] */
> +#define C2C_SYSREG_MO(30) /* Master On [30] */
> +#define C2C_SYSREG_FCLK  (20) /* Default Functional Clock Freq 
> [29:20] */
> +#define C2C_SYSREG_TXW   (18) /* Default Tx Width [19:18] */
> +#define C2C_SYSREG_RXW   (16) /* Default Rx Width [17:16] */
> +#define C2C_SYSREG_RST   (15) /* Reset [15] */
> +#define C2C_SYSREG_MD(14) /* Master On [14] */
> +#define C2C_SYSREG_RTRST (13) /* Reset retention registers [13] */
> +#define C2C_SYSREG_BASE_ADDR (3)  /* DRAM Base Address [12:3] */
> +#define C2C_SYSREG_DRAM_SIZE (0)  /* DRAM Size [2:0] */
> +
> +#define C2C_GENIO_LATENCY_INT(26)
> +#define C2C_GENIO_OPP_INT(27)
> +#define C2C_GENIO_OPP_MODE0  (28)
> +#define C2C_GENIO_OPP_MODE1  (29)
> +#define C2C_GENIO_LATENCY0   (30)
> +#define C2C_GENIO_LATENCY1   (31)

Could we have the parentheses around numbers removed ? They don't seem
to be useful for anything.

> +#endif /* __ASM_ARM_REGS_S5P_C2C_H */

--

Thanks,
Sylwester
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Re: [PATCH 2/2] misc: c2c: Add C2C(Chip to Chip) device driver for EXYNOS

2012-02-04 Thread Sylwester Nawrocki

Hi,

On 02/04/2012 09:15 AM, Kisang Lee wrote:
> Cc: Arnd Bergmann  arndb.de>
> Cc: Greg Kroah-Hartman  kroah.com>

Commit description aren't expected to be empty, especially when
you're adding a new driver. There is little clue what the driver
is needed for. Could you please be a little bit more verbose 
here ?

> Signed-off-by: Kisang Lee
> ---
>   drivers/misc/Kconfig   |1 +
>   drivers/misc/Makefile  |1 +
>   drivers/misc/c2c/Kconfig   |   10 +
>   drivers/misc/c2c/Makefile  |5 +
>   drivers/misc/c2c/samsung-c2c.c |  500 
> 
>   drivers/misc/c2c/samsung-c2c.h |  300 
>   6 files changed, 817 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/misc/c2c/Kconfig
>   create mode 100644 drivers/misc/c2c/Makefile
>   create mode 100644 drivers/misc/c2c/samsung-c2c.c
>   create mode 100644 drivers/misc/c2c/samsung-c2c.h
> 
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 6a1a092..2ec3f48 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -516,5 +516,6 @@ source "drivers/misc/ti-st/Kconfig"
>   source "drivers/misc/lis3lv02d/Kconfig"
>   source "drivers/misc/carma/Kconfig"
>   source "drivers/misc/altera-stapl/Kconfig"
> +source "drivers/misc/c2c/Kconfig"
> 
>   endif # MISC_DEVICES
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 3e1d801..bd96ed7 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -49,3 +49,4 @@ obj-y   += carma/
>   obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
>   obj-$(CONFIG_ALTERA_STAPL)  +=altera-stapl/
>   obj-$(CONFIG_MAX8997_MUIC)  += max8997-muic.o
> +obj-$(CONFIG_SAMSUNG_C2C)+= c2c/
> diff --git a/drivers/misc/c2c/Kconfig b/drivers/misc/c2c/Kconfig
> new file mode 100644
> index 000..cd13078
> --- /dev/null
> +++ b/drivers/misc/c2c/Kconfig
> @@ -0,0 +1,10 @@
> +#
> +# C2C(Chip to Chip) Device
> +#
> +
> +config SAMSUNG_C2C
> + tristate "C2C Support"
> + depends on SOC_EXYNOS4212 || SOC_EXYNOS5250
> + default n

The default is 'n' so you can drop this line.

> + help
> +   It is for supporting C2C driver.
> diff --git a/drivers/misc/c2c/Makefile b/drivers/misc/c2c/Makefile
> new file mode 100644
> index 000..1af7d3a
> --- /dev/null
> +++ b/drivers/misc/c2c/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for C2C(Chip to Chip) device
^^^
White-space after C2C ?
> +#
> +
> +obj-$(CONFIG_SAMSUNG_C2C)+= samsung-c2c.o
> diff --git a/drivers/misc/c2c/samsung-c2c.c b/drivers/misc/c2c/samsung-c2c.c
> new file mode 100644
> index 000..ee08ac6
> --- /dev/null
> +++ b/drivers/misc/c2c/samsung-c2c.c
> @@ -0,0 +1,500 @@
> +/*
> + * Samsung C2C driver
> + *
> + * Copyright (C) 2011 Samsung Electronics Co.Ltd

2012 or 2011 - 2012 ?

I think the proper form is:

Copyright (C) 2012 Samsung Electronics Co., Ltd.

> + * Author: Kisang Lee
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +
> +#include "samsung-c2c.h"
> +
> +void c2c_reset_ops(void)
> +{
> + u32 set_clk = 0;
> +
> + if (c2c_con.opp_mode == C2C_OPP100)

Would it make sense to make an effort to get rid of the global c2c_con
variable ? I mean when there is more than one instance of the C2C device
in the system this driver won't work as is. However if there is always
only one hardware instance then there is no issue.
I would strongly recommend not relying on such a global variable though.

> + set_clk = c2c_con.clk_opp100;
> + else if (c2c_con.opp_mode == C2C_OPP50)
> + set_clk = c2c_con.clk_opp50;
> + else if (c2c_con.opp_mode == C2C_OPP25)
> + set_clk = c2c_con.clk_opp25;
> +
> + dev_info(c2c_con.c2c_dev, "c2c_reset_ops()\n");
> + clk_set_rate(c2c_con.c2c_sclk, (set_clk + 1) * MHZ);
> + c2c_set_func_clk(set_clk);
> +
> + /* C2C block reset */
> + c2c_set_reset(C2C_CLEAR);
> + c2c_set_reset(C2C_SET);
> +
> + c2c_set_clock_gating(C2C_CLEAR);
> + c2c_writel(c2c_con.retention_reg, EXYNOS_C2C_IRQ_EN_SET1);
> + c2c_writel(set_clk, EXYNOS_C2C_FCLK_FREQ);
> + c2c_writel(set_clk, EXYNOS_C2C_RX_MAX_FREQ);
> + c2c_set_clock_gating(C2C_SET);
> +}
> +
> +static ssize_t c2c_ctrl_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + int ret = 0;
> + ret = sprintf(buf, "C2C State");
> + ret += sprintf(&buf[ret], "SysReg : 0x%x\n",

nit: You could use "%#x" notation here and anywhere else for
hex numbers, that's one charac

Re: [PATCH 1/2] ARM: EXYNOS: Add files about definition of C2C

2012-02-04 Thread Kyungmin Park

On Sat, Feb 4, 2012 at 5:13 PM, Kisang Lee  wrote:
> Cc: Arnd Bergmann  arndb.de>
> Cc: Greg Kroah-Hartman  kroah.com>
>
> Following files are added for C2C driver
> c2c.h : Definition of C2C platform data and mode
> regs-c2c.h : Definition of C2C registers
>
> Signed-off-by: Kisang Lee 
> ---
Hi,
>  arch/arm/mach-exynos/include/mach/c2c.h      |   65 +++
One nit. some parts are c2c common and gpio and platform setup codes
are exynos specific.
>  arch/arm/mach-exynos/include/mach/regs-c2c.h |   71 
> ++
Are there any reason to put here? I think you can merge with 2/2
patch. I mean you can move it under drivers/misc/c2c.

Thank you,
Kyungmin Park
>  2 files changed, 136 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-exynos/include/mach/c2c.h
>  create mode 100644 arch/arm/mach-exynos/include/mach/regs-c2c.h
>
> diff --git a/arch/arm/mach-exynos/include/mach/c2c.h 
> b/arch/arm/mach-exynos/include/mach/c2c.h
> new file mode 100644
> index 000..c3d6131
> --- /dev/null
> +++ b/arch/arm/mach-exynos/include/mach/c2c.h
> @@ -0,0 +1,65 @@
> +/* linux/arch/arm/mach-exynos/include/mach/c2c.h
> + *
> + * Copyright 2011 Samsung Electronics Co., Ltd.
> + *             http://www.samsung.com/
> + *
> + * Platform header file for Samsung C2C Interface driver
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +#ifndef __ASM_PLAT_C2C_H
> +#define __ASM_PLAT_C2C_H __FILE__
> +
> +#define C2C_SHAREDMEM_BASE 0x6000
> +
> +enum c2c_opp_mode {
> +       C2C_OPP0 = 0,
> +       C2C_OPP25 = 1,
> +       C2C_OPP50 = 2,
> +       C2C_OPP100 = 3,
> +};
> +
> +enum c2c_buswidth {
> +       C2C_BUSWIDTH_8 = 0,
> +       C2C_BUSWIDTH_10 = 1,
> +       C2C_BUSWIDTH_16 = 2,
> +};
> +
> +enum c2c_shrdmem_size {
> +       C2C_MEMSIZE_4 = 0,
> +       C2C_MEMSIZE_8 = 1,
> +       C2C_MEMSIZE_16 = 2,
> +       C2C_MEMSIZE_32 = 3,
> +       C2C_MEMSIZE_64 = 4,
> +       C2C_MEMSIZE_128 = 5,
> +       C2C_MEMSIZE_256 = 6,
> +       C2C_MEMSIZE_512 = 7,
> +};
> +
> +struct exynos_c2c_platdata {
> +       void (*setup_gpio)(enum c2c_buswidth rx_width,
> +                       enum c2c_buswidth tx_width);
> +
> +       u32 shdmem_addr;
> +       enum c2c_shrdmem_size shdmem_size;
> +
> +       void __iomem *ap_sscm_addr;
> +       void __iomem *cp_sscm_addr;
> +
> +       enum c2c_buswidth rx_width;
> +       enum c2c_buswidth tx_width;
> +       u32 clk_opp100; /* clock of OPP100 mode */
> +       u32 clk_opp50;  /* clock of OPP50 mode */
> +       u32 clk_opp25;  /* clock of OPP25 */
> +       enum c2c_opp_mode default_opp_mode;
> +
> +       void __iomem *c2c_sysreg;       /* System Register address for C2C */
> +       char *c2c_clk;
> +};
> +
> +extern void exynos_c2c_set_platdata(struct exynos_c2c_platdata *pd);
> +extern void exynos_c2c_cfg_gpio(enum c2c_buswidth rx_width,
> +                               enum c2c_buswidth tx_width);
> +#endif /*__ASM_PLAT_C2C_H */
> diff --git a/arch/arm/mach-exynos/include/mach/regs-c2c.h 
> b/arch/arm/mach-exynos/include/mach/regs-c2c.h
> new file mode 100644
> index 000..0c3d005
> --- /dev/null
> +++ b/arch/arm/mach-exynos/include/mach/regs-c2c.h
> @@ -0,0 +1,71 @@
> +/* linux/arch/arm/mach-exynos/include/mach/regs-c2c.h
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + *
> + * Register definition file for Samsung C2C
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#ifndef __ASM_ARM_REGS_S5P_C2C_H
> +#define __ASM_ARM_REGS_S5P_C2C_H
> +
> +/***/
> +/* C2C Registers part                          */
> +/***/
> +#define EXYNOS_C2C_REVISION            0x0
> +#define EXYNOS_C2C_SYSCONFIG           0x4
> +#define EXYNOS_C2C_SYSSTATUS           0x8
> +#define EXYNOS_C2C_PORTCONFIG          0xc
> +#define EXYNOS_C2C_MIRRORMODE          0x10
> +#define EXYNOS_C2C_IRQ_RAW_STAT0       0x14
> +#define EXYNOS_C2C_IRQ_RAW_STAT1       0x18
> +#define EXYNOS_C2C_IRQ_EN_STAT0        0x1c
> +#define EXYNOS_C2C_IRQ_EN_STAT1        0x20
> +#define EXYNOS_C2C_IRQ_EN_SET0         0x24
> +#define EXYNOS_C2C_IRQ_EN_SET1         0x28
> +#define EXYNOS_C2C_IRQ_EN_CLEAR0       0x2c
> +#define EXYNOS_C2C_IRQ_EN_CLEAR1       0x30
> +#define EXYNOS_C2C_IRQ_EOI             0x34
> +
> +#define EXYNOS_C2C_FCLK_FREQ           0x40
> +#define EXYNOS_C2C_RX_MAX_FREQ         0x44
> +#define EXYNOS_C2C_TX_MAX_FREQ         0x48
> +#define EXYNOS_C2C_RX_MAX_FREQ_ACK     0x4c
> +#define EXYNOS_C2C_WAKE_REQ            0x50
> +#define EXYNOS_C2C_WAKE_ACK            0x54
> +#define EXYNOS

[PATCH 2/2] misc: c2c: Add C2C(Chip to Chip) device driver for EXYNOS

2012-02-04 Thread Kisang Lee

Cc: Arnd Bergmann  arndb.de>
Cc: Greg Kroah-Hartman  kroah.com>

Signed-off-by: Kisang Lee 
---
 drivers/misc/Kconfig   |1 +
 drivers/misc/Makefile  |1 +
 drivers/misc/c2c/Kconfig   |   10 +
 drivers/misc/c2c/Makefile  |5 +
 drivers/misc/c2c/samsung-c2c.c |  500 
 drivers/misc/c2c/samsung-c2c.h |  300 
 6 files changed, 817 insertions(+), 0 deletions(-)
 create mode 100644 drivers/misc/c2c/Kconfig
 create mode 100644 drivers/misc/c2c/Makefile
 create mode 100644 drivers/misc/c2c/samsung-c2c.c
 create mode 100644 drivers/misc/c2c/samsung-c2c.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 6a1a092..2ec3f48 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -516,5 +516,6 @@ source "drivers/misc/ti-st/Kconfig"
 source "drivers/misc/lis3lv02d/Kconfig"
 source "drivers/misc/carma/Kconfig"
 source "drivers/misc/altera-stapl/Kconfig"
+source "drivers/misc/c2c/Kconfig"
 
 endif # MISC_DEVICES
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3e1d801..bd96ed7 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,3 +49,4 @@ obj-y += carma/
 obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
 obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/
 obj-$(CONFIG_MAX8997_MUIC) += max8997-muic.o
+obj-$(CONFIG_SAMSUNG_C2C)  += c2c/
diff --git a/drivers/misc/c2c/Kconfig b/drivers/misc/c2c/Kconfig
new file mode 100644
index 000..cd13078
--- /dev/null
+++ b/drivers/misc/c2c/Kconfig
@@ -0,0 +1,10 @@
+#
+# C2C(Chip to Chip) Device
+#
+
+config SAMSUNG_C2C
+   tristate "C2C Support"
+   depends on SOC_EXYNOS4212 || SOC_EXYNOS5250
+   default n
+   help
+ It is for supporting C2C driver.
diff --git a/drivers/misc/c2c/Makefile b/drivers/misc/c2c/Makefile
new file mode 100644
index 000..1af7d3a
--- /dev/null
+++ b/drivers/misc/c2c/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for C2C(Chip to Chip) device
+#
+
+obj-$(CONFIG_SAMSUNG_C2C)  += samsung-c2c.o
diff --git a/drivers/misc/c2c/samsung-c2c.c b/drivers/misc/c2c/samsung-c2c.c
new file mode 100644
index 000..ee08ac6
--- /dev/null
+++ b/drivers/misc/c2c/samsung-c2c.c
@@ -0,0 +1,500 @@
+/*
+ * Samsung C2C driver
+ *
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Kisang Lee 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "samsung-c2c.h"
+
+void c2c_reset_ops(void)
+{
+   u32 set_clk = 0;
+
+   if (c2c_con.opp_mode == C2C_OPP100)
+   set_clk = c2c_con.clk_opp100;
+   else if (c2c_con.opp_mode == C2C_OPP50)
+   set_clk = c2c_con.clk_opp50;
+   else if (c2c_con.opp_mode == C2C_OPP25)
+   set_clk = c2c_con.clk_opp25;
+
+   dev_info(c2c_con.c2c_dev, "c2c_reset_ops()\n");
+   clk_set_rate(c2c_con.c2c_sclk, (set_clk + 1) * MHZ);
+   c2c_set_func_clk(set_clk);
+
+   /* C2C block reset */
+   c2c_set_reset(C2C_CLEAR);
+   c2c_set_reset(C2C_SET);
+
+   c2c_set_clock_gating(C2C_CLEAR);
+   c2c_writel(c2c_con.retention_reg, EXYNOS_C2C_IRQ_EN_SET1);
+   c2c_writel(set_clk, EXYNOS_C2C_FCLK_FREQ);
+   c2c_writel(set_clk, EXYNOS_C2C_RX_MAX_FREQ);
+   c2c_set_clock_gating(C2C_SET);
+}
+
+static ssize_t c2c_ctrl_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   int ret = 0;
+   ret = sprintf(buf, "C2C State");
+   ret += sprintf(&buf[ret], "SysReg : 0x%x\n",
+   readl(c2c_con.c2c_sysreg));
+   ret += sprintf(&buf[ret], "Port Config : 0x%x\n",
+   c2c_readl(EXYNOS_C2C_PORTCONFIG));
+   ret += sprintf(&buf[ret], "FCLK_FREQ : %d\n",
+   c2c_readl(EXYNOS_C2C_FCLK_FREQ));
+   ret += sprintf(&buf[ret], "RX_MAX_FREQ : %d\n",
+   c2c_readl(EXYNOS_C2C_RX_MAX_FREQ));
+   ret += sprintf(&buf[ret], "IRQ_EN_SET1 : 0x%x\n",
+   c2c_readl(EXYNOS_C2C_IRQ_EN_SET1));
+   ret += sprintf(&buf[ret], "Get C2C sclk rate : %ld\n",
+   clk_get_rate(c2c_con.c2c_sclk));
+   ret += sprintf(&buf[ret], "Get C2C aclk rate : %ld\n",
+   clk_get_rate(c2c_con.c2c_aclk));
+
+   return ret;
+}
+
+static ssize_t c2c_ctrl_store(struct device *dev, struct device_attribute 
*attr,
+   const char *buf, size_t count)
+{
+   int ops_num, opp_val, req_clk;
+   sscanf(buf, "%d", &ops_num);
+
+   switch (ops_num) {
+   case 1:
+   c2c_reset_ops();
+

[PATCH 1/2] ARM: EXYNOS: Add files about definition of C2C

2012-02-04 Thread Kisang Lee

Cc: Arnd Bergmann  arndb.de>
Cc: Greg Kroah-Hartman  kroah.com>

Following files are added for C2C driver
c2c.h : Definition of C2C platform data and mode
regs-c2c.h : Definition of C2C registers

Signed-off-by: Kisang Lee 
---
 arch/arm/mach-exynos/include/mach/c2c.h  |   65 +++
 arch/arm/mach-exynos/include/mach/regs-c2c.h |   71 ++
 2 files changed, 136 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/include/mach/c2c.h
 create mode 100644 arch/arm/mach-exynos/include/mach/regs-c2c.h

diff --git a/arch/arm/mach-exynos/include/mach/c2c.h 
b/arch/arm/mach-exynos/include/mach/c2c.h
new file mode 100644
index 000..c3d6131
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/c2c.h
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-exynos/include/mach/c2c.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Platform header file for Samsung C2C Interface driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_PLAT_C2C_H
+#define __ASM_PLAT_C2C_H __FILE__
+
+#define C2C_SHAREDMEM_BASE 0x6000
+
+enum c2c_opp_mode {
+   C2C_OPP0 = 0,
+   C2C_OPP25 = 1,
+   C2C_OPP50 = 2,
+   C2C_OPP100 = 3,
+};
+
+enum c2c_buswidth {
+   C2C_BUSWIDTH_8 = 0,
+   C2C_BUSWIDTH_10 = 1,
+   C2C_BUSWIDTH_16 = 2,
+};
+
+enum c2c_shrdmem_size {
+   C2C_MEMSIZE_4 = 0,
+   C2C_MEMSIZE_8 = 1,
+   C2C_MEMSIZE_16 = 2,
+   C2C_MEMSIZE_32 = 3,
+   C2C_MEMSIZE_64 = 4,
+   C2C_MEMSIZE_128 = 5,
+   C2C_MEMSIZE_256 = 6,
+   C2C_MEMSIZE_512 = 7,
+};
+
+struct exynos_c2c_platdata {
+   void (*setup_gpio)(enum c2c_buswidth rx_width,
+   enum c2c_buswidth tx_width);
+
+   u32 shdmem_addr;
+   enum c2c_shrdmem_size shdmem_size;
+
+   void __iomem *ap_sscm_addr;
+   void __iomem *cp_sscm_addr;
+
+   enum c2c_buswidth rx_width;
+   enum c2c_buswidth tx_width;
+   u32 clk_opp100; /* clock of OPP100 mode */
+   u32 clk_opp50;  /* clock of OPP50 mode */
+   u32 clk_opp25;  /* clock of OPP25 */
+   enum c2c_opp_mode default_opp_mode;
+
+   void __iomem *c2c_sysreg;   /* System Register address for C2C */
+   char *c2c_clk;
+};
+
+extern void exynos_c2c_set_platdata(struct exynos_c2c_platdata *pd);
+extern void exynos_c2c_cfg_gpio(enum c2c_buswidth rx_width,
+   enum c2c_buswidth tx_width);
+#endif /*__ASM_PLAT_C2C_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-c2c.h 
b/arch/arm/mach-exynos/include/mach/regs-c2c.h
new file mode 100644
index 000..0c3d005
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-c2c.h
@@ -0,0 +1,71 @@
+/* linux/arch/arm/mach-exynos/include/mach/regs-c2c.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Register definition file for Samsung C2C
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_REGS_S5P_C2C_H
+#define __ASM_ARM_REGS_S5P_C2C_H
+
+/***/
+/* C2C Registers part  */
+/***/
+#define EXYNOS_C2C_REVISION0x0
+#define EXYNOS_C2C_SYSCONFIG   0x4
+#define EXYNOS_C2C_SYSSTATUS   0x8
+#define EXYNOS_C2C_PORTCONFIG  0xc
+#define EXYNOS_C2C_MIRRORMODE  0x10
+#define EXYNOS_C2C_IRQ_RAW_STAT0   0x14
+#define EXYNOS_C2C_IRQ_RAW_STAT1   0x18
+#define EXYNOS_C2C_IRQ_EN_STAT00x1c
+#define EXYNOS_C2C_IRQ_EN_STAT10x20
+#define EXYNOS_C2C_IRQ_EN_SET0 0x24
+#define EXYNOS_C2C_IRQ_EN_SET1 0x28
+#define EXYNOS_C2C_IRQ_EN_CLEAR0   0x2c
+#define EXYNOS_C2C_IRQ_EN_CLEAR1   0x30
+#define EXYNOS_C2C_IRQ_EOI 0x34
+
+#define EXYNOS_C2C_FCLK_FREQ   0x40
+#define EXYNOS_C2C_RX_MAX_FREQ 0x44
+#define EXYNOS_C2C_TX_MAX_FREQ 0x48
+#define EXYNOS_C2C_RX_MAX_FREQ_ACK 0x4c
+#define EXYNOS_C2C_WAKE_REQ0x50
+#define EXYNOS_C2C_WAKE_ACK0x54
+#define EXYNOS_C2C_STANDBY 0x60
+#define EXYNOS_C2C_STANDBY_IN  0x64
+#define EXYNOS_C2C_WAIT0x68
+#define EXYNOS_C2C_GENI_CONTROL0x70
+#define EXYNOS_C2C_GENI_MASK   0x74
+#define EXYNOS_C2C_GENO_STATUS 0x80
+
+#define EXYNOS_C2C_GENO_INT0x84
+#define EXYNOS_C2C_GENO_LEVEL  0x88
+
+/***/
+/* C2C Bit definition part */
+/***/
+/* SYSR

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