[PATCH] ARM: EXYNOS: Add I2S SFR base addresses
The base address of I2S 0 controller is similar in exynos4 and exynos5
platforms. So this patch defines a common macro for the I2S controller
0 base address in both the platforms and use the same macro.
This patch also defines the I2S controller 1,2 base addresses in exynos5
and correct the I2S controller 1 base address in exynos4
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/dev-audio.c|2 +-
arch/arm/mach-exynos/include/mach/map.h |6 --
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index b33a5b6..5dbc9a2 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -62,7 +62,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
};
static struct resource exynos4_i2s0_resource[] = {
- [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
+ [0] = DEFINE_RES_MEM(EXYNOS_PA_I2S0, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..5cf7d91 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -39,9 +39,11 @@
#define EXYNOS4_PA_G2D 0x1280
-#define EXYNOS4_PA_I2S00x0383
-#define EXYNOS4_PA_I2S10xE310
+#define EXYNOS_PA_I2S0 0x0383
+#define EXYNOS4_PA_I2S10xE210
#define EXYNOS4_PA_I2S20xE2A0
+#define EXYNOS5_PA_I2S10x12D6
+#define EXYNOS5_PA_I2S20x12D7
#define EXYNOS4_PA_PCM00x0384
#define EXYNOS4_PA_PCM10x1398
--
1.7.4.4
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[PATCH] ARM: EXYNOS: Add static mapping for EXYNOS Audio Subsystem
The CMU of EXYNOS can't control Audio Subsystem's clocks because
AUDSS SFRs aren't located in CMU. But AUDSS is a kind of CMU for
Audio Subsystem and need to use clock framework. This mapping
address will be used for AUDSS clock control.
Signed-off-by: sangsu4u.park sangsu4u.p...@samsung.com
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/common.c|5 +
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/plat-samsung/include/plat/map-s5p.h |2 ++
3 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..4070c79 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -109,6 +109,11 @@ static struct map_desc exynos_iodesc[] __initdata = {
.pfn= __phys_to_pfn(EXYNOS_PA_CHIPID),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual= (unsigned long)S5P_VA_AUDSS,
+ .pfn= __phys_to_pfn(EXYNOS_PA_AUDSS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 5cf7d91..9c044a0 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -39,6 +39,7 @@
#define EXYNOS4_PA_G2D 0x1280
+#define EXYNOS_PA_AUDSS0x0381
#define EXYNOS_PA_I2S0 0x0383
#define EXYNOS4_PA_I2S10xE210
#define EXYNOS4_PA_I2S20xE2A0
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h
b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bda..3558277 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -40,6 +40,8 @@
#define S5P_VA_GIC_CPU S3C_ADDR(0x0281)
#define S5P_VA_GIC_DISTS3C_ADDR(0x0282)
+#define S5P_VA_AUDSS S3C_ADDR(0x0291)
+
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x1))
#define VA_VIC0VA_VIC(0)
#define VA_VIC1VA_VIC(1)
--
1.7.4.4
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[PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
board specific. So this patch adds a function to set the required
audio codec clk frequency from machine file.
This patch also adds all the required clock instances for audio
subsystem and adds the clock alias names for i2sclk and busclk.
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: sangsu4u.park sangsu4u.p...@samsung.com
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 129
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/include/mach/regs-audss.h | 12 ++
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
4 files changed, 143 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..681450a 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -20,10 +20,13 @@
#include plat/pll.h
#include plat/s5p-clock.h
#include plat/clock-clksrc.h
+#include plat/devs.h
#include plat/pm.h
+#include plat/cpu.h
#include mach/map.h
#include mach/regs-clock.h
+#include mach/regs-audss.h
#include mach/sysmmu.h
#include common.h
@@ -106,6 +109,16 @@ static struct clk exynos5_clk_sclk_usbphy = {
.rate = 4800,
};
+struct clk exynos5_clk_audiocdclk0 = {
+ .id = -1,
+ .name = audiocdclk,
+};
+
+void exynos5_set_audiocdclk_rate(unsigned long rate)
+{
+ clk_default_setrate(exynos5_clk_audiocdclk0, rate);
+}
+
static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
@@ -171,6 +184,16 @@ static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int
enable)
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
}
+static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+static int exynos5_clk_audss_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS_CLKGATE_AUDSS, clk, enable);
+}
+
static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -635,6 +658,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 3),
}, {
.name = iis,
+ .devname= samsung-i2s.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 2),
+ }, {
+ .name = iis,
.devname= samsung-i2s.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 20),
@@ -645,6 +673,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 21),
}, {
.name = pcm,
+ .devname= samsung-pcm.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 4),
+ }, {
+ .name = pcm,
.devname= samsung-pcm.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 22),
@@ -870,6 +903,95 @@ static struct clk exynos5_init_clocks_on[] = {
}
};
+static struct clk *clkset_sclk_audio0_list[] = {
+ [0] = exynos5_clk_audiocdclk0,
+ [1] = clk_ext_xtal_mux,
+ [2] = exynos5_clk_sclk_hdmi27m,
+ [3] = exynos5_clk_sclk_dptxphy,
+ [4] = exynos5_clk_sclk_usbphy,
+ [5] = exynos5_clk_sclk_hdmiphy,
+ [6] = exynos5_clk_mout_mpll.clk,
+ [7] = exynos5_clk_mout_epll.clk,
+ [8] = exynos5_clk_sclk_vpll.clk,
+ [9] = exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio0 = {
+ .sources= clkset_sclk_audio0_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio0 = {
+ .clk= {
+ .name = audio-bus,
+ .enable = exynos5_clksrc_mask_maudio_ctrl,
+ .ctrlbit= (1 0),
+ },
+ .sources = exynos5_clkset_sclk_audio0,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_mout_audss_list[] = {
+ clk_ext_xtal_mux,
+ clk_fout_epll,
+};
+
+static struct clksrc_sources clkset_mout_audss = {
+ .sources= exynos5_clkset_mout_audss_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_audss_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_audss = {
+ .clk= {
+ .name = mout_audss,
+ },
+ .sources = clkset_mout_audss,
+ .reg_src = { .reg =
[PATCH 0/2] ASOC: SAMSUNG: Add dt support for i2s
This patch series adds device tree based discovery support for Samsung's i2s controller. This is tested on Exynos5250 with 8994 codec for playback and capturing modes on 3.5.0-rc7 Padmavathi Venna (2): ASOC: SAMSUNG: Add DT support for i2s ASOC: SAMSUNG: Add dma_prop variable in s3c_dma_params .../devicetree/bindings/sound/samsung-i2s.txt | 62 ++ sound/soc/samsung/dma.c|1 + sound/soc/samsung/dma.h|1 + sound/soc/samsung/i2s.c| 228 +++- 4 files changed, 243 insertions(+), 49 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/samsung-i2s.txt -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ASOC: SAMSUNG: Add DT support for i2s
Add support for device based discovery.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 62 ++
sound/soc/samsung/i2s.c| 228 +++-
2 files changed, 241 insertions(+), 49 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/samsung-i2s.txt
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
new file mode 100644
index 000..74739a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -0,0 +1,62 @@
+* Samsung I2S controller
+
+Required SoC Specific properties:
+
+- compatible : samsung,samsung-i2s
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- tx-dma-channel-secondary: The dma channel specifier for secondary tx
+ operations. The format of the dma specifier depends on the dma
+ controller.
+- tx-dma-channel: The dma channel specifier for tx operations. The format of
+ the dma specifier depends on the dma controller.
+- rx-dma-channel: The dma channel specifier for rx operations. The format of
+ the dma specifier depends on the dma controller.
+- supports-6ch: If the Primary DAI has 5.1 Channel support, this flag is
+ enabled.
+- supports-rstclr: This flag should be set if I2S software reset bit control is
+ required. When this flag is set I2S software reset bit will be enabled or
+ disabled based on need.
+- supports-secdai: If the I2S block has a secondary sound source support, then
+ this flag is enabled.
+
+Required Board Specific Properties:
+
+- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
+ interface lines. The format of the gpio specifier depends on the gpio
+ controller.
+- idma-addr: Internal DMA register base address of the audio sub system(used in
+ secondary sound source).
+
+Aliases:
+
+- All the I2S controller nodes should be represented in the aliases node using
+ the following format 'i2s{n}' where n is a unique number for the alias.
+
+Example:
+
+- SoC Specific Portion:
+
+i2s@0383 {
+ compatible = samsung,samsung-i2s;
+ reg = 0x0383 0x100;
+ tx-dma-channel-secondary = pdma0 8;
+ tx-dma-channel = pdma0 10;
+ rx-dma-channel = pdma0 9;
+ supports-6ch;
+ supports-rstclr;
+ supports-secdai;
+};
+
+- Board Specific Portion:
+
+i2s_0: i2s@0383 {
+ gpios = gpz 0 2 0 0,
+ gpz 1 2 0 0,
+ gpz 2 2 0 0,
+ gpz 3 2 0 0,
+ gpz 4 2 0 0,
+ gpz 5 2 0 0,
+ gpz 6 2 0 0;
+ idma-addr = 0x0300;
+};
diff --git a/sound/soc/samsung/i2s.c b/sound/soc/samsung/i2s.c
index 6ac7b82..ccaed7d 100644
--- a/sound/soc/samsung/i2s.c
+++ b/sound/soc/samsung/i2s.c
@@ -15,12 +15,15 @@
#include linux/clk.h
#include linux/io.h
#include linux/module.h
+#include linux/of.h
+#include linux/of_gpio.h
#include linux/pm_runtime.h
#include sound/soc.h
#include sound/pcm_params.h
#include plat/audio.h
+#include plat/dma-pl330.h
#include dma.h
#include idma.h
@@ -49,8 +52,6 @@ struct i2s_dai {
struct clk *clk;
/* Clock for generating I2S signals */
struct clk *op_clk;
- /* Array of clock names for op_clk */
- const char **src_clk;
/* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
struct i2s_dai *pri_dai;
/* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
@@ -68,6 +69,8 @@ struct i2s_dai {
u32 suspend_i2smod;
u32 suspend_i2scon;
u32 suspend_i2spsr;
+ unsigned long gpios[7]; /* i2s gpio line numbers */
+ int dev_id; /* i2s dev id */
};
/* Lock for cross i/f checks */
@@ -385,6 +388,7 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = i2s-pri_dai ? : i2s-sec_dai;
u32 mod = readl(i2s-addr + I2SMOD);
+ char clk_name[16];
switch (clk_id) {
case SAMSUNG_I2S_CDCLK:
@@ -432,8 +436,9 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
}
}
+ sprintf(clk_name, i2s_opclk%d, clk_id);
i2s-op_clk = clk_get(i2s-pdev-dev,
- i2s-src_clk[clk_id]);
+ clk_name);
clk_enable(i2s-op_clk);
i2s-rclk_srcrate = clk_get_rate(i2s-op_clk);
@@ -980,8 +985,9 @@ struct i2s_dai *i2s_alloc_dai(struct platform_device *pdev,
bool sec)
i2s-i2s_dai_drv.capture.formats = SAMSUNG_I2S_FMTS;
} else {/* Create a new platform_device for Secondary */
i2s-pdev = platform_device_register_resndata(NULL,
- pdev-name,
[PATCH 2/2] ASOC: SAMSUNG: Add dma_prop variable in s3c_dma_params
In DT based implementation, the DMA channel number need to be parsed as
a property from device tree. So add dma_prop variable in s3c_dma_params
to get the i2s DMA channel number.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
sound/soc/samsung/dma.c |1 +
sound/soc/samsung/dma.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index f3ebc38..28a7c37 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -170,6 +170,7 @@ static int dma_hw_params(struct snd_pcm_substream
*substream,
req.cap = (samsung_dma_has_circular() ?
DMA_CYCLIC : DMA_SLAVE);
req.client = prtd-params-client;
+ req.dt_dmach_prop = prtd-params-dma_prop;
config.direction =
(substream-stream == SNDRV_PCM_STREAM_PLAYBACK
? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index 7d1ead7..2e60415 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -19,6 +19,7 @@ struct s3c_dma_params {
int dma_size; /* Size of the DMA transfer */
unsigned ch;
struct samsung_dma_ops *ops;
+ struct property *dma_prop;
};
#endif
--
1.7.4.4
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[PATCH 0/2] ARM: Exynos: Enable I2S platform support for Exynos5
This patch set enables device tree based platform support for the three I2S controllers on Samsung's Exynos5 SoC's. Padmavathi Venna (2): ARM: dts: Add nodes for i2s controllers for Samsung Exynos5 platforms ARM: EXYNOS: Enable platform support for I2S controllers arch/arm/boot/dts/exynos5250-smdk5250.dts | 15 +++ arch/arm/boot/dts/exynos5250.dtsi | 28 arch/arm/mach-exynos/mach-exynos5-dt.c|6 ++ 3 files changed, 49 insertions(+), 0 deletions(-) -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: dts: Add nodes for i2s controllers for Samsung Exynos5 platforms
Add device nodes for the three instances of i2s controllers in Exynos5
platforms. Enable instance i2s 0 for exynos5250 board and disable all
other i2s instances.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 15 +++
arch/arm/boot/dts/exynos5250.dtsi | 28
2 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 8a5e348..615d1c4 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -109,4 +109,19 @@
spi_2: spi@12d4 {
status = disabled;
};
+
+ i2s_0: i2s@0383 {
+ gpios = gpz 0 2 0 0, gpz 1 2 0 0, gpz 2 2 0 0,
+ gpz 3 2 0 0, gpz 4 2 0 0, gpz 5 2 0 0,
+ gpz 6 2 0 0;
+ idma-addr = 0x0300;
+ };
+
+ i2s_1: i2s@12D6 {
+ status = disabled;
+ };
+
+ i2s_2: i2s@12D7 {
+ status = disabled;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index a3a2eb2..6ff78ba 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -27,6 +27,9 @@
spi0 = spi_0;
spi1 = spi_1;
spi2 = spi_2;
+ i2s0 = i2s_0;
+ i2s1 = i2s_1;
+ i2s2 = i2s_2;
};
gic:interrupt-controller@10481000 {
@@ -182,6 +185,31 @@
#size-cells = 0;
};
+ i2s_0: i2s@0383 {
+ compatible = samsung,samsung-i2s;
+ reg = 0x0383 0x100;
+ tx-dma-channel-secondary = pdma0 8;
+ tx-dma-channel = pdma0 10;
+ rx-dma-channel = pdma0 9;
+ supports-6ch;
+ supports-rstclr;
+ supports-secdai;
+ };
+
+ i2s_1: i2s@12D6 {
+ compatible = samsung,samsung-i2s;
+ reg = 0x12D6 0x100;
+ tx-dma-channel = pdma1 12;
+ rx-dma-channel = pdma1 11;
+ };
+
+ i2s_2: i2s@12D7 {
+ compatible = samsung,samsung-i2s;
+ reg = 0x12D7 0x100;
+ tx-dma-channel = pdma0 12;
+ rx-dma-channel = pdma0 11;
+ };
+
amba {
#address-cells = 1;
#size-cells = 1;
--
1.7.4.4
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[PATCH 2/2] ARM: EXYNOS: Enable platform support for I2S controllers
Add AUXDATA entries for i2s controller driver so as to set the device
name for clock lookups
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/mach-exynos5-dt.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index c334eea..cf5a0f5 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -56,6 +56,12 @@ static const struct of_dev_auxdata
exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA(arm,pl330, EXYNOS5_PA_PDMA0, dma-pl330.0, NULL),
OF_DEV_AUXDATA(arm,pl330, EXYNOS5_PA_PDMA1, dma-pl330.1, NULL),
OF_DEV_AUXDATA(arm,pl330, EXYNOS5_PA_MDMA1, dma-pl330.2, NULL),
+ OF_DEV_AUXDATA(samsung,samsung-i2s, EXYNOS_PA_I2S0,
+ samsung-i2s.0, NULL),
+ OF_DEV_AUXDATA(samsung,samsung-i2s, EXYNOS5_PA_I2S1,
+ samsung-i2s.1, NULL),
+ OF_DEV_AUXDATA(samsung,samsung-i2s, EXYNOS5_PA_I2S2,
+ samsung-i2s.2, NULL),
{},
};
--
1.7.4.4
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[PATCH] ASoC: Samsung: Update Kconfig for Exynos5250 and Exynos4412
Update Kconfig file to support the Exynos5250 and Exynos4412 Signed-off-by: Sangsu Park sangsu4u.p...@samsung.com Signed-off-by: Sangbeom Kim sbki...@samsung.com Signed-off-by: Padmavathi Venna padm...@samsung.com --- sound/soc/samsung/Kconfig |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig index fe3995c..d54e400 100644 --- a/sound/soc/samsung/Kconfig +++ b/sound/soc/samsung/Kconfig @@ -1,6 +1,6 @@ config SND_SOC_SAMSUNG tristate ASoC support for Samsung - depends on ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_EXYNOS4 + depends on PLAT_SAMSUNG select S3C64XX_DMA if ARCH_S3C64XX select S3C2410_DMA if ARCH_S3C24XX help @@ -63,7 +63,7 @@ config SND_SOC_SAMSUNG_SMDK_WM8580 config SND_SOC_SAMSUNG_SMDK_WM8994 tristate SoC I2S Audio support for WM8994 on SMDK - depends on SND_SOC_SAMSUNG (MACH_SMDKV310 || MACH_SMDKC210 || MACH_SMDK4212) + depends on SND_SOC_SAMSUNG (MACH_SMDKV310 || MACH_SMDKC210 || MACH_SMDK4212 || MACH_SMDK4412 || SOC_EXYNOS5250) depends on I2C=y GENERIC_HARDIRQS select MFD_WM8994 select SND_SOC_WM8994 @@ -162,7 +162,7 @@ config SND_SOC_GONI_AQUILA_WM8994 config SND_SOC_SAMSUNG_SMDK_SPDIF tristate SoC S/PDIF Audio support for SMDK - depends on SND_SOC_SAMSUNG (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310 || MACH_SMDK4212) + depends on SND_SOC_SAMSUNG (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210 || MACH_SMDKV310 || MACH_SMDK4212 || MACH_SMDK4412 || SOC_EXYNOS5250) select SND_SAMSUNG_SPDIF help Say Y if you want to add support for SoC S/PDIF audio on the SMDK. @@ -177,7 +177,7 @@ config SND_SOC_SMDK_WM8580_PCM config SND_SOC_SMDK_WM8994_PCM tristate SoC PCM Audio support for WM8994 on SMDK - depends on SND_SOC_SAMSUNG (MACH_SMDKC210 || MACH_SMDKV310 || MACH_SMDK4212) + depends on SND_SOC_SAMSUNG (MACH_SMDKC210 || MACH_SMDKV310 || MACH_SMDK4212 || MACH_SMDK4412 || SOC_EXYNOS5250) depends on I2C=y GENERIC_HARDIRQS select MFD_WM8994 select SND_SOC_WM8994 -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] mmc: dw_mmc: add busmode selection support
On 24 July 2012 19:14, Jae hoon Chung jh80.ch...@gmail.com wrote:
2012/7/24 Girish K S girish.shivananja...@linaro.org:
On 24 July 2012 18:37, Jae hoon Chung jh80.ch...@gmail.com wrote:
Hi Girish,
Right, it be mentioned about the open-drain mode in synopsys spec.
But if didn't work on other board, there is some problem.
We can consider the location of set_busmode() .
may i know the board on which you are testing. i will try to use the
same and simulate the problem
Exynos4 board and eMMC4.5 card, Synopsys IP version is 2.40a
Just now i tested it on exynos4 board/ eMMC 4.4 card Synopsis 2.40a
host controller. Everything works fine. this patch doesnt have any
side effect on the exynos4 board
please check from ur end. might be some other issue.
Best Regards,
Jaehoon Chung
2012/7/24 Girish K S girish.shivananja...@linaro.org:
On 24 July 2012 17:06, Girish K S girish.shivananja...@linaro.org wrote:
On 24 July 2012 16:39, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi Girish,
Well..just tested on my board.
this patch didn't work.(eMMC card didn't initialize)
meaning of ios-bus_mode and synosys's bus_mode is same?
Yes it is same. synopsys spec says this is specific to MMC
initialization. when the card core sets this mode during
initialization. the host has to set this bit
How did you test this patch?
Tested it on exynos5 board using dt patches of thomas (with some
modification to his patch)
Best Regards,
Jaehoon Chung
On 07/23/2012 08:16 PM, Girish K S wrote:
Synopsis Designware host controller has suppport for open
drain mode selection. During the mmc card initialization the
host controller can select the open-drain bit to allow the device
initialization in the open-drain mode. Once the device enters
the standby mode this bit can be reset to enter push-pull mode.
Signed-off-by: Girish K S girish.shivananja...@linaro.org
---
drivers/mmc/host/dw_mmc.c | 14 ++
drivers/mmc/host/dw_mmc.h |1 +
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 72dc3cd..da11e5a 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -773,6 +773,18 @@ static void dw_mci_request(struct mmc_host *mmc,
struct mmc_request *mrq)
spin_unlock_bh(host-lock);
}
+static void dw_mci_set_busmode(struct dw_mci_slot *slot)
+{
+ struct mmc_ios *ios = slot-mmc-ios;
+ u32 reg;
+
+ reg = mci_readl(slot-host, CTRL);
+ if (ios-bus_mode == MMC_BUSMODE_OPENDRAIN)
+ mci_writel(slot-host, CTRL, reg | SDMMC_CTRL_ENABLE_OD);
+ else
+ mci_writel(slot-host, CTRL, reg ~SDMMC_CTRL_ENABLE_OD);
+}
+
static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct dw_mci_slot *slot = mmc_priv(mmc);
@@ -818,6 +830,8 @@ static void dw_mci_set_ios(struct mmc_host *mmc,
struct mmc_ios *ios)
default:
break;
}
+
+ dw_mci_set_busmode(slot);
}
static int dw_mci_get_ro(struct mmc_host *mmc)
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 15c27e1..1a53fb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -67,6 +67,7 @@
/* Control register defines */
#define SDMMC_CTRL_USE_IDMAC BIT(25)
+#define SDMMC_CTRL_ENABLE_OD BIT(24)
#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
#define SDMMC_CTRL_SEND_CCSD BIT(9)
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[PATCH 0/2] Add support to enable ARM PMU for EXYNOS4/5
This patchset fixes irq numbers of ARM Performance Monitoring unit. We need to seperate arm-pmu(performance measurement unit) and exynos-pmu(power management unit). The exynos4 and 5 use 2 more cpu core which has its own pmu. We should define pmu irq numbers according to the number of cpus. The pmu irq of exynos4 and 5 uses combiner-irq type. To enable perf(performance counter), we need to implement a set_irq_affinity function about the combiner-irq. Chanho Park (2): ARM: EXYNOS: Fix ARM PMU irq numbers ARM: EXYNOS: Add set_irq_affinity function for combiner_irq arch/arm/mach-exynos/common.c| 30 +- arch/arm/mach-exynos/include/mach/irqs.h | 18 -- arch/arm/plat-samsung/devs.c |9 - 3 files changed, 49 insertions(+), 8 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ARM: EXYNOS: Fix ARM PMU irq numbers
This patch fixes irq numbers of ARM PMU(Perfromance Monitoring Unit).
We need to seperate arm-pmu(performance measurement unit) and exynos-pmu(power
management unit). I decide to change EXYNOS4_IRQ_PMU to EXYNOS4_IRQ_POWER_PMU
because there are no one use it.
A max cpu number of exynos4 is four in case of exynos44xx. So we should define 3
additional pmu irq numbers and enable it according to the number of cpus.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/include/mach/irqs.h | 18 --
arch/arm/plat-samsung/devs.c |9 -
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..329b07d 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMUIRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPSIRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSSIRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUSIRQ_SPI(113)
@@ -136,6 +136,11 @@
#define EXYNOS4_IRQ_TSIIRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMUCOMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMUEXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNCEXYNOS4_IRQ_FIMD0_VSYNC
@@ -453,6 +457,16 @@
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS5
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS1
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define IRQ_PMUEXYNOS4_IRQ_PMU
+#define IRQ_PMU1 EXYNOS4_IRQ_PMU_CPU1
+#define IRQ_PMU2 EXYNOS4_IRQ_PMU_CPU2
+#define IRQ_PMU3 EXYNOS4_IRQ_PMU_CPU3
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define IRQ_PMUEXYNOS5_IRQ_PMU
+#define IRQ_PMU1 EXYNOS5_IRQ_PMU_CPU1
+#endif
+
#define MAX_COMBINER_NR(EXYNOS4_MAX_COMBINER_NR
EXYNOS5_MAX_COMBINER_NR ? \
EXYNOS4_MAX_COMBINER_NR :
EXYNOS5_MAX_COMBINER_NR)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..91048a6 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1100,7 +1100,14 @@ struct platform_device s5p_device_onenand = {
#ifdef CONFIG_PLAT_S5P
static struct resource s5p_pmu_resource[] = {
- DEFINE_RES_IRQ(IRQ_PMU)
+ DEFINE_RES_IRQ(IRQ_PMU),
+#if (CONFIG_NR_CPUS 1)
+ DEFINE_RES_IRQ(IRQ_PMU1),
+#elif (CONFIG_NR_CPUS 2)
+ DEFINE_RES_IRQ(IRQ_PMU2),
+#elif (CONFIG_NR_CPUS 3)
+ DEFINE_RES_IRQ(IRQ_PMU3),
+#endif
};
static struct platform_device s5p_device_pmu = {
--
1.7.9.5
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[PATCH 2/2] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq
This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the irq of exynos's pmu is declared
combiner_irq.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/common.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4eb39cd..f194bbc 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -405,6 +405,7 @@ struct combiner_chip_data {
unsigned int irq_offset;
unsigned int irq_mask;
void __iomem *base;
+ unsigned int parent_irq;
};
static struct irq_domain *combiner_irq_domain;
@@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq,
struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+const struct cpumask *mask_val, bool force)
+{
+ struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+ struct irq_chip *chip = irq_get_chip(chip_data-parent_irq);
+ struct irq_data *data = irq_get_irq_data(chip_data-parent_irq);
+
+ if (chip chip-irq_set_affinity)
+ return chip-irq_set_affinity(data, mask_val, force);
+ else
+ return -EINVAL;
+}
+#endif
+
static struct irq_chip combiner_chip = {
- .name = COMBINER,
- .irq_mask = combiner_mask_irq,
- .irq_unmask = combiner_unmask_irq,
+ .name = COMBINER,
+ .irq_mask = combiner_mask_irq,
+ .irq_unmask = combiner_unmask_irq,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = combiner_set_affinity,
+#endif
};
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int
irq)
@@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int
combiner_nr, unsigned int i
}
static void __init combiner_init_one(unsigned int combiner_nr,
-void __iomem *base)
+void __iomem *base, unsigned int irq)
{
combiner_data[combiner_nr].base = base;
combiner_data[combiner_nr].irq_offset = irq_find_mapping(
combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
combiner_data[combiner_nr].irq_mask = 0xff ((combiner_nr % 4) 3);
+ combiner_data[combiner_nr].parent_irq = irq;
/* Disable all interrupts */
__raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem
*combiner_base,
}
for (i = 0; i max_nr; i++) {
- combiner_init_one(i, combiner_base + (i 2) * 0x10);
irq = IRQ_SPI(i);
#ifdef CONFIG_OF
if (np)
irq = irq_of_parse_and_map(np, i);
#endif
+ combiner_init_one(i, combiner_base + (i 2) * 0x10, irq);
combiner_cascade_irq(i, irq);
}
}
--
1.7.9.5
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Re: [PATCH] mmc: dw_mmc: add busmode selection support
On 24 July 2012 18:37, Jae hoon Chung jh80.ch...@gmail.com wrote:
Hi Girish,
Right, it be mentioned about the open-drain mode in synopsys spec.
But if didn't work on other board, there is some problem.
We can consider the location of set_busmode() .
Sure. Currently i am setting the bus mode after sending the command
during the clock setting. since the bus mode has affect on the cmd
line i will try to move the location of calling bus mode before
setting the clock.
you can just check whether card gets detected by moving the set mode
function just below the switch statement of bus width.
On my board irrespective of the set bus mode location it works fine
Best Regards,
Jaehoon Chung
2012/7/24 Girish K S girish.shivananja...@linaro.org:
On 24 July 2012 17:06, Girish K S girish.shivananja...@linaro.org wrote:
On 24 July 2012 16:39, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi Girish,
Well..just tested on my board.
this patch didn't work.(eMMC card didn't initialize)
meaning of ios-bus_mode and synosys's bus_mode is same?
Yes it is same. synopsys spec says this is specific to MMC
initialization. when the card core sets this mode during
initialization. the host has to set this bit
How did you test this patch?
Tested it on exynos5 board using dt patches of thomas (with some
modification to his patch)
Best Regards,
Jaehoon Chung
On 07/23/2012 08:16 PM, Girish K S wrote:
Synopsis Designware host controller has suppport for open
drain mode selection. During the mmc card initialization the
host controller can select the open-drain bit to allow the device
initialization in the open-drain mode. Once the device enters
the standby mode this bit can be reset to enter push-pull mode.
Signed-off-by: Girish K S girish.shivananja...@linaro.org
---
drivers/mmc/host/dw_mmc.c | 14 ++
drivers/mmc/host/dw_mmc.h |1 +
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 72dc3cd..da11e5a 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -773,6 +773,18 @@ static void dw_mci_request(struct mmc_host *mmc,
struct mmc_request *mrq)
spin_unlock_bh(host-lock);
}
+static void dw_mci_set_busmode(struct dw_mci_slot *slot)
+{
+ struct mmc_ios *ios = slot-mmc-ios;
+ u32 reg;
+
+ reg = mci_readl(slot-host, CTRL);
+ if (ios-bus_mode == MMC_BUSMODE_OPENDRAIN)
+ mci_writel(slot-host, CTRL, reg | SDMMC_CTRL_ENABLE_OD);
+ else
+ mci_writel(slot-host, CTRL, reg ~SDMMC_CTRL_ENABLE_OD);
+}
+
static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct dw_mci_slot *slot = mmc_priv(mmc);
@@ -818,6 +830,8 @@ static void dw_mci_set_ios(struct mmc_host *mmc,
struct mmc_ios *ios)
default:
break;
}
+
+ dw_mci_set_busmode(slot);
}
static int dw_mci_get_ro(struct mmc_host *mmc)
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 15c27e1..1a53fb2 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -67,6 +67,7 @@
/* Control register defines */
#define SDMMC_CTRL_USE_IDMAC BIT(25)
+#define SDMMC_CTRL_ENABLE_OD BIT(24)
#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
#define SDMMC_CTRL_SEND_CCSD BIT(9)
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Re: [PATCH 1/2] ARM: EXYNOS: Fix ARM PMU irq numbers
On 26 July 2012 06:05, Chanho Park chanho61.p...@samsung.com wrote:
This patch fixes irq numbers of ARM PMU(Perfromance Monitoring Unit).
We need to seperate arm-pmu(performance measurement unit) and exynos-pmu(power
management unit). I decide to change EXYNOS4_IRQ_PMU to EXYNOS4_IRQ_POWER_PMU
because there are no one use it.
A max cpu number of exynos4 is four in case of exynos44xx. So we should
define 3
additional pmu irq numbers and enable it according to the number of cpus.
Signed-off-by: Chanho Park chanho61.p...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/include/mach/irqs.h | 18 --
arch/arm/plat-samsung/devs.c |9 -
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..329b07d 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMUIRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPSIRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSSIRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUSIRQ_SPI(113)
@@ -136,6 +136,11 @@
#define EXYNOS4_IRQ_TSIIRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
+#define EXYNOS4_IRQ_PMUCOMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
+
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
@@ -230,7 +235,6 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMUEXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNCEXYNOS4_IRQ_FIMD0_VSYNC
@@ -453,6 +457,16 @@
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS5
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS1
+#if defined(CONFIG_ARCH_EXYNOS4)
+#define IRQ_PMUEXYNOS4_IRQ_PMU
+#define IRQ_PMU1 EXYNOS4_IRQ_PMU_CPU1
+#define IRQ_PMU2 EXYNOS4_IRQ_PMU_CPU2
+#define IRQ_PMU3 EXYNOS4_IRQ_PMU_CPU3
+#elif defined(CONFIG_ARCH_EXYNOS5)
+#define IRQ_PMUEXYNOS5_IRQ_PMU
+#define IRQ_PMU1 EXYNOS5_IRQ_PMU_CPU1
+#endif
This will not work when both Exynos 4 and 5 are enabled.
+
#define MAX_COMBINER_NR(EXYNOS4_MAX_COMBINER_NR
EXYNOS5_MAX_COMBINER_NR ? \
EXYNOS4_MAX_COMBINER_NR :
EXYNOS5_MAX_COMBINER_NR)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 74e31ce..91048a6 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1100,7 +1100,14 @@ struct platform_device s5p_device_onenand = {
#ifdef CONFIG_PLAT_S5P
static struct resource s5p_pmu_resource[] = {
- DEFINE_RES_IRQ(IRQ_PMU)
+ DEFINE_RES_IRQ(IRQ_PMU),
+#if (CONFIG_NR_CPUS 1)
+ DEFINE_RES_IRQ(IRQ_PMU1),
+#elif (CONFIG_NR_CPUS 2)
+ DEFINE_RES_IRQ(IRQ_PMU2),
+#elif (CONFIG_NR_CPUS 3)
+ DEFINE_RES_IRQ(IRQ_PMU3),
+#endif
};
static struct platform_device s5p_device_pmu = {
--
1.7.9.5
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Re: [PATCH V2] mmc: dwmmc: Add quirk for broken Hardware Config
On 24 July 2012 10:48, Seungwon Jeon tgih@samsung.com wrote:
Hi Girish,
July 23, 2012, Girish K S girish.shivananja...@linaro.org wrote:
In some Soc'S that integrate Designware mmc host controllers, the
HCON register is broken. The hardware configuration is not
updated. One specific usecase is the IDMAC. In Exysons5 SoC
there exist a internal DMA, but the HCON register's DMA_INTERFACE
field is not set to indicate its existance.
This quirk can be used in such case to force the existance broken
HCON field.
changes in v2:
-moved the implementation to quirk framework as per venkat's
review comment.
changes in v1:
-modified the caps2 field access per controller index.Reported
by Jaehoon Chung jh80.ch...@samsung.com.
-replaced the pointer to device with the pointer to platform
device in struct dw_mci.
Change related to adding pointer of platform_device is needed in this patch
seriously?
I guess that the purpose is to get id of platform_device in case of non-dt.
Although a lot of replace is done throughout dw_mmc, actual usage is only in
dw_get_platform_device_id.
You can split it into another patch if this change is needed, or it's good to
use other way.
For example, to_platform_device macro is useful to get pointer of
platform_device.
I will make the necessary changes as suggested once Thomas's patches
gets accepted
Best regards,
Seungwon Jeon
-updated driver data for all 4 mmc controllers of exynos5 SoC.
-added non device-tree support for ctrl_id access.
Signed-off-by: Girish K S girish.shivananja...@linaro.org
---
drivers/mmc/host/dw_mmc-pltfm.c | 10 +++-
drivers/mmc/host/dw_mmc.c | 151
---
drivers/mmc/host/dw_mmc.h |1 +
include/linux/mmc/dw_mmc.h |4 +-
4 files changed, 107 insertions(+), 59 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c
b/drivers/mmc/host/dw_mmc-pltfm.c
index 900f412..7d31e90 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -35,9 +35,17 @@ static unsigned long exynos5250_dwmmc_caps[4] = {
MMC_CAP_CMD23,
};
+static unsigned long exynos5250_dwmmc_quirks[4] = {
+ DW_MCI_QUIRK_NO_HCON_DMA_INFO,
+ DW_MCI_QUIRK_NO_HCON_DMA_INFO,
+ DW_MCI_QUIRK_NO_HCON_DMA_INFO,
+ DW_MCI_QUIRK_NO_HCON_DMA_INFO,
+};
+
static struct dw_mci_drv_data exynos5250_drv_data = {
.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
.caps = exynos5250_dwmmc_caps,
+ .quirks = exynos5250_dwmmc_quirks,
};
static const struct of_device_id dw_mci_pltfm_match[] = {
@@ -74,7 +82,7 @@ static int dw_mci_pltfm_probe(struct platform_device *pdev)
goto err_free;
}
- host-dev = pdev-dev;
+ host-pdev = pdev;
host-irq_flags = 0;
host-pdata = pdev-dev.platform_data;
ret = -ENOMEM;
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 000da16..b32e200 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -283,8 +283,10 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc,
struct mmc_command *cmd)
static void dw_mci_start_command(struct dw_mci *host,
struct mmc_command *cmd, u32 cmd_flags)
{
+ struct device *dev = host-pdev-dev;
+
host-cmd = cmd;
- dev_vdbg(host-dev,
+ dev_vdbg(dev,
start command: ARGR=0x%08x CMDR=0x%08x\n,
cmd-arg, cmd_flags);
@@ -323,10 +325,11 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
static void dw_mci_dma_cleanup(struct dw_mci *host)
{
struct mmc_data *data = host-data;
+ struct device *dev = host-pdev-dev;
if (data)
if (!data-host_cookie)
- dma_unmap_sg(host-dev,
+ dma_unmap_sg(dev,
data-sg,
data-sg_len,
dw_mci_get_dma_dir(data));
@@ -351,8 +354,9 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
static void dw_mci_idmac_complete_dma(struct dw_mci *host)
{
struct mmc_data *data = host-data;
+ struct device *dev = host-pdev-dev;
- dev_vdbg(host-dev, DMA complete\n);
+ dev_vdbg(dev, DMA complete\n);
host-dma_ops-cleanup(host);
@@ -420,10 +424,27 @@ static void dw_mci_idmac_start_dma(struct dw_mci
*host, unsigned int sg_len)
mci_writel(host, PLDMND, 1);
}
+static int dw_get_platform_device_id(struct dw_mci *host)
+{
+ int ctrl_id;
+ struct device *dev = host-pdev-dev;
+
+ if (dev-of_node)
+ ctrl_id = of_alias_get_id(dev-of_node, mshc);
+ else
+ ctrl_id = host-pdev-id;
+
+ if (ctrl_id 0)
+ ctrl_id = 0;
+
+ return ctrl_id;
+}
+
static int dw_mci_idmac_init(struct dw_mci *host)
{
struct idmac_desc
Re: [PATCH] ARM: EXYNOS: Add I2S SFR base addresses
On 25 July 2012 17:35, Padmavathi Venna padm...@samsung.com wrote:
The base address of I2S 0 controller is similar in exynos4 and exynos5
platforms. So this patch defines a common macro for the I2S controller
0 base address in both the platforms and use the same macro.
This patch also defines the I2S controller 1,2 base addresses in exynos5
and correct the I2S controller 1 base address in exynos4
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/dev-audio.c|2 +-
arch/arm/mach-exynos/include/mach/map.h |6 --
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/dev-audio.c
b/arch/arm/mach-exynos/dev-audio.c
index b33a5b6..5dbc9a2 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -62,7 +62,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
};
static struct resource exynos4_i2s0_resource[] = {
- [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
+ [0] = DEFINE_RES_MEM(EXYNOS_PA_I2S0, SZ_256),
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index c72b675..5cf7d91 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -39,9 +39,11 @@
#define EXYNOS4_PA_G2D 0x1280
-#define EXYNOS4_PA_I2S00x0383
-#define EXYNOS4_PA_I2S10xE310
+#define EXYNOS_PA_I2S0 0x0383
+#define EXYNOS4_PA_I2S10xE210
#define EXYNOS4_PA_I2S20xE2A0
As per the TRM, these addresses (I2S1 and I2S2) are 0x1396 and
0x1397 respectively on Exynos4412 SoC.
Please verify.
+#define EXYNOS5_PA_I2S10x12D6
+#define EXYNOS5_PA_I2S20x12D7
#define EXYNOS4_PA_PCM00x0384
#define EXYNOS4_PA_PCM10x1398
--
1.7.4.4
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Sachin
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