Re: [PATCH] ARM: dts: add pinctrl nodes for Exynos5250 SoC
On Thu, Dec 13, 2012 at 2:06 PM, Thomas Abraham wrote: > Add pinctrl device nodes for Exynos5250 SoC. > > Signed-off-by: Thomas Abraham Acked-by: Linus Walleij > - The individual device nodes which are using the old style Samsung gpio > bindings have not been converted over to pinctrl bindings yet. It might > also be important to know if Linus's pinctrl grab in device core patch > (http://comments.gmane.org/gmane.linux.kernel/1409263) gets accepted. Greg seems happy with it and the plan is to have it merged for kernel v3.9. I intend to push Greg for an ACK and queue it for linux-next right after the merge window. > - This patch should not be merged for now which otherwise would break existing > platforms which are using the old samsung gpio driver bindings. This patch > is intended to get started with the migration to pinctrl framework. > It is probably better to first prepare all the migration patches and > merge them as a bunch. Sure. I guess it'll be taken through the Samsung tree anyway, right? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names
On 14 December 2012 21:43, Dongjin Kim wrote:
> Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
>
> Signed-off-by: Dongjin Kim
> ---
> arch/arm/mach-exynos/clock-exynos4.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c
> b/arch/arm/mach-exynos/clock-exynos4.c
> index efead60..bbcb3de 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -529,7 +529,7 @@ static struct clk exynos4_init_clocks_off[] = {
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 8),
> }, {
> - .name = "dwmmc",
> + .name = "biu",
> .parent = &exynos4_clk_aclk_133.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 9),
> @@ -1134,7 +1134,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4
> },
> }, {
> .clk= {
> - .name = "sclk_dwmmc",
> + .name = "ciu",
> .parent = &exynos4_clk_dout_mmc4.clk,
> .enable = exynos4_clksrc_mask_fsys_ctrl,
> .ctrlbit= (1 << 16),
> --
Acked-by: Thomas Abraham
> 1.7.9.5
>
> --
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[PATCH] ARM: EXYNOS: Fix MSHC clocks instance names
Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
Signed-off-by: Dongjin Kim
---
arch/arm/mach-exynos/clock-exynos4.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c
b/arch/arm/mach-exynos/clock-exynos4.c
index efead60..bbcb3de 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -529,7 +529,7 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 8),
}, {
- .name = "dwmmc",
+ .name = "biu",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 9),
@@ -1134,7 +1134,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk= {
- .name = "sclk_dwmmc",
+ .name = "ciu",
.parent = &exynos4_clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit= (1 << 16),
--
1.7.9.5
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Re: [PATCH 1/2] i2c-core: Add gpio based bus arbitration implementation
On 12/13/2012 10:50 PM, Naveen Krishna Chatradhi wrote: > The arbitrator is a general purpose function which uses two GPIOs to > communicate with another device to claim/release a bus. > diff --git a/Documentation/devicetree/bindings/i2c/arbitrator-i2c.txt > b/Documentation/devicetree/bindings/i2c/arbitrator-i2c.txt > new file mode 100644 > index 000..cb91ea8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/i2c/arbitrator-i2c.txt > @@ -0,0 +1,56 @@ > +Device-Tree bindings for i2c gpio based bus arbitrator > + > +bus-arbitration-gpios : > + Two GPIOs to use with the GPIO-based bus arbitration protocol > +(see below). > +The first should be an output, and is used to claim the I2C bus, > +the second should be an input, and signals that the other side (Client) > +wants to claim the bus. This allows two masters to share the same I2C bus. I'm confused why this is even needed; the I2C protocol itself defines how multi-master is supposed to work, just using the regular SCL/SDA lines. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: Fix MSHC clocks instance names
Hi Dongjin,
On 14 December 2012 20:29, Dongjin Kim wrote:
> Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
>
> Signed-off-by: Dongjin Kim
> ---
> arch/arm/mach-exynos/clock-exynos4.c | 25 ++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c
> b/arch/arm/mach-exynos/clock-exynos4.c
> index efead60..ae83011 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -529,8 +529,8 @@ static struct clk exynos4_init_clocks_off[] = {
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 8),
> }, {
> - .name = "dwmmc",
> - .parent = &exynos4_clk_aclk_133.clk,
> + .name = "biu",
> + .parent = &exynos4_clk_aclk_200.clk,
> .enable = exynos4_clk_ip_fsys_ctrl,
> .ctrlbit= (1 << 9),
> }, {
> @@ -1132,15 +1132,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
> .sources = &exynos4_clkset_mout_mfc,
> .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1
> },
> .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4
> },
> - }, {
> - .clk= {
> - .name = "sclk_dwmmc",
> - .parent = &exynos4_clk_dout_mmc4.clk,
> - .enable = exynos4_clksrc_mask_fsys_ctrl,
> - .ctrlbit= (1 << 16),
> - },
> - .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size =
> 8 },
> - }
> + },
> };
>
> static struct clksrc_clk exynos4_clk_sclk_uart0 = {
> @@ -1235,6 +1227,16 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
> .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
> };
>
> +static struct clksrc_clk exynos4_clk_sclk_dwmci = {
> + .clk= {
> + .name = "ciu",
> + .parent = &exynos4_clk_dout_mmc4.clk,
> + .enable = exynos4_clksrc_mask_fsys_ctrl,
> + .ctrlbit= (1 << 16),
> + },
> + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
> +};
> +
It is not required to move the above clock instance out of the
exynos4_clksrcs[] array. Just changing the clock name to 'ciu' is
sufficient. And this will avoid the below change as well.
> static struct clksrc_clk exynos4_clk_mdout_spi0 = {
> .clk= {
> .name = "mdout_spi",
> @@ -1348,6 +1350,7 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
> &exynos4_clk_sclk_mmc1,
> &exynos4_clk_sclk_mmc2,
> &exynos4_clk_sclk_mmc3,
> + &exynos4_clk_sclk_dwmci,
> &exynos4_clk_sclk_spi0,
> &exynos4_clk_sclk_spi1,
> &exynos4_clk_sclk_spi2,
> --
> 1.7.9.5
Thanks,
Thomas.
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Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data
Hi Linus, On 14 December 2012 21:21, Linus Walleij wrote: > On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham > wrote: > >> Add Samsung Exynos5250 SoC specific data to enable pinctrl support for >> all platforms based on Exynos5250. >> >> Signed-off-by: Thomas Abraham > > Acked-by: Linus Walleij > > For this series, I guess you'll fix it through the Samsung tree? Thanks for your ack. Since there are patches to be prepared for migrating the rest of Exynos5250 related code to the pinctrl framework, it would be easier if this series goes through the Samsung tree. Thanks, Thomas. > > Yours, > Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data
On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham wrote: > Add Samsung Exynos5250 SoC specific data to enable pinctrl support for > all platforms based on Exynos5250. > > Signed-off-by: Thomas Abraham Acked-by: Linus Walleij For this series, I guess you'll fix it through the Samsung tree? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: EXYNOS: Fix MSHC clocks instance names
Replace clock instance name of MSHC controller for BIC and CIU of Exynos4412.
Signed-off-by: Dongjin Kim
---
arch/arm/mach-exynos/clock-exynos4.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c
b/arch/arm/mach-exynos/clock-exynos4.c
index efead60..ae83011 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -529,8 +529,8 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 8),
}, {
- .name = "dwmmc",
- .parent = &exynos4_clk_aclk_133.clk,
+ .name = "biu",
+ .parent = &exynos4_clk_aclk_200.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit= (1 << 9),
}, {
@@ -1132,15 +1132,7 @@ static struct clksrc_clk exynos4_clksrcs[] = {
.sources = &exynos4_clkset_mout_mfc,
.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
- }, {
- .clk= {
- .name = "sclk_dwmmc",
- .parent = &exynos4_clk_dout_mmc4.clk,
- .enable = exynos4_clksrc_mask_fsys_ctrl,
- .ctrlbit= (1 << 16),
- },
- .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8
},
- }
+ },
};
static struct clksrc_clk exynos4_clk_sclk_uart0 = {
@@ -1235,6 +1227,16 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
+static struct clksrc_clk exynos4_clk_sclk_dwmci = {
+ .clk= {
+ .name = "ciu",
+ .parent = &exynos4_clk_dout_mmc4.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit= (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+};
+
static struct clksrc_clk exynos4_clk_mdout_spi0 = {
.clk= {
.name = "mdout_spi",
@@ -1348,6 +1350,7 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_mmc1,
&exynos4_clk_sclk_mmc2,
&exynos4_clk_sclk_mmc3,
+ &exynos4_clk_sclk_dwmci,
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
--
1.7.9.5
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Re: [PATCH] gpio: samsung: remove exynos_gpio_cfg
Hi Joonyoung, On Friday 14 of December 2012 19:44:01 Joonyoung Shim wrote: > The exynos_gpio_cfg can be substituted to samsung_gpio_cfgs[8]. > > Signed-off-by: Joonyoung Shim Since recently Thomas Abraham posted patches for pin control support of Exynos5250, basically making the legacy GPIO support useless, I think there is no need to extend it. Instead existing boards should be made to use the pinctrl driver. Best regards, -- Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] pinctrl: exynos: add support for Samsung's Exynos5250
Hi Thomas, On Thursday 13 of December 2012 17:24:01 Thomas Abraham wrote: > This patch series adds pinctrl driver support for Samsung's Exynos5250 > SoC. The first patch adds the required Exynos5250 SoC specific data > which is used by the Samsung pinctrl driver to setup the > pinctrl/pinmux/eint controllers. The second and third patches skips the > wakeup interrupt and gpiolib registration if the pinctrl support is > enabled for Exynos5250. > > Thomas Abraham (3): > pinctrl: exynos: add exynos5250 SoC specific data > gpio: samsung: skip gpiolib registration if pinctrl support is enabled > for exynos5250 arm: exynos: skip wakeup interrupt registration for > exynos5250 if pinctrl is enabled > > arch/arm/mach-exynos/common.c |1 + > drivers/gpio/gpio-samsung.c |1 + > drivers/pinctrl/pinctrl-exynos.c | 108 > + drivers/pinctrl/pinctrl-samsung.c > |2 + > drivers/pinctrl/pinctrl-samsung.h |1 + > 5 files changed, 113 insertions(+), 0 deletions(-) > > -- > To unsubscribe from this list: send the line "unsubscribe > linux-samsung-soc" in the body of a message to > majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html Looks good. For the whole series: Reviewed-by: Tomasz Figa Best regards, -- Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5] ARM: EXYNOS: Add MFC device tree support
Arun Kumar K samsung.com> writes:
>
> This patch adds device tree entry for MFC v6 in the Exynos5
> SoC. Makes the required changes in the clock files and adds
> MFC to the DT device list.
>
> Signed-off-by: Naveen Krishna Chatradhi samsung.com>
> Signed-off-by: Arun Kumar K samsung.com>
> ---
> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> +Required properties:
> + - compatible : value should be either one among the following
> + (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
> + (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
Sorry for replying on this patch so late, but this thread came
to my attention only recently.
I thought generic comaptibles like this are discouraged and instead
you are supposed to ground the compatible property to a real silicon name.
So you would use something like "samsung,exynos4212-mfc" and so on.
> + - samsung,mfc-r : Base address of the first memory bank used by MFC
> + for DMA contiguous memory allocation and its size.
> +
> + - samsung,mfc-l : Base address of the second memory bank used by MFC
> + for DMA contiguous memory allocation and its size.
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> +
> + codec 1100 {
> + samsung,mfc-r = <0x4300 0x80>;
> + samsung,mfc-l = <0x5100 0x80>;
> + };
How are these addresses determined? Are they defined by hardware (so they are
not user configurable) or is the user free to choose them depending on where
he intends the contiguous memory to lie? If it is the later, I wonder if it
is considered okay to define this in device tree since it is supposed to be
a description of the hardware.
We have a similar situation on DaVinci and we are wondering how this should
be handled. The ideal choice seems to be module parameters, but there are
some challenges there. See:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/136996.html
I understand I am speaking too late on this patch (seems like it is already
merged into linux-next at the least), but I still wanted to start the
conversation here for future sake.
Thanks,
Sekhar
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[PATCH] gpio: samsung: add GPIO interrupt registration for exynos5
This adds GPIO interrupt registration and modification needs to register
GPIO interrupt rightly for exynos5 SoCs. EXYNOS5_GPYx gpios shouldn't be
counted to GPIO interrupt group register number because they doesn't
support GPIO interrupt, so their struct samsung_gpio_cfg should be
initialized to &samsung_gpio_cfgs[8] in declaration ahead.
Signed-off-by: Joonyoung Shim
---
drivers/gpio/gpio-samsung.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index e30cd60..a462f2c 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -2519,42 +2519,49 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
.label = "GPD1",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY0(0),
.ngpio = EXYNOS5_GPIO_Y0_NR,
.label = "GPY0",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY1(0),
.ngpio = EXYNOS5_GPIO_Y1_NR,
.label = "GPY1",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY2(0),
.ngpio = EXYNOS5_GPIO_Y2_NR,
.label = "GPY2",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY3(0),
.ngpio = EXYNOS5_GPIO_Y3_NR,
.label = "GPY3",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY4(0),
.ngpio = EXYNOS5_GPIO_Y4_NR,
.label = "GPY4",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY5(0),
.ngpio = EXYNOS5_GPIO_Y5_NR,
.label = "GPY5",
},
}, {
+ .config = &samsung_gpio_cfgs[8],
.chip = {
.base = EXYNOS5_GPY6(0),
.ngpio = EXYNOS5_GPIO_Y6_NR,
@@ -3002,6 +3009,24 @@ static __init void exynos5_gpiolib_init(void)
}
samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
nr_chips, gpio_base4);
+
+#ifdef CONFIG_S5P_GPIO_INT
+ s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XA, 0,
+ EXYNOS5_IRQ_GPIO1_NR_GROUPS);
+ s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XB,
+ EXYNOS5_IRQ_GPIO1_NR_GROUPS,
+ EXYNOS5_IRQ_GPIO2_NR_GROUPS);
+ s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_C2C,
+ EXYNOS5_IRQ_GPIO1_NR_GROUPS +
+ EXYNOS5_IRQ_GPIO2_NR_GROUPS,
+ EXYNOS5_IRQ_GPIO3_NR_GROUPS);
+ s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO,
+ EXYNOS5_IRQ_GPIO1_NR_GROUPS +
+ EXYNOS5_IRQ_GPIO2_NR_GROUPS +
+ EXYNOS5_IRQ_GPIO3_NR_GROUPS,
+ EXYNOS5_IRQ_GPIO4_NR_GROUPS);
+#endif
+
return;
err_ioremap4:
--
1.7.9.5
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[PATCH] gpio: samsung: remove exynos_gpio_cfg
The exynos_gpio_cfg can be substituted to samsung_gpio_cfgs[8].
Signed-off-by: Joonyoung Shim
---
drivers/gpio/gpio-samsung.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 6f93d36..a462f2c 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -452,15 +452,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
};
#endif
-#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
-static struct samsung_gpio_cfg exynos_gpio_cfg = {
- .set_pull = exynos_gpio_setpull,
- .get_pull = exynos_gpio_getpull,
- .set_config = samsung_gpio_setcfg_4bit,
- .get_config = samsung_gpio_getcfg_4bit,
-};
-#endif
-
#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
.cfg_eint = 0x3,
@@ -2181,7 +2172,7 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
* Followings are the gpio banks in EXYNOS SoCs
*
* The 'config' member when left to NULL, is initialized to the default
- * structure exynos_gpio_cfg in the init function below.
+ * structure samsung_gpio_cfgs[8] in the init function below.
*
* The 'base' member is also initialized in the init function below.
* Note: The initialization of 'base' member of samsung_gpio_chip structure
@@ -2837,7 +2828,7 @@ static __init void exynos4_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -2864,7 +2855,7 @@ static __init void exynos4_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -2885,7 +2876,7 @@ static __init void exynos4_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -2940,7 +2931,7 @@ static __init void exynos5_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -2961,7 +2952,7 @@ static __init void exynos5_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -2989,7 +2980,7 @@ static __init void exynos5_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
@@ -3010,7 +3001,7 @@ static __init void exynos5_gpiolib_init(void)
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
- chip->config = &exynos_gpio_cfg;
+ chip->config = &samsung_gpio_cfgs[8];
chip->group = group++;
}
exynos_gpiolib_attach_ofnode(chip,
--
1.7.9.5
--
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[PATCH] ARM: EXYNOS: Fix compile error in dev-audio.c
arch/arm/mach-exynos/dev-audio.c:58:4: error: unknown field 'src_clk'
specified in initializer
arch/arm/mach-exynos/dev-audio.c:58:4: warning: initialization makes integer
from pointer without a cast [enabled by default]
arch/arm/mach-exynos/dev-audio.c:58:4: warning: (near initialization for
'i2sv5_pdata.type.i2s.idma_addr') [enabled by default]
arch/arm/mach-exynos/dev-audio.c:91:4: error: unknown field 'src_clk'
specified in initializer
arch/arm/mach-exynos/dev-audio.c:91:4: warning: initialization makes integer
from pointer without a cast [enabled by default]
arch/arm/mach-exynos/dev-audio.c:91:4: warning: (near initialization for
'i2sv3_pdata.type.i2s.idma_addr') [enabled by default]
Signed-off-by: Jonghwan Choi
---
arch/arm/mach-exynos/dev-audio.c | 12
1 files changed, 0 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-exynos/dev-audio.c
b/arch/arm/mach-exynos/dev-audio.c
index a1cb42c..9d1a609 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -23,11 +23,6 @@
#include
#include
-static const char *rclksrc[] = {
- [0] = "busclk",
- [1] = "i2sclk",
-};
-
static int exynos4_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
@@ -55,7 +50,6 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
- .src_clk = rclksrc,
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
},
},
@@ -78,17 +72,11 @@ struct platform_device exynos4_device_i2s0 = {
},
};
-static const char *rclksrc_v3[] = {
- [0] = "sclk_i2s",
- [1] = "no_such_clock",
-};
-
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_NO_MUXPSR,
- .src_clk = rclksrc_v3,
},
},
};
--
1.7.4.1
--
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