RE: [PATCH V5 2/2] ASoC: SAMSUNG: Add DT support for i2s
Kukjin Kim wrote: Re-sending due to e-mail client problem :( Padma Venkat wrote: Hi, On Wed, Dec 19, 2012 at 10:39 PM, Mark Brown broo...@opensource.wolfsonmicro.com wrote: On Wed, Dec 19, 2012 at 01:24:14PM +, Grant Likely wrote: On Thu, 13 Dec 2012 16:12:53 +0530, Padmavathi Venna padm...@samsung.com wrote: +- compatible : samsung,samsung-i2s Isn't that kind of redundant? :-) The format of the compatible strings should be vendor,part- number-i2s. Please be specific about the part number that you're doing the binding for. For example; use samsung,exynos4210-i2s instead of samsung,exynos-i2s. There are actually versioned IPs here (where the versions are used publically in a few places) but it's not clearly documented which is which. It would be reasonable to use the IP versions here I think. Samsung has three i2s drivers one for s3c24xx, one for s3c2412 and one for rest of the platforms. The above mentioned other platforms has Version 3/4/5 of i2s controllers. This dt binding is for for the i2s Where is the version defined such as 3, 4, 5? So, what is the sound/soc/Samsung/s3c-i2s-v2.[ch]? driver that has support for Version 3/4/5 of i2s controller. So samsung,i2s-v5 is okay as compatible name? Please suggest me. I agree with using version here but we need some consensus about that. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 0/2] usb: exynos: Fix compatible strings used for device
Kukjin Kim wrote:
Re-sending due to e-mail client problem...
Doug Anderson wrote:
On Fri, Dec 21, 2012 at 12:14 AM, Vivek Gautam
gautamvivek1...@gmail.com wrote:
On Wed, Dec 19, 2012 at 7:16 PM, Vivek Gautam
gautamvivek1...@gmail.com wrote:
On Sat, Dec 15, 2012 at 12:50 PM, Grant Likely
grant.lik...@secretlab.ca wrote:
On Thu, 13 Dec 2012 20:22:26 +0530, Vivek Gautam
gautam.vi...@samsung.com wrote:
Using chip specific compatible string as it should be.
So fixing this for ehci-s5p, ohci-exynos and dwc3-exynos
which till now used a generic 'exynos' in their compatible strings.
This goes as per the discussion happened in the thread for
[PATCH v2] ARM: Exynos5250: Enabling dwc3-exynos driver
available at:
http://www.spinics.net/lists/linux-usb/msg74145.html
Vivek Gautam (2):
usb: ehci-s5p/ohci-exynos: Fix compatible strings for the device
usb: dwc3-exynos: Fix compatible strings for the device
for both patches:
Acked-by: Grant Likely grant.lik...@secretlab.ca
Any more thought about this patch-set?
Or does this change seems fine?
These two changes look good to me. For both of them:
Reviewed-by: Doug Anderson diand...@chromium.org
Well, I have another idea. Yes, I know, specific chip name should be used.
But
you know the specific chip name in compatible can cause another confusion
on other SoC which has same IP. So I think, we need to consider to use
common name or any specific name not chip in compatible for IP/driver like
following?
- { .compatible = samsung,exynos-dwc3 },
+ { .compatible = samsung,synopsis-dwc3 },
Or if any version or something, how about following?
+ { .compatible = samsung,dwc-v3 },
- Kukjin
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Re: [PATCH V5 2/2] ASoC: SAMSUNG: Add DT support for i2s
Hi, On Sat, Dec 22, 2012 at 12:32 AM, Kukjin Kim kgene@samsung.com wrote: Padma Venkat wrote: Hi, On Wed, Dec 19, 2012 at 10:39 PM, Mark Brown broo...@opensource.wolfsonmicro.com wrote: On Wed, Dec 19, 2012 at 01:24:14PM +, Grant Likely wrote: On Thu, 13 Dec 2012 16:12:53 +0530, Padmavathi Venna padm...@samsung.com wrote: +- compatible : samsung,samsung-i2s Isn't that kind of redundant? :-) The format of the compatible strings should be vendor,part- number-i2s. Please be specific about the part number that you're doing the binding for. For example; use samsung,exynos4210-i2s instead of samsung,exynos-i2s. There are actually versioned IPs here (where the versions are used publically in a few places) but it's not clearly documented which is which. It would be reasonable to use the IP versions here I think. Samsung has three i2s drivers one for s3c24xx, one for s3c2412 and one for rest of the platforms. The above mentioned other platforms has Version 3/4/5 of i2s controllers. This dt binding is for for the i2s Where is the version defined such as 3, 4, 5? So, what is the sound/soc/Samsung/s3c-i2s-v2.[ch]? Versions 3, 4, 5 are defined in dev-audio.c file of corresponding platforms. s3c-i2s-v2 is used in s3c2412 platform. driver that has support for Version 3/4/5 of i2s controller. So samsung,i2s-v5 is okay as compatible name? Please suggest me. I agree with using version here but we need some consensus about that. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Thanks Padma -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Choi, The method Save/restore clock source register - CLK_SRC_TOP3 was suggested as well as preferred by our hardware team. Would it be possible to give more information on this alternate method ? On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi jhbird.c...@gmail.com wrote: Hi~ This code should be changed. I insert this code (save/restore clock source register - CLK_SRC_TOP3) temporary. But we removed this code. And we use another method to fix it. I think this is not right way. Thanks. On Fri, Dec 21, 2012 at 6:06 AM, tomasz.f...@gmail.com wrote: Hi Prasanna, On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote: This patch adds a software workaround to the hardware problem found in exynos5 while powergating. It is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC. The value of clock source register is restored once the powergating operation is completed. Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code. Altering clock configuration registers from power domain code looks really ugly... Best regards, Tomasz Figa -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Thanks Prasanna Kumar -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi tomasz, On Fri, Dec 21, 2012 at 2:36 AM, tomasz.f...@gmail.com wrote: Hi Prasanna, On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote: This patch adds a software workaround to the hardware problem found in exynos5 while powergating. It is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC. The value of clock source register is restored once the powergating operation is completed. Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code. The problem is only seen in following sequence. 1. Suspend and then Resume the system 2. Power Gating ( On- Off ) of the associated power domain ( Gscaler , MFC ...) I rechecked clock save/restore part of power management code.The register is already being saved clock save/restore part of power management code. ( exynos5_clock_save. in clock-exynos5.c). I hope you have understood the situation here. Best regards, Tomasz Figa ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Thanks Prasanna Kumar -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Choi, On Mon, Dec 24, 2012 at 9:56 AM, Prasanna Kumar prasannapadubi...@gmail.com wrote: Hi Choi, The method Save/restore clock source register - CLK_SRC_TOP3 was suggested as well as preferred by our hardware team. Would it be possible to give more information on this alternate method ? I just wanted to be more clear on the last sentence of my previous email. Here alternate method means, the method you have used to fix the issue. Kindly share information on that. -- Thanks On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi jhbird.c...@gmail.com wrote: Hi~ This code should be changed. I insert this code (save/restore clock source register - CLK_SRC_TOP3) temporary. But we removed this code. And we use another method to fix it. I think this is not right way. Thanks. On Fri, Dec 21, 2012 at 6:06 AM, tomasz.f...@gmail.com wrote: Hi Prasanna, On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote: This patch adds a software workaround to the hardware problem found in exynos5 while powergating. It is observed that CLK_TOP_SRC3 register gets modified if the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets set to XXTI which results in the device running very slow . A big drop in performance is noticed whilerunning the video. This issue also occurs while powergating MFC. The value of clock source register is restored once the powergating operation is completed. Is the problem really related to power gating at all? From what you described in comment in the code, it seems like it's a problem with suspend/resume, not power gating, so it should be rather saved on suspend and restored on resume. Please recheck clock save/restore part of power management code. Altering clock configuration registers from power domain code looks really ugly... Best regards, Tomasz Figa -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Thanks Prasanna Kumar -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
