Re: [PATCH 1/2] i2c: exynos5: add High Speed I2C controller driver
Hello Balbi,
On 28 December 2012 04:27, Felipe Balbi wrote:
> Hi,
>
> On Tue, Dec 25, 2012 at 04:55:54PM +0530, Naveen Krishna Chatradhi wrote:
>> Adds support for High Speed I2C driver found in Exynos5 and later
>> SoCs from Samsung. This driver currently supports Auto mode.
>>
>> Driver only supports Device Tree method.
>>
>> Signed-off-by: Taekgyun Ko
>> Signed-off-by: Naveen Krishna Chatradhi
>> ---
>> Changes since v1:
>> Fixed the comments from Felipe Balbi and Thomas Abraham.
>>
>> drivers/i2c/busses/Kconfig |7 +
>> drivers/i2c/busses/Makefile |1 +
>> drivers/i2c/busses/i2c-exynos5.c | 652
>> ++
>> drivers/i2c/busses/i2c-exynos5.h | 102 ++
>> 4 files changed, 762 insertions(+)
>> create mode 100644 drivers/i2c/busses/i2c-exynos5.c
>> create mode 100644 drivers/i2c/busses/i2c-exynos5.h
>>
>> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
>> index bdca511..4caea76 100644
>> --- a/drivers/i2c/busses/Kconfig
>> +++ b/drivers/i2c/busses/Kconfig
>> @@ -618,6 +618,13 @@ config I2C_S3C2410
>> Say Y here to include support for I2C controller in the
>> Samsung SoCs.
>>
>> +config I2C_EXYNOS5
>> + tristate "Exynos5 high-speed I2C driver"
>> + depends on ARCH_EXYNOS5
>> + help
>> + Say Y here to include support for High-speed I2C controller in the
>> + Exynos5 based Samsung SoCs.
>> +
>> config I2C_S6000
>> tristate "S6000 I2C support"
>> depends on XTENSA_VARIANT_S6000
>> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
>> index 6181f3f..4b1548c 100644
>> --- a/drivers/i2c/busses/Makefile
>> +++ b/drivers/i2c/busses/Makefile
>> @@ -61,6 +61,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
>> obj-$(CONFIG_I2C_PXA)+= i2c-pxa.o
>> obj-$(CONFIG_I2C_PXA_PCI)+= i2c-pxa-pci.o
>> obj-$(CONFIG_I2C_S3C2410)+= i2c-s3c2410.o
>> +obj-$(CONFIG_I2C_EXYNOS5)+= i2c-exynos5.o
>> obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
>> obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
>> obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
>> diff --git a/drivers/i2c/busses/i2c-exynos5.c
>> b/drivers/i2c/busses/i2c-exynos5.c
>> new file mode 100644
>> index 000..7614f60
>> --- /dev/null
>> +++ b/drivers/i2c/busses/i2c-exynos5.c
>> @@ -0,0 +1,652 @@
>> +/* linux/drivers/i2c/busses/i2c-exynos5.c
>
> no need for the full path. Generally this would look like:
>
> * i2c-exynos5.c - Samsung Exynos 5 I2C Controller Driver
>
> no strong feelings however.
>
>> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
>> + *
>> + * High speed I2C controller driver
>> + * for Exynos5 and later SoCs from Samsung.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "i2c-exynos5.h"
>
> it doesn't look like this header is even needed. All those macros could
> be defined here in the C-source file which is the only user.
>
>> +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
>> +
>> +/* timeout for pm runtime autosuspend */
>> +#define EXYNOS5_I2C_PM_TIMEOUT 1000/* ms */
>> +
>> +struct exynos5_i2c {
>> + struct i2c_adapter adap;
>> + unsigned intsuspended:1;
>> +
>> + struct i2c_msg *msg;
>> + unsigned intmsg_idx;
>> + struct completion msg_complete;
>> + unsigned intmsg_ptr;
>> +
>> + unsigned intirq;
>> +
>> + void __iomem*regs;
>> + struct clk *clk;
>> + struct device *dev;
>> + int gpios[2];
>> +
>> + int bus_num;
>> + int speed_mode;
>> +};
>> +
>> +static const struct of_device_id exynos5_i2c_match[] = {
>> + { .compatible = "samsung,exynos5-hsi2c" },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
>> +
>> +/* TODO: Should go to debugfs */
>> +static inline void dump_i2c_register(struct exynos5_i2c *i2c)
>> +{
>> + dev_vdbg(i2c->dev, "Register dump(%d) :\n %x\n %x\n %x\n %x\n"
>> + " %x\n %x\n %x\n %x\n %x\n"
>> + " %x\n %x\n %x\n %x\n %x\n"
>> + " %x\n %x\n %x\n %x\n %x\n"
>> + " %x\n %x\n %x\n %x\n %x\n",
>> + i2c->suspended,
>> + readl(i2c->regs + HSI2C_CTL),
>> + readl(i2c->regs + HSI2C_FIFO_CTL),
>> + readl(i2c->regs + HSI2C_TRAILIG_CTL),
>> + readl(i2c->regs + HSI2C_CLK_CTL),
>> + readl(i2c->regs + HSI2C_CLK_SLOT),
>> +
Re: [PATCH] video: drm: exynos: mie bypass enable for fimd
2012/12/28 Leela Krishna Amudala :
> Hello Inki Dae,
>
> On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote:
>>
>> Hi,
>>
>> DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So
>> it's not good that this register is controlled in fimd module. And I think
>> the function to control the register should be placed in SoC common file .
>> In other words, other drivers should be able to control the register through
>> common thing also.
>>
>
> Thanks for reviewing the patch.
> You mean to say that this functionality should be implemented at arch side
> and called by drivers using call back functions ?
>
> If so, then if we moved the driver to full DT version, all the call
> backs will be removed.
> Then how to make a call to this function?
>
> So I thought other drivers (apart from Fimd) also parses the
> appropriate nodes and
> program the register as per the need.
>
> Please correct me if my understanding is wrong.
>
The base address of DISP1BLK_CFG already was iorempped by
iotable_init() at machine init. So you can control DISP1BLK_CFG
register using only offset. But your patch does ioremap again and also
even not iounmap. This is ugly. Please see
arch/arm/plat-samsung/setup-mipiphy.c how the common register is
controlled and this is a good example. And please abuse dt.
> Best Wishes,
> Leela Krishna Amudala.
>
>
>> Thanks,
>> Inki Dae
>>
>> 2012/12/26 Leela Krishna Amudala
>>>
>>> Bypasses the mie for fimd by parsing the register and bit offset values
>>> from "mie-bypass" node, if "mie-bypass" node is present in the dts file.
>>>
>>> Signed-off-by: Leela Krishna Amudala
>>> ---
>>> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 55
>>>
>>> 1 file changed, 55 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> index bf0d9ba..f8ad259 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> @@ -118,6 +118,12 @@ static const struct of_device_id
>>> fimd_driver_dt_match[] = {
>>> MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
>>> #endif
>>>
>>> +struct mie_bypass {
>>> + u32 enable_bypass;
>>> + void __iomem*bypass_reg;
>>> + u32 bypass_bit_offset;
>>> +};
>>> +
>>> static inline struct fimd_driver_data *drm_fimd_get_driver_data(
>>> struct platform_device *pdev)
>>> {
>>> @@ -133,6 +139,41 @@ static inline struct fimd_driver_data
>>> *drm_fimd_get_driver_data(
>>> platform_get_device_id(pdev)->driver_data;
>>> }
>>>
>>> +static struct mie_bypass *parse_mie_bypass_for_fimd(struct device *dev,
>>> + struct device_node
>>> *mie_bypass_node)
>>> +{
>>> + struct mie_bypass *bypass_data;
>>> + u32 phy_address;
>>> +
>>> + bypass_data = devm_kzalloc(dev, sizeof(*bypass_data),
>>> GFP_KERNEL);
>>> + if (!bypass_data) {
>>> + dev_err(dev, "memory allocation for bypass data
>>> failed\n");
>>> + return ERR_PTR(-ENOMEM);
>>> + }
>>> + of_property_read_u32(mie_bypass_node,
>>> "samsung,mie-bypass-enable",
>>> + &bypass_data->enable_bypass);
>>> + of_property_read_u32(mie_bypass_node, "samsung,disp1blk-cfg-reg",
>>> + &phy_address);
>>> + of_property_read_u32(mie_bypass_node,
>>> "samsung,bypass-bit-offset",
>>> + &bypass_data->bypass_bit_offset);
>>> +
>>> + bypass_data->bypass_reg = ioremap(phy_address, SZ_4);
>>>
>>> + if (!bypass_data->bypass_reg) {
>>> + dev_err(dev, "failed to ioremap phy_address\n");
>>> + return ERR_PTR(-ENOMEM);
>>> + }
>>> + return bypass_data;
>>> +}
>>>
>>> +
>>> +static void mie_bypass_for_fimd(struct mie_bypass *bypass_data)
>>> +{
>>> + u32 reg;
>>> +
>>> + reg = __raw_readl(bypass_data->bypass_reg);
>>> + reg |= (1 << bypass_data->bypass_bit_offset);
>>> + __raw_writel(reg, bypass_data->bypass_reg);
>>> +}
>>> +
>>> static bool fimd_display_is_connected(struct device *dev)
>>> {
>>> DRM_DEBUG_KMS("%s\n", __FILE__);
>>> @@ -906,12 +947,26 @@ static int __devinit fimd_probe(struct
>>> platform_device *pdev)
>>> struct exynos_drm_fimd_pdata *pdata;
>>> struct exynos_drm_panel_info *panel;
>>> struct resource *res;
>>> + struct device_node *mie_bypass_node;
>>> + struct mie_bypass *bypass_data = NULL;
>>> int win;
>>> int ret = -EINVAL;
>>>
>>> DRM_DEBUG_KMS("%s\n", __FILE__);
>>>
>>> pdata = pdev->dev.platform_data;
>>> + if (pdev->dev.of_node) {
>>> + mie_bypass_node = of_find_node_by_name(pdev->dev.of_node,
>>> + "mie-bypass");
>>> + if (mie_bypass_node) {
>>> +
Re: [PATCH] video: drm: exynos: mie bypass enable for fimd
Hello Inki Dae,
On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote:
>
> Hi,
>
> DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So
> it's not good that this register is controlled in fimd module. And I think
> the function to control the register should be placed in SoC common file .
> In other words, other drivers should be able to control the register through
> common thing also.
>
Thanks for reviewing the patch.
You mean to say that this functionality should be implemented at arch side
and called by drivers using call back functions ?
If so, then if we moved the driver to full DT version, all the call
backs will be removed.
Then how to make a call to this function?
So I thought other drivers (apart from Fimd) also parses the
appropriate nodes and
program the register as per the need.
Please correct me if my understanding is wrong.
Best Wishes,
Leela Krishna Amudala.
> Thanks,
> Inki Dae
>
> 2012/12/26 Leela Krishna Amudala
>>
>> Bypasses the mie for fimd by parsing the register and bit offset values
>> from "mie-bypass" node, if "mie-bypass" node is present in the dts file.
>>
>> Signed-off-by: Leela Krishna Amudala
>> ---
>> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 55
>>
>> 1 file changed, 55 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> index bf0d9ba..f8ad259 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> @@ -118,6 +118,12 @@ static const struct of_device_id
>> fimd_driver_dt_match[] = {
>> MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
>> #endif
>>
>> +struct mie_bypass {
>> + u32 enable_bypass;
>> + void __iomem*bypass_reg;
>> + u32 bypass_bit_offset;
>> +};
>> +
>> static inline struct fimd_driver_data *drm_fimd_get_driver_data(
>> struct platform_device *pdev)
>> {
>> @@ -133,6 +139,41 @@ static inline struct fimd_driver_data
>> *drm_fimd_get_driver_data(
>> platform_get_device_id(pdev)->driver_data;
>> }
>>
>> +static struct mie_bypass *parse_mie_bypass_for_fimd(struct device *dev,
>> + struct device_node
>> *mie_bypass_node)
>> +{
>> + struct mie_bypass *bypass_data;
>> + u32 phy_address;
>> +
>> + bypass_data = devm_kzalloc(dev, sizeof(*bypass_data),
>> GFP_KERNEL);
>> + if (!bypass_data) {
>> + dev_err(dev, "memory allocation for bypass data
>> failed\n");
>> + return ERR_PTR(-ENOMEM);
>> + }
>> + of_property_read_u32(mie_bypass_node,
>> "samsung,mie-bypass-enable",
>> + &bypass_data->enable_bypass);
>> + of_property_read_u32(mie_bypass_node, "samsung,disp1blk-cfg-reg",
>> + &phy_address);
>> + of_property_read_u32(mie_bypass_node,
>> "samsung,bypass-bit-offset",
>> + &bypass_data->bypass_bit_offset);
>> +
>> + bypass_data->bypass_reg = ioremap(phy_address, SZ_4);
>>
>> + if (!bypass_data->bypass_reg) {
>> + dev_err(dev, "failed to ioremap phy_address\n");
>> + return ERR_PTR(-ENOMEM);
>> + }
>> + return bypass_data;
>> +}
>>
>> +
>> +static void mie_bypass_for_fimd(struct mie_bypass *bypass_data)
>> +{
>> + u32 reg;
>> +
>> + reg = __raw_readl(bypass_data->bypass_reg);
>> + reg |= (1 << bypass_data->bypass_bit_offset);
>> + __raw_writel(reg, bypass_data->bypass_reg);
>> +}
>> +
>> static bool fimd_display_is_connected(struct device *dev)
>> {
>> DRM_DEBUG_KMS("%s\n", __FILE__);
>> @@ -906,12 +947,26 @@ static int __devinit fimd_probe(struct
>> platform_device *pdev)
>> struct exynos_drm_fimd_pdata *pdata;
>> struct exynos_drm_panel_info *panel;
>> struct resource *res;
>> + struct device_node *mie_bypass_node;
>> + struct mie_bypass *bypass_data = NULL;
>> int win;
>> int ret = -EINVAL;
>>
>> DRM_DEBUG_KMS("%s\n", __FILE__);
>>
>> pdata = pdev->dev.platform_data;
>> + if (pdev->dev.of_node) {
>> + mie_bypass_node = of_find_node_by_name(pdev->dev.of_node,
>> + "mie-bypass");
>> + if (mie_bypass_node) {
>> + bypass_data =
>> parse_mie_bypass_for_fimd(&pdev->dev,
>> + mie_bypass_node);
>>
>> + if (IS_ERR(bypass_data))
>> + return PTR_ERR(bypass_data);
>> + if (bypass_data->enable_bypass)
>> + mie_bypass_for_fimd(bypass_data);
>> + }
>> + }
>> if (!pdata) {
>> dev_err(dev, "no platform data specified\n");
>> return -EINVAL;
Re: [PATCH 2/2] i2c-exynos5: add debugfs support for registers
On Tue, Dec 25, 2012 at 04:55:55PM +0530, Naveen Krishna Chatradhi wrote:
> This patch replaces the dev_vdbg with debugfs function calls
> in i2c-exynos5.c driver.
>
> Signed-off-by: Naveen Krishna Chatradhi
> ---
> Changes since v1:
> The debugfs implementation is a suggestion by Felipe Balbi.
> Its not tested, Implemented only for review purpose..
>
> drivers/i2c/busses/i2c-exynos5.c | 140
> +-
> 1 file changed, 109 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-exynos5.c
> b/drivers/i2c/busses/i2c-exynos5.c
> index 7614f60..2d2da22 100644
> --- a/drivers/i2c/busses/i2c-exynos5.c
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -12,6 +12,7 @@
>
> #include
> #include
> +#include
>
> #include
> #include
> @@ -55,6 +56,7 @@ struct exynos5_i2c {
>
> int bus_num;
> int speed_mode;
> + struct dentry *debugfs_root;
> };
>
> static const struct of_device_id exynos5_i2c_match[] = {
> @@ -63,39 +65,112 @@ static const struct of_device_id exynos5_i2c_match[] = {
> };
> MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
>
> -/* TODO: Should go to debugfs */
> -static inline void dump_i2c_register(struct exynos5_i2c *i2c)
> +static int exynos5_i2c_regs_show(struct seq_file *s, void *data)
> {
> - dev_vdbg(i2c->dev, "Register dump(%d) :\n %x\n %x\n %x\n %x\n"
> - " %x\n %x\n %x\n %x\n %x\n"
> - " %x\n %x\n %x\n %x\n %x\n"
> - " %x\n %x\n %x\n %x\n %x\n"
> - " %x\n %x\n %x\n %x\n %x\n",
> - i2c->suspended,
> - readl(i2c->regs + HSI2C_CTL),
> - readl(i2c->regs + HSI2C_FIFO_CTL),
> - readl(i2c->regs + HSI2C_TRAILIG_CTL),
> - readl(i2c->regs + HSI2C_CLK_CTL),
> - readl(i2c->regs + HSI2C_CLK_SLOT),
> - readl(i2c->regs + HSI2C_INT_ENABLE),
> - readl(i2c->regs + HSI2C_INT_STATUS),
> - readl(i2c->regs + HSI2C_ERR_STATUS),
> - readl(i2c->regs + HSI2C_FIFO_STATUS),
> - readl(i2c->regs + HSI2C_TX_DATA),
> - readl(i2c->regs + HSI2C_RX_DATA),
> - readl(i2c->regs + HSI2C_CONF),
> - readl(i2c->regs + HSI2C_AUTO_CONF),
> - readl(i2c->regs + HSI2C_TIMEOUT),
> - readl(i2c->regs + HSI2C_MANUAL_CMD),
> - readl(i2c->regs + HSI2C_TRANS_STATUS),
> - readl(i2c->regs + HSI2C_TIMING_HS1),
> - readl(i2c->regs + HSI2C_TIMING_HS2),
> - readl(i2c->regs + HSI2C_TIMING_HS3),
> - readl(i2c->regs + HSI2C_TIMING_FS1),
> - readl(i2c->regs + HSI2C_TIMING_FS2),
> - readl(i2c->regs + HSI2C_TIMING_FS3),
> - readl(i2c->regs + HSI2C_TIMING_SLA),
> + struct exynos5_i2c *i2c = (struct exynos5_i2c *)s->private;
> +
> + if (i2c->suspended) {
> + seq_printf(s, "i2c suspended, can't read registers\n");
> + return 0;
> + }
> +
> + pm_runtime_get_sync(i2c->dev);
> +
> + seq_printf(s, "CTL:\t\t0x%08x\n",
> + readl(i2c->regs + HSI2C_CTL));
BTW, there is a generic regdump debugfs interface nowadays, please use
that instead (look for debugfs_create_regset32)
--
balbi
signature.asc
Description: Digital signature
Re: [PATCH 1/2] i2c: exynos5: add High Speed I2C controller driver
Hi,
On Tue, Dec 25, 2012 at 04:55:54PM +0530, Naveen Krishna Chatradhi wrote:
> Adds support for High Speed I2C driver found in Exynos5 and later
> SoCs from Samsung. This driver currently supports Auto mode.
>
> Driver only supports Device Tree method.
>
> Signed-off-by: Taekgyun Ko
> Signed-off-by: Naveen Krishna Chatradhi
> ---
> Changes since v1:
> Fixed the comments from Felipe Balbi and Thomas Abraham.
>
> drivers/i2c/busses/Kconfig |7 +
> drivers/i2c/busses/Makefile |1 +
> drivers/i2c/busses/i2c-exynos5.c | 652
> ++
> drivers/i2c/busses/i2c-exynos5.h | 102 ++
> 4 files changed, 762 insertions(+)
> create mode 100644 drivers/i2c/busses/i2c-exynos5.c
> create mode 100644 drivers/i2c/busses/i2c-exynos5.h
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index bdca511..4caea76 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -618,6 +618,13 @@ config I2C_S3C2410
> Say Y here to include support for I2C controller in the
> Samsung SoCs.
>
> +config I2C_EXYNOS5
> + tristate "Exynos5 high-speed I2C driver"
> + depends on ARCH_EXYNOS5
> + help
> + Say Y here to include support for High-speed I2C controller in the
> + Exynos5 based Samsung SoCs.
> +
> config I2C_S6000
> tristate "S6000 I2C support"
> depends on XTENSA_VARIANT_S6000
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 6181f3f..4b1548c 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -61,6 +61,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
> obj-$(CONFIG_I2C_PXA)+= i2c-pxa.o
> obj-$(CONFIG_I2C_PXA_PCI)+= i2c-pxa-pci.o
> obj-$(CONFIG_I2C_S3C2410)+= i2c-s3c2410.o
> +obj-$(CONFIG_I2C_EXYNOS5)+= i2c-exynos5.o
> obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
> obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
> obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
> diff --git a/drivers/i2c/busses/i2c-exynos5.c
> b/drivers/i2c/busses/i2c-exynos5.c
> new file mode 100644
> index 000..7614f60
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -0,0 +1,652 @@
> +/* linux/drivers/i2c/busses/i2c-exynos5.c
no need for the full path. Generally this would look like:
* i2c-exynos5.c - Samsung Exynos 5 I2C Controller Driver
no strong feelings however.
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + *
> + * High speed I2C controller driver
> + * for Exynos5 and later SoCs from Samsung.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "i2c-exynos5.h"
it doesn't look like this header is even needed. All those macros could
be defined here in the C-source file which is the only user.
> +#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
> +
> +/* timeout for pm runtime autosuspend */
> +#define EXYNOS5_I2C_PM_TIMEOUT 1000/* ms */
> +
> +struct exynos5_i2c {
> + struct i2c_adapter adap;
> + unsigned intsuspended:1;
> +
> + struct i2c_msg *msg;
> + unsigned intmsg_idx;
> + struct completion msg_complete;
> + unsigned intmsg_ptr;
> +
> + unsigned intirq;
> +
> + void __iomem*regs;
> + struct clk *clk;
> + struct device *dev;
> + int gpios[2];
> +
> + int bus_num;
> + int speed_mode;
> +};
> +
> +static const struct of_device_id exynos5_i2c_match[] = {
> + { .compatible = "samsung,exynos5-hsi2c" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
> +
> +/* TODO: Should go to debugfs */
> +static inline void dump_i2c_register(struct exynos5_i2c *i2c)
> +{
> + dev_vdbg(i2c->dev, "Register dump(%d) :\n %x\n %x\n %x\n %x\n"
> + " %x\n %x\n %x\n %x\n %x\n"
> + " %x\n %x\n %x\n %x\n %x\n"
> + " %x\n %x\n %x\n %x\n %x\n"
> + " %x\n %x\n %x\n %x\n %x\n",
> + i2c->suspended,
> + readl(i2c->regs + HSI2C_CTL),
> + readl(i2c->regs + HSI2C_FIFO_CTL),
> + readl(i2c->regs + HSI2C_TRAILIG_CTL),
> + readl(i2c->regs + HSI2C_CLK_CTL),
> + readl(i2c->regs + HSI2C_CLK_SLOT),
> + readl(i2c->regs + HSI2C_INT_ENABLE),
> + readl(i2c->regs + HSI2C_INT_STATUS),
> + readl(i2c->regs + HSI2C_ERR_STATUS),
> + readl(i2c->regs + HSI2C_FIFO_STATUS),
> +
Re: [PATCH 2/2] i2c-exynos5: add debugfs support for registers
On Tue, Dec 25, 2012 at 04:55:55PM +0530, Naveen Krishna Chatradhi wrote: > This patch replaces the dev_vdbg with debugfs function calls > in i2c-exynos5.c driver. > > Signed-off-by: Naveen Krishna Chatradhi merge with previous -- balbi signature.asc Description: Digital signature
RE: [PATCH] ARM: EXYNOS4: Add support for rtc wakeup
Inderpal Singh wrote: > > Set the gic arch extension callback to support rtc wakeup. > > Signed-off-by: Inderpal Singh > --- > arch/arm/mach-exynos/common.c |2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach- > exynos/common.c > index 578a610..bf2ee1d 100644 > --- a/arch/arm/mach-exynos/common.c > +++ b/arch/arm/mach-exynos/common.c > @@ -747,6 +747,8 @@ void __init exynos4_init_irq(void) >* uses GIC instead of VIC. >*/ > s5p_init_irq(NULL, 0); > + > + gic_arch_extn.irq_set_wake = s3c_irq_wake; > } > > void __init exynos5_init_irq(void) > -- > 1.7.9.5 Applied, thanks - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] ARM: exynos: Revise HDMI resource size
Prathyush K wrote:
>
> From: Sean Paul
>
> Reduce the HDMI resource size from 0x10 to 0x7 so it
> doesn't overlap the Displayport resource space.
> HDMI: (0x1453 - 0x145A
> DP: (0x145B - 0x145B1000)
>
> Signed-off-by: Sean Paul
> Signed-off-by: Prathyush K
> ---
> arch/arm/boot/dts/exynos5250.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index 45799e8..30485de 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -580,7 +580,7 @@
>
> hdmi {
> compatible = "samsung,exynos5-hdmi";
> - reg = <0x1453 0x10>;
> + reg = <0x1453 0x7>;
> interrupts = <0 95 0>;
> };
>
> --
> 1.8.0
Yes, applied, thanks.
- Kukjin
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[PATCH] ARM: EXYNOS: fix uncompress.h and debug-macro.S for EXYNOS5440
This patch fixes uart base address for uncompress and debug-macro on EXYNOS5440. Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/debug-macro.S | 25 +-- arch/arm/mach-exynos/include/mach/map.h |1 + arch/arm/mach-exynos/include/mach/uncompress.h | 20 +++--- 3 files changed, 33 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S index e0c86ea..69e3e52 100644 --- a/arch/arm/mach-exynos/include/mach/debug-macro.S +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S @@ -21,12 +21,25 @@ */ .macro addruart, rp, rv, tmp - mrc p15, 0, \tmp, c0, c0, 0 - and \tmp, \tmp, #0xf0 - teq \tmp, #0xf0 @@ A15 - ldreq \rp, =EXYNOS5_PA_UART - movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4 - ldr \rv, =S3C_VA_UART + mov \rp, #0x1000 + ldr \rp, [\rp, #0] + and \rp, \rp, #0x0ff0 + teq \rp, #0x0320@ EXYNOS4210, EXYNOS4212 + beq 4f + teq \rp, #0x0440@ EXYNOS4412 + beq 4f + teq \rp, #0x0350@ EXYNOS5250 + beq 5f + b 54f + +4: mov \rp, #EXYNOS4_PA_UART + b 99f +5: mov \rp, #EXYNOS5_PA_UART + b 99f +54:mov \rp, #EXYNOS5440_PA_UART + b 99f +99:ldr \rv, =S3C_VA_UART + #if CONFIG_DEBUG_S3C_UART != 0 add \rp, \rp, #(0x1 * CONFIG_DEBUG_S3C_UART) add \rv, \rv, #(0x1 * CONFIG_DEBUG_S3C_UART) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 1df6abb..cba083e 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -203,6 +203,7 @@ #define EXYNOS4_PA_UART0x1380 #define EXYNOS5_PA_UART0x12C0 +#define EXYNOS5440_PA_UART 0x000B #define EXYNOS4_PA_VP 0x12C0 #define EXYNOS4_PA_MIXER 0x12C1 diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h index 2979995..ace9be2 100644 --- a/arch/arm/mach-exynos/include/mach/uncompress.h +++ b/arch/arm/mach-exynos/include/mach/uncompress.h @@ -31,16 +31,22 @@ static void arch_detect_cpu(void) /* * product_id is bits 31:12 -*bits 23:20 describe the exynosX family -* +*bits 27:20 describe the exynosX family */ chip_id >>= 20; - chip_id &= 0xf; - - if (chip_id == 0x5) - uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); + chip_id &= 0xff; + + if (chip_id == 0x32 || chip_id == 0x44) + /* EXYNOS4210, EXYNOS4212 and EXYNOS4412 */ + uart_base = (volatile u8 *)EXYNOS4_PA_UART; + else if (chip_id == 0x35) + /* EXYNOS5250 */ + uart_base = (volatile u8 *)EXYNOS5_PA_UART; else - uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT); + /* EXYNOS5440 */ + uart_base = (volatile u8 *)EXYNOS5440_PA_UART; + + uart_base += S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT; /* * For preventing FIFO overrun or infinite loop of UART console, -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: SAMSUNG: fix the cpu id for EXYNOS5440
The value of CPU ID for EXYNOS5440 should be 0xE544. Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/include/plat/cpu.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index e0072ce..b69e11d 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -43,7 +43,7 @@ extern unsigned long samsung_cpu_id; #define EXYNOS4_CPU_MASK 0xFFFE #define EXYNOS5250_SOC_ID 0x4352 -#define EXYNOS5440_SOC_ID 0x5440 +#define EXYNOS5440_SOC_ID 0xE544 #define EXYNOS5_SOC_MASK 0xF000 #define IS_SAMSUNG_CPU(name, id, mask) \ -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: use uart port0 for console on exynos5440-ssdk5440
Signed-off-by: Kukjin Kim
---
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 921c83c..81e2c96 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -21,7 +21,7 @@
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x8100,8M
console=ttySAC2,115200 init=/linuxrc";
+ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x8100,8M
console=ttySAC0,115200 init=/linuxrc";
};
spi {
--
1.7.10.4
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[PATCH] ARM: dts: use uart port1 for console on exynos4210-smdkv310
Signed-off-by: Kukjin Kim
---
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 9b23a82..f634907 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -26,7 +26,7 @@
};
chosen {
- bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc";
+ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC1,115200 init=/linuxrc";
};
sdhci@1253 {
--
1.7.4.1
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[PATCH] ARM: EXYNOS: enable PINCTRL for EXYNOS5440
This patch removes following warning in kernel boot log, Because EXYNOS5440 can support only Pinctrl not GPIO. WARNING: at drivers/gpio/gpio-samsung.c:3102 samsung_gpiolib_init+0x68/0x8c() Unknown SoC in gpio-samsung, no GPIOs added Cc: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 91d5b6f..e103c29 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -74,6 +74,8 @@ config SOC_EXYNOS5440 depends on ARCH_EXYNOS5 select ARM_ARCH_TIMER select AUTO_ZRELADDR + select PINCTRL + select PINCTRL_EXYNOS5440 help Enable EXYNOS5440 SoC support -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] pinctrl: samsung: removing duplicated condition for PINCTRL_SAMSUNG
Now, PINCTRL_SAMSUNG should be enabled with PINCTRL_EXYNOS so we don't need to add 'depends on' condition already added in PINCTRL_EXYNOS. Cc: Thomas Abraham Signed-off-by: Kukjin Kim --- drivers/pinctrl/Kconfig |1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c31aeb0..efaecef 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -181,7 +181,6 @@ config PINCTRL_COH901 config PINCTRL_SAMSUNG bool - depends on OF && GPIOLIB select PINMUX select PINCONF -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] gpio: samsung: silent build warning for EXYNOS5 SoCs
This patch fixes following warning:
drivers/gpio/gpio-samsung.c:450:32: warning: 'exynos_gpio_cfg' defined but not
used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2450:33: warning: 'exynos5_gpios_1' defined but not
used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2618:33: warning: 'exynos5_gpios_2' defined but not
used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2679:33: warning: 'exynos5_gpios_3' defined but not
used [-Wunused-variable]
drivers/gpio/gpio-samsung.c:2715:33: warning: 'exynos5_gpios_4' defined but not
used [-Wunused-variable]
Because current gpio-samsung is valid only on EXYNOS5250.
Cc: Thomas Abraham
Signed-off-by: Kukjin Kim
---
drivers/gpio/gpio-samsung.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index f890ea5..cce8edc 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -446,7 +446,7 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
};
#endif
-#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
static struct samsung_gpio_cfg exynos_gpio_cfg = {
.set_pull = exynos_gpio_setpull,
.get_pull = exynos_gpio_getpull,
@@ -2446,7 +2446,7 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
};
#endif
-#ifdef CONFIG_ARCH_EXYNOS5
+#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_1[] = {
{
.chip = {
@@ -2614,7 +2614,7 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
};
#endif
-#ifdef CONFIG_ARCH_EXYNOS5
+#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_2[] = {
{
.chip = {
@@ -2675,7 +2675,7 @@ static struct samsung_gpio_chip exynos5_gpios_2[] = {
};
#endif
-#ifdef CONFIG_ARCH_EXYNOS5
+#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_3[] = {
{
.chip = {
@@ -2711,7 +2711,7 @@ static struct samsung_gpio_chip exynos5_gpios_3[] = {
};
#endif
-#ifdef CONFIG_ARCH_EXYNOS5
+#ifdef CONFIG_SOC_EXYNOS5250
static struct samsung_gpio_chip exynos5_gpios_4[] = {
{
.chip = {
--
1.7.10.4
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[PATCH] gpio: samsung: fix pinctrl condition for exynos and exynos5440
Since EXYNOS5440 can select PINCTRL_EXYNOS5440 without PINCTRL_SAMSUNG, it should be fixed. In detail, PINCTRL_SAMSUNG is a kind of frame work for supporting pinctrl on most Samsung SoCs including S3C, S5P as well except EXYNOS5440 so PINCTRL_EXYNOS5440 has been implemented separated. Cc: Thomas Abraham Signed-off-by: Kukjin Kim --- drivers/gpio/gpio-samsung.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index 365ecce..509c08c 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -3010,7 +3010,7 @@ static __init int samsung_gpiolib_init(void) int i, nr_chips; int group = 0; -#ifdef CONFIG_PINCTRL_SAMSUNG +#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440) /* * This gpio driver includes support for device tree support and there * are platforms using it. In order to maintain compatibility with those -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/3] pinctrl: exynos: add exynos5250 SoC specific data
Thomas Abraham wrote: > > Hi Linus, > > On 14 December 2012 21:21, Linus Walleij wrote: > > On Thu, Dec 13, 2012 at 12:54 PM, Thomas Abraham > > wrote: > > > >> Add Samsung Exynos5250 SoC specific data to enable pinctrl support for > >> all platforms based on Exynos5250. > >> > >> Signed-off-by: Thomas Abraham > > > > Acked-by: Linus Walleij > > > > For this series, I guess you'll fix it through the Samsung tree? > > Thanks for your ack. Since there are patches to be prepared for > migrating the rest of Exynos5250 related code to the pinctrl > framework, it would be easier if this series goes through the Samsung > tree. > I applied this series, thanks. And I think, would be clear if the config could be changed like following. 8<-- From: Kukjin Kim Subject: [PATCH] pinctrl: exynos: change PINCTRL_EXYNOS option Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham Cc: Linus Walleij Cc: Grant Likely Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 91d5b6f..e1f63e7 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -412,7 +412,7 @@ config MACH_EXYNOS4_DT select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL - select PINCTRL_EXYNOS4 + select PINCTRL_EXYNOS select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c31aeb0..f59feab 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -185,8 +185,8 @@ config PINCTRL_SAMSUNG select PINMUX select PINCONF -config PINCTRL_EXYNOS4 - bool "Pinctrl driver data for Exynos4 SoC" +config PINCTRL_EXYNOS + bool "Pinctrl driver data for Samsung EXYNOS SoCs" depends on OF && GPIOLIB select PINCTRL_SAMSUNG diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fc4606f..6e87e52 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o -obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o +obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 8<-- - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V5 2/2] ASoC: SAMSUNG: Add DT support for i2s
On Wed, Dec 26, 2012 at 04:21:58PM +0530, Padma Venkat wrote: > Hi, > > On Mon, Dec 24, 2012 at 9:33 AM, Padma Venkat wrote: > > Hi, You should always delete irrelevant text from mails, it makes it much easier for people to find whatever content you've added. > >> I agree with using version here but we need some consensus about that. > Any suggestions on i2s compatible name or "samsung,i2s-v5" is okay? I think that's fine. signature.asc Description: Digital signature
Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Prasanna,
On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
> This patch adds a software workaround to the hardware
> problem found in exynos5 while powergating.
>
> It is observed that CLK_TOP_SRC3 register gets modified if
> the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> set to XXTI which results in the device running very slow .
> A big drop in performance is noticed whilerunning the video.
> This issue also occurs while powergating MFC.
>
> The value of clock source register is restored once the powergating
> operation is completed.
>
> Signed-off-by: Prasanna Kumar
> ---
> arch/arm/mach-exynos/pm_domains.c | 27 +++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/pm_domains.c
> b/arch/arm/mach-exynos/pm_domains.c index 9f1351d..bd8a41e 100644
> --- a/arch/arm/mach-exynos/pm_domains.c
> +++ b/arch/arm/mach-exynos/pm_domains.c
> @@ -24,6 +24,8 @@
>
> #include
> #include
> +#include
> +#include
>
> /*
> * Exynos specific wrapper around the generic power domain
> @@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain
> *domain, bool power_on) void __iomem *base;
> u32 timeout, pwr;
> char *op;
> + u32 tmp = 0;
> +
> + /*
> + *It is found that the CLK SRC register in exynos5
> + *gets modified when power domain of gsc/mfc/isp/disp1
> + *is powered off.This happens only after the system is
> + *suspended and resumed and not before that.
> + *The following fix adresses this hardware issue.
> + *It saves the value of clock source register and
> + *resores it later
> + */
> +
> + if (of_machine_is_compatible("samsung,exynos5250")) {
> + if (!power_on) {
> + /* save clock source register */
> + tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
I really think this problem needs more investigation, but if gating
a power domain can really change a clock source register and save/restore
when gating is really required, then the code must be reworked so it does
not access clock registers directly.
At the moment it is not a problem, but we are going to have Exynos support
for Common Clock Framework merged in near future and it will remove static
mapping of clock registers.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform
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Re: [PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating
Hi Thomas,
On Tuesday 04 of December 2012 14:29:24 Thomas Abraham wrote:
> On 27 November 2012 17:52, Prasanna Kumar
wrote:
> > From: Prasanna Kumar
> >
> > This patch adds a software workaround to the hardware
> > problem found in exynos5 while powergating.
> >
> > It is observed that CLK_TOP_SRC3 register gets modified if
> > the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
> > set to XXTI which results in the device running very slow .
> > A big drop in performance is noticed whilerunning the video.
> > This issue also occurs while powergating MFC.
> >
> > The value of clock source register is restored once the powergating
> > operation is completed.
> >
> > Signed-off-by: Prasanna Kumar
> > ---
> >
> > arch/arm/mach-exynos/pm_domains.c | 27 +++
> > 1 files changed, 27 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/pm_domains.c
> > b/arch/arm/mach-exynos/pm_domains.c index 9f1351d..955cbe3 100644
> > --- a/arch/arm/mach-exynos/pm_domains.c
> > +++ b/arch/arm/mach-exynos/pm_domains.c
> > @@ -24,6 +24,8 @@
> >
> > #include
> > #include
> >
> > +#include
> > +#include
> >
> > /*
> >
> > * Exynos specific wrapper around the generic power domain
> >
> > @@ -41,6 +43,7 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)>
> > void __iomem *base;
> > u32 timeout, pwr;
> > char *op;
> >
> > + u32 tmp = 0;
> >
> > pd = container_of(domain, struct exynos_pm_domain, pd);
> > base = pd->base;
> >
> > @@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)>
> > pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
> > __raw_writel(pwr, base);
> >
> > + /*
> > +*It is found that the CLK SRC register in exynos5
> > +*gets modified when power domain of gsc/mfc/isp/disp1
> > +*is powered off.This happens only after the system is
> > +*suspended and resumed and not before that.
> > +*The following fix adresses this hardware issue.
> > +*It saves the value of clock source register and
> > +*resores it later
> > +*/
> > +
> > + if (soc_is_exynos5250()) {
> > + if (!power_on) {
> > + /* save clock source register */
> > + tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
> > + }
> > + }
>
> Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the
> G-Scaler/MFC devices are power gated?
>
> - If yes, the value of CLKSRC register should be saved before the
> power domain register is programmed.
>
> - If not, as mentioned in the comment, if this issue occurs during a
> suspend-resume cycle, the value of this register can be saved and
> restored in the clock driver code itself.
>
> The other thing that needs to be relooked into here is the use of
> EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers
> are statically io-remapped. With the upcoming migration to common
> clock for Exynos5, the clock registers will not be statically
> io-remapped but instead remapped during clock initialization. So the
> use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into
> this.
>
> > +
> >
> > /* Wait max 1ms */
> > timeout = 10;
> >
> > @@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain
> > *domain, bool power_on)>
> > cpu_relax();
> > usleep_range(80, 100);
> >
> > }
> >
> > +
> > + if (soc_is_exynos5250()) {
>
> We could use the of_machine_is_compatible api here instead of
> soc_is_exynos5250() macro.
I don't think that of_machine_is_compatible() is preferred over
soc_is_xxx(). The former has dependencies on OF support and requires
a string comparison, while the latter is just a single integer check.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
SW Solution Development, Linux Platform
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Re: [PATCH 2/2] USB: ehci-s5p: Add to get interrupt from DT
Hi Sergei,
Yes, you are right.
I made this patch to read its interrupt number from dtb directly. But
now platform_get_irq() returns correct irq since "OF_DEV_AUXDATA(...)"
is added as my first patch.
This patch is useless.
Thanks and best regards,
Dongjin.
On Thu, Dec 27, 2012 at 5:18 AM, Sergei Shtylyov wrote:
>
> Hello.
>
> On 12/26/2012 09:42 PM, Dongjin Kim wrote:
>
> > This patch support to get interrupt resource from device tree as well as
> > platform device if ehci node is defined in device tree and it's irq is
> > described.
>
> > Signed-off-by: Dongjin Kim
> > ---
> > drivers/usb/host/ehci-s5p.c |8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
>
> > diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
> > index 319dcfa..0fc5e5e 100644
> > --- a/drivers/usb/host/ehci-s5p.c
> > +++ b/drivers/usb/host/ehci-s5p.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -156,7 +157,12 @@ static int s5p_ehci_probe(struct platform_device
> > *pdev)
> > goto fail_io;
> > }
> >
> > - irq = platform_get_irq(pdev, 0);
> > + if (pdev->dev.of_node)
> > + irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
>
>platform_get_irq() should still work for device tree based platform
> devices.
> I don't see the point on the patch?
>
> > + else {
> > + irq = platform_get_irq(pdev, 0);
> > + }
>
>Hm, why {} out of the blue? Both arms of *if* are single-stratement.
>
> > +
>
>No need for empty line here.
>
> > if (!irq) {
> > dev_err(&pdev->dev, "Failed to get IRQ\n");
> > err = -ENODEV;
>
> WBR, Sergei
>
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Re: [PATCH v4] usb: phy: samsung: Add support to set pmu isolation
Hi Sylwester,
On Thu, Dec 27, 2012 at 4:00 AM, Sylwester Nawrocki
wrote:
> On 12/26/2012 01:28 PM, Vivek Gautam wrote:
>>
>> Adding support to parse device node data in order to get
>> required properties to set pmu isolation for usb-phy.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>> .../devicetree/bindings/usb/samsung-usbphy.txt | 31
>> drivers/usb/phy/samsung-usbphy.c | 145
>> +---
>> 2 files changed, 155 insertions(+), 21 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> index 7b26e2d..6b873fd 100644
>> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -9,3 +9,34 @@ Required properties:
>> - compatible : should be "samsung,exynos4210-usbphy"
>> - reg : base physical address of the phy registers and length of memory
>> mapped
>> region.
>> +
>> +Optional properties:
>> +- #address-cells: should be '1' when usbphy node has a child node with
>> 'reg'
>> + property.
>> +- #size-cells: should be '1' when usbphy node has a child node with 'reg'
>> + property.
>> +
>> +- The child node 'usbphy-pmu' to the node usbphy should provide the
>> following
>> + information required by usb-phy controller to enable/disable the phy.
>> + - reg : base physical address of PHY control register in PMU which
>> + enables/disables the phy controller.
>> + The size of this register is the total sum of size of all
>> phy-control
>> + registers that the SoC has. For example, the size will be
>> + '0x4' in case we have only one phy-control register (like in
>> S3C64XX) or
>> + '0x8' in case we have two phy-control registers (like in
>> Exynos4210)
>> + and so on.
>> +
>> +Example:
>> + - Exysno4210
>
>
> s/Exysno/Exynos
>
Sure will amend this.
>
>> +
>> + usbphy@125B {
>> + #address-cells =<1>;
>> + #size-cells =<1>;
>> + compatible = "samsung,exynos4210-usbphy";
>> + reg =<0x125B 0x100>;
>> +
>> + usbphy-pmu {
>> + /* USB device and host PHY_CONTROL registers */
>> + reg =<0x10020704 0x8>;
>> + };
>> + };
>> diff --git a/drivers/usb/phy/samsung-usbphy.c
>> b/drivers/usb/phy/samsung-usbphy.c
>> index 5c5e1bb5..b9f4f42 100644
>> --- a/drivers/usb/phy/samsung-usbphy.c
>> +++ b/drivers/usb/phy/samsung-usbphy.c
>> @@ -60,20 +60,42 @@
>> #define MHZ (1000*1000)
>> #endif
>>
>> +#define S3C64XX_USBPHY_ENABLE (0x1<< 16)
>> +#define EXYNOS_USBPHY_ENABLE (0x1<< 0)
>> +
>> enum samsung_cpu_type {
>> TYPE_S3C64XX,
>> TYPE_EXYNOS4210,
>> };
>>
>> /*
>> + * struct samsung_usbphy_drvdata - driver data for various SoC variants
>> + * @cpu_type: machine identifier
>> + * @devphy_en_mask: device phy enable mask for PHY CONTROL register
>> + *
>> + * Here we have a separate mask for device type phy.
>> + * Having different masks for host and device type phy helps
>> + * in setting independent masks in case of SoCs like S5PV210,
>> + * in which PHY0 and PHY1 enable bits belong to same register
>> + * placed at [0] and [1] respectively.
>
>
> "and are placed at positions 0 and 1 respectively" ?
>
Ok, will change this.
>
>> + * Although for newer SoCs like exynos these bits belong to
>> + * different registers altogether placed at [0].
>> + */
>> +struct samsung_usbphy_drvdata {
>> + int cpu_type;
>> + int devphy_en_mask;
>> +};
>> +
>> +/*
>>* struct samsung_usbphy - transceiver driver state
>>* @phy: transceiver structure
>>* @plat: platform data
>>* @dev: The parent device supplied to the probe function
>>* @clk: usb phy clock
>>* @regs: usb phy register memory base
>> + * @phyctrl_pmureg: usb device phy-control pmu register memory base
>
>
> nit: Perhaps we could just call it "pmureg' ?
>
Sure we can use the name 'pmureg'.
>
>>* @ref_clk_freq: reference clock frequency selection
>> - * @cpu_type: machine identifier
>> + * @drv_data: driver data available for different cpu types
>
>
> Actually it's for different SoCs, not CPUs, right ?
>
Right, will change this.
>
>>*/
>> struct samsung_usbphy {
>> struct usb_phy phy;
>> @@ -81,12 +103,67 @@ struct samsung_usbphy {
>> struct device *dev;
>> struct clk *clk;
>> void __iomem*regs;
>> + void __iomem*phyctrl_pmureg;
>> int ref_clk_freq;
>> - int cpu_type;
>> + const struct samsung_usbphy_drvdata *drv_data;
>> };
>>
>> #define phy_to_sphy(x)container_of((x), struct
>> samsung_usbphy, phy)
>>
>> +static int samsung_usbphy_parse_dt_param(struct samsung_usbphy *sphy)
>
>
Re: [PATCH v4] usb: phy: samsung: Add support to set pmu isolation
Hi Russell,
On Thu, Dec 27, 2012 at 5:56 AM, Russell King - ARM Linux
wrote:
> On Wed, Dec 26, 2012 at 05:58:32PM +0530, Vivek Gautam wrote:
>> + if (!ret)
>> + sphy->phyctrl_pmureg = ioremap(reg[0], reg[1]);
>> +
>> + of_node_put(usbphy_pmu);
>> +
>> + if (IS_ERR_OR_NULL(sphy->phyctrl_pmureg)) {
>
> No. Learn what the error return values are from functions. Using the
> wrong ones is buggy. ioremap() only ever returns NULL on error. You
> must check against NULL, and not use the IS_ERR stuff.
>
True, i should have checked the things. :-(
ioremap() won't return error. Will amend this to check against NULL.
>> +/*
>> + * Set isolation here for phy.
>> + * SOCs control this by controlling corresponding PMU registers
>> + */
>> +static void samsung_usbphy_set_isolation(struct samsung_usbphy *sphy, int
>> on)
>> +{
>> + u32 reg;
>> + int en_mask;
>> +
>> + if (!sphy->phyctrl_pmureg) {
>> + dev_warn(sphy->dev, "Can't set pmu isolation\n");
>> + return;
>> + }
>> +
>> + reg = readl(sphy->phyctrl_pmureg);
>> +
>> + en_mask = sphy->drv_data->devphy_en_mask;
>> +
>> + if (on)
>> + writel(reg & ~en_mask, sphy->phyctrl_pmureg);
>> + else
>> + writel(reg | en_mask, sphy->phyctrl_pmureg);
>
> What guarantees that this read-modify-write sequence of this register safe?
> And, btw, this can't be optimised very well because of the barrier inside
> writel(). This would be better:
>
> if (on)
> reg &= ~en_mask;
> else
> reg |= en_mask;
>
> writel(reg, sphy->phyctrl_pmureg);
>
Sure will amend this.
A similar way suggested by Sylwester in the earlier mail in this thread:
reg = on ? reg & ~mask : reg | mask;
writel(reg, sphy->phyctrl_pmureg);
Does this look fine ?
>> +static inline struct samsung_usbphy_drvdata
>> +*samsung_usbphy_get_driver_data(struct platform_device *pdev)
>> {
>> if (pdev->dev.of_node) {
>> const struct of_device_id *match;
>> match = of_match_node(samsung_usbphy_dt_match,
>> pdev->dev.of_node);
>> - return (int) match->data;
>> + return (struct samsung_usbphy_drvdata *) match->data;
>
> match->data is a const void pointer. Is there a reason you need this
> cast here? What if you made the returned pointer from this function
> also const and fixed up all its users (no user should modify this
> data.)
>
Right, we won't need this cast since match->data is a void pointer.
Will also make the returned pointer const.
>> #ifdef CONFIG_OF
>> static const struct of_device_id samsung_usbphy_dt_match[] = {
>> {
>> .compatible = "samsung,s3c64xx-usbphy",
>> - .data = (void *)TYPE_S3C64XX,
>> + .data = (void *)&usbphy_s3c64xx,
>
> Why do you need this cast?
>
True we don't need this cast. Will remove this one.
>> }, {
>> .compatible = "samsung,exynos4210-usbphy",
>> - .data = (void *)TYPE_EXYNOS4210,
>> + .data = (void *)&usbphy_exynos4,
>
> Ditto.
True we don't need this cast. Will remove this one.
Thanks for the review :-)
--
Regards
Vivek
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[PATCH] ARM: EXYNOS: Interchange control bits of sysmmu mfc_l and mfc_r
The control bits for mfc_l and mfc_r sysmmus are incorrectly set.
This patch interchanges the control bits so that the mfc sysmmus
function correctly.
Signed-off-by: Prathyush K
---
arch/arm/mach-exynos/clock-exynos5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 0208c3a..730d54c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -873,13 +873,13 @@ static struct clk exynos5_init_clocks_off[] = {
.devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ops= &exynos5_gate_clk_ops,
- .ctrlbit= (1 << 1),
+ .ctrlbit= (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.enable = &exynos5_clk_ip_mfc_ctrl,
.ops= &exynos5_gate_clk_ops,
- .ctrlbit= (1 << 2),
+ .ctrlbit= (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname= SYSMMU_CLOCK_DEVNAME(tv, 2),
--
1.8.0
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[PATCH] ARM: exynos: Revise HDMI resource size
From: Sean Paul
Reduce the HDMI resource size from 0x10 to 0x7 so it
doesn't overlap the Displayport resource space.
HDMI: (0x1453 - 0x145A
DP: (0x145B - 0x145B1000)
Signed-off-by: Sean Paul
Signed-off-by: Prathyush K
---
arch/arm/boot/dts/exynos5250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 45799e8..30485de 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -580,7 +580,7 @@
hdmi {
compatible = "samsung,exynos5-hdmi";
- reg = <0x1453 0x10>;
+ reg = <0x1453 0x7>;
interrupts = <0 95 0>;
};
--
1.8.0
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