[PATCH 1/1] video: drm: exynos: Adds display-timing node parsing using video helper function

[Leela Krishna Amudala]

This patch adds display-timing node parsing using video helper function

Signed-off-by: Leela Krishna Amudala 
Tested-by: Vikas Sajjan 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 31 +++
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 9537761..19dc842 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -876,6 +876,8 @@ static int fimd_probe(struct platform_device *pdev)
struct fimd_context *ctx;
struct exynos_drm_subdrv *subdrv;
struct exynos_drm_fimd_pdata *pdata;
+   struct fb_videomode *fbmode;
+   struct device *disp_dev = &pdev->dev;
struct exynos_drm_panel_info *panel;
struct resource *res;
int win;
@@ -883,10 +885,31 @@ static int fimd_probe(struct platform_device *pdev)
 
DRM_DEBUG_KMS("%s\n", __FILE__);
 
-   pdata = pdev->dev.platform_data;
-   if (!pdata) {
-   dev_err(dev, "no platform data specified\n");
-   return -EINVAL;
+   if (pdev->dev.of_node) {
+   pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+   if (!pdata) {
+   DRM_ERROR("memory allocation for pdata failed\n");
+   return -ENOMEM;
+   }
+
+   fbmode = devm_kzalloc(dev, sizeof(*fbmode), GFP_KERNEL);
+   if (!fbmode) {
+   DRM_ERROR("memory allocation for fbmode failed\n");
+   return -ENOMEM;
+   }
+
+   ret = of_get_fb_videomode(disp_dev->of_node, fbmode, -1);
+   if (ret) {
+   DRM_ERROR("failed to get fb_videomode\n");
+   return -EINVAL;
+   }
+   pdata->panel.timing = (struct fb_videomode) *fbmode;
+   } else {
+   pdata = pdev->dev.platform_data;
+   if (!pdata) {
+   DRM_ERROR("no platform data specified\n");
+   return -EINVAL;
+   }
}
 
panel = &pdata->panel;
-- 
1.8.0

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[PATCH 0/1] Adds display-timing node parsing to exynos drm fimd

[Leela Krishna Amudala]

This patch adds display-timing node parsing to drm fimd, this depends on
the display helper patchset at
http://lists.freedesktop.org/archives/dri-devel/2013-January/033998.html

Patch is based on branch "exynos-drm-next" at
http://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git/

It is tested on Exynos5250 and Exynos4412 board by applying dependent patches 
available at
http://lists.freedesktop.org/archives/dri-devel/2013-January/033998.html

Leela Krishna Amudala (1):
  video: drm: exynos: Adds display-timing node parsing using video
helper function

 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 31 +++
 1 file changed, 27 insertions(+), 4 deletions(-)

-- 
1.8.0

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Re: [PATCH V6 09/10] ASoC: Samsung: Update Kconfig for I2S,SPDIF and PCM audio

[Mark Brown]

On Fri, Jan 18, 2013 at 05:17:08PM +0530, Padmavathi Venna wrote:
> Update Kconfig file to enable I2S,PCM audio for wm8994 and spdif on all
> samsung platforms.

Applied, thanks.


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Re: [PATCH V6 08/10] ARM: dts: Modify SPI nodes according generic DMA DT bindings

[Mark Brown]

On Fri, Jan 18, 2013 at 05:17:07PM +0530, Padmavathi Venna wrote:
> This patch removes custom way of adding spi dma channels and
> adds according to new generic DMA DT bindings.

Applied, thanks.


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Re: [PATCH V6 07/10] ASoC: SMDK: WM8994: Add device tree support for machine file

[Mark Brown]

On Fri, Jan 18, 2013 at 05:17:06PM +0530, Padmavathi Venna wrote:

> +Samsung SMDK audio complex

This is just for SMDKs with WM8994.  I'll apply but please send a
followup patch to clarify this - it'll be a different binding for others
like the older boards using WM8580 and WM9713.

> + samsung,i2s-controller = <&i2s0>;
> + samsung,audio-codec = <&wm8994>;

I was thinking this should really point at the DAI but since it's
specific to the SMDKs I don't think it particularly matters - they all
use AIF1 anyway.


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Re: [PATCH v4 3/4] ARM: Exynos5250: Add clock information for dwc3-exynos

[Vivek Gautam]

Hi Tomasz,


On Wed, Jan 16, 2013 at 8:35 PM, Vivek Gautam  wrote:
> Hi Tomasz,
>
>
> On Wed, Jan 16, 2013 at 1:19 PM, Tomasz Figa  wrote:
>> Hi Vivek,
>>
>> Don't you need also some clkdev lookup entry to make the clock available
>> in the driver?
>>
>
> This clock source we added with a motive of completion, however it's
> not being used as of now.
> As far as i could see the lookup structure contains clocks for devices
> having multiple instances.
> Do you feel that i should be adding an entry in clk_lookup structure ?
> May be i am missing here something. Can you please elaborate on the
> use-case of clk_lookup
> entries.
>

As indicated above "sclk_usbdrd30" is added with a motive of
completion, however it's
not being used as of now.
And "usbdrd30" is the actual device clock used, where 'drd30' is just
an indicative of
'dual role device and usb 3.0'. So the clock name 'usbdrd30' is the
usb 3.0 clock for drd.

Am i missing something that you wanted to convey here ?

>>
>> On Tuesday 15 of January 2013 19:08:31 Vivek Gautam wrote:
>>> Adding necessary device clock to exynos5 needed for
>>> the DWC3 controller.
>>>
>>> Signed-off-by: Vivek Gautam 
>>> ---
>>>  arch/arm/mach-exynos/clock-exynos5.c |   24 
>>>  1 files changed, 24 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
>>> b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..13af020 100644
>>> --- a/arch/arm/mach-exynos/clock-exynos5.c
>>> +++ b/arch/arm/mach-exynos/clock-exynos5.c
>>> @@ -757,6 +757,11 @@ static struct clk exynos5_init_clocks_off[] = {
>>>   .enable = exynos5_clk_ip_fsys_ctrl ,
>>>   .ctrlbit= (1 << 18),
>>>   }, {
>>> + .name   = "usbdrd30",
>>> + .parent = &exynos5_clk_aclk_200.clk,
>>> + .enable = exynos5_clk_ip_fsys_ctrl,
>>> + .ctrlbit= (1 << 19),
>>> + }, {
>>>   .name   = "usbotg",
>>>   .enable = exynos5_clk_ip_fsys_ctrl,
>>>   .ctrlbit= (1 << 7),
>>> @@ -1035,6 +1040,16 @@ static struct clksrc_sources exynos5_clkset_group
>>> = { .nr_sources   = ARRAY_SIZE(exynos5_clkset_group_list),
>>>  };
>>>
>>> +struct clk *exynos5_clkset_usbdrd30_list[] = {
>>> + [0] = &exynos5_clk_mout_mpll.clk,
>>> + [1] = &exynos5_clk_mout_cpll.clk,
>>> +};
>>> +
>>> +struct clksrc_sources exynos5_clkset_usbdrd30 = {
>>> + .sources= exynos5_clkset_usbdrd30_list,
>>> + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
>>> +};
>>> +
>>>  /* Possible clock sources for aclk_266_gscl_sub Mux */
>>>  static struct clk *clk_src_gscl_266_list[] = {
>>>   [0] = &clk_ext_xtal_mux,
>>> @@ -1329,6 +1344,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
>>>   .parent = &exynos5_clk_mout_cpll.clk,
>>>   },
>>>   .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3
>> },
>>> + }, {
>>> + .clk= {
>>> + .name   = "sclk_usbdrd30",
>>> + .enable = exynos5_clksrc_mask_fsys_ctrl,
>>> + .ctrlbit= (1 << 28),
>>> + },
>>> + .sources = &exynos5_clkset_usbdrd30,
>>> + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size =
>> 1 },
>>> + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size =
>> 4 },
>>>   },
>>>  };
>
>


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Re: [PATCH V6 03/10] ARM: SAMSUNG: Make dma request compatible to generic dma bindings.

[Mark Brown]

On Fri, Jan 18, 2013 at 05:17:02PM +0530, Padmavathi Venna wrote:
> This patch make the dma dev request operation compatible for both
> DT and non-DT cases. It takes the all the arguments required for
> dma_request_slave_channel and dma_request_channel. If the driver
> is initiated via DT or non-DT the corresponding call will be made.

OK, so this is where the SPI change came from - the API has been changed
incompatibly and SPI needs updating.  For bisection this API update
ought to be done in a single commit, otherwise there will be steps in
the bisection where nothing will work.

Anyway, I'll go ahead and apply this, the SPI and the ASoC ones but this
is something to bear in mind for the future.


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RE: Failure due to missing (Exynos related) pinctrl patch

[Kukjin Kim]

Sachin Kamat wrote:
> 
> Hi Linus, Kukjin,
> 
> Patch titled "pinctrl: exynos: change PINCTRL_EXYNOS option"
> (linux-next commit Id: 7452b64d) which is present in linux-next is
> missing in the mainline kernel. This patch is required along with the
> patch "gpio: samsung: fix pinctrl condition for exynos and exynos5440"
> (mainline commit Id: e4a5da51) which has already made it into
> mainline. Without the missing patch we get the following boot up
> warnings and subsequent failures with dt boot on 4412 based board:
> 
>  WARNING: at drivers/gpio/gpio-samsung.c:3102
> samsung_gpiolib_init+0x29c/0x2e8()
>  Unknown SoC in gpio-samsung, no GPIOs added
>  Modules linked in:
>  [] (unwind_backtrace+0x0/0xf8) from []
> (warn_slowpath_common+0x4c/0x64)
>  [] (warn_slowpath_common+0x4c/0x64) from []
> (warn_slowpath_fmt+0x30/0x40)
>  [] (warn_slowpath_fmt+0x30/0x40) from []
> (samsung_gpiolib_init+0x29c/0x2e8)
>  [] (samsung_gpiolib_init+0x29c/0x2e8) from []
> (do_one_initcall+0x34/0x174)
>  [] (do_one_initcall+0x34/0x174) from []
> (kernel_init_freeable+0xfc/0x1c8)
>  [] (kernel_init_freeable+0xfc/0x1c8) from []
> (kernel_init+0x8/0xe4)
>  [] (kernel_init+0x8/0xe4) from []
> (ret_from_fork+0x14/0x3c)
> 
Sachin, thanks for your information.

Linus, can you check following again?

https://lkml.org/lkml/2013/1/18/461

Thanks.

- Kukjin


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RE: [PATCH] Fix compilation error on S3C2440

[Kukjin Kim]

Alexey Galakhov wrote:
> 
> There was a compilation error introduced on Dec 7, 2012
> by commit a08485d8fdf6f67ca5f173b68d8f873c574745f2.
> 
Following is better:

The commit a08485d8 ("ASoC: Samsung: Do not register samsung audio dma
device as pdev") introduced compilation error.

> Combination of CONFIG_CPU_S3C2440 and CONFIG_SND_S3C24XX_I2S
> caused the following:
> sound/soc/samsung/s3c24xx-i2s.c: In function 's3c24xx_iis_dev_probe':
> sound/soc/samsung/s3c24xx-i2s.c:472:2: error: implicit declaration of
> function 's3c_i2sv2_register_dai' [-Werror=implicit-function-declaration]
> sound/soc/samsung/s3c24xx-i2s.c:472:48: error: 's3c2412_i2s_dai'
> undeclared (first use in this function)
> 
> This patch fixes the problem and makes S3C2440 I2S usable again.
> 
> Signed-off-by: Alexey Galakhov 

Cc: Padmavathi Venna 
Cc: Sangbeom Kim 
Cc: Mark Brown 

> ---
>  sound/soc/samsung/s3c24xx-i2s.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/sound/soc/samsung/s3c24xx-i2s.c
> b/sound/soc/samsung/s3c24xx-i2s.c
> index ee10e87..13f6dd1 100644
> --- a/sound/soc/samsung/s3c24xx-i2s.c
> +++ b/sound/soc/samsung/s3c24xx-i2s.c
> @@ -469,7 +469,7 @@ static int s3c24xx_iis_dev_probe(struct
> platform_device *pdev)
>  {
>   int ret = 0;
> 
> - ret = s3c_i2sv2_register_dai(&pdev->dev, -1, &s3c2412_i2s_dai);
> + ret = snd_soc_register_dai(&pdev->dev, &s3c24xx_i2s_dai);
>   if (ret) {
>   pr_err("failed to register the dai\n");
>   return ret;
> --
> 1.7.10.4

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Re: [PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller

[Vivek Gautam]

CC: Doug Anderson


On Mon, Jan 28, 2013 at 3:56 PM, Vivek Gautam  wrote:
> Adding PHY driver support for USB 3.0 controller for Samsung's
> SoCs.
>
> Signed-off-by: Vivek Gautam 
> ---
>
> Changes from v3:
>  - Making SAMSUNG_USB3PHY dependent on SAMSUNG_USBPHY.
>  - Adding USB_DWC3 to dependencies of SAMSUNG_USB2PHY since
>dwc3 controller also looks for USB2 type PHY.
>
>  drivers/usb/phy/Kconfig  |   11 +-
>  drivers/usb/phy/Makefile |1 +
>  drivers/usb/phy/samsung-usb3.c   |  349 
> ++
>  drivers/usb/phy/samsung-usbphy.h |   81 +
>  4 files changed, 441 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/usb/phy/samsung-usb3.c
>
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index cc0d230..9325a95 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -52,14 +52,23 @@ config SAMSUNG_USBPHY
> help
>   Enable this to support Samsung USB phy controllers for Samsung
>   SoCs.
> + Further enable USB 2.0 type PHY or USB 3.0 type PHY as required
> + for USB controllers in use.
>
>  if SAMSUNG_USBPHY
>
>  config SAMSUNG_USB2PHY
> bool "Samsung USB 2.0 PHY controller Driver"
> -   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
> +   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS || 
> USB_DWC3
> help
>   Enable this to support Samsung USB 2.0 (High Speed) phy controller
>   for Samsung SoCs.
>
> +config SAMSUNG_USB3PHY
> +   bool "Samsung USB 3.0 PHY controller Driver"
> +   depends on USB_DWC3
> +   help
> + Enable this to support Samsung USB 3.0 (Super Speed) phy controller
> + for samsung SoCs.
> +
>  endif
> diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
> index 7ba9862..b8505ac 100644
> --- a/drivers/usb/phy/Makefile
> +++ b/drivers/usb/phy/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA)  += tegra_usb_phy.o
>  obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
>  obj-$(CONFIG_SAMSUNG_USBPHY)   += samsung-usbphy.o
>  obj-$(CONFIG_SAMSUNG_USB2PHY)  += samsung-usb2.o
> +obj-$(CONFIG_SAMSUNG_USB3PHY)  += samsung-usb3.o
> diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
> new file mode 100644
> index 000..29e1321
> --- /dev/null
> +++ b/drivers/usb/phy/samsung-usb3.c
> @@ -0,0 +1,349 @@
> +/* linux/drivers/usb/phy/samsung-usb3.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *  http://www.samsung.com
> + *
> + * Author: Vivek Gautam 
> + *
> + * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "samsung-usbphy.h"
> +
> +/*
> + * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock 
> core.
> + */
> +static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
> +{
> +   u32 reg;
> +   u32 refclk;
> +
> +   refclk = sphy->ref_clk_freq;
> +
> +   reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
> +   PHYCLKRST_FSEL(refclk);
> +
> +   switch (refclk) {
> +   case FSEL_CLKSEL_50M:
> +   reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
> +   PHYCLKRST_SSC_REFCLKSEL(0x00));
> +   break;
> +   case FSEL_CLKSEL_20M:
> +   reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
> +   PHYCLKRST_SSC_REFCLKSEL(0x00));
> +   break;
> +   case FSEL_CLKSEL_19200K:
> +   reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
> +   PHYCLKRST_SSC_REFCLKSEL(0x88));
> +   break;
> +   case FSEL_CLKSEL_24M:
> +   default:
> +   reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
> +   PHYCLKRST_SSC_REFCLKSEL(0x88));
> +   break;
> +   }
> +
> +   return reg;
> +}
> +
> +static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
> +{
> +   void __iomem *regs = sphy->regs;
> +   u32 phyparam0;
> +   u32 phyparam1;
> +   u32 linksystem;
> +   u32 phybatchg;
> +   u32 phytest;
> +   u32 phyclkrst;
> +
> +   /* Reset USB 3.0 PHY */
> +   writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
> +
> +   phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
> +   /* Select PHY CLK source */
> +   phyparam0 &= ~

RE: [PATCH 0/3] ARM:exynos5:power-domain: Save and restore CLK_TOP_SRC3 via clock framework.

[Kukjin Kim]

Prasanna Kumar wrote:
> 
> After Suspend-Resume operation of exynos5, CLK_TOP_SRC3 register
> modified
> while power gating G-scaler and MFC power domains.This is seen only after
> suspend and resume.
> 
> The solution to this problem is to save CLK_SRC_TOP3 register and restore
> it while powergating. But CLK_SRC_TOP3 register cannot accessed directly
> by power domain code.
> Please refer below URL to know the background of this issue.
> http://www.mail-archive.com/linux-samsung-
> s...@vger.kernel.org/msg14347.html.
> 
> This patch set adds clock framework support for save and restore
> clock register (CLK_SRC_TOP3)  for G-scaler and MFC power domains.
> 
> This patch set depends on
> http://www.mail-archive.com/linux-samsung-
> s...@vger.kernel.org/msg14648.html
> 
> Prasanna Kumar (3):
>   ARM: dts: exynos5: Add power domain clocks to pd node of Gscaler and
> MFC
>   ARM:exynos5:dts: Bindings for clock definitions are added.
>   ARM: exynos5: Add clock save and restore operation(CLK_SRC_TOP3) using
> clock framework.
> 
>  .../bindings/arm/exynos/power_domain.txt   |   14 ++
>  arch/arm/boot/dts/exynos5250.dtsi  |2 +
>  arch/arm/mach-exynos/pm_domains.c  |  125
> 
>  3 files changed, 141 insertions(+), 0 deletions(-)
> 
> --
> 1.7.5.4

I think, you need to re-submit this after addressing comments from some
guys.

Thanks.

- Kukjin

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RE: [PATCH 1/2] arm: exynos5: Enable PM generic domain support in Kconfig

[Kukjin Kim]

Prasanna Kumar wrote:
> 
> This patch adds support to enable PM generic domains
> under Exynos5 family
> 
> Signed-off-by: Prasanna Kumar 
> ---
>  arch/arm/mach-exynos/Kconfig |1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-
> exynos/Kconfig
> index e103c29..871be97 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -63,6 +63,7 @@ config SOC_EXYNOS5250
>   depends on ARCH_EXYNOS5
>   select S5P_PM if PM
>   select S5P_SLEEP if PM
> + select PM_GENERIC_DOMAINS if PM
>   select S5P_DEV_MFC
>   select SAMSUNG_DMADEV
>   help
> --
> 1.7.5.4

Firstly, this patch can be squashed into 2nd one.
Secondly, please put the statements alphanumerically.
Finally, please use the same format for subject like following:
"ARM: EXYNOS: ..."

Thanks.

- Kukjin

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Re: [PATCH V6 04/10] spi: s3c64xx: Modify SPI driver to use generic DMA DT support

[Mark Brown]

On Fri, Jan 18, 2013 at 05:17:03PM +0530, Padmavathi Venna wrote:
> This patch modifies the SPI driver to use generic dma dt bindings
> support. This passes all the required arguments to dma dev request
> functon which in turn calls the dma_request_slave_channel or dma__
> request_channel based on DT or non-DT respectively.

This loooks OK and I'm actually applying SPI patches so I could apply it
but I'm not sure I see the relevance of this patch to the rest of the
series (which is about ASoC).  Is there some reason why it's included in
this patch series or can it be applied to the SPI tree?  The SMDKs use
I2C for their CODEC control rather than SPI.

Also is there a binding document update or device tree file update to go
with this?

> + if (!sdd->pdev->dev.of_node) {
> + res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
> + if (!res) {
> + dev_err(&pdev->dev, "Unable to get SPI tx dma "
> + "resource\n");

I appreciate that this is cut'n'paste from the code you're refactoring
but please don't split error messages over lines, it makes it hard to
grep for them in the kernel source.


signature.asc
Description: Digital signature

Failure due to missing (Exynos related) pinctrl patch

[Sachin Kamat]

Hi Linus, Kukjin,

Patch titled "pinctrl: exynos: change PINCTRL_EXYNOS option"
(linux-next commit Id: 7452b64d) which is present in linux-next is
missing in the mainline kernel. This patch is required along with the
patch "gpio: samsung: fix pinctrl condition for exynos and exynos5440"
(mainline commit Id: e4a5da51) which has already made it into
mainline. Without the missing patch we get the following boot up
warnings and subsequent failures with dt boot on 4412 based board:

 WARNING: at drivers/gpio/gpio-samsung.c:3102 samsung_gpiolib_init+0x29c/0x2e8()
 Unknown SoC in gpio-samsung, no GPIOs added
 Modules linked in:
 [] (unwind_backtrace+0x0/0xf8) from []
(warn_slowpath_common+0x4c/0x64)
 [] (warn_slowpath_common+0x4c/0x64) from []
(warn_slowpath_fmt+0x30/0x40)
 [] (warn_slowpath_fmt+0x30/0x40) from []
(samsung_gpiolib_init+0x29c/0x2e8)
 [] (samsung_gpiolib_init+0x29c/0x2e8) from []
(do_one_initcall+0x34/0x174)
 [] (do_one_initcall+0x34/0x174) from []
(kernel_init_freeable+0xfc/0x1c8)
 [] (kernel_init_freeable+0xfc/0x1c8) from []
(kernel_init+0x8/0xe4)
 [] (kernel_init+0x8/0xe4) from [] (ret_from_fork+0x14/0x3c)

-- 
With warm regards,
Sachin
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[PATCH 6/6] ARM: dts: Add MFC codec entry to exynos4412-smdk4412 DT file

[Sachin Kamat]

Added MFC DT entry to exynos4412-smdk4412.dts file.

Signed-off-by: Sachin Kamat 
---
 arch/arm/boot/dts/exynos4412-smdk4412.dts |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts 
b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index e885971..dcd1f33 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -49,4 +49,9 @@
serial@1383 {
status = "okay";
};
+
+   codec@1340 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
-- 
1.7.4.1

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[PATCH 5/6] ARM: dts: Add MFC codec entry to exynos4412-origen DT file

[Sachin Kamat]

Added MFC codec entry to exynos4412-origen.dts.

Signed-off-by: Sachin Kamat 
---
 arch/arm/boot/dts/exynos4412-origen.dts |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4412-origen.dts 
b/arch/arm/boot/dts/exynos4412-origen.dts
index 4eba374..d9766da 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -59,4 +59,9 @@
serial@1383 {
status = "okay";
};
+
+   codec@1340 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
-- 
1.7.4.1

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[PATCH 4/6] ARM: dts: Add MFC codec support to Origen DT

[Sachin Kamat]

This patch adds MFC codec support to Origen DT file.

Signed-off-by: Sachin Kamat 
---
 arch/arm/boot/dts/exynos4210-origen.dts |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210-origen.dts 
b/arch/arm/boot/dts/exynos4210-origen.dts
index f271001..cd0d1e2 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -121,4 +121,9 @@
linux,default-trigger = "heartbeat";
};
};
+
+   codec@1340 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
-- 
1.7.4.1

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[PATCH 3/6] ARM: dts: Add MFC codec support to SMDKV310 DT

[Sachin Kamat]

Added MFC codec support to SMDKV310 DT file.

Signed-off-by: Sachin Kamat 
---
 arch/arm/boot/dts/exynos4210-smdkv310.dts |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts 
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f634907..8481f8f 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -189,4 +189,9 @@
};
};
};
+
+   codec@1340 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+   };
 };
-- 
1.7.4.1

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[PATCH 2/6] ARM: dts: Add MFC codec support for Exynos4 DT machines

[Sachin Kamat]

This patch adds MFC codec support for Exynos4 DT machines.

Signed-off-by: Sachin Kamat 
---
 arch/arm/boot/dts/exynos4.dtsi |7 +++
 arch/arm/mach-exynos/mach-exynos4-dt.c |   17 +
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e1347fc..1122fb1 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -289,4 +289,11 @@
interrupts = <0 34 0>;
};
};
+
+   mfc: codec@1340 {
+   compatible = "samsung,mfc-v5";
+   reg = <0x1340 0x1>;
+   interrupts = <0 94 0>;
+   samsung,power-domain = <&pd_mfc>;
+   };
 };
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c 
b/arch/arm/mach-exynos/mach-exynos4-dt.c
index ab1dacc..8ae8da1 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -12,7 +12,9 @@
 */
 
 #include 
+#include 
 #include 
+#include 
 
 #include 
 #include 
@@ -20,6 +22,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common.h"
 
@@ -80,6 +83,7 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] 
__initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
"exynos-tmu", NULL),
+   OF_DEV_AUXDATA("samsung,mfc-v5", 0x1340, "s5p-mfc", NULL),
{},
 };
 
@@ -102,6 +106,18 @@ static char const *exynos4_dt_compat[] __initdata = {
NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+   struct s5p_mfc_dt_meminfo mfc_mem;
+
+   /* Reserve memory for MFC only if it's available */
+   mfc_mem.compatible = "samsung,mfc-v5";
+   if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+   s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+   mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
/* Maintainer: Thomas Abraham  */
.smp= smp_ops(exynos_smp_ops),
@@ -114,4 +130,5 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened 
Device Tree)")
.timer  = &exynos4_timer,
.dt_compat  = exynos4_dt_compat,
.restart= exynos4_restart,
+   .reserve= exynos4_reserve,
 MACHINE_END
-- 
1.7.4.1

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[PATCH 1/6] ARM: dts: Update MFC DT binding documentation

[Sachin Kamat]

Added an example for bindings for illustration and clarity.

Cc: devicetree-disc...@lists.ozlabs.org
Cc: Arun Kumar K 
Signed-off-by: Sachin Kamat 
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   13 +
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 67ec3d4..261c9dc 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,3 +21,16 @@ Required properties:
 
   - samsung,mfc-l : Base address of the second memory bank used by MFC
for DMA contiguous memory allocation and its size.
+
+Example:
+
+mfc: codec@1340 {
+   compatible = "samsung,mfc-v5";
+   reg = <0x1340 0x1>;
+   interrupts = <0 94 0>;
+};
+
+codec@1340 {
+   samsung,mfc-r = <0x4300 0x80>;
+   samsung,mfc-l = <0x5100 0x80>;
+};
-- 
1.7.4.1

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[PATCH Resend 0/6] ARM: dts: Add MFC support for Exynos4

[Sachin Kamat]

Resending this series after adding support for some Exynos4412 boards
(patches 5 and 6) and renaming the patch titles to "ARM: dts: ".

This series is based on for-next branch of Kukjin Kim's tree.
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git

Sachin Kamat (6):
  ARM: dts: Update MFC DT binding documentation
  ARM: dts: Add MFC codec support for Exynos4 DT machines
  ARM: dts: Add MFC codec support to SMDKV310 DT
  ARM: dts: Add MFC codec support to Origen DT
  ARM: dts: Add MFC codec entry to exynos4412-origen DT file
  ARM: dts: Add MFC codec entry to exynos4412-smdk4412 DT file

 .../devicetree/bindings/media/s5p-mfc.txt  |   13 +
 arch/arm/boot/dts/exynos4.dtsi |7 +++
 arch/arm/boot/dts/exynos4210-origen.dts|5 +
 arch/arm/boot/dts/exynos4210-smdkv310.dts  |5 +
 arch/arm/boot/dts/exynos4412-origen.dts|5 +
 arch/arm/boot/dts/exynos4412-smdk4412.dts  |5 +
 arch/arm/mach-exynos/mach-exynos4-dt.c |   17 +
 7 files changed, 57 insertions(+), 0 deletions(-)

-- 
1.7.4.1

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Re: [PATCH v4 5/5] mmc: dw_mmc: Remove DW_MCI_QUIRK_NO_WRITE_PROTECT

[Chris Ball]

Hi Doug,

On Mon, Jan 14 2013, Doug Anderson wrote:
> The whole bundle of all 5 patches at v4 is here:
> http://patchwork.kernel.org/bundle/dianders/mmc_wp/

Thanks, I've pushed all 5 to mmc-next for 3.9 now with the collected ACKs.

- Chris.
-- 
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One Laptop Per Child
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Re: [PATCH 2/4] DMA: PL330: Register the DMA controller with the generic DMA helpers

[Jon Hunter]

On 01/28/2013 12:01 PM, Arnd Bergmann wrote:
> On Monday 28 January 2013, Jon Hunter wrote:
>> On 01/28/2013 08:51 AM, Arnd Bergmann wrote:
>>> On Friday 18 January 2013, Padmavathi Venna wrote:
 +   pfi = devm_kzalloc(&adev->dev, sizeof(*pfi), GFP_KERNEL);
 +   if (!pfi) {
 +   dev_err(&adev->dev, "unable to allocate mem\n");
 +   return -ENOMEM;
 +   }
 +
 +   pfi->dma_cap = pd->cap_mask;
 +   pfi->filter_fn = pl330_filter;
 +
 +   ret = of_dma_controller_register(adev->dev.of_node,
 +of_dma_pl330_xlate, pfi);
>>>
>>> Why do you pass a 'struct of_dma_filter_info' here? I would
>>> expect that you pass the pdmac object as the third argument.
>>
>> I believe it is because that is the data that the xlate function is
>> using. Are you suggesting the data should be stored in the pdmac object
>> and extracted from there? That could be done too given that this
>> controller has its own xlate.
> 
> It just seems weird that we are passing a constant cap_mask in
> a data structure, and that we need our own filter function still,
> but don't pass the pointer to the data structure that we actually
> need in the filter function (the dma_device *).

Gotcha. I was still thinking about the generic case, but in this case if
you know the dma controller, it is redundant.

Cheers
Jon
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Re: [PATCH v4 3/7] ARM: Exynos: add device tree support for MCT controller driver

[Stephen Warren]

On 01/21/2013 03:02 AM, Thomas Abraham wrote:
> Allow the MCT controller base address and interrupts to be obtained from
> device tree and remove unused static definitions of these. The non-dt support
> for Exynos5250 is removed but retained for Exynos4210 based platforms.

Patches 3 and later in this series, fairly quickly,
Reviewed-by: Stephen Warren 

Sorry for the slow review.

I'm not 100% sure if I like Mark's #global-interrupts suggestion or not,
but I'd be fine with the binding either way, so choose as you see fit.
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Re: [PATCH v4 4/7] ARM: Exynos: allow dt based discovery of mct controller using clocksource_of_init

[Stephen Warren]

On 01/21/2013 03:02 AM, Thomas Abraham wrote:
> Add entries to __clksrc_of_table so that Exynos MCT controller is discoverable
> using call to clocksource_of_init. With this change, it would be appropriate 
> to
> rename the function 'exynos4_timer_init' as 'mct_init' since it aptly 
> describes
> this function. Additionally, the 'init_time' callback of all machine 
> descriptors
> for exynos platforms that were previously set to 'exynos4_timer_init' are now
> set to either 'mct_init' or 'clocksource_of_init'.

> diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c

> +#ifdef CONFIG_CLKSRC_OF
> +CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init)
> +CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init)
> +#endif

I suggested in another review (IIRC for a different SoC) that
CLOCKSOURCE_OF_DECLARE() should always be declared so you don't need
that ifdef. Would you care to send a patch to add to arm-soc's
timer/cleanup branch to do that? If not, let me know and I can.
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Re: [RFC/PATCH 29/32] usb: gadget: pxa27x_udc: let udc-core manage gadget->dev

[Robert Jarzmik]

Felipe Balbi  writes:

> By simply setting a flag, we can drop some
> boilerplate code.
>
> Signed-off-by: Felipe Balbi 
> ---
>  drivers/usb/gadget/pxa27x_udc.c | 9 +
Acked-by: Robert Jarzmik 

And I tested also your patch and it works in my environment. For next patches
I'd like to be CCed for pxa27x_udc stuff as I'm maintaining that one since its
beginning (and yes, I know, I didn't put that in MAINTAINERS ...).

Cheers.

--
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Re: [PATCH 1/4] ARM: dts: add support for hdmi to exynos4

[Tomasz Figa]

On Monday 28 of January 2013 14:53:10 Rahul Sharma wrote:
> Hi Tomasz,
> 
> On Mon, Jan 28, 2013 at 2:14 PM, Tomasz Figa  
wrote:
> > Hi Rahul,
> > 
> > On Monday 28 of January 2013 12:25:27 Rahul Sharma wrote:
> >> Hi Thomas,
> >> 
> >> On Fri, Jan 25, 2013 at 11:10 PM, Thomas Abraham
> >> 
> >>  wrote:
> >> > On 25 January 2013 02:39, Rahul Sharma 
> > 
> > wrote:
> >> >> Signed-off-by: Rahul Sharma 
> >> >> 
> >> >> Conflicts:
> >> >> arch/arm/mach-exynos/mach-exynos4-dt.c
> >> >> 
> >> >> ---
> >> >> 
> >> >>  arch/arm/boot/dts/exynos4.dtsi | 7 +++
> >> >>  arch/arm/mach-exynos/mach-exynos4-dt.c | 2 ++
> >> >>  2 files changed, 9 insertions(+)
> >> >> 
> >> >> diff --git a/arch/arm/boot/dts/exynos4.dtsi
> >> >> b/arch/arm/boot/dts/exynos4.dtsi index e1347fc..6c2c79d 100644
> >> >> --- a/arch/arm/boot/dts/exynos4.dtsi
> >> >> +++ b/arch/arm/boot/dts/exynos4.dtsi
> >> >> @@ -289,4 +289,11 @@
> >> >> 
> >> >> interrupts = <0 34 0>;
> >> >> 
> >> >> };
> >> >> 
> >> >> };
> >> >> 
> >> >> +
> >> >> +   hdmi {
> >> >> +   compatible = "samsung,exynos4-hdmi14";
> >> >> +   reg = <0x12D0 0x7>;
> >> >> +   interrupts = <0 95 0>;
> >> >> +   hpd-gpio = <&gpx3 7 0xf 1 3>;
> >> > 
> >> > This is using the older gpio dt bindings but exynos4 has started
> >> > using
> >> > the pinctrl bindings. So this is not sufficient to do the
> >> > pinmux/pinconfig settings on Exynos4.
> >> > 
> >> > Thanks,
> >> > Thomas.
> >> 
> >> I have chosen this as exynos5 DT using it in same way and parsed by
> >> common code in driver for exy4 and 5. Secondly, one-time initial
> >> configuration is sufficient for
> >> hdmi hpd-gpio. Please share your opinion.
> > 
> > Exynos4 SoCs use pin control for pin mux configuration, which implies
> > different GPIO specifiers than what you used. On Exynos4 generic GPIO
> > specifiers are used:
> > 
> > <&gpio-controller pin flags>
> > 
> > As you can see, it does not contain pin mux configuration, which must
> > be
> > configured if special function is to be used. In case of EINTs and
> > input/output functions, they are configured automatically, respectively
> > by request_irq (with appropriate interrupt trigger flag) and
> > gpio_direction_*.
> > 
> > Keep in mind that Exynos5 will be eventually moved to pin control as
> > well and its old GPIO bindings will be dropped as they are only
> > temporary.
> > 
> > Best regards,
> > Tomasz
> 
> Since Exynos5 pinctrl is not yet merged, either I need to add "hpd-
> gpio" in non-pinctrl way and keep the parsing code (in driver) same
> for exynos4 and 5, as I have done in posted patch. This is same for
> exynos5.
> Or, I need to parse gpio information in a two different manners for
> the two SoC series.
> 
> It will remain as a special case till we have exynos5 pinctrl driver.
> IMO, above code looks better till I can provide same solution for both,
> exynos4 & exynos5.

Well, it might look better, but it is incorrect, so I don't see the point 
of merging it. Please either provide a patch which handles Exynos4 properly 
or wait until Exynos5 pin control support gets merged.

You can look at sdhci-s3c driver for an example how to handle multiple pin 
mux configuration methods.

Best regards,
Tomasz

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Re: [PATCH 2/4] DMA: PL330: Register the DMA controller with the generic DMA helpers

[Arnd Bergmann]

On Monday 28 January 2013, Jon Hunter wrote:
> On 01/28/2013 08:51 AM, Arnd Bergmann wrote:
> > On Friday 18 January 2013, Padmavathi Venna wrote:
> >> +   pfi = devm_kzalloc(&adev->dev, sizeof(*pfi), GFP_KERNEL);
> >> +   if (!pfi) {
> >> +   dev_err(&adev->dev, "unable to allocate mem\n");
> >> +   return -ENOMEM;
> >> +   }
> >> +
> >> +   pfi->dma_cap = pd->cap_mask;
> >> +   pfi->filter_fn = pl330_filter;
> >> +
> >> +   ret = of_dma_controller_register(adev->dev.of_node,
> >> +of_dma_pl330_xlate, pfi);
> > 
> > Why do you pass a 'struct of_dma_filter_info' here? I would
> > expect that you pass the pdmac object as the third argument.
> 
> I believe it is because that is the data that the xlate function is
> using. Are you suggesting the data should be stored in the pdmac object
> and extracted from there? That could be done too given that this
> controller has its own xlate.

It just seems weird that we are passing a constant cap_mask in
a data structure, and that we need our own filter function still,
but don't pass the pointer to the data structure that we actually
need in the filter function (the dma_device *).

Arnd
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Re: [PATCH 2/4] DMA: PL330: Register the DMA controller with the generic DMA helpers

[Jon Hunter]

On 01/28/2013 08:51 AM, Arnd Bergmann wrote:
> On Friday 18 January 2013, Padmavathi Venna wrote:
>> +   pfi = devm_kzalloc(&adev->dev, sizeof(*pfi), GFP_KERNEL);
>> +   if (!pfi) {
>> +   dev_err(&adev->dev, "unable to allocate mem\n");
>> +   return -ENOMEM;
>> +   }
>> +
>> +   pfi->dma_cap = pd->cap_mask;
>> +   pfi->filter_fn = pl330_filter;
>> +
>> +   ret = of_dma_controller_register(adev->dev.of_node,
>> +of_dma_pl330_xlate, pfi);
> 
> Why do you pass a 'struct of_dma_filter_info' here? I would
> expect that you pass the pdmac object as the third argument.

I believe it is because that is the data that the xlate function is
using. Are you suggesting the data should be stored in the pdmac object
and extracted from there? That could be done too given that this
controller has its own xlate.

Cheers
Jon
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[PATCH] Fix compilation error on S3C2440

[Alexey Galakhov]

There was a compilation error introduced on Dec 7, 2012
by commit a08485d8fdf6f67ca5f173b68d8f873c574745f2.

Combination of CONFIG_CPU_S3C2440 and CONFIG_SND_S3C24XX_I2S
caused the following:
sound/soc/samsung/s3c24xx-i2s.c: In function 's3c24xx_iis_dev_probe':
sound/soc/samsung/s3c24xx-i2s.c:472:2: error: implicit declaration of
function 's3c_i2sv2_register_dai' [-Werror=implicit-function-declaration]
sound/soc/samsung/s3c24xx-i2s.c:472:48: error: 's3c2412_i2s_dai'
undeclared (first use in this function)

This patch fixes the problem and makes S3C2440 I2S usable again.

Signed-off-by: Alexey Galakhov 
---
 sound/soc/samsung/s3c24xx-i2s.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/samsung/s3c24xx-i2s.c b/sound/soc/samsung/s3c24xx-i2s.c
index ee10e87..13f6dd1 100644
--- a/sound/soc/samsung/s3c24xx-i2s.c
+++ b/sound/soc/samsung/s3c24xx-i2s.c
@@ -469,7 +469,7 @@ static int s3c24xx_iis_dev_probe(struct platform_device 
*pdev)
 {
int ret = 0;
 
-   ret = s3c_i2sv2_register_dai(&pdev->dev, -1, &s3c2412_i2s_dai);
+   ret = snd_soc_register_dai(&pdev->dev, &s3c24xx_i2s_dai);
if (ret) {
pr_err("failed to register the dai\n");
return ret;
-- 
1.7.10.4

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Re: [PATCH 0/4] Add generic DMA DT binding support

[Arnd Bergmann]

On Monday 28 January 2013, Vinod Koul wrote:
> On Fri, Jan 18, 2013 at 05:03:40PM +0530, Padmavathi Venna wrote:
> > This patch set adds support for generic dma device tree bindings for
> > Samsung platforms and is dependent on the following patches from
> > Vinod Koul next branch
> > 1)of: Add generic device tree DMA helpers
> > 2)dmaengine: add helper function to request a slave DMA channel
> Changes look fairly decent. I need somone with better knowldge of DT to akc 
> this
> before this is applied. Arnd...?

Thanks for the pointer, it seems everthing is coming together today ;-)

The binding looks good, aside from the wording on some of the properties
in there that could be a little clearer.

The method of calling dma_request_channel() from the xlate() function
is a little bit clumsy IMHO, but it does work and is the easiest way
to retrofit generic DT support to this driver, given that it already
provides a global filter function. It's also apparently what Jon had
in mind, and what Matt is doing on AM33XX.

I'll probably propose something similar on dw_dma, since I was just
(this hour, actually) looking at the same problem there. I believe
you had something smarter in mind when we discussed it in San Diego,
but I don't remember what the idea was.  I would need something
like

struct dma_chan *dma_channel_get(struct dma_device *);

and I assume that there is a reason for why I can't call this
from the xlate() function but instead have to go through
dma_request_channel(), but I don't completely understand that part
of the puzzle.

Arnd
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Re: [PATCH 1/4] DMA: PL330: Add xlate function

[Arnd Bergmann]

On Friday 18 January 2013, Padmavathi Venna wrote:
> +struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
> +   struct of_dma *ofdma)
> +{
> +   int count = dma_spec->args_count;
> +   struct of_dma_filter_info *info = ofdma->of_dma_data;
> +
> +   if (!info || !info->filter_fn)
> +   return NULL;
> +
> +   if (count != 1)
> +   return NULL;
> +
> +   return dma_request_channel(info->dma_cap, info->filter_fn, dma_spec);
> +}
> +EXPORT_SYMBOL_GPL(of_dma_pl330_xlate);

It seems a little sad that we still have to use dma_request_channel()
to implement this, when that function will go off searching all channels
and pass them tino the filter, which then has to look for the device node
and match it with each channel. We already know the controller and should
just be able to get a channel for it, although I don't exactly know how
that is done.

Further, your function is almost identical to the of_dma_simple_xlate
function. Can't you use that one instead?

Arnd
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Re: [PATCH 2/4] DMA: PL330: Register the DMA controller with the generic DMA helpers

[Arnd Bergmann]

On Friday 18 January 2013, Padmavathi Venna wrote:
> +   pfi = devm_kzalloc(&adev->dev, sizeof(*pfi), GFP_KERNEL);
> +   if (!pfi) {
> +   dev_err(&adev->dev, "unable to allocate mem\n");
> +   return -ENOMEM;
> +   }
> +
> +   pfi->dma_cap = pd->cap_mask;
> +   pfi->filter_fn = pl330_filter;
> +
> +   ret = of_dma_controller_register(adev->dev.of_node,
> +of_dma_pl330_xlate, pfi);

Why do you pass a 'struct of_dma_filter_info' here? I would
expect that you pass the pdmac object as the third argument.

Arnd
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Re: [PATCH 3/4] ARM: dts: Add #dma-cells for generic dma binding support

[Arnd Bergmann]

On Friday 18 January 2013, Padmavathi Venna wrote:
> diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt 
> b/Documentation/devicetree/bindings/dma/arm-pl330.txt
> index 36e27d5..457a233 100644
> --- a/Documentation/devicetree/bindings/dma/arm-pl330.txt
> +++ b/Documentation/devicetree/bindings/dma/arm-pl330.txt
> @@ -8,6 +8,8 @@ Required properties:
>- reg: physical base address of the controller and length of memory mapped
>  region.
>- interrupts: interrupt number to the cpu.
> +  - #dma-cells: must be at least 1. used to represent the number of integer
> +cells in the dmas property of client device.

The wording 'at least' seems wrong here: that is what we use in the
generic DMA binding, but in the part that is specific to one
driver, I would expect to see

- #dma-cells: must be <1>

Since that is what this particular driver requires.

>  Client drivers (device nodes requiring dma transfers from dev-to-mem or
> @@ -27,7 +30,7 @@ as shown below.
>[property name]  = <[phandle of the dma controller] [dma request id]>;
>  
>where 'dma request id' is the dma request number which is connected
> -  to the client controller. The 'property name' is recommended to be
> -  of the form -dma-channel.
> +  to the client controller. The 'property name' is 'dmas' as recommended
> +  by the generic dma device tree binding helpers.

s/recommended/required/

Also, the "dma-names" property is required as well.

Arnd
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Re: [PATCH V6 10/10] dmaengine: Fix compilation error in non-DT case

[Vinod Koul]

On Fri, Jan 18, 2013 at 05:17:09PM +0530, Padmavathi Venna wrote:
> Signed-off-by: Padmavathi Venna 
> ---
>  include/linux/dmaengine.h |2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 8cd0e25..c88f302 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -992,7 +992,7 @@ static inline struct dma_chan 
> *__dma_request_channel(dma_cap_mask_t *mask,
>  static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
>char *name)
>  {
> - return NULL
> + return NULL;
what tree was this generated against? this was fixed by 678bd8

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Re: [PATCH 0/4] Add generic DMA DT binding support

[Vinod Koul]

On Fri, Jan 18, 2013 at 05:03:40PM +0530, Padmavathi Venna wrote:
> This patch set adds support for generic dma device tree bindings for
> Samsung platforms and is dependent on the following patches from
> Vinod Koul next branch
> 1)of: Add generic device tree DMA helpers
> 2)dmaengine: add helper function to request a slave DMA channel
Changes look fairly decent. I need somone with better knowldge of DT to akc this
before this is applied. Arnd...?
> 
> This patch set is made based Kukjin Kim for-next branch
> 
> Padmavathi Venna (4):
>   DMA: PL330: Add xlate function
>   DMA: PL330: Register the DMA controller with the generic DMA helpers
>   ARM: dts: Add #dma-cells for generic dma binding support
>   DMA: PL330: Modify pl330 filter based on new generic dma dt bindings.
> 
>  .../devicetree/bindings/dma/arm-pl330.txt  |9 +++-
>  arch/arm/boot/dts/exynos5250.dtsi  |4 ++
>  drivers/dma/pl330.c|   48 
> 
>  3 files changed, 49 insertions(+), 12 deletions(-)
> 
> -- 
> 1.7.4.4
> 
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Re: [PATCH 2/4] USB: dwc3: Adjust runtime pm the dwc3 driver to allow runtime suspend

[Vivek Gautam]

Hi Felipe,


On Mon, Jan 28, 2013 at 5:15 PM, Felipe Balbi  wrote:
> On Mon, Jan 28, 2013 at 05:12:26PM +0530, Vivek Gautam wrote:
>> The current code in the dwc3 probe effectively disables runtime pm
>> from ever working because it calls a get() that was never put() until
>> device removal.  Change the runtime pm code to match the standard
>> formula and allow runtime pm to function.
>>
>> Note that this doesn't enable full runtime pm on the DWC3 device in
>> that the port isn't put into a lower power mode when not used.
>> However it does allow users of dwc3 (like dwc3-exynos) to do some
>> amount of runtime power management.
>>
>> Signed-off-by: Vivek Gautam 
>> Signed-off-by: Doug Anderson 
>> ---
>>  drivers/usb/dwc3/core.c |4 +++-
>>  1 files changed, 3 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 3a4004a..59c2494 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -453,6 +453,7 @@ static int dwc3_probe(struct platform_device *pdev)
>>   if (of_get_property(node, "tx-fifo-resize", NULL))
>>   dwc->needs_fifo_resize = true;
>>
>> + pm_runtime_set_active(dev);
>
> this usage of pm_runtime_set_active() actually makes me a bit scared. At
> least OMAP starts with the device switched off, so this will probably
> break OMAP at least.

I am fine with dropping pm_runtime_set_active(), actually thought
to put device in active state so that as and when system finds it idle,
force into suspend state.

I fact should i drop  pm_runtime_set_active() calls from other places too
(xhci-plat, dwc3-exynos, and samsung-usb3 phy) and call get_sync() alongwith
enable() ?

> OTOH, calling ->runtime_resume() during probe()
> might not make that much sense after all, but the way OMAP is
> implemented, we won't get clocks turned on if this ->runtime_resume()
> method isn't called.
>
> /me starts to wonder whether OMAP implementation is flakey and what
> should be done here...
>



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Re: [PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Felipe Balbi]

On Mon, Jan 28, 2013 at 06:54:42PM +0530, Vivek Gautam wrote:
> Hi Felipe,
> 
> 
> On Mon, Jan 28, 2013 at 6:37 PM, Felipe Balbi  wrote:
> > Hi,
> >
> > On Mon, Jan 28, 2013 at 06:34:15PM +0530, Vivek Gautam wrote:
> >> >> @@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct 
> >> >> samsung_usbphy *sphy)
> >> >>   return reg;
> >> >>  }
> >> >>
> >> >> -static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
> >> >> +/*
> >> >> + * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from 
> >> >> external PLL.
> >> >> + */
> >> >> +static u32 samsung_usb3_phy_set_refclk_ext(void)
> >> >> +{
> >> >> + u32 reg;
> >> >> +
> >> >> + reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
> >> >> + PHYCLKRST_FSEL_PAD_100MHZ |
> >> >> + PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
> >> >> +
> >> >> + return reg;
> >> >> +}
> >> >
> >> > I wonder if you really need this small function (likewise for
> >> > set_refclk_int()). They don't do much, so you could just inline them on
> >> > the only caller.
> >> >
> >>
> >> Created this just to keep symmetry, ;-)
> >> will move this in the caller only.
> >
> > you can have a patch before this series moving the refclk_int() to the
> > caller, then you will have symmetry ;-)
> >
> 
> refclk_int() was rather slightly a big chunk :-(
> as available in below patch as samsung_usb3_phy_set_refclk() :
> [PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
> http://www.mail-archive.com/linux-usb@vger.kernel.org/msg13796.html
> 
> Will try to figure best possible way and amend.

oh, right... In that case, keep the way it is. Ignore my comment ;-)

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Re: [PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Vivek Gautam]

Hi Felipe,


On Mon, Jan 28, 2013 at 6:37 PM, Felipe Balbi  wrote:
> Hi,
>
> On Mon, Jan 28, 2013 at 06:34:15PM +0530, Vivek Gautam wrote:
>> >> @@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct 
>> >> samsung_usbphy *sphy)
>> >>   return reg;
>> >>  }
>> >>
>> >> -static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
>> >> +/*
>> >> + * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from 
>> >> external PLL.
>> >> + */
>> >> +static u32 samsung_usb3_phy_set_refclk_ext(void)
>> >> +{
>> >> + u32 reg;
>> >> +
>> >> + reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
>> >> + PHYCLKRST_FSEL_PAD_100MHZ |
>> >> + PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
>> >> +
>> >> + return reg;
>> >> +}
>> >
>> > I wonder if you really need this small function (likewise for
>> > set_refclk_int()). They don't do much, so you could just inline them on
>> > the only caller.
>> >
>>
>> Created this just to keep symmetry, ;-)
>> will move this in the caller only.
>
> you can have a patch before this series moving the refclk_int() to the
> caller, then you will have symmetry ;-)
>

refclk_int() was rather slightly a big chunk :-(
as available in below patch as samsung_usb3_phy_set_refclk() :
[PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller
http://www.mail-archive.com/linux-usb@vger.kernel.org/msg13796.html

Will try to figure best possible way and amend.


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Re: [PATCH] drivers: cpufreq: exynos: update related_cpus mask to fix hotplug dump

[Rafael J. Wysocki]

On Monday, January 28, 2013 06:29:35 PM Viresh Kumar wrote:
> On 28 January 2013 17:56, Rafael J. Wysocki  wrote:
> > So here's a deal: I'll drop "cpufreq: Simplify cpufreq_add_dev()" for now 
> > and
> > you'll generate a new patch that won't cause the WARN_ON() to trigger.  OK?
> 
> :(
> 
> Or what about set all cpus from policy->cpus into related_cpus in our core 
> code?
> So, if platform sets any additional cpus, they would be retained?

Well, that might work.

Please do whatever you think is the most appropriate and doesn't introcude any
regressions.

Thanks,
Rafael


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Re: [PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Felipe Balbi]

Hi,

On Mon, Jan 28, 2013 at 06:34:15PM +0530, Vivek Gautam wrote:
> >> @@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct 
> >> samsung_usbphy *sphy)
> >>   return reg;
> >>  }
> >>
> >> -static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
> >> +/*
> >> + * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from external 
> >> PLL.
> >> + */
> >> +static u32 samsung_usb3_phy_set_refclk_ext(void)
> >> +{
> >> + u32 reg;
> >> +
> >> + reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
> >> + PHYCLKRST_FSEL_PAD_100MHZ |
> >> + PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
> >> +
> >> + return reg;
> >> +}
> >
> > I wonder if you really need this small function (likewise for
> > set_refclk_int()). They don't do much, so you could just inline them on
> > the only caller.
> >
> 
> Created this just to keep symmetry, ;-)
> will move this in the caller only.

you can have a patch before this series moving the refclk_int() to the
caller, then you will have symmetry ;-)

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Re: [PATCH 5/6] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs

[Dave Martin]

On Mon, Jan 28, 2013 at 09:02:40AM +, Mark Rutland wrote:
> On Fri, Jan 25, 2013 at 07:15:48PM +, Kukjin Kim wrote:
> > Tomasz Figa wrote:
> > 
> > [...]
> > 
> > > > Well, the number of CPU types does not grow rapidly.  It will be much
> > > > less than one per SoC -- so keeping the list up to date shouldn't be
> > > > that much effort.
> > > >
> > > > For ARM1176JZF-S, it could make sense for the comatible list to be
> > > >
> > > > "arm,arm1176jzf-s", "arm,arm1176"
> > > >
> > > > ...since the differences between 1176 variants are software probeable
> > > > (i.e., whether there is an FPU or not).  AFAIK the J, Z apply to all
> > > > ARM1176, and the -S (synthesisable RTL) is nothing to do with software.
> > > > The kernel probably only really needs to know "arm,arm1176".
> > > 
> > > OK. So the conclusion is that I should change the cpus node to following:
> > > 
> > >cpus {
> > >cpu {
> > 
> > cpu@0 { ?
> 
> As the CPU has no MPIDR, and thus doesn't have a reg property, there's no 
> reason
> to have a unit address. Just "cpu" should be fine.
> 
> > 
> > >compatible = "arm,arm1176jzf-s", "arm,arm1176";
> > >};
> > >};
> > > 
> > > Am I right?
> > > 
> > I think so :-)
> > 
> > - Kukjin
> > 
> 
> As Dave pointed out, the "jzf-s" portion might be superfluous. It's worth
> having the "arm,arm1176", though.

I think we should always have a fully-qualified part name as the first
compatible entry, following general devicetree policy.  It's better to
have this and not need it than to discover later that we want it and
incompatibly backport it in.

Before deciding, do we follow a consistent policy for other CPUs, such
as arm1136?


The issues there are similar: the only software-visible difference between
arm1136j-s and arm1136jf-s should be the absence/presence of VFP, and it
looks like the code in vfpmodule.c should be able to probe it.

Cheers
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Re: [PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Vivek Gautam]

Hi Felipe,


On Mon, Jan 28, 2013 at 5:39 PM, Felipe Balbi  wrote:
> Hi,
>
> On Mon, Jan 28, 2013 at 05:12:28PM +0530, Vivek Gautam wrote:
>> Enabling runtime power management support on samsung-usb3 phy
>> and further adding support to turn off the PHY ref_clk PLL.
>> It thereby requires PHY ref_clk to be switched between internal
>> core clock and external PLL clock.
>>
>> Signed-off-by: Vivek Gautam 
>
> this needs to be broken down a bit. I can see three patches at least:
> add support for external clock, add support for phy gpio powerdown and
> add runtime pm ;-)
>

Alright, will break this into required number of patches.

>> ---
>>  drivers/usb/phy/samsung-usb3.c   |  107 
>> +++--
>>  drivers/usb/phy/samsung-usbphy.c |   26 +
>>  drivers/usb/phy/samsung-usbphy.h |1 +
>>  3 files changed, 128 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
>> index 29e1321..4dbef15 100644
>> --- a/drivers/usb/phy/samsung-usb3.c
>> +++ b/drivers/usb/phy/samsung-usb3.c
>> @@ -22,8 +22,10 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>
>> @@ -32,7 +34,7 @@
>>  /*
>>   * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock 
>> core.
>>   */
>> -static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
>> +static u32 samsung_usb3_phy_set_refclk_int(struct samsung_usbphy *sphy)
>>  {
>>   u32 reg;
>>   u32 refclk;
>> @@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct 
>> samsung_usbphy *sphy)
>>   return reg;
>>  }
>>
>> -static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
>> +/*
>> + * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from external 
>> PLL.
>> + */
>> +static u32 samsung_usb3_phy_set_refclk_ext(void)
>> +{
>> + u32 reg;
>> +
>> + reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
>> + PHYCLKRST_FSEL_PAD_100MHZ |
>> + PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
>> +
>> + return reg;
>> +}
>
> I wonder if you really need this small function (likewise for
> set_refclk_int()). They don't do much, so you could just inline them on
> the only caller.
>

Created this just to keep symmetry, ;-)
will move this in the caller only.

>> @@ -80,7 +97,11 @@ static int samsung_exynos5_usb3_phy_enable(struct 
>> samsung_usbphy *sphy)
>>
>>   phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
>>   /* Select PHY CLK source */
>> - phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
>> + if (use_ext_clk)
>> + phyparam0 |= PHYPARAM0_REF_USE_PAD;
>> + else
>> + phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
>> +
>>   /* Set Loss-of-Signal Detector sensitivity */
>>   phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
>>   phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
>> @@ -115,7 +136,10 @@ static int samsung_exynos5_usb3_phy_enable(struct 
>> samsung_usbphy *sphy)
>>   /* UTMI Power Control */
>>   writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
>>
>> - phyclkrst = samsung_usb3_phy_set_refclk(sphy);
>> + if (use_ext_clk)
>> + phyclkrst = samsung_usb3_phy_set_refclk_ext();
>> + else
>> + phyclkrst = samsung_usb3_phy_set_refclk_int(sphy);
>>
>>   phyclkrst |= PHYCLKRST_PORTRESET |
>>   /* Digital power supply in normal operating mode */
>> @@ -163,7 +187,7 @@ static void samsung_exynos5_usb3_phy_disable(struct 
>> samsung_usbphy *sphy)
>>   writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
>>  }
>>
>> -static int samsung_usb3_phy_init(struct usb_phy *phy)
>> +static int samsung_exynos5_usb3_phy_init(struct usb_phy *phy, bool 
>> use_ext_clk)
>>  {
>>   struct samsung_usbphy *sphy;
>>   unsigned long flags;
>> @@ -187,7 +211,7 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
>>   samsung_usbphy_set_isolation(sphy, false);
>>
>>   /* Initialize usb phy registers */
>> - samsung_exynos5_usb3_phy_enable(sphy);
>> + samsung_exynos5_usb3_phy_enable(sphy, use_ext_clk);
>>
>>   spin_unlock_irqrestore(&sphy->lock, flags);
>>
>> @@ -198,6 +222,34 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
>>  }
>>
>>  /*
>> + * Switch  between internal core clock and external oscillator clock
>> + * for PHY reference clock
>> + */
>> +static int samsung_exynos5_usb3phy_clk_switch(struct usb_phy *phy,
>> + bool use_ext_clk)
>> +{
>> + /*
>> +  * This will switch PHY refclk from internal core clock
>> +  * to external PLL clock when device is in use and vice versa
>> +  * when device plunge into runtime suspend mode.
>> +  */
>> + return samsung_exynos5_usb3_phy_init(phy, use_ext_clk);
>> +}
>> +
>> +/*
>> + * The function passed to the usb driver for phy initialization
>> + */
>> +static int samsung_usb3_phy_init(struct usb_phy *phy)
>> +{
>> + /*
>> +  * We

Re: [PATCH] drivers: cpufreq: exynos: update related_cpus mask to fix hotplug dump

[Viresh Kumar]

On 28 January 2013 17:56, Rafael J. Wysocki  wrote:
> So here's a deal: I'll drop "cpufreq: Simplify cpufreq_add_dev()" for now and
> you'll generate a new patch that won't cause the WARN_ON() to trigger.  OK?

:(

Or what about set all cpus from policy->cpus into related_cpus in our core code?
So, if platform sets any additional cpus, they would be retained?
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Re: [PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Felipe Balbi]

On Mon, Jan 28, 2013 at 05:57:04PM +0530, Vivek Gautam wrote:
> On Mon, Jan 28, 2013 at 5:42 PM, Felipe Balbi  wrote:
> > Hi,
> >
> > On Mon, Jan 28, 2013 at 05:28:30PM +0530, Vivek Gautam wrote:
> >> >> +static int dwc3_exynos_runtime_resume(struct device *dev)
> >> >> +{
> >> >> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
> >> >> + struct platform_device  *pdev_dwc = exynos->dwc3;
> >> >> + struct dwc3 *dwc = NULL;
> >> >> +
> >> >> + dwc = platform_get_drvdata(pdev_dwc);
> >> >> +
> >> >> + clk_enable(exynos->clk);
> >> >> +
> >> >> + if (!dwc)
> >> >> + return 0;
> >> >> +
> >> >> + pm_runtime_get_sync(dwc->usb3_phy->dev);
> >> >
> >> > dude, this is wrong :-)
> >> >
> >> > look at this:
> >> >
> >> > pm_runtime_get() -> dwc3_exynos_runtime_resume() ->
> >> > pm_runtime_get_sync() -> dwc3_exynos_runtime_resume() -> ...
> >> >
> >> > only your clock enalbe should do
> >> >
> >>
> >> We want to wake up "dwc->usb3_phy" so tried to call pm_runtime_get_sync()
> >> with "dwc->usb3_phy->dev".
> >> Missing something ? :-(
> >
> > oh, my bad. That's the PHY... But we can't really do that for samsung
> > only. It needs to be done generically for the entire dwc3 core driver,
> > and for that we need to introduce usb_phy_autopm_get(),
> > usb_phy_autopm_get_sync() and friends.
> >
> 
> aah!! Ok. I definitely missed that part. :-(
> 
> > Then, from dwc_probe() we call:
> >
> > phy = usb_get_phy();
> > usb_phy_autopm_enable(phy);
> > usb_phy_autopm_get_sync(phy);
> >
> > or something similar ;-) Bottom line, you shouldn't fiddle with phy->dev
> > directly.
> >
> 
> Ok, the core should actually be handling the 'phy' not the glue layers.
> Right ?

that's right, thanks for doing this ;-)

> Will try putting these helper functions in place and come up with a
> solution. :-)

awesome ;-)

cheers

-- 
balbi


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Re: [PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Vivek Gautam]

On Mon, Jan 28, 2013 at 5:42 PM, Felipe Balbi  wrote:
> Hi,
>
> On Mon, Jan 28, 2013 at 05:28:30PM +0530, Vivek Gautam wrote:
>> >> +static int dwc3_exynos_runtime_resume(struct device *dev)
>> >> +{
>> >> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
>> >> + struct platform_device  *pdev_dwc = exynos->dwc3;
>> >> + struct dwc3 *dwc = NULL;
>> >> +
>> >> + dwc = platform_get_drvdata(pdev_dwc);
>> >> +
>> >> + clk_enable(exynos->clk);
>> >> +
>> >> + if (!dwc)
>> >> + return 0;
>> >> +
>> >> + pm_runtime_get_sync(dwc->usb3_phy->dev);
>> >
>> > dude, this is wrong :-)
>> >
>> > look at this:
>> >
>> > pm_runtime_get() -> dwc3_exynos_runtime_resume() ->
>> > pm_runtime_get_sync() -> dwc3_exynos_runtime_resume() -> ...
>> >
>> > only your clock enalbe should do
>> >
>>
>> We want to wake up "dwc->usb3_phy" so tried to call pm_runtime_get_sync()
>> with "dwc->usb3_phy->dev".
>> Missing something ? :-(
>
> oh, my bad. That's the PHY... But we can't really do that for samsung
> only. It needs to be done generically for the entire dwc3 core driver,
> and for that we need to introduce usb_phy_autopm_get(),
> usb_phy_autopm_get_sync() and friends.
>

aah!! Ok. I definitely missed that part. :-(

> Then, from dwc_probe() we call:
>
> phy = usb_get_phy();
> usb_phy_autopm_enable(phy);
> usb_phy_autopm_get_sync(phy);
>
> or something similar ;-) Bottom line, you shouldn't fiddle with phy->dev
> directly.
>

Ok, the core should actually be handling the 'phy' not the glue layers.
Right ?

Will try putting these helper functions in place and come up with a
solution. :-)


-- 
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Vivek
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Re: [PATCH] drivers: cpufreq: exynos: update related_cpus mask to fix hotplug dump

[Rafael J. Wysocki]

On Monday, January 28, 2013 09:45:02 AM Viresh Kumar wrote:
> On Thu, Jan 24, 2013 at 9:40 AM, Inderpal Singh
>  wrote:
> > commit "7e6087e595d3...cpufreq: Simplify cpufreq_add_dev()" started using
> > related_cpus mask to check if the current cpu is already managed.
> >
> > With above commit hotplug in exynos gives following dump.
> >
> > / $ echo 1 > /sys/devices/system/cpu/cpu1/online
> > CPU1: Booted secondary processor
> > [ cut here ]
> > WARNING: at fs/sysfs/dir.c:536 sysfs_add_one+0x88/0xbc()
> > sysfs: cannot create duplicate filename '/devices/system/cpu/cpu0/cpufreq'
> > Modules linked in:
> > [] (unwind_backtrace+0x0/0xf8) from [] 
> > (warn_slowpath_common+0x4c/0x64)
> > [] (warn_slowpath_common+0x4c/0x64) from [] 
> > (warn_slowpath_fmt+0x30/0x40)
> > [] (warn_slowpath_fmt+0x30/0x40) from [] 
> > (sysfs_add_one+0x88/0xbc)
> > [] (sysfs_add_one+0x88/0xbc) from [] 
> > (sysfs_do_create_link+0x110/0x208)
> > [] (sysfs_do_create_link+0x110/0x208) from [] 
> > (cpufreq_add_dev_interface+0x218/0x2b0)
> > [] (cpufreq_add_dev_interface+0x218/0x2b0) from [] 
> > (cpufreq_add_dev+0x30c/0x448)
> > [] (cpufreq_add_dev+0x30c/0x448) from [] 
> > (cpufreq_cpu_callback+0x94/0x9c)
> > [] (cpufreq_cpu_callback+0x94/0x9c) from [] 
> > (notifier_call_chain+0x44/0x84)
> > [] (notifier_call_chain+0x44/0x84) from [] 
> > (__cpu_notify+0x28/0x44)
> > [] (__cpu_notify+0x28/0x44) from [] 
> > (_cpu_up+0x104/0x154)
> > [] (_cpu_up+0x104/0x154) from [] (cpu_up+0x64/0x84)
> > [] (cpu_up+0x64/0x84) from [] (store_online+0x50/0x78)
> > [] (store_online+0x50/0x78) from [] 
> > (dev_attr_store+0x18/0x24)
> > [] (dev_attr_store+0x18/0x24) from [] 
> > (sysfs_write_file+0x168/0x198)
> > [] (sysfs_write_file+0x168/0x198) from [] 
> > (vfs_write+0x9c/0x140)
> > [] (vfs_write+0x9c/0x140) from [] (sys_write+0x3c/0x70)
> > [] (sys_write+0x3c/0x70) from [] 
> > (ret_fast_syscall+0x0/0x30)
> > ---[ end trace 3d002b0ded69f43b ]---
> >
> > This patch fixes it by updating the related_cpus mask.
> >
> > Tested on Rafael's linux-next.
> >
> > Signed-off-by: Inderpal Singh 
> > ---
> >  drivers/cpufreq/exynos-cpufreq.c |1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/cpufreq/exynos-cpufreq.c 
> > b/drivers/cpufreq/exynos-cpufreq.c
> > index 7012ea8..8ba4cdb 100644
> > --- a/drivers/cpufreq/exynos-cpufreq.c
> > +++ b/drivers/cpufreq/exynos-cpufreq.c
> > @@ -238,6 +238,7 @@ static int exynos_cpufreq_cpu_init(struct 
> > cpufreq_policy *policy)
> > cpumask_copy(policy->cpus, cpu_online_mask);
> > } else {
> > policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
> > +   cpumask_setall(policy->related_cpus);
> > cpumask_setall(policy->cpus);
> 
> This is required for all SMP systems.

Grumble.

So here's a deal: I'll drop "cpufreq: Simplify cpufreq_add_dev()" for now and
you'll generate a new patch that won't cause the WARN_ON() to trigger.  OK?

Rafael


-- 
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Re: [PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Felipe Balbi]

Hi,

On Mon, Jan 28, 2013 at 05:28:30PM +0530, Vivek Gautam wrote:
> >> +static int dwc3_exynos_runtime_resume(struct device *dev)
> >> +{
> >> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
> >> + struct platform_device  *pdev_dwc = exynos->dwc3;
> >> + struct dwc3 *dwc = NULL;
> >> +
> >> + dwc = platform_get_drvdata(pdev_dwc);
> >> +
> >> + clk_enable(exynos->clk);
> >> +
> >> + if (!dwc)
> >> + return 0;
> >> +
> >> + pm_runtime_get_sync(dwc->usb3_phy->dev);
> >
> > dude, this is wrong :-)
> >
> > look at this:
> >
> > pm_runtime_get() -> dwc3_exynos_runtime_resume() ->
> > pm_runtime_get_sync() -> dwc3_exynos_runtime_resume() -> ...
> >
> > only your clock enalbe should do
> >
> 
> We want to wake up "dwc->usb3_phy" so tried to call pm_runtime_get_sync()
> with "dwc->usb3_phy->dev".
> Missing something ? :-(

oh, my bad. That's the PHY... But we can't really do that for samsung
only. It needs to be done generically for the entire dwc3 core driver,
and for that we need to introduce usb_phy_autopm_get(),
usb_phy_autopm_get_sync() and friends.

Then, from dwc_probe() we call:

phy = usb_get_phy();
usb_phy_autopm_enable(phy);
usb_phy_autopm_get_sync(phy);

or something similar ;-) Bottom line, you shouldn't fiddle with phy->dev
directly.

-- 
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Re: [PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Felipe Balbi]

Hi,

On Mon, Jan 28, 2013 at 05:12:28PM +0530, Vivek Gautam wrote:
> Enabling runtime power management support on samsung-usb3 phy
> and further adding support to turn off the PHY ref_clk PLL.
> It thereby requires PHY ref_clk to be switched between internal
> core clock and external PLL clock.
> 
> Signed-off-by: Vivek Gautam 

this needs to be broken down a bit. I can see three patches at least:
add support for external clock, add support for phy gpio powerdown and
add runtime pm ;-)

> ---
>  drivers/usb/phy/samsung-usb3.c   |  107 +++--
>  drivers/usb/phy/samsung-usbphy.c |   26 +
>  drivers/usb/phy/samsung-usbphy.h |1 +
>  3 files changed, 128 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
> index 29e1321..4dbef15 100644
> --- a/drivers/usb/phy/samsung-usb3.c
> +++ b/drivers/usb/phy/samsung-usb3.c
> @@ -22,8 +22,10 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -32,7 +34,7 @@
>  /*
>   * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock 
> core.
>   */
> -static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
> +static u32 samsung_usb3_phy_set_refclk_int(struct samsung_usbphy *sphy)
>  {
>   u32 reg;
>   u32 refclk;
> @@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct 
> samsung_usbphy *sphy)
>   return reg;
>  }
>  
> -static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
> +/*
> + * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from external 
> PLL.
> + */
> +static u32 samsung_usb3_phy_set_refclk_ext(void)
> +{
> + u32 reg;
> +
> + reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
> + PHYCLKRST_FSEL_PAD_100MHZ |
> + PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
> +
> + return reg;
> +}

I wonder if you really need this small function (likewise for
set_refclk_int()). They don't do much, so you could just inline them on
the only caller.

> @@ -80,7 +97,11 @@ static int samsung_exynos5_usb3_phy_enable(struct 
> samsung_usbphy *sphy)
>  
>   phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
>   /* Select PHY CLK source */
> - phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
> + if (use_ext_clk)
> + phyparam0 |= PHYPARAM0_REF_USE_PAD;
> + else
> + phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
> +
>   /* Set Loss-of-Signal Detector sensitivity */
>   phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
>   phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
> @@ -115,7 +136,10 @@ static int samsung_exynos5_usb3_phy_enable(struct 
> samsung_usbphy *sphy)
>   /* UTMI Power Control */
>   writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
>  
> - phyclkrst = samsung_usb3_phy_set_refclk(sphy);
> + if (use_ext_clk)
> + phyclkrst = samsung_usb3_phy_set_refclk_ext();
> + else
> + phyclkrst = samsung_usb3_phy_set_refclk_int(sphy);
>  
>   phyclkrst |= PHYCLKRST_PORTRESET |
>   /* Digital power supply in normal operating mode */
> @@ -163,7 +187,7 @@ static void samsung_exynos5_usb3_phy_disable(struct 
> samsung_usbphy *sphy)
>   writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
>  }
>  
> -static int samsung_usb3_phy_init(struct usb_phy *phy)
> +static int samsung_exynos5_usb3_phy_init(struct usb_phy *phy, bool 
> use_ext_clk)
>  {
>   struct samsung_usbphy *sphy;
>   unsigned long flags;
> @@ -187,7 +211,7 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
>   samsung_usbphy_set_isolation(sphy, false);
>  
>   /* Initialize usb phy registers */
> - samsung_exynos5_usb3_phy_enable(sphy);
> + samsung_exynos5_usb3_phy_enable(sphy, use_ext_clk);
>  
>   spin_unlock_irqrestore(&sphy->lock, flags);
>  
> @@ -198,6 +222,34 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
>  }
>  
>  /*
> + * Switch  between internal core clock and external oscillator clock
> + * for PHY reference clock
> + */
> +static int samsung_exynos5_usb3phy_clk_switch(struct usb_phy *phy,
> + bool use_ext_clk)
> +{
> + /*
> +  * This will switch PHY refclk from internal core clock
> +  * to external PLL clock when device is in use and vice versa
> +  * when device plunge into runtime suspend mode.
> +  */
> + return samsung_exynos5_usb3_phy_init(phy, use_ext_clk);
> +}
> +
> +/*
> + * The function passed to the usb driver for phy initialization
> + */
> +static int samsung_usb3_phy_init(struct usb_phy *phy)
> +{
> + /*
> +  * We start with using PHY refclk from external PLL,
> +  * once runtime suspend for the device is called this
> +  * will change to internal core clock
> +  */
> + return  samsung_exynos5_usb3_phy_init(phy, true);
> +}
> +
> +/*
>   * The function passed to the usb driver for phy shutdown
>   */
>  static void samsung_usb3

Re: [PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Vivek Gautam]

Hi Balbi,


On Mon, Jan 28, 2013 at 5:17 PM, Felipe Balbi  wrote:
> On Mon, Jan 28, 2013 at 05:12:27PM +0530, Vivek Gautam wrote:
>> Enabling runtime power management on dwc3-exynos to save
>> power and allow its PHY's power to be managed at runtime.
>>
>> Signed-off-by: Vivek Gautam 
>> ---
>>  drivers/usb/dwc3/dwc3-exynos.c |   47 
>> 
>>  1 files changed, 47 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
>> index aae5328..c51e8c1 100644
>> --- a/drivers/usb/dwc3/dwc3-exynos.c
>> +++ b/drivers/usb/dwc3/dwc3-exynos.c
>> @@ -157,11 +157,15 @@ static int dwc3_exynos_probe(struct platform_device 
>> *pdev)
>>   goto err4;
>>   }
>>
>> + pm_runtime_set_active(&pdev->dev);
>> + pm_runtime_enable(&pdev->dev);
>> +
>>   return 0;
>>
>>  err4:
>>   clk_disable(clk);
>>   clk_put(clk);
>> + pm_runtime_disable(&pdev->dev);
>>  err3:
>>   platform_device_put(dwc3);
>>  err1:
>> @@ -174,6 +178,8 @@ static int dwc3_exynos_remove(struct platform_device 
>> *pdev)
>>  {
>>   struct dwc3_exynos  *exynos = platform_get_drvdata(pdev);
>>
>> + pm_runtime_disable(&pdev->dev);
>> +
>>   platform_device_unregister(exynos->dwc3);
>>   platform_device_unregister(exynos->usb2_phy);
>>   platform_device_unregister(exynos->usb3_phy);
>> @@ -186,6 +192,46 @@ static int dwc3_exynos_remove(struct platform_device 
>> *pdev)
>>   return 0;
>>  }
>>
>> +static int dwc3_exynos_runtime_suspend(struct device *dev)
>> +{
>> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
>> + struct platform_device  *pdev_dwc = exynos->dwc3;
>> + struct dwc3 *dwc = NULL;
>> +
>> + dwc = platform_get_drvdata(pdev_dwc);
>> +
>> + if (!dwc)
>> + return 0;
>> +
>> + pm_runtime_put_sync(dwc->usb3_phy->dev);
>> +
>> + clk_disable(exynos->clk);
>> +
>> + return 0;
>> +}
>> +static int dwc3_exynos_runtime_resume(struct device *dev)
>> +{
>> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
>> + struct platform_device  *pdev_dwc = exynos->dwc3;
>> + struct dwc3 *dwc = NULL;
>> +
>> + dwc = platform_get_drvdata(pdev_dwc);
>> +
>> + clk_enable(exynos->clk);
>> +
>> + if (!dwc)
>> + return 0;
>> +
>> + pm_runtime_get_sync(dwc->usb3_phy->dev);
>
> dude, this is wrong :-)
>
> look at this:
>
> pm_runtime_get() -> dwc3_exynos_runtime_resume() ->
> pm_runtime_get_sync() -> dwc3_exynos_runtime_resume() -> ...
>
> only your clock enalbe should do
>

We want to wake up "dwc->usb3_phy" so tried to call pm_runtime_get_sync()
with "dwc->usb3_phy->dev".
Missing something ? :-(




-- 
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Vivek
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Re: [PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Felipe Balbi]

On Mon, Jan 28, 2013 at 05:12:27PM +0530, Vivek Gautam wrote:
> Enabling runtime power management on dwc3-exynos to save
> power and allow its PHY's power to be managed at runtime.
> 
> Signed-off-by: Vivek Gautam 
> ---
>  drivers/usb/dwc3/dwc3-exynos.c |   47 
> 
>  1 files changed, 47 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
> index aae5328..c51e8c1 100644
> --- a/drivers/usb/dwc3/dwc3-exynos.c
> +++ b/drivers/usb/dwc3/dwc3-exynos.c
> @@ -157,11 +157,15 @@ static int dwc3_exynos_probe(struct platform_device 
> *pdev)
>   goto err4;
>   }
>  
> + pm_runtime_set_active(&pdev->dev);
> + pm_runtime_enable(&pdev->dev);
> +
>   return 0;
>  
>  err4:
>   clk_disable(clk);
>   clk_put(clk);
> + pm_runtime_disable(&pdev->dev);
>  err3:
>   platform_device_put(dwc3);
>  err1:
> @@ -174,6 +178,8 @@ static int dwc3_exynos_remove(struct platform_device 
> *pdev)
>  {
>   struct dwc3_exynos  *exynos = platform_get_drvdata(pdev);
>  
> + pm_runtime_disable(&pdev->dev);
> +
>   platform_device_unregister(exynos->dwc3);
>   platform_device_unregister(exynos->usb2_phy);
>   platform_device_unregister(exynos->usb3_phy);
> @@ -186,6 +192,46 @@ static int dwc3_exynos_remove(struct platform_device 
> *pdev)
>   return 0;
>  }
>  
> +static int dwc3_exynos_runtime_suspend(struct device *dev)
> +{
> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
> + struct platform_device  *pdev_dwc = exynos->dwc3;
> + struct dwc3 *dwc = NULL;
> +
> + dwc = platform_get_drvdata(pdev_dwc);
> +
> + if (!dwc)
> + return 0;
> +
> + pm_runtime_put_sync(dwc->usb3_phy->dev);
> +
> + clk_disable(exynos->clk);
> +
> + return 0;
> +}
> +static int dwc3_exynos_runtime_resume(struct device *dev)
> +{
> + struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
> + struct platform_device  *pdev_dwc = exynos->dwc3;
> + struct dwc3 *dwc = NULL;
> +
> + dwc = platform_get_drvdata(pdev_dwc);
> +
> + clk_enable(exynos->clk);
> +
> + if (!dwc)
> + return 0;
> +
> + pm_runtime_get_sync(dwc->usb3_phy->dev);

dude, this is wrong :-)

look at this:

pm_runtime_get() -> dwc3_exynos_runtime_resume() ->
pm_runtime_get_sync() -> dwc3_exynos_runtime_resume() -> ...

only your clock enalbe should do

-- 
balbi


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Description: Digital signature

Re: [PATCH 2/4] USB: dwc3: Adjust runtime pm the dwc3 driver to allow runtime suspend

[Felipe Balbi]

On Mon, Jan 28, 2013 at 05:12:26PM +0530, Vivek Gautam wrote:
> The current code in the dwc3 probe effectively disables runtime pm
> from ever working because it calls a get() that was never put() until
> device removal.  Change the runtime pm code to match the standard
> formula and allow runtime pm to function.
> 
> Note that this doesn't enable full runtime pm on the DWC3 device in
> that the port isn't put into a lower power mode when not used.
> However it does allow users of dwc3 (like dwc3-exynos) to do some
> amount of runtime power management.
> 
> Signed-off-by: Vivek Gautam 
> Signed-off-by: Doug Anderson 
> ---
>  drivers/usb/dwc3/core.c |4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3a4004a..59c2494 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -453,6 +453,7 @@ static int dwc3_probe(struct platform_device *pdev)
>   if (of_get_property(node, "tx-fifo-resize", NULL))
>   dwc->needs_fifo_resize = true;
>  
> + pm_runtime_set_active(dev);

this usage of pm_runtime_set_active() actually makes me a bit scared. At
least OMAP starts with the device switched off, so this will probably
break OMAP at least. OTOH, calling ->runtime_resume() during probe()
might not make that much sense after all, but the way OMAP is
implemented, we won't get clocks turned on if this ->runtime_resume()
method isn't called.

/me starts to wonder whether OMAP implementation is flakey and what
should be done here...

-- 
balbi


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[PATCH 4/4] usb: phy: samsung: Enable runtime power management on samsung-usb3

[Vivek Gautam]

Enabling runtime power management support on samsung-usb3 phy
and further adding support to turn off the PHY ref_clk PLL.
It thereby requires PHY ref_clk to be switched between internal
core clock and external PLL clock.

Signed-off-by: Vivek Gautam 
---
 drivers/usb/phy/samsung-usb3.c   |  107 +++--
 drivers/usb/phy/samsung-usbphy.c |   26 +
 drivers/usb/phy/samsung-usbphy.h |1 +
 3 files changed, 128 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
index 29e1321..4dbef15 100644
--- a/drivers/usb/phy/samsung-usb3.c
+++ b/drivers/usb/phy/samsung-usb3.c
@@ -22,8 +22,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -32,7 +34,7 @@
 /*
  * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock 
core.
  */
-static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
+static u32 samsung_usb3_phy_set_refclk_int(struct samsung_usbphy *sphy)
 {
u32 reg;
u32 refclk;
@@ -65,7 +67,22 @@ static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy 
*sphy)
return reg;
 }
 
-static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
+/*
+ * Sets the phy clk as ref_pad_clk (XusbXTI) which is clock from external PLL.
+ */
+static u32 samsung_usb3_phy_set_refclk_ext(void)
+{
+   u32 reg;
+
+   reg = PHYCLKRST_REFCLKSEL_PAD_REFCLK |
+   PHYCLKRST_FSEL_PAD_100MHZ |
+   PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF;
+
+   return reg;
+}
+
+static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy,
+   bool use_ext_clk)
 {
void __iomem *regs = sphy->regs;
u32 phyparam0;
@@ -80,7 +97,11 @@ static int samsung_exynos5_usb3_phy_enable(struct 
samsung_usbphy *sphy)
 
phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
/* Select PHY CLK source */
-   phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+   if (use_ext_clk)
+   phyparam0 |= PHYPARAM0_REF_USE_PAD;
+   else
+   phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+
/* Set Loss-of-Signal Detector sensitivity */
phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
@@ -115,7 +136,10 @@ static int samsung_exynos5_usb3_phy_enable(struct 
samsung_usbphy *sphy)
/* UTMI Power Control */
writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
 
-   phyclkrst = samsung_usb3_phy_set_refclk(sphy);
+   if (use_ext_clk)
+   phyclkrst = samsung_usb3_phy_set_refclk_ext();
+   else
+   phyclkrst = samsung_usb3_phy_set_refclk_int(sphy);
 
phyclkrst |= PHYCLKRST_PORTRESET |
/* Digital power supply in normal operating mode */
@@ -163,7 +187,7 @@ static void samsung_exynos5_usb3_phy_disable(struct 
samsung_usbphy *sphy)
writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
 }
 
-static int samsung_usb3_phy_init(struct usb_phy *phy)
+static int samsung_exynos5_usb3_phy_init(struct usb_phy *phy, bool use_ext_clk)
 {
struct samsung_usbphy *sphy;
unsigned long flags;
@@ -187,7 +211,7 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
samsung_usbphy_set_isolation(sphy, false);
 
/* Initialize usb phy registers */
-   samsung_exynos5_usb3_phy_enable(sphy);
+   samsung_exynos5_usb3_phy_enable(sphy, use_ext_clk);
 
spin_unlock_irqrestore(&sphy->lock, flags);
 
@@ -198,6 +222,34 @@ static int samsung_usb3_phy_init(struct usb_phy *phy)
 }
 
 /*
+ * Switch  between internal core clock and external oscillator clock
+ * for PHY reference clock
+ */
+static int samsung_exynos5_usb3phy_clk_switch(struct usb_phy *phy,
+   bool use_ext_clk)
+{
+   /*
+* This will switch PHY refclk from internal core clock
+* to external PLL clock when device is in use and vice versa
+* when device plunge into runtime suspend mode.
+*/
+   return samsung_exynos5_usb3_phy_init(phy, use_ext_clk);
+}
+
+/*
+ * The function passed to the usb driver for phy initialization
+ */
+static int samsung_usb3_phy_init(struct usb_phy *phy)
+{
+   /*
+* We start with using PHY refclk from external PLL,
+* once runtime suspend for the device is called this
+* will change to internal core clock
+*/
+   return  samsung_exynos5_usb3_phy_init(phy, true);
+}
+
+/*
  * The function passed to the usb driver for phy shutdown
  */
 static void samsung_usb3_phy_shutdown(struct usb_phy *phy)
@@ -287,6 +339,9 @@ static int samsung_usb3_phy_probe(struct platform_device 
*pdev)
 
platform_set_drvdata(pdev, sphy);
 
+   pm_runtime_set_active(&pdev->dev);
+   pm_runtime_enable(&pdev->dev);
+
return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB3);
 }
 
@@ -296,6 +351,8 @@ static int samsu

[PATCH 3/4] usb: dwc3: exynos: Enable runtime power management

[Vivek Gautam]

Enabling runtime power management on dwc3-exynos to save
power and allow its PHY's power to be managed at runtime.

Signed-off-by: Vivek Gautam 
---
 drivers/usb/dwc3/dwc3-exynos.c |   47 
 1 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index aae5328..c51e8c1 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -157,11 +157,15 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
goto err4;
}
 
+   pm_runtime_set_active(&pdev->dev);
+   pm_runtime_enable(&pdev->dev);
+
return 0;
 
 err4:
clk_disable(clk);
clk_put(clk);
+   pm_runtime_disable(&pdev->dev);
 err3:
platform_device_put(dwc3);
 err1:
@@ -174,6 +178,8 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 {
struct dwc3_exynos  *exynos = platform_get_drvdata(pdev);
 
+   pm_runtime_disable(&pdev->dev);
+
platform_device_unregister(exynos->dwc3);
platform_device_unregister(exynos->usb2_phy);
platform_device_unregister(exynos->usb3_phy);
@@ -186,6 +192,46 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
return 0;
 }
 
+static int dwc3_exynos_runtime_suspend(struct device *dev)
+{
+   struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
+   struct platform_device  *pdev_dwc = exynos->dwc3;
+   struct dwc3 *dwc = NULL;
+
+   dwc = platform_get_drvdata(pdev_dwc);
+
+   if (!dwc)
+   return 0;
+
+   pm_runtime_put_sync(dwc->usb3_phy->dev);
+
+   clk_disable(exynos->clk);
+
+   return 0;
+}
+static int dwc3_exynos_runtime_resume(struct device *dev)
+{
+   struct dwc3_exynos  *exynos = dev_get_drvdata(dev);
+   struct platform_device  *pdev_dwc = exynos->dwc3;
+   struct dwc3 *dwc = NULL;
+
+   dwc = platform_get_drvdata(pdev_dwc);
+
+   clk_enable(exynos->clk);
+
+   if (!dwc)
+   return 0;
+
+   pm_runtime_get_sync(dwc->usb3_phy->dev);
+
+   return 0;
+}
+
+static const struct dev_pm_ops dwc3_exynos_pm_ops = {
+   SET_RUNTIME_PM_OPS(dwc3_exynos_runtime_suspend,
+   dwc3_exynos_runtime_resume, NULL)
+};
+
 #ifdef CONFIG_OF
 static const struct of_device_id exynos_dwc3_match[] = {
{ .compatible = "samsung,exynos-dwc3" },
@@ -200,6 +246,7 @@ static struct platform_driver dwc3_exynos_driver = {
.driver = {
.name   = "exynos-dwc3",
.of_match_table = of_match_ptr(exynos_dwc3_match),
+   .pm = &dwc3_exynos_pm_ops,
},
 };
 
-- 
1.7.6.5

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[PATCH 2/4] USB: dwc3: Adjust runtime pm the dwc3 driver to allow runtime suspend

[Vivek Gautam]

The current code in the dwc3 probe effectively disables runtime pm
from ever working because it calls a get() that was never put() until
device removal.  Change the runtime pm code to match the standard
formula and allow runtime pm to function.

Note that this doesn't enable full runtime pm on the DWC3 device in
that the port isn't put into a lower power mode when not used.
However it does allow users of dwc3 (like dwc3-exynos) to do some
amount of runtime power management.

Signed-off-by: Vivek Gautam 
Signed-off-by: Doug Anderson 
---
 drivers/usb/dwc3/core.c |4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3a4004a..59c2494 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -453,6 +453,7 @@ static int dwc3_probe(struct platform_device *pdev)
if (of_get_property(node, "tx-fifo-resize", NULL))
dwc->needs_fifo_resize = true;
 
+   pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
pm_runtime_forbid(dev);
@@ -517,6 +518,7 @@ static int dwc3_probe(struct platform_device *pdev)
goto err2;
}
 
+   pm_runtime_put(dev);
pm_runtime_allow(dev);
 
return 0;
@@ -543,6 +545,7 @@ err1:
 
 err0:
dwc3_free_event_buffers(dwc);
+   pm_runtime_disable(&pdev->dev);
 
return ret;
 }
@@ -554,7 +557,6 @@ static int dwc3_remove(struct platform_device *pdev)
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-   pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
 
dwc3_debugfs_exit(dwc);
-- 
1.7.6.5

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[PATCH 1/4] usb: xhci: Enable runtime pm in xhci-plat

[Vivek Gautam]

By enabling runtime pm in this driver is allows users of xhci-plat to
enter into runtime pm.  This is not full runtime pm support (AKA
xhci-plat doesn't actually power anything off when in runtime suspend
mode) but just basic enablement.

Signed-off-by: Vivek Gautam 
Signed-off-by: Doug Anderson 
---
 drivers/usb/host/xhci-plat.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index df90fe5..6ad7cfb 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -139,6 +139,10 @@ static int xhci_plat_probe(struct platform_device *pdev)
goto dealloc_usb2_hcd;
}
 
+   pm_runtime_set_active(&pdev->dev);
+   pm_runtime_enable(&pdev->dev);
+   pm_runtime_forbid(&pdev->dev);
+
/*
 * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset)
 * is called by usb_add_hcd().
@@ -149,10 +153,13 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (ret)
goto put_usb3_hcd;
 
+   pm_runtime_allow(&pdev->dev);
+
return 0;
 
 put_usb3_hcd:
usb_put_hcd(xhci->shared_hcd);
+   pm_runtime_disable(&pdev->dev);
 
 dealloc_usb2_hcd:
usb_remove_hcd(hcd);
@@ -174,6 +181,8 @@ static int xhci_plat_remove(struct platform_device *dev)
struct usb_hcd  *hcd = platform_get_drvdata(dev);
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 
+   pm_runtime_disable(&dev->dev);
+
usb_remove_hcd(xhci->shared_hcd);
usb_put_hcd(xhci->shared_hcd);
 
-- 
1.7.6.5

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[PATCH 0/4] usb: dwc3/xhci: Enable runtime power management

[Vivek Gautam]

This patch-series enables runtime power management on xhci-plat,
dwc3-core, dwc3-exynos as well as on samsung-usb3 type PHY.
This allows usb 3.0 host ports to be power managed at runtime.
We also turn off the PHY ref_clk PLL, which supplies reference clock
to USB3 type phy, when ports are not in use.

This patch-series is based on 'usb-next' with follwing patches:

usb: phy: samsung: Introducing usb phy driver for hsotg
usb: phy: s3c-hsotg: adding phy driver support

usb: phy: samsung: Add support to set pmu isolation
ARM: EXYNOS: Update & move usb-phy types to generic include layer
usb: phy: samsung: Add host phy support to samsung-phy driver
USB: ehci-s5p: Add phy driver support
USB: ohci-exynos: Add phy driver support
usb: phy: samsung: Remove __devinit, __devexit_p and __exit annotations

[PATCH v4 1/2] usb: phy: samsung: Common out the generic stuff
[PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller

Vivek Gautam (4):
  usb: xhci: Enable runtime pm in xhci-plat
  USB: dwc3: Adjust runtime pm the dwc3 driver to allow runtime suspend
  usb: dwc3: exynos: Enable runtime power management
  usb: phy: samsung: Enable runtime power management on samsung-usb3

 drivers/usb/dwc3/core.c  |4 +-
 drivers/usb/dwc3/dwc3-exynos.c   |   47 +
 drivers/usb/host/xhci-plat.c |9 +++
 drivers/usb/phy/samsung-usb3.c   |  107 +++--
 drivers/usb/phy/samsung-usbphy.c |   26 +
 drivers/usb/phy/samsung-usbphy.h |1 +
 6 files changed, 187 insertions(+), 7 deletions(-)

-- 
1.7.6.5

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[PATCH v4 2/2] usb: phy: samsung: Add PHY support for USB 3.0 controller

[Vivek Gautam]

Adding PHY driver support for USB 3.0 controller for Samsung's
SoCs.

Signed-off-by: Vivek Gautam 
---

Changes from v3:
 - Making SAMSUNG_USB3PHY dependent on SAMSUNG_USBPHY.
 - Adding USB_DWC3 to dependencies of SAMSUNG_USB2PHY since
   dwc3 controller also looks for USB2 type PHY.

 drivers/usb/phy/Kconfig  |   11 +-
 drivers/usb/phy/Makefile |1 +
 drivers/usb/phy/samsung-usb3.c   |  349 ++
 drivers/usb/phy/samsung-usbphy.h |   81 +
 4 files changed, 441 insertions(+), 1 deletions(-)
 create mode 100644 drivers/usb/phy/samsung-usb3.c

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index cc0d230..9325a95 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -52,14 +52,23 @@ config SAMSUNG_USBPHY
help
  Enable this to support Samsung USB phy controllers for Samsung
  SoCs.
+ Further enable USB 2.0 type PHY or USB 3.0 type PHY as required
+ for USB controllers in use.
 
 if SAMSUNG_USBPHY
 
 config SAMSUNG_USB2PHY
bool "Samsung USB 2.0 PHY controller Driver"
-   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS || USB_DWC3
help
  Enable this to support Samsung USB 2.0 (High Speed) phy controller
  for Samsung SoCs.
 
+config SAMSUNG_USB3PHY
+   bool "Samsung USB 3.0 PHY controller Driver"
+   depends on USB_DWC3
+   help
+ Enable this to support Samsung USB 3.0 (Super Speed) phy controller
+ for samsung SoCs.
+
 endif
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index 7ba9862..b8505ac 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_USB_EHCI_TEGRA)  += tegra_usb_phy.o
 obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
 obj-$(CONFIG_SAMSUNG_USBPHY)   += samsung-usbphy.o
 obj-$(CONFIG_SAMSUNG_USB2PHY)  += samsung-usb2.o
+obj-$(CONFIG_SAMSUNG_USB3PHY)  += samsung-usb3.o
diff --git a/drivers/usb/phy/samsung-usb3.c b/drivers/usb/phy/samsung-usb3.c
new file mode 100644
index 000..29e1321
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb3.c
@@ -0,0 +1,349 @@
+/* linux/drivers/usb/phy/samsung-usb3.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *  http://www.samsung.com
+ *
+ * Author: Vivek Gautam 
+ *
+ * Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "samsung-usbphy.h"
+
+/*
+ * Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock 
core.
+ */
+static u32 samsung_usb3_phy_set_refclk(struct samsung_usbphy *sphy)
+{
+   u32 reg;
+   u32 refclk;
+
+   refclk = sphy->ref_clk_freq;
+
+   reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
+   PHYCLKRST_FSEL(refclk);
+
+   switch (refclk) {
+   case FSEL_CLKSEL_50M:
+   reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+   PHYCLKRST_SSC_REFCLKSEL(0x00));
+   break;
+   case FSEL_CLKSEL_20M:
+   reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+   PHYCLKRST_SSC_REFCLKSEL(0x00));
+   break;
+   case FSEL_CLKSEL_19200K:
+   reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+   PHYCLKRST_SSC_REFCLKSEL(0x88));
+   break;
+   case FSEL_CLKSEL_24M:
+   default:
+   reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+   PHYCLKRST_SSC_REFCLKSEL(0x88));
+   break;
+   }
+
+   return reg;
+}
+
+static int samsung_exynos5_usb3_phy_enable(struct samsung_usbphy *sphy)
+{
+   void __iomem *regs = sphy->regs;
+   u32 phyparam0;
+   u32 phyparam1;
+   u32 linksystem;
+   u32 phybatchg;
+   u32 phytest;
+   u32 phyclkrst;
+
+   /* Reset USB 3.0 PHY */
+   writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
+
+   phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
+   /* Select PHY CLK source */
+   phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
+   /* Set Loss-of-Signal Detector sensitivity */
+   phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+   phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
+   writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
+
+   writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
+
+   /*
+* Setting the Frame length Adj value[6:1] to default 0x20

[PATCH v4 1/2] usb: phy: samsung: Common out the generic stuff

[Vivek Gautam]

Moving register and structure definitions to header file,
and keeping the generic functions to be used across
multiple PHYs in common file "samsung-usbphy.c".
Also renaming the usb 2.0 phy driver to "samsung-usb2.c"

Signed-off-by: Vivek Gautam 
---

Changes from v3:
 - Using separate config SAMSUNG_USB2PHY dependent on
   SAMSUNG_USBPHY for samsung-usb2 type PHY controller.

 drivers/usb/phy/Kconfig  |   14 +-
 drivers/usb/phy/Makefile |1 +
 drivers/usb/phy/samsung-usb2.c   |  511 +++
 drivers/usb/phy/samsung-usbphy.c |  714 +-
 drivers/usb/phy/samsung-usbphy.h |  247 +
 5 files changed, 778 insertions(+), 709 deletions(-)
 create mode 100644 drivers/usb/phy/samsung-usb2.c
 create mode 100644 drivers/usb/phy/samsung-usbphy.h

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index fae4d08..cc0d230 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -48,8 +48,18 @@ config USB_RCAR_PHY
 
 config SAMSUNG_USBPHY
bool "Samsung USB PHY controller Driver"
-   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
select USB_OTG_UTILS
help
- Enable this to support Samsung USB phy controller for samsung
+ Enable this to support Samsung USB phy controllers for Samsung
  SoCs.
+
+if SAMSUNG_USBPHY
+
+config SAMSUNG_USB2PHY
+   bool "Samsung USB 2.0 PHY controller Driver"
+   depends on USB_S3C_HSOTG || USB_EHCI_S5P || USB_OHCI_EXYNOS
+   help
+ Enable this to support Samsung USB 2.0 (High Speed) phy controller
+ for Samsung SoCs.
+
+endif
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index ec304f6..7ba9862 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_MV_U3D_PHY)  += mv_u3d_phy.o
 obj-$(CONFIG_USB_EHCI_TEGRA)   += tegra_usb_phy.o
 obj-$(CONFIG_USB_RCAR_PHY) += rcar-phy.o
 obj-$(CONFIG_SAMSUNG_USBPHY)   += samsung-usbphy.o
+obj-$(CONFIG_SAMSUNG_USB2PHY)  += samsung-usb2.o
diff --git a/drivers/usb/phy/samsung-usb2.c b/drivers/usb/phy/samsung-usb2.c
new file mode 100644
index 000..9a9d1d0
--- /dev/null
+++ b/drivers/usb/phy/samsung-usb2.c
@@ -0,0 +1,511 @@
+/* linux/drivers/usb/phy/samsung-usb2.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *  http://www.samsung.com
+ *
+ * Author: Praveen Paneri 
+ *
+ * Samsung USB2.0 PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
+ * OHCI-EXYNOS controllers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "samsung-usbphy.h"
+
+int samsung_usbphy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+   if (!otg)
+   return -ENODEV;
+
+   if (!otg->host)
+   otg->host = host;
+
+   return 0;
+}
+
+static bool exynos5_phyhost_is_on(void *regs)
+{
+   u32 reg;
+
+   reg = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+   return !(reg & HOST_CTRL0_SIDDQ);
+}
+
+static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
+{
+   void __iomem *regs = sphy->regs;
+   u32 phyclk = sphy->ref_clk_freq;
+   u32 phyhost;
+   u32 phyotg;
+   u32 phyhsic;
+   u32 ehcictrl;
+   u32 ohcictrl;
+
+   /*
+* phy_usage helps in keeping usage count for phy
+* so that the first consumer enabling the phy is also
+* the last consumer to disable it.
+*/
+
+   atomic_inc(&sphy->phy_usage);
+
+   if (exynos5_phyhost_is_on(regs)) {
+   dev_info(sphy->dev, "Already power on PHY\n");
+   return;
+   }
+
+   /* Host configuration */
+   phyhost = readl(regs + EXYNOS5_PHY_HOST_CTRL0);
+
+   /* phy reference clock configuration */
+   phyhost &= ~HOST_CTRL0_FSEL_MASK;
+   phyhost |= HOST_CTRL0_FSEL(phyclk);
+
+   /* host phy reset */
+   phyhost &= ~(HOST_CTRL0_PHYSWRST |
+   HOST_CTRL0_PHYSWRSTALL |
+   HOST_CTRL0_SIDDQ |
+   /* Enable normal mode of operation */
+   HOST_CTRL0_FORCESUSPEND |
+   HOST_CTRL0_FORCESLEEP);
+
+   /* Link reset */
+   phyhost |= (HOST_CTRL0_LINKSWRST |
+   HOST_CTRL0_UTMISWRST |
+   /* COMMON Block configuration during suspend */
+   HOST_CTRL0_COMMONON_N)

Re: [PATCH 1/4] ARM: dts: add support for hdmi to exynos4

[Rahul Sharma]

Hi Tomasz,

On Mon, Jan 28, 2013 at 2:14 PM, Tomasz Figa  wrote:
> Hi Rahul,
>
> On Monday 28 of January 2013 12:25:27 Rahul Sharma wrote:
>> Hi Thomas,
>>
>> On Fri, Jan 25, 2013 at 11:10 PM, Thomas Abraham
>>
>>  wrote:
>> > On 25 January 2013 02:39, Rahul Sharma 
> wrote:
>> >> Signed-off-by: Rahul Sharma 
>> >>
>> >> Conflicts:
>> >> arch/arm/mach-exynos/mach-exynos4-dt.c
>> >>
>> >> ---
>> >>
>> >>  arch/arm/boot/dts/exynos4.dtsi | 7 +++
>> >>  arch/arm/mach-exynos/mach-exynos4-dt.c | 2 ++
>> >>  2 files changed, 9 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/exynos4.dtsi
>> >> b/arch/arm/boot/dts/exynos4.dtsi index e1347fc..6c2c79d 100644
>> >> --- a/arch/arm/boot/dts/exynos4.dtsi
>> >> +++ b/arch/arm/boot/dts/exynos4.dtsi
>> >> @@ -289,4 +289,11 @@
>> >>
>> >> interrupts = <0 34 0>;
>> >>
>> >> };
>> >>
>> >> };
>> >>
>> >> +
>> >> +   hdmi {
>> >> +   compatible = "samsung,exynos4-hdmi14";
>> >> +   reg = <0x12D0 0x7>;
>> >> +   interrupts = <0 95 0>;
>> >> +   hpd-gpio = <&gpx3 7 0xf 1 3>;
>> >
>> > This is using the older gpio dt bindings but exynos4 has started using
>> > the pinctrl bindings. So this is not sufficient to do the
>> > pinmux/pinconfig settings on Exynos4.
>> >
>> > Thanks,
>> > Thomas.
>>
>> I have chosen this as exynos5 DT using it in same way and parsed by
>> common code in driver for exy4 and 5. Secondly, one-time initial
>> configuration is sufficient for
>> hdmi hpd-gpio. Please share your opinion.
>
> Exynos4 SoCs use pin control for pin mux configuration, which implies
> different GPIO specifiers than what you used. On Exynos4 generic GPIO
> specifiers are used:
>
> <&gpio-controller pin flags>
>
> As you can see, it does not contain pin mux configuration, which must be
> configured if special function is to be used. In case of EINTs and
> input/output functions, they are configured automatically, respectively by
> request_irq (with appropriate interrupt trigger flag) and gpio_direction_*.
>
> Keep in mind that Exynos5 will be eventually moved to pin control as well
> and its old GPIO bindings will be dropped as they are only temporary.
>
> Best regards,
> Tomasz
>

Since Exynos5 pinctrl is not yet merged, either I need to add "hpd-
gpio" in non-pinctrl way and keep the parsing code (in driver) same
for exynos4 and 5, as I have done in posted patch. This is same for
exynos5.
Or, I need to parse gpio information in a two different manners for
the two SoC series.

It will remain as a special case till we have exynos5 pinctrl driver. IMO,
above code looks better till I can provide same solution for both,
exynos4 & exynos5.

regards,
Rahul Sharma.
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Re: [PATCH 5/6] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs

[Mark Rutland]

On Fri, Jan 25, 2013 at 07:15:48PM +, Kukjin Kim wrote:
> Tomasz Figa wrote:
> 
> [...]
> 
> > > Well, the number of CPU types does not grow rapidly.  It will be much
> > > less than one per SoC -- so keeping the list up to date shouldn't be
> > > that much effort.
> > >
> > > For ARM1176JZF-S, it could make sense for the comatible list to be
> > >
> > >   "arm,arm1176jzf-s", "arm,arm1176"
> > >
> > > ...since the differences between 1176 variants are software probeable
> > > (i.e., whether there is an FPU or not).  AFAIK the J, Z apply to all
> > > ARM1176, and the -S (synthesisable RTL) is nothing to do with software.
> > > The kernel probably only really needs to know "arm,arm1176".
> > 
> > OK. So the conclusion is that I should change the cpus node to following:
> > 
> >cpus {
> >cpu {
> 
> cpu@0 { ?

As the CPU has no MPIDR, and thus doesn't have a reg property, there's no reason
to have a unit address. Just "cpu" should be fine.

> 
> >compatible = "arm,arm1176jzf-s", "arm,arm1176";
> >};
> >};
> > 
> > Am I right?
> > 
> I think so :-)
> 
> - Kukjin
> 

As Dave pointed out, the "jzf-s" portion might be superfluous. It's worth
having the "arm,arm1176", though.

Thanks,
Mark.

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Re: [PATCH 1/4] ARM: dts: add support for hdmi to exynos4

[Tomasz Figa]

Hi Rahul,

On Monday 28 of January 2013 12:25:27 Rahul Sharma wrote:
> Hi Thomas,
> 
> On Fri, Jan 25, 2013 at 11:10 PM, Thomas Abraham
> 
>  wrote:
> > On 25 January 2013 02:39, Rahul Sharma  
wrote:
> >> Signed-off-by: Rahul Sharma 
> >> 
> >> Conflicts:
> >> arch/arm/mach-exynos/mach-exynos4-dt.c
> >> 
> >> ---
> >> 
> >>  arch/arm/boot/dts/exynos4.dtsi | 7 +++
> >>  arch/arm/mach-exynos/mach-exynos4-dt.c | 2 ++
> >>  2 files changed, 9 insertions(+)
> >> 
> >> diff --git a/arch/arm/boot/dts/exynos4.dtsi
> >> b/arch/arm/boot/dts/exynos4.dtsi index e1347fc..6c2c79d 100644
> >> --- a/arch/arm/boot/dts/exynos4.dtsi
> >> +++ b/arch/arm/boot/dts/exynos4.dtsi
> >> @@ -289,4 +289,11 @@
> >> 
> >> interrupts = <0 34 0>;
> >> 
> >> };
> >> 
> >> };
> >> 
> >> +
> >> +   hdmi {
> >> +   compatible = "samsung,exynos4-hdmi14";
> >> +   reg = <0x12D0 0x7>;
> >> +   interrupts = <0 95 0>;
> >> +   hpd-gpio = <&gpx3 7 0xf 1 3>;
> > 
> > This is using the older gpio dt bindings but exynos4 has started using
> > the pinctrl bindings. So this is not sufficient to do the
> > pinmux/pinconfig settings on Exynos4.
> > 
> > Thanks,
> > Thomas.
> 
> I have chosen this as exynos5 DT using it in same way and parsed by
> common code in driver for exy4 and 5. Secondly, one-time initial
> configuration is sufficient for
> hdmi hpd-gpio. Please share your opinion.

Exynos4 SoCs use pin control for pin mux configuration, which implies 
different GPIO specifiers than what you used. On Exynos4 generic GPIO 
specifiers are used:

<&gpio-controller pin flags>

As you can see, it does not contain pin mux configuration, which must be 
configured if special function is to be used. In case of EINTs and 
input/output functions, they are configured automatically, respectively by 
request_irq (with appropriate interrupt trigger flag) and gpio_direction_*.

Keep in mind that Exynos5 will be eventually moved to pin control as well 
and its old GPIO bindings will be dropped as they are only temporary.

Best regards,
Tomasz

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Re: [PATCH 2/4] ARM: dts: add support for mixer to exynos4

[Tomasz Figa]

Hi Rahul, Sylwester,

On Monday 28 of January 2013 12:14:38 Rahul Sharma wrote:
> On Mon, Jan 28, 2013 at 2:34 AM, Sylwester Nawrocki
> 
>  wrote:
> > On 01/25/2013 11:39 AM, Rahul Sharma wrote:
> >> diff --git a/arch/arm/boot/dts/exynos4.dtsi
> >> b/arch/arm/boot/dts/exynos4.dtsi
> >> index 6c2c79d..07cb7d4 100644
> >> --- a/arch/arm/boot/dts/exynos4.dtsi
> >> +++ b/arch/arm/boot/dts/exynos4.dtsi
> >> @@ -296,4 +296,12 @@
> >> 
> >> interrupts =<0 95 0>;
> >> hpd-gpio =<&gpx3 7 0xf 1 3>;
> >> 
> >> };
> >> 
> >> +
> >> +   mixer: mixer {
> >> +   compatible = "samsung,exynos4-mixer";
> > 
> > I'm afraid this compatible property it too generic. Is the video mixer
> > IP really identical an all the Exynos4 series SoCs ?
> 
> It is same in Exynos4210, 4212 and 4412.

The convention is to use the name of SoC on which this IP version appeared 
first. In this case it would be samsung,exynos4210-mixer.

Best regards,
Tomasz

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