Re: s3c24xx pinctrl help
Hi Heiko, On Friday 08 of March 2013 15:38:04 Heiko Stübner wrote: > Hi Thomas, > > taking you up on your offer of helping, I would be cool if you could > simply give me a push in the right direction :-) . > > > From what I've seen so far, the bank handling itself is very similar > between exynos and s3c24xx as the underlying structures already handle > multiple widths of the register contents. More interesting is the eint > handling around which I couldn't wrap my head yet. > > The basic structure is again similar with special eint registers, but > adds some quirks. EINT banks are gpf (8 eints) and gpg (8 or 16 eints > depending on the SoC). > > The current way on Exynos seems to be to mark the offset in the eint > register and attach an irq_domain to the bank, which gets mapped to the > eints starting at the offset. The eints seem to have a parent interrupt > that is provided via the dt. > > On the S3C24xx the gpg bank is doing this similar but gpf is very > strange. > > The first half of the bank (gpf0 to gpf3) is not handled in eintpend > registers but in the main interrupt controller (bits 0 to 3), while the > second half of gpf is handled in eintpend. The new interrupt > declaration might show this better, which can be found at [0]. > > An exception is the s3c2412 which adds still another quirk where each > interrupt of gpf0 to gpf3 is represented in both the normal intc and > eint registers, again for reference probably easier to see in [1]. > > > So I'm still quite stumped on how this could fit into the current > framework and would be really glad for some small pointers :-) I wonder if some of my patches for pinctrl on S3C64xx might be helpful: https://github.com/tom3q/linux/commits/v3.8-s3c64xx-dt-pinctrl Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
s3c24xx pinctrl help
Hi Thomas, taking you up on your offer of helping, I would be cool if you could simply give me a push in the right direction :-) . >From what I've seen so far, the bank handling itself is very similar between exynos and s3c24xx as the underlying structures already handle multiple widths of the register contents. More interesting is the eint handling around which I couldn't wrap my head yet. The basic structure is again similar with special eint registers, but adds some quirks. EINT banks are gpf (8 eints) and gpg (8 or 16 eints depending on the SoC). The current way on Exynos seems to be to mark the offset in the eint register and attach an irq_domain to the bank, which gets mapped to the eints starting at the offset. The eints seem to have a parent interrupt that is provided via the dt. On the S3C24xx the gpg bank is doing this similar but gpf is very strange. The first half of the bank (gpf0 to gpf3) is not handled in eintpend registers but in the main interrupt controller (bits 0 to 3), while the second half of gpf is handled in eintpend. The new interrupt declaration might show this better, which can be found at [0]. An exception is the s3c2412 which adds still another quirk where each interrupt of gpf0 to gpf3 is represented in both the normal intc and eint registers, again for reference probably easier to see in [1]. So I'm still quite stumped on how this could fit into the current framework and would be really glad for some small pointers :-) Thanks Heiko [0] https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/tree/arch/arm/mach-s3c24xx/irq.c?h=next/irq-s3c24xx-2&id=17453dd2e7df20612770ebbf1ab5d506a432210c#n574 [1] https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/tree/arch/arm/mach-s3c24xx/irq.c?h=next/irq-s3c24xx-2&id=17453dd2e7df20612770ebbf1ab5d506a432210c#n712 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 12/12] mipi-csis: Enable all interrupts for fimc-is usage
FIMC-IS firmware needs all the MIPI-CSIS interrupts to be enabled. This patch enables all those MIPI interrupts. Signed-off-by: Arun Kumar K --- drivers/media/platform/s5p-fimc/mipi-csis.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c b/drivers/media/platform/s5p-fimc/mipi-csis.c index debda7c..11eef67 100644 --- a/drivers/media/platform/s5p-fimc/mipi-csis.c +++ b/drivers/media/platform/s5p-fimc/mipi-csis.c @@ -64,7 +64,7 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)"); /* Interrupt mask */ #define S5PCSIS_INTMSK 0x10 -#define S5PCSIS_INTMSK_EN_ALL 0xf000103f +#define S5PCSIS_INTMSK_EN_ALL 0xfc00103f #define S5PCSIS_INTMSK_EVEN_BEFORE (1 << 31) #define S5PCSIS_INTMSK_EVEN_AFTER (1 << 30) #define S5PCSIS_INTMSK_ODD_BEFORE (1 << 29) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 11/12] exynos-fimc-is: Adds the Kconfig and Makefile
Modifies the exynos5-is Makefile and Kconfig to include the new fimc-is driver. Signed-off-by: Arun Kumar K Signed-off-by: Kilyeon Im --- drivers/media/platform/exynos5-is/Kconfig | 12 drivers/media/platform/exynos5-is/Makefile |3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig index 7aacf3b..588103e 100644 --- a/drivers/media/platform/exynos5-is/Kconfig +++ b/drivers/media/platform/exynos5-is/Kconfig @@ -5,3 +5,15 @@ config VIDEO_SAMSUNG_EXYNOS5_MDEV This is a v4l2 based media controller driver for Exynos5 SoC. +if VIDEO_SAMSUNG_EXYNOS5_MDEV + +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS + tristate "Samsung Exynos5 SoC FIMC-IS driver" + depends on VIDEO_V4L2_SUBDEV_API + depends on VIDEO_SAMSUNG_EXYNOS5_MDEV + select VIDEOBUF2_DMA_CONTIG + help + This is a v4l2 driver for Samsung Exynos5 SoC series Imaging + subsystem known as FIMC-IS. + +endif #VIDEO_SAMSUNG_EXYNOS5_MDEV diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile index 472d8e1..e5003d0 100644 --- a/drivers/media/platform/exynos5-is/Makefile +++ b/drivers/media/platform/exynos5-is/Makefile @@ -1,4 +1,7 @@ ccflags-y += -Idrivers/media/platform/s5p-fimc +exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o fimc-is-sensor.o +exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o exynos-mdevice-objs := exynos5-mdev.o +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_MDEV) += exynos-mdevice.o -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 10/12] exynos-fimc-is: Adds the hardware interface module
The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
.../media/platform/exynos5-is/fimc-is-interface.c | 1003
.../media/platform/exynos5-is/fimc-is-interface.h | 130 +++
2 files changed, 1133 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..2537220
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,1003 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg, unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ switch (index) {
+ case INTR_GENERAL:
+ msg->id = 0;
+ msg->command = com_regs->ihcmd;
+ msg->instance = com_regs->ihc_sensorid;
+ msg->parameter1 = com_regs->ihc_param1;
+ msg->parameter2 = com_regs->ihc_param2;
+ msg->parameter3 = com_regs->ihc_param3;
+ msg->parameter4 = com_regs->ihc_param4;
+ break;
+ case INTR_SCC_FDONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scc_sensor_id;
+ msg->parameter1 = com_regs->scc_param1;
+ msg->parameter2 = com_regs->scc_param2;
+ msg->parameter3 = com_regs->scc_param3;
+ msg->parameter4 = 0;
+ break;
+ case INTR_SCP_FDONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scp_sensor_id;
+ msg->parameter1 = com_regs->scp_param1;
+ msg->parameter2 = com_regs->scp_param2;
+ msg->parameter3 = com_regs->scp_param3;
+ msg->parameter4 = 0;
+ break;
+ case INTR_META_DONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->meta_sensor_id;
+ msg->parameter1 = com_regs->meta_param1;
+ msg->parameter2 = 0;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ break;
+ case INTR_SHOT_DONE:
+ msg->id = 0;
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->shot_sensor_id;
+ msg->parameter1 = com_regs->shot_param1;
+ msg->parameter2 = com_regs->shot_param2;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ break;
+ default:
+ msg->id = 0;
+ msg->command = 0;
+ msg->instance = 0;
+ msg->parameter1 = 0;
+ msg->parameter2 = 0;
+ msg->parameter3 = 0;
+ msg->parameter4 = 0;
+ is_err("unknown command getting\n");
+ break;
+ }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+ unsigned int status;
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+ com_regs->scc_iflag |
+ com_regs->scp_iflag |
+ com_regs->meta_iflag |
+ com_regs->shot_iflag;
+
+ return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ set_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ clear_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ int ret = 0;
+
[RFC 08/12] exynos-fimc-is: Adds scaler subdev
FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
drivers/media/platform/exynos5-is/fimc-is-scaler.c | 595
drivers/media/platform/exynos5-is/fimc-is-scaler.h | 107
2 files changed, 702 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..86ac9b8
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,595 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DEBUG
+#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
+
+#include
+#include
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+ {
+ .name = "YUV 4:2:0 3p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .depth = {8, 2, 2},
+ .num_planes = 3,
+ },
+ {
+ .name = "YUV 4:2:0 2p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .depth = {8, 4},
+ .num_planes = 2,
+ },
+ {
+ .name = "YUV 4:2:2 1p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .depth = {16},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ }
+ return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ /* Scaler start */
+ ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+ ctx->scaler_id,
+ (unsigned int **)ctx->buf_paddr,
+ ctx->num_buffers,
+ ctx->fmt->num_planes);
+ if (ret) {
+ is_err("Scaler start failed.\n");
+ return -EINVAL;
+ }
+
+ set_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ /* Scaler stop */
+ ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+ if (ret)
+ is_dbg(3, "Scaler already stopped.\n");
+
+ clear_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_fmt *fmt = ctx->fmt;
+ unsigned int wh;
+ int i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = ctx->width * ctx->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = ctx->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+ struct fimc_is_fmt *fmt;
+ int i;
+
+ buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+ /* Initialize buffer */
+ buf->vb = vb;
+ fmt = ctx->fmt;
+ for (i = 0; i < fmt->num_planes; i++)
+ buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+ ctx->cap_buf_cnt++;
+ return 0;
+}
+
+static void scaler_video_capture_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &ctx->capture_bufs[vb->v4l2_buf.index];
+
+ /* Add buffer to the wait queue */
+ is_dbg(5, "Add buffer %d in Scaler %d
[RFC 07/12] exynos-fimc-is: Adds isp subdev
fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
drivers/media/platform/exynos5-is/fimc-is-isp.c | 546 +++
drivers/media/platform/exynos5-is/fimc-is-isp.h | 88
2 files changed, 634 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..e68e936
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,546 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+
+#include "fimc-is.h"
+
+static struct fimc_is_fmt formats[] = {
+ {
+ .name = "Bayer GR-BG 8bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .depth = {8},
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 10bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .depth = {10},
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 12bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .depth = {12},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ }
+ return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ /* Set state to RUNNING */
+ set_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ clear_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_fmt *fmt = isp->fmt;
+ unsigned int wh, i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = isp->width * isp->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = isp->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &isp->output_bufs[vb->v4l2_buf.index];
+ /* Initialize buffer */
+ buf->vb = vb;
+ buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ isp->out_buf_cnt++;
+ return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ buf = &isp->output_bufs[vb->v4l2_buf.index];
+
+ fimc_is_pipeline_buf_lock(isp->pipeline);
+ fimc_is_isp_wait_queue_add(isp, buf);
+ fimc_is_pipeline_buf_unlock(isp->pipeline);
+
+ /* Call shot command */
+ fimc_is_pipeline_shot(isp->pipeline);
+}
+
+static void isp_lock(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ mutex_lock(&isp->video_lock);
+}
+
+static void isp_unlock(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ mutex_unlock(&isp->video_lock);
+}
+
+static const struct vb2_ops isp_video_output_qops = {
+ .queue_setup = isp_video_output_queue_setup,
+ .buf_init= isp_video_output_buffer_init,
+ .buf_queue = isp_video_output_buffer_queue,
+ .wait_prepare= isp_unlock,
+ .wait_finish = isp_lock,
+ .start_streaming = isp_video_output_start_streaming,
+ .stop_streaming = isp_video_output_s
[RFC 06/12] exynos-fimc-is: Adds the sensor subdev
FIMC-IS uses certain sensors which are exclusively controlled
from the IS firmware. This patch adds the sensor subdev for the
fimc-is sensors.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
drivers/media/platform/exynos5-is/fimc-is-sensor.c | 337
drivers/media/platform/exynos5-is/fimc-is-sensor.h | 170 ++
2 files changed, 507 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..c031493
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,337 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ * Kil-yeon Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "fimc-is-sensor.h"
+#include "fimc-is.h"
+
+static char *sensor_clock_name[] = {
+ [SCLK_BAYER]= "sclk_bayer",
+ [SCLK_CAM0] = "sclk_cam0",
+ [SCLK_CAM1] = "sclk_cam1",
+};
+
+static struct fimc_is_sensor_info sensor_info[] = {
+ [SENSOR_S5K4E5] = {
+ .sensor_id = SENSOR_S5K4E5,
+ .sensor_name = "samsung,s5k4e5",
+ .pixel_width = SENSOR_4E5_WIDTH + 16,
+ .pixel_height = SENSOR_4E5_HEIGHT + 10,
+ .active_width = SENSOR_4E5_WIDTH,
+ .active_height = SENSOR_4E5_HEIGHT,
+ .max_framerate = 30,
+ .setfile_name = "setfile_4e5.bin",
+ .ext = {
+ .actuator_con = {
+ .product_name = ACTUATOR_NAME_DW,
+ .peri_type = SE_I2C,
+ .peri_setting.i2c.channel = SENSOR_CONTROL_I2C0,
+ },
+ .flash_con = {
+ .product_name = FLADRV_NAME_KTD267,
+ .peri_type = SE_GPIO,
+ .peri_setting.gpio.first_gpio_port_no = 1,
+ .peri_setting.gpio.second_gpio_port_no = 2,
+ },
+ .from_con.product_name = FROMDRV_NAME_NOTHING,
+ .mclk = 0,
+ .mipi_lane_num = 0,
+ .mipi_speed = 0,
+ .fast_open_sensor = 0,
+ .self_calibration_mode = 0,
+ },
+
+ },
+ [SENSOR_S5K6A3] = {
+ .sensor_id = SENSOR_S5K6A3,
+ .sensor_name = "samsung,s5k6a3",
+ .pixel_width = SENSOR_6A3_WIDTH + 16,
+ .pixel_height = SENSOR_6A3_HEIGHT + 10,
+ .active_width = SENSOR_6A3_WIDTH,
+ .active_height = SENSOR_6A3_HEIGHT,
+ .max_framerate = 30,
+ .setfile_name = "setfile_6a3.bin",
+ },
+};
+
+/* Sensor supported formats */
+static struct v4l2_mbus_framefmt sensor_formats[FIMC_IS_MAX_SENSORS] = {
+ [SENSOR_S5K4E5] = {
+ .width = SENSOR_4E5_WIDTH + 16,
+ .height = SENSOR_4E5_HEIGHT + 10,
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ },
+ [SENSOR_S5K6A3] = {
+ .width = SENSOR_6A3_WIDTH + 16,
+ .height = SENSOR_6A3_HEIGHT + 10,
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .field = V4L2_FIELD_NONE,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ },
+};
+
+static struct fimc_is_sensor *sd_to_fimc_is_sensor(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct fimc_is_sensor, subdev);
+}
+
+static void sensor_clk_put(struct fimc_is_sensor *sensor)
+{
+ int i;
+
+ for (i = 0; i < SCLK_MAX_NUM; i++) {
+ if (IS_ERR_OR_NULL(sensor->clock[i]))
+ continue;
+ clk_unprepare(sensor->clock[i]);
+ clk_put(sensor->clock[i]);
+ sensor->clock[i] = NULL;
+ }
+}
+
+static int sensor_clk_init(struct fimc_is_sensor *sensor)
+{
+ int i, ret;
+
+ /* Get CAM clocks */
+ for (i = 0; i < SCLK_MAX_NUM; i++) {
+ sensor->clock[i] = clk_get(NULL, sensor_clock_name[i]);
+ if (IS_ERR(sensor->clock[i]))
+ goto err;
+ ret = clk_prepare(sensor->clock[i]);
+ if (ret < 0) {
+ clk_put(sensor->clock[i]);
+ sensor->clock[i] = NULL;
+
[RFC 05/12] exynos-fimc-is: Adds the register definition and context header
This patch adds the register definition file for the fimc-is driver and also the header file containing the main context for the driver. Signed-off-by: Arun Kumar K Signed-off-by: Kilyeon Im --- drivers/media/platform/exynos5-is/fimc-is-regs.h | 352 ++ drivers/media/platform/exynos5-is/fimc-is.h | 151 ++ 2 files changed, 503 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h new file mode 100644 index 000..43ed011 --- /dev/null +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h @@ -0,0 +1,352 @@ +/* + * Samsung Exynos5 SoC series FIMC-IS driver + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef FIMC_IS_REGS_H +#define FIMC_IS_REGS_H + +#include + +/* WDT_ISP register */ +#define WDT0x0017 +/* MCUCTL register */ +#define MCUCTL 0x0018 +/* MCU Controller Register */ +#define MCUCTLR(MCUCTL+0x00) +#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) << 16) +#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) << 12) +#define MCUCTLR_MSWRST (1 << 0) +/* Boot Base OFfset Address Register */ +#define BBOAR (MCUCTL+0x04) +#define BBOAR_BBOA(x) ((x) << 0) +/* Interrupt Generation Register 0 from Host CPU to VIC */ +#define INTGR0 (MCUCTL+0x08) +#define INTGR0_INTGC9 (1 << 25) +#define INTGR0_INTGC8 (1 << 24) +#define INTGR0_INTGC7 (1 << 23) +#define INTGR0_INTGC6 (1 << 22) +#define INTGR0_INTGC5 (1 << 21) +#define INTGR0_INTGC4 (1 << 20) +#define INTGR0_INTGC3 (1 << 19) +#define INTGR0_INTGC2 (1 << 18) +#define INTGR0_INTGC1 (1 << 17) +#define INTGR0_INTGC0 (1 << 16) +#define INTGR0_INTGD5 (1 << 5) +#define INTGR0_INTGD4 (1 << 4) +#define INTGR0_INTGD3 (1 << 3) +#define INTGR0_INTGD2 (1 << 2) +#define INTGR0_INTGD1 (1 << 1) +#define INTGR0_INTGD0 (1 << 0) +/* Interrupt Clear Register 0 from Host CPU to VIC */ +#define INTCR0 (MCUCTL+0x0c) +#define INTCR0_INTCC9 (1 << 25) +#define INTCR0_INTCC8 (1 << 24) +#define INTCR0_INTCC7 (1 << 23) +#define INTCR0_INTCC6 (1 << 22) +#define INTCR0_INTCC5 (1 << 21) +#define INTCR0_INTCC4 (1 << 20) +#define INTCR0_INTCC3 (1 << 19) +#define INTCR0_INTCC2 (1 << 18) +#define INTCR0_INTCC1 (1 << 17) +#define INTCR0_INTCC0 (1 << 16) +#define INTCR0_INTCD5 (1 << 5) +#define INTCR0_INTCD4 (1 << 4) +#define INTCR0_INTCD3 (1 << 3) +#define INTCR0_INTCD2 (1 << 2) +#define INTCR0_INTCD1 (1 << 1) +#define INTCR0_INTCD0 (1 << 0) +/* Interrupt Mask Register 0 from Host CPU to VIC */ +#define INTMR0 (MCUCTL+0x10) +#define INTMR0_INTMC9 (1 << 25) +#define INTMR0_INTMC8 (1 << 24) +#define INTMR0_INTMC7 (1 << 23) +#define INTMR0_INTMC6 (1 << 22) +#define INTMR0_INTMC5 (1 << 21) +#define INTMR0_INTMC4 (1 << 20) +#define INTMR0_INTMC3 (1 << 19) +#define INTMR0_INTMC2 (1 << 18) +#define INTMR0_INTMC1 (1 << 17) +#define INTMR0_INTMC0 (1 << 16) +#define INTMR0_INTMD5 (1 << 5) +#define INTMR0_INTMD4 (1 << 4) +#define INTMR0_INTMD3 (1 << 3) +#define INTMR0_INTMD2 (1 << 2) +#define INTMR0_INTMD1 (1 << 1) +#define INTMR0_INTMD0 (1 << 0) +/* Interrupt Status Register 0 from Host CPU to VIC */ +#define INTSR0 (MCUCTL+0x14) +#define INTSR0_GET_INTSD0(x) (((x) >> 0) & 0x1) +#define INTSR0_GET_INTSD1(x) (((x) >> 1) & 0x1) +#define INTSR0_GET_INTSD2(x) (((x) >> 2) & 0x1) +#define INTSR0_GET_INTSD3(x) (((x) >> 3) & 0x1) +#define INTSR0_GET_INTSD4(x) (((x) >> 4) & 0x1) +#define INTSR0_GET_INTSC0(x) (((x) >> 16) & 0x1) +#define INTSR0_GET_INTSC1(x) (((x) >> 17) & 0x1) +#define INTSR0_GET_INTSC2(x) (((x) >> 18) & 0x1) +#define INTSR0_GET_INTSC3(x) (((x)
[RFC 03/12] exynos-fimc-is: Adds fimc-is driver core files
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 421 ++
drivers/media/platform/exynos5-is/fimc-is-core.h | 140 +++
2 files changed, 561 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..2a257c5
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,421 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "fimc-is.h"
+
+int fimc_is_debug;
+module_param(fimc_is_debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(fimc_is_debug, "Debug level for exynos-fimc-is driver");
+
+static char *fimc_is_clock_name[] = {
+ [IS_CLK_GATE0] = "fimc-is0",
+ [IS_CLK_GATE1] = "fimc-is1",
+ [IS_CLK_266]= "aclk_266_isp",
+ [IS_CLK_266_DIV0] = "aclk_266_isp_div0",
+ [IS_CLK_266_DIV1] = "aclk_266_isp_div1",
+ [IS_CLK_266_DIV_MPWM] = "aclk_266_isp_divmpwm",
+ [IS_CLK_400]= "aclk_400_isp",
+ [IS_CLK_400_DIV0] = "aclk_400_isp_div0",
+ [IS_CLK_400_DIV1] = "aclk_400_isp_div1",
+};
+
+static int fimc_is_create_sensor_subdevs(struct fimc_is *is)
+{
+ struct fimc_is_platdata *pdata = is->pdata;
+ int ret;
+
+ if (pdata->sensor_data[SENSOR_CAM0].enabled) {
+ /* Sensor0 */
+ ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM0],
+ &pdata->sensor_data[SENSOR_CAM0],
+ &is->pipeline);
+ if (ret < 0)
+ is_err("Error creating sensor0 subdev");
+ }
+
+ if (pdata->sensor_data[SENSOR_CAM1].enabled) {
+ /* Sensor1 */
+ ret = fimc_is_sensor_subdev_create(&is->sensor[SENSOR_CAM1],
+ &pdata->sensor_data[SENSOR_CAM1],
+ &is->pipeline);
+ if (ret < 0)
+ is_err("Error creating sensor1 subdev");
+ }
+
+ return 0;
+}
+
+static int fimc_is_unregister_sensor_subdevs(struct fimc_is *is)
+{
+ struct fimc_is_platdata *pdata = is->pdata;
+
+ if (pdata->sensor_data[SENSOR_CAM0].enabled)
+ fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM0]);
+ if (pdata->sensor_data[SENSOR_CAM1].enabled)
+ fimc_is_sensor_subdev_destroy(&is->sensor[SENSOR_CAM1]);
+
+ return 0;
+}
+
+static struct fimc_is_platdata *fimc_is_parse_dt(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct device_node *child, *ep, *port;
+ struct fimc_is_platdata *pdata;
+ struct fimc_is_sensor_data *sensor_data;
+ struct v4l2_of_endpoint endpoint;
+ unsigned int i, snum;
+ int num_gpios;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ is_err("Memory allocation for pdata failed\n");
+ return NULL;
+ }
+
+ /* Parse sensor properties */
+ for (snum = 0; snum < FIMC_IS_NUM_SENSORS; snum++) {
+
+ child = of_get_next_child(np, child);
+ if (!child) {
+ is_err("Child node not found\n");
+ continue;
+ }
+
+ sensor_data = &pdata->sensor_data[snum];
+ num_gpios = of_gpio_named_count(child, "gpios");
+ if (num_gpios < 0) {
+ is_err("Sensor gpio property not found\n");
+ of_node_put(child);
+ goto exit;
+ }
+ sensor_data->num_gpios = num_gpios;
+ of_property_read_string(child, "compatible",
+ (const char **)&sensor_data->name);
+ is_dbg(1, "Rear sensor name : %s\n", sensor_data->name);
+ for (i = 0; i < num_gpios; i++) {
+ sensor_data->gpios[i] =
+ of_get_named_gpio(child, "gpios", i);
+
[RFC 02/12] exynos-fimc-is: Adding ARCH support for fimc-is
Adds new clocks needed for ISP submodules in the camera
subsystem of Exynos5250. Also adds the AUXDATA entry in
mach-exynos5-dt.c.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
arch/arm/mach-exynos/clock-exynos5.c | 129
arch/arm/mach-exynos/include/mach/map.h|2 +
arch/arm/mach-exynos/include/mach/regs-clock.h |7 ++
arch/arm/mach-exynos/mach-exynos5-dt.c |2 +
4 files changed, 140 insertions(+)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 4536515..b2c0825 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -28,6 +28,8 @@
#include "common.h"
+#define FIMC_IS_NAME "exynos5-fimc-is"
+
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos5_clock_save[] = {
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
@@ -863,6 +865,16 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit= (1 << 4),
}, {
+ .name = "fimc-is0",
+ .devname= FIMC_IS_NAME,
+ .enable = exynos5_clk_ip_isp0_ctrl,
+ .ctrlbit= (0xFFC << 20) | (0xFF << 0),
+ }, {
+ .name = "fimc-is1",
+ .devname= FIMC_IS_NAME,
+ .enable = exynos5_clk_ip_isp1_ctrl,
+ .ctrlbit= (0x3 << 12) | (0x7 << 0)
+ }, {
.name = "csis",
.devname= "s5p-mipi-csis.0",
.enable = exynos5_clk_ip_gscl_ctrl,
@@ -1248,6 +1260,107 @@ static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
};
+/* For ACLK_400_ISP */
+static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = {
+ .clk= {
+ .name = "mout_aclk_400_isp",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = {
+ .clk= {
+ .name = "dout_aclk_400_isp",
+ .parent = &exynos5_clk_mout_aclk_400_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_aclk_400_isp_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_dout_aclk_400_isp.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_400_isp = {
+ .sources= exynos5_clkset_aclk_400_isp_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp = {
+ .clk= {
+ .name = "aclk_400_isp",
+ .devname= FIMC_IS_NAME,
+ },
+ .sources = &exynos5_clkset_aclk_400_isp,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp = {
+ .clk= {
+ .name = "aclk_266_isp",
+ .devname= FIMC_IS_NAME,
+
+ },
+ .sources = &clk_src_gscl_266,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div0 = {
+ .clk= {
+ .name = "aclk_266_isp_div0",
+ .devname= FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_div1 = {
+ .clk= {
+ .name = "aclk_266_isp_div1",
+ .devname= FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266_isp_divmpwm = {
+ .clk= {
+ .name = "aclk_266_isp_divmpwm",
+ .devname= FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_266_isp_div1.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp_div0 = {
+ .clk= {
+ .name = "aclk_400_isp_div0",
+ .devname= FIMC_IS_NAME,
+ .parent = &exynos5_clk_aclk_400_isp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400_isp_div1 = {
+ .clk= {
+ .name = "aclk_400_isp_div1",
+
[RFC 01/12] exynos-fimc-is: Adding device tree nodes
Add the fimc-is node and the required pinctrl nodes for
fimc-is driver for Exynos5. Also adds the DT binding documentation
for the new fimc-is node.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
---
.../devicetree/bindings/media/soc/exynos5-is.txt | 81
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 60 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts | 54 -
arch/arm/boot/dts/exynos5250.dtsi |8 ++
4 files changed, 201 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/soc/exynos5-is.txt
mode change 100644 => 100755 arch/arm/boot/dts/exynos5250-smdk5250.dts
mode change 100644 => 100755 arch/arm/boot/dts/exynos5250.dtsi
diff --git a/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
new file mode 100644
index 000..e0fdf02
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/soc/exynos5-is.txt
@@ -0,0 +1,81 @@
+Samsung EXYNOS SoC Camera Subsystem
+---
+
+The camera subsystem on Samsung Exynos5 SoC has some changes relative
+to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and
+FIMC-LITE IPs but removed the FIMC-CAPTURE. Instead it has an improved
+FIMC-IS which can provide imate data DMA output.
+
+The device tree binding remain similar to the Exynos4 bindings which can
+be seen at samsung-fimc.txt with the addition of fimc-is sub-node which will
+be explained here.
+
+fimc-is subnode of camera node
+--
+
+Required properties:
+
+- compatible : must be "samsung,exynos5250-fimc-is"
+- reg : physical base address and size of the memory mapped
+ registers
+- interrupt-parent : Parent interrupt controller
+- interrupts : fimc-is interrupt to the parent combiner
+
+Board specific properties:
+
+- pinctrl-names: pinctrl names for camera port pinmux control, at least
+"default" needs to be specified.
+- pinctrl-0...N : pinctrl properties corresponding to pinctrl-names
+
+Sensor sub-nodes:
+
+FIMC-IS IP supports custom built sensors to be controlled exclusively by
+the FIMC-IS firmware. These sensor properties are to be defined here.
+Sensor nodes are described in the same way as in generic sensors used in
+Exynos4 and described in samsung-fimc.txt.
+
+Example:
+
+SoC common node:
+
+ fimc_is: fimc-is@1300 {
+ compatible = "samsung,exynos5250-fimc-is";
+ reg = <0x1300 0x20>;
+ interrupt-parent = <&combiner>;
+ interrupts = <19 1>;
+ status = "disabled";
+ };
+
+Board specific node:
+
+ fimc-is@1300 {
+ status = "okay";
+ pinctrl-0 =
+ <&cam_port_a_clk_active
+ &cam_bayer_clk_active
+ &isp_uart
+ &cam_i2c0
+ &cam_i2c1>;
+ pinctrl-names = "default";
+ s5k4e5 {
+ compatible = "samsung,s5k4e5";
+ gpios = <&gpx1 2 1>;
+ clock-frequency = <2400>;
+ port {
+ is_s5k4e5_ep: endpoint {
+ remote-endpoint = <&csis0_ep>;
+ };
+ };
+ };
+ s5k6a3 {
+ compatible = "samsung,s5k6a3";
+ gpios = <&gpx1 0 1>;
+ clock-frequency = <2400>;
+ port {
+ is_s5k6a3_ep: endpoint {
+ remote-endpoint = <&csis1_ep>;
+ };
+ };
+ };
+ };
+
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 3caaa21..320c22b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -556,6 +556,38 @@
};
pinctrl@1340 {
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells
[RFC 00/12] Exynos5 FIMC-IS driver
This patchset adds a new driver for the FIMC-IS IP available in Samsung Exynos5 SoC onwards. The camera subsystem in Exynos5 is significantly different from that of Exynos4 and before. In Exynos4, the FIMC-IS is a sub component of the camera subsystem which takes input from fimc-lite and does post processing of the image and passes it to the fimc-capture which writes to the output DMA. But in case of Exynos5, the fimc-capture IP is removed and instead a more powerful fimc-is takes the role of giving scaled image output via DMA. FIMC-IS internally has two scalers for this in addition to other post-processing components like dynamic range compression, optical distortion correction, digital image stabilization, 3D noise reduction and face detection. FIMC-IS also has capability to directly control certain sensors and the sensors compatible with the fimc-is will be termed as fimc-is sensors. This patchset adds support for two such fimc-is sensors - s5k4e5 and s5k6a3. These sensors are controlled exclusively by the fimc-is firmware. They provide only SRGB unscaled output which will reach fimc-is via mipi-csis and fimc-lite. The color space conversion, scaling and all other post processing will be then done by the fimc-is IP components. The fimc-is driver operates in the following manner: The sensor subdevice created by this driver will be used by the exynos5 media-device's pipeline0 which connects it with mipi-csis and fimc-lite. |fimc-is-sensor|--->|mipi-csis|--->|fimc-lite|--->|Memory| The output bayer image dumped by the fimc-lite subdev into memory is fed into the ISP subdev of fimc-is driver. For that the pipeline1 of exynos5 media-device will look like this: |Memory|--->|fimc-is-isp|--->|fimc-is-scaler-codec|--->|fimc-is-scaler-preview| The isp subdev accepts bayer input buffer at its OUTPUT_MPLANE. It will do a set of post processing operations and passes it on-the-fly to the scalers. The two scalers can give two different scaled outputs which can be used for recording and preview simultaneously. Both scaler-codec and scaler-preview dumps DMA data out through its CAPTURE_MPLANE. This first RFC contains the basic version of the driver which accepts bayer input data and provides 2 different scaled outputs with most of the post processing blocks disabled. This has to be applied on exynos5 media device patchset posted by Shaik Ameer Basha [1] and its based on media-tree v3.9. [1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg16191.html Arun Kumar K (12): exynos-fimc-is: Adding device tree nodes exynos-fimc-is: Adding ARCH support for fimc-is exynos-fimc-is: Adds fimc-is driver core files exynos-fimc-is: Adds common driver header files exynos-fimc-is: Adds the register definition and context header exynos-fimc-is: Adds the sensor subdev exynos-fimc-is: Adds isp subdev exynos-fimc-is: Adds scaler subdev exynos-fimc-is: Adds the hardware pipeline control exynos-fimc-is: Adds the hardware interface module exynos-fimc-is: Adds the Kconfig and Makefile mipi-csis: Enable all interrupts for fimc-is usage .../devicetree/bindings/media/soc/exynos5-is.txt | 81 + arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 60 + arch/arm/boot/dts/exynos5250-smdk5250.dts | 54 +- arch/arm/boot/dts/exynos5250.dtsi |8 + arch/arm/mach-exynos/clock-exynos5.c | 129 ++ arch/arm/mach-exynos/include/mach/map.h|2 + arch/arm/mach-exynos/include/mach/regs-clock.h |7 + arch/arm/mach-exynos/mach-exynos5-dt.c |2 + drivers/media/platform/exynos5-is/Kconfig | 12 + drivers/media/platform/exynos5-is/Makefile |3 + drivers/media/platform/exynos5-is/fimc-is-cmd.h| 211 ++ drivers/media/platform/exynos5-is/fimc-is-core.c | 421 drivers/media/platform/exynos5-is/fimc-is-core.h | 140 ++ drivers/media/platform/exynos5-is/fimc-is-err.h| 258 +++ .../media/platform/exynos5-is/fimc-is-interface.c | 1003 + .../media/platform/exynos5-is/fimc-is-interface.h | 130 ++ drivers/media/platform/exynos5-is/fimc-is-isp.c| 546 + drivers/media/platform/exynos5-is/fimc-is-isp.h| 88 + .../media/platform/exynos5-is/fimc-is-metadata.h | 771 +++ drivers/media/platform/exynos5-is/fimc-is-param.h | 2163 .../media/platform/exynos5-is/fimc-is-pipeline.c | 1961 ++ .../media/platform/exynos5-is/fimc-is-pipeline.h | 129 ++ drivers/media/platform/exynos5-is/fimc-is-regs.h | 352 drivers/media/platform/exynos5-is/fimc-is-scaler.c | 595 ++ drivers/media/platform/exynos5-is/fimc-is-scaler.h | 107 + drivers/media/platform/exynos5-is/fimc-is-sensor.c | 337 +++ drivers/media/platform/exynos5-is/fimc-is-sensor.h | 170 ++ drivers/media/platform/exynos5-is/fimc-is.h| 151 ++ drivers/media/platform/s5p-fimc/mipi-csis.c|2 +- 29 files changed, 9890 insertions(+), 3 delet
Re: [PATCH 00/23] RFC: exynos multiplatform support
On Friday 08 March 2013, Tomasz Figa wrote: > I have a question regarding making this an MFD driver. > > As you know, the main clocksource driver must be initialized early, from > init_time callback of machine_desc. How does using the MFD subsystem fit > into this scheme? > > P.S. I'm still not convinced about any benefits of options 2 and 3 over > option 1, which has the obvious advantage of requiring least amount of > changes to existing code and not binding the PWM and clocksource drivers > together (on Exynos SoCs only the PWM driver is used, clocksource is > handled by different hardware block - MCT). I think the main motivation for the MFD here is that you have a shared register set, which would be described as a single device node in DT as its natural representation, but it's not easy to have two drivers be responsible for the same platform device. Similarly, the Linux resource handling tries hard to ensure that multiple device drivers do not share a single register set. If you have an MFD driver, that could bind do the platform_device created from the DT device node, and provide a simple interface for both the timer and the pwm driver to talk to, without exposing those registers directly. Or you could use the syscon regmap approach to expose those registers in a more controlled way. With syscon, you don't actually have to write an MFD driver but could just use the one that is already there. Since you want the timer driver to be available really early, you could also make that timer driver the master and expose an interface for the PWM driver to use. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: EXYNOS: Use wfi macro in platform_do_lowpower
As per commit b3377d186572 ("ARM: 7064/1: vexpress: Use wfi macro
in platform_do_lowpower."), wfi macro should be used instead
of the hardcoded WFI instruction.
This fixes following oops when the kernel is compiled in Thumb-2 mode
on EXYNOS5. (Tested on EXYNOS5250 based Arndale board)
$ reboot
Disabling non-boot CPUs ...
IRQ153 no longer affine to CPU1
CPU1: shutdown
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP THUMB2
Modules linked in:
CPU: 1Not tainted (3.9.0-rc1-00015-gce76372 #1)
PC is at 0xc065858e
LR is at exynos_cpu_die+0x53/0xc0
Signed-off-by: Tushar Behera
---
arch/arm/mach-exynos/hotplug.c |8 +---
1 files changed, 1 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index c3f825b..d9712fe 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -99,13 +99,7 @@ static inline void platform_do_lowpower(unsigned int cpu,
int *spurious)
if (cpu == 1)
__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
- /*
-* here's the WFI
-*/
- asm(".word 0xe320f003\n"
- :
- :
- : "memory", "cc");
+ wfi();
if (pen_release == cpu_logical_map(cpu)) {
/*
--
1.7.4.1
--
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Re: [PATCH RFC] drm/exynos: hdmi: move hdmiphy related code to hdmiphy driver
On Thu, Mar 7, 2013 at 2:05 PM, Inki Dae wrote: > > >> -Original Message- >> From: 김승우 [mailto:sw0312@samsung.com] >> Sent: Thursday, March 07, 2013 4:04 PM >> To: Rahul Sharma >> Cc: Inki Dae; linux-samsung-soc@vger.kernel.org; Sean Paul; sunil joshi; >> dri-de...@lists.freedesktop.org; Rahul Sharma; sw0312@samsung.com >> Subject: Re: [PATCH RFC] drm/exynos: hdmi: move hdmiphy related code to >> hdmiphy driver >> >> >> >> On 2013년 03월 07일 15:45, Rahul Sharma wrote: >> > Thanks Seung Woo, Mr. Dae, >> > >> > On Thu, Mar 7, 2013 at 10:13 AM, Inki Dae wrote: >> >> 2013/3/7 김승우 : >> >>> >> >>> >> >>> On 2013년 03월 04일 23:05, Rahul Sharma wrote: >> Thanks Sean, >> >> On Wed, Feb 27, 2013 at 9:47 PM, Sean Paul >> wrote: >> > On Wed, Feb 27, 2013 at 8:22 AM, Rahul Sharma >> wrote: >> >> Right now hdmiphy operations and configs are kept inside hdmi >> driver. hdmiphy related >> >> code is tightly coupled with hdmi ip driver. Physicaly they are >> different devices and >> > >> > s/Physicaly/Physically/ >> > >> >> should be instantiated independently. >> >> >> >> In terms of versions/mapping/configurations Hdmi and hdmiphy are >> independent of each >> >> other. It is preferred to isolate them and maintained > independently. >> >> >> >> This implementations is tested for: >> >> 1) Resolutions supported by exynos4 and 5 hdmi. >> >> 2) Runtime PM and S2R scenarions for exynos5. >> >> >> > >> > I don't like the idea of spawning off yet another driver in here. It >> > adds more globals, more suspend/resume ordering issues, and more >> > implicit dependencies. I understand, however, that this is the >> Chosen >> > Way for the exynos driver, so I will save my rant. >> > >> >> I agree to it. splitting phy to a new driver will complicate the >> power related >> scenarios. But in upcoming SoC,s, Phy is changing considerably in >> terms of >> config values, mapping (i2c/platform bus) etc. Handling this >> diversity >> inside hdmi driver is complicating it with unrelated changes. >> >>> >> >>> Basically, I agree with the idea to split hdmiphy from hdmi. And it >> >>> seems that already existing hdmiphy i2c device is just reused and >> >>> hdmiphy_power_on is reorganized to hdmiphy dpms operation: even >> calling >> >>> flow of power operations is reordered. >> >>> >> >>> But I'm not sure exynos_hdmiphy_driver_register() really need to be >> >>> called from exynos_drm_init() of exynos_drm_drv.c. IMO, it is enough >> to >> >>> call exynos_hdmiphy_driver_register() from hdmi_probe() because >> hdmiphy >> >>> is only used from hdmi. >> >>> >> >> >> >> I agree with Seung-Woo. The hdmiphy is just one part of HDMI subsystem. >> >> >> > >> > I agree to the Seung Woo's point that hdmi-phy used to be solely >> accessed by >> > hdmi driver. But in this RFC, hdmi-phy is not called by hdmi driver >> > anymore. Phy >> > ops will be called from drm-common-hdmi platform driver along with mixer >> and >> > hdmi ops. >> >> Considering this, exynos_drm_hdmi_probe() is more proper position. >> >> > >> > The rational behind my implementation is that I am projecting hdmi-phy >> as >> > a device which is peer to hdmi ip and mixer. These 3 devices together >> makes >> > DRM HDMI subsystem. >> > >> > Even physically hdmi-phy doesn't seems to be a part of hdmi ip though >> > configurations are listed under hdmi ip user manual. It looks like a >> > isolated module accessed by i2c. >> > >> > Though I don't find anything wrong with Seung Woo suggestion but above >> > placement of hdmi-phy (parallel to hdmi and mixer) makes more sense >> > to me. >> > >> > Please have a another look at it and let me know your opinion. >> > >> > Another things which bothers me is registering mixer, hdmi driver inside >> > exynos_drm_init(). If we strictly follow the hierarchy inside drm, >> > exynos_drm_init() >> > should register drm-common-hdmi only. drm-common-hdmi should register >> > mixer and hdmi (or hdmi-phy as well). >> >> Yes, it makes sense. All real hw blocks for hdmi including mixer, hdmi, >> and hdmiphy shoulde be registered in exynos_drm_hdmi (drm-common-hdmi >> for exynos). >> > > Ideally, right. But the reason I designed and implemented hdmi subsystem > framework like this, is that there was one issue that > platform_device_register() can't be called at probe(). On other words, when > one platform device driver is being probed, anyone can't be probed. Anyway, > existing way needs to be improved. So let's find better way and improve the > hdmi subsystem framework this time. :) Mr. Dae, if we move exynos_drm_drv.o towards last in the makefile, we can conveniently move all driver(or plf device for drm-comon-hdmi) registrations from exynos_drm_init to module_init of the respective drivers. I verified above changes for hdmi and S2R scenarios. regards, Rahul Sharma > > Thanks, > Inki Dae > >> Thanks and Regards, >> -
