Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
> This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
> Like s5k6a3, it is also another fimc-is firmware controlled
> sensor. This minimal sensor driver doesn't do any I2C communications
> as its done by ISP firmware. It can be updated if needed to a
> regular sensor driver by adding the I2C communication.
>
> Signed-off-by: Arun Kumar K
> Reviewed-by: Sylwester Nawrocki
> ---
> .../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
> drivers/media/i2c/Kconfig |8 +
> drivers/media/i2c/Makefile |1 +
> drivers/media/i2c/s5k4e5.c | 361
>
> 4 files changed, 413 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
> create mode 100644 drivers/media/i2c/s5k4e5.c
>
...
> diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
> new file mode 100644
> index 000..0a6ece6
> --- /dev/null
> +++ b/drivers/media/i2c/s5k4e5.c
> @@ -0,0 +1,361 @@
> +/*
> + * Samsung S5K4E5 image sensor driver
> + *
> + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
> + * Author: Arun Kumar K
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define S5K4E5_SENSOR_MAX_WIDTH 2576
> +#define S5K4E5_SENSOR_MAX_HEIGHT 1930
> +
> +#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
> +#define S5K4E5_SENSOR_ACTIVE_HEIGHT 1920
> +
> +#define S5K4E5_SENSOR_MIN_WIDTH (32 + 16)
> +#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
> +
> +#define S5K4E5_DEF_WIDTH 1296
> +#define S5K4E5_DEF_HEIGHT732
> +
> +#define S5K4E5_DRV_NAME "S5K4E5"
> +#define S5K4E5_CLK_NAME "mclk"
> +
> +#define S5K4E5_NUM_SUPPLIES 2
> +
> +#define S5K4E5_DEF_CLK_FREQ 2400
> +
> +/**
> + * struct s5k4e5 - s5k4e5 sensor data structure
> + * @dev: pointer to this I2C client device structure
> + * @subdev: the image sensor's v4l2 subdev
> + * @pad: subdev media source pad
> + * @supplies: image sensor's voltage regulator supplies
> + * @gpio_reset: GPIO connected to the sensor's reset pin
> + * @lock: mutex protecting the structure's members below
> + * @format: media bus format at the sensor's source pad
> + */
> +struct s5k4e5 {
> + struct device *dev;
> + struct v4l2_subdev subdev;
> + struct media_pad pad;
> + struct regulator_bulk_data supplies[S5K4E5_NUM_SUPPLIES];
> + int gpio_reset;
> + struct mutex lock;
> + struct v4l2_mbus_framefmt format;
> + struct clk *clock;
> + u32 clock_frequency;
> +};
> +
> +static const char * const s5k4e5_supply_names[] = {
> + "svdda",
> + "svddio"
> +};
I'm no regulator expert, but shouldn't this list come from the DT or
platform_data?
Or are these names specific to this sensor?
Regards,
Hans
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[PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 38
arch/arm/boot/dts/exynos5420.dtsi | 36 +++
3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
specific extensions.
+ - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..6e65278 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,44 @@
};
};
+ dwmmc0@1220 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ dwmmc2@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ };
+ };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..694e7f1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
aliases {
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,39 @@
clock-names = "mfc";
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1220 0x2000>;
+ clocks = <&clock 351>, <&clock 132>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1221 0x2000>;
+ clocks = <&clock 352>, <&clock 133>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1222 0x2000>;
+ clocks = <&clock 353>, <&clock 134>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
--
1.7.9.5
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[PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
From: Yuvaraj Kumar C D
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++
arch/arm/boot/dts/exynos5250.dtsi | 16
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
dwmmc0@1220 {
+ status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
- dwmmc1@1221 {
- status = "disabled";
- };
-
dwmmc2@1222 {
+ status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -180,10 +178,6 @@
};
};
- dwmmc3@1223 {
- status = "disabled";
- };
-
spi_0: spi@12d2 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,21 +387,36 @@
};
dwmmc_0: dwmmc0@1220 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
+ status = "disabled";
};
dwmmc_1: dwmmc1@1221 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
+ status = "disabled";
};
dwmmc_2: dwmmc2@1222 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
+ status = "disabled";
};
dwmmc_3: dwmmc3@1223 {
@@ -412,6 +427,7 @@
#size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
+ status = "disabled";
};
i2s0: i2s@0383 {
--
1.7.9.5
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[PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
From: Yuvaraj Kumar C D
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source.
Changes since V1: none
Signed-off-by: Yuvaraj Kumar C D
---
arch/arm/boot/dts/exynos5.dtsi | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..24140f0 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = <1 9 0xf04>;
};
- dwmmc_0: dwmmc0@1220 {
- compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 75 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- dwmmc_1: dwmmc1@1221 {
- compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 76 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- dwmmc_2: dwmmc2@1222 {
- compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 77 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
serial@12C0 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C0 0x100>;
--
1.7.9.5
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[PATCH v7 09/13] [media] exynos5-fimc-is: Add the hardware pipeline control
This patch adds the crucial hardware pipeline control for the
fimc-is driver. All the subdev nodes will call this pipeline
interfaces to reach the hardware. Responsibilities of this module
involves configuring and maintaining the hardware pipeline involving
multiple sub-ips like ISP, DRC, Scalers, ODC, 3DNR, FD etc.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
Reviewed-by: Sylwester Nawrocki
---
.../media/platform/exynos5-is/fimc-is-pipeline.c | 1692
.../media/platform/exynos5-is/fimc-is-pipeline.h | 128 ++
2 files changed, 1820 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-pipeline.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
new file mode 100644
index 000..7d91469
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-pipeline.c
@@ -0,0 +1,1692 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ * Kil-yeon Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is.h"
+#include "fimc-is-pipeline.h"
+#include "fimc-is-metadata.h"
+#include "fimc-is-regs.h"
+#include "fimc-is-cmd.h"
+#include
+#include
+
+/* Default setting values */
+#define DEFAULT_PREVIEW_STILL_WIDTH1280
+#define DEFAULT_PREVIEW_STILL_HEIGHT 720
+#define DEFAULT_CAPTURE_VIDEO_WIDTH1920
+#define DEFAULT_CAPTURE_VIDEO_HEIGHT 1080
+#define DEFAULT_CAPTURE_STILL_WIDTH2560
+#define DEFAULT_CAPTURE_STILL_HEIGHT 1920
+#define DEFAULT_CAPTURE_STILL_CROP_WIDTH 2560
+#define DEFAULT_CAPTURE_STILL_CROP_HEIGHT 1440
+#define DEFAULT_PREVIEW_VIDEO_WIDTH640
+#define DEFAULT_PREVIEW_VIDEO_HEIGHT 480
+
+/* Init params for pipeline devices */
+static const struct sensor_param init_sensor_param = {
+ .frame_rate = {
+ .frame_rate = 30,
+ },
+};
+
+static const struct isp_param init_isp_param = {
+ .control = {
+ .cmd = CONTROL_COMMAND_START,
+ .bypass = CONTROL_BYPASS_DISABLE,
+ },
+ .otf_input = {
+ .cmd = OTF_INPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_INPUT_FORMAT_BAYER,
+ .bitwidth = OTF_INPUT_BIT_WIDTH_10BIT,
+ .order = OTF_INPUT_ORDER_BAYER_GR_BG,
+ .frametime_max = 3,
+ },
+ .dma1_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .dma2_input = {
+ .cmd = DMA_INPUT_COMMAND_DISABLE,
+ },
+ .aa = {
+ .cmd = ISP_AA_COMMAND_START,
+ .target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
+ ISP_AA_TARGET_AWB,
+ .mode = ISP_AF_CONTINUOUS,
+ },
+ .flash = {
+ .cmd = ISP_FLASH_COMMAND_DISABLE,
+ .redeye = ISP_FLASH_REDEYE_DISABLE,
+ },
+ .awb = {
+ .cmd = ISP_AWB_COMMAND_AUTO,
+ },
+ .effect = {
+ .cmd = ISP_IMAGE_EFFECT_DISABLE,
+ },
+ .iso = {
+ .cmd = ISP_ISO_COMMAND_AUTO,
+ },
+ .adjust = {
+ .cmd = ISP_ADJUST_COMMAND_AUTO,
+ },
+ .metering = {
+ .cmd = ISP_METERING_COMMAND_CENTER,
+ .win_width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .win_height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ },
+ .afc = {
+ .cmd = ISP_AFC_COMMAND_AUTO,
+ },
+ .otf_output = {
+ .cmd = OTF_OUTPUT_COMMAND_ENABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = OTF_OUTPUT_FORMAT_YUV444,
+ .bitwidth = OTF_OUTPUT_BIT_WIDTH_12BIT,
+ .order = OTF_OUTPUT_ORDER_BAYER_GR_BG,
+ },
+ .dma1_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_INPUT_FORMAT_YUV444,
+ .bitwidth = DMA_INPUT_BIT_WIDTH_8BIT,
+ .plane = 1,
+ .order = DMA_INPUT_ORDER_YCBCR,
+ },
+ .dma2_output = {
+ .cmd = DMA_OUTPUT_COMMAND_DISABLE,
+ .width = DEFAULT_CAPTURE_STILL_WIDTH,
+ .height = DEFAULT_CAPTURE_STILL_HEIGHT,
+ .format = DMA_OUTPUT_FORMAT_BAYER,
+ .bitwidth = DMA_OUTPUT_BIT_WIDTH_12BIT,
+ .plane = 1,
+
[PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Signed-off-by: Yuvaraj Kumar C D
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 41
arch/arm/boot/dts/exynos5420.dtsi | 33
3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
specific extensions.
+ - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..4530700 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,45 @@
clock-frequency = <2400>;
};
};
+
+ dwmmc0@1220 {
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = "disabled";
+ };
+
+ dwmmc2@1222 {
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..8559aa8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = "samsung,exynos5420";
aliases {
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -65,6 +68,36 @@
#clock-cells = <1>;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1220 0x2000>;
+ clocks = <&clock 351>, <&clock 132>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1221 0x2000>;
+ clocks = <&clock 352>, <&clock 133>;
+ clock-names = "biu", "ciu";
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1222 0x2000>;
+ clocks = <&clock 353>, <&clock 134>;
+ clock-names = "biu", "ciu";
+ };
+
mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
--
1.7.9.5
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[PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K
Reviewed-by: Sylwester Nawrocki
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
create mode 100644 drivers/media/i2c/s5k4e5.c
diff --git a/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
new file mode 100644
index 000..5af462c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
@@ -0,0 +1,43 @@
+* Samsung S5K4E5 Raw Image Sensor
+
+S5K4E5 is a raw image sensor with maximum resolution of 2560x1920
+pixels. Data transfer is carried out via MIPI CSI-2 port and controls
+via I2C bus.
+
+Required Properties:
+- compatible : must be "samsung,s5k4e5"
+- reg : I2C device address
+- gpios: reset gpio pin
+- clocks : clock specifier for the clock-names property
+- clock-names : must contain "mclk" entry
+- svdda-supply : core voltage supply
+- svddio-supply: I/O voltage supply
+
+Optional Properties:
+- clock-frequency : operating frequency for the sensor
+default value will be taken if not provided.
+
+The device node should be added to respective control bus controller
+(e.g. I2C0) nodes and linked to the csis port node, using the common
+video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ i2c-isp@1313 {
+ s5k4e5@20 {
+ compatible = "samsung,s5k4e5";
+ reg = <0x20>;
+ gpios = <&gpx1 2 1>;
+ clock-frequency = <2400>;
+ clocks = <&clock 129>;
+ clock-names = "mclk";
+ svdda-supply = <...>;
+ svddio-supply = <...>;
+ port {
+ is_s5k4e5_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csis0_ep>;
+ };
+ };
+ };
+ };
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index f7e9147..271028b 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -572,6 +572,14 @@ config VIDEO_S5K6A3
This is a V4L2 sensor-level driver for Samsung S5K6A3 raw
camera sensor.
+config VIDEO_S5K4E5
+ tristate "Samsung S5K4E5 sensor support"
+ depends on MEDIA_CAMERA_SUPPORT
+ depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
+ ---help---
+ This is a V4L2 sensor-level driver for Samsung S5K4E5 raw
+ camera sensor.
+
config VIDEO_S5K4ECGX
tristate "Samsung S5K4ECGX sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index cf3cf03..0aeed8e 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
obj-$(CONFIG_VIDEO_NOON010PC30)+= noon010pc30.o
obj-$(CONFIG_VIDEO_S5K6AA) += s5k6aa.o
obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o
+obj-$(CONFIG_VIDEO_S5K4E5) += s5k4e5.o
obj-$(CONFIG_VIDEO_S5K4ECGX) += s5k4ecgx.o
obj-$(CONFIG_VIDEO_S5C73M3)+= s5c73m3/
obj-$(CONFIG_VIDEO_ADP1653)+= adp1653.o
diff --git a/drivers/media/i2c/s5k4e5.c b/drivers/media/i2c/s5k4e5.c
new file mode 100644
index 000..0a6ece6
--- /dev/null
+++ b/drivers/media/i2c/s5k4e5.c
@@ -0,0 +1,361 @@
+/*
+ * Samsung S5K4E5 image sensor driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define S5K4E5_SENSOR_MAX_WIDTH2576
+#define S5K4E5_SENSOR_MAX_HEIGHT 1930
+
+#define S5K4E5_SENSOR_ACTIVE_WIDTH 2560
+#define S5K4E5_SENSOR_ACTIVE_HEIGHT1920
+
+#define S5K4E5_SENSOR_MIN_WIDTH(32 + 16)
+#define S5K4E5_SENSOR_MIN_HEIGHT (32 + 10)
+
+#define S5K4E5_DEF_WIDTH 1296
[PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
arch/arm/boot/dts/exynos5420-smdk5420.dts | 39
arch/arm/boot/dts/exynos5420.dtsi | 36 ++
3 files changed, 77 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
specific extensions.
+ - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..0b2e464 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,43 @@
clock-frequency = <2400>;
};
};
+
+ dwmmc0@1220 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ bypass-smu;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ dwmmc2@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ };
+ };
+
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..d9220c3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = "samsung,exynos5420";
aliases {
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -65,6 +68,39 @@
#clock-cells = <1>;
};
+ dwmmc_0: dwmmc0@1220 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 75 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1220 0x2000>;
+ clocks = <&clock 351>, <&clock 132>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_1: dwmmc1@1221 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 76 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1221 0x2000>;
+ clocks = <&clock 352>, <&clock 133>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ dwmmc_2: dwmmc2@1222 {
+ compatible = "samsung,exynos5420-dw-mshc";
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1222 0x2000>;
+ clocks = <&clock 353>, <&clock 134>;
+ clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
--
1.7.9.5
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[PATCH v7 12/13] V4L: s5k6a3: Change sensor min/max resolutions
s5k6a3 sensor has actual pixel resolution of 1408x1402 against the active resolution 1392x1392. The real resolution is needed when raw sensor SRGB data is dumped to memory by fimc-lite. Signed-off-by: Arun Kumar K Reviewed-by: Sylwester Nawrocki --- drivers/media/i2c/s5k6a3.c | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c index ccbb4fc..34c3165 100644 --- a/drivers/media/i2c/s5k6a3.c +++ b/drivers/media/i2c/s5k6a3.c @@ -25,10 +25,12 @@ #include #include -#define S5K6A3_SENSOR_MAX_WIDTH1392 -#define S5K6A3_SENSOR_MAX_HEIGHT 1392 -#define S5K6A3_SENSOR_MIN_WIDTH32 -#define S5K6A3_SENSOR_MIN_HEIGHT 32 +#define S5K6A3_SENSOR_MAX_WIDTH1408 +#define S5K6A3_SENSOR_MAX_HEIGHT 1402 +#define S5K6A3_SENSOR_ACTIVE_WIDTH 1392 +#define S5K6A3_SENSOR_ACTIVE_HEIGHT1392 +#define S5K6A3_SENSOR_MIN_WIDTH(32 + 16) +#define S5K6A3_SENSOR_MIN_HEIGHT (32 + 10) #define S5K6A3_DEF_PIX_WIDTH 1296 #define S5K6A3_DEF_PIX_HEIGHT 732 @@ -107,10 +109,11 @@ static void s5k6a3_try_format(struct v4l2_mbus_framefmt *mf) fmt = find_sensor_format(mf); mf->code = fmt->code; - v4l_bound_align_image(&mf->width, S5K6A3_SENSOR_MIN_WIDTH, - S5K6A3_SENSOR_MAX_WIDTH, 0, - &mf->height, S5K6A3_SENSOR_MIN_HEIGHT, - S5K6A3_SENSOR_MAX_HEIGHT, 0, 0); + v4l_bound_align_image(&mf->width, + S5K6A3_SENSOR_MIN_WIDTH, S5K6A3_SENSOR_MAX_WIDTH, 0, + &mf->height, + S5K6A3_SENSOR_MIN_HEIGHT, S5K6A3_SENSOR_MAX_HEIGHT, 0, + 0); } static struct v4l2_mbus_framefmt *__s5k6a3_get_format( -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 08/13] [media] exynos5-fimc-is: Add sensor interface
Some sensors to be used with fimc-is are exclusively controlled
by the fimc-is firmware. This minimal sensor driver provides
the required info for the firmware to configure the sensors
sitting on I2C bus.
Signed-off-by: Arun Kumar K
Reviewed-by: Sylwester Nawrocki
---
drivers/media/platform/exynos5-is/fimc-is-sensor.c | 45 ++
drivers/media/platform/exynos5-is/fimc-is-sensor.h | 65
2 files changed, 110 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-sensor.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.c
b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
new file mode 100644
index 000..475f1c3
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.c
@@ -0,0 +1,45 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "fimc-is-sensor.h"
+
+static const struct sensor_drv_data s5k6a3_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K6A3,
+ .open_timeout = S5K6A3_OPEN_TIMEOUT,
+ .setfile_name = "exynos5_s5k6a3_setfile.bin",
+};
+
+static const struct sensor_drv_data s5k4e5_drvdata = {
+ .id = FIMC_IS_SENSOR_ID_S5K4E5,
+ .open_timeout = S5K4E5_OPEN_TIMEOUT,
+ .setfile_name = "exynos5_s5k4e5_setfile.bin",
+};
+
+static const struct of_device_id fimc_is_sensor_of_ids[] = {
+ {
+ .compatible = "samsung,s5k6a3",
+ .data = &s5k6a3_drvdata,
+ },
+ {
+ .compatible = "samsung,s5k4e5",
+ .data = &s5k4e5_drvdata,
+ },
+ { }
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node)
+{
+ const struct of_device_id *of_id;
+
+ of_id = of_match_node(fimc_is_sensor_of_ids, node);
+ return of_id ? of_id->data : NULL;
+}
diff --git a/drivers/media/platform/exynos5-is/fimc-is-sensor.h
b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
new file mode 100644
index 000..0ba5733
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-sensor.h
@@ -0,0 +1,65 @@
+/*
+ * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef FIMC_IS_SENSOR_H_
+#define FIMC_IS_SENSOR_H_
+
+#include
+#include
+
+#define S5K6A3_OPEN_TIMEOUT2000 /* ms */
+#define S5K6A3_SENSOR_WIDTH1392
+#define S5K6A3_SENSOR_HEIGHT 1392
+
+#define S5K4E5_OPEN_TIMEOUT2000 /* ms */
+#define S5K4E5_SENSOR_WIDTH2560
+#define S5K4E5_SENSOR_HEIGHT 1920
+
+#define SENSOR_WIDTH_PADDING 16
+#define SENSOR_HEIGHT_PADDING 10
+
+enum fimc_is_sensor_id {
+ FIMC_IS_SENSOR_ID_S5K3H2 = 1,
+ FIMC_IS_SENSOR_ID_S5K6A3,
+ FIMC_IS_SENSOR_ID_S5K4E5,
+ FIMC_IS_SENSOR_ID_S5K3H7,
+ FIMC_IS_SENSOR_ID_CUSTOM,
+ FIMC_IS_SENSOR_ID_END
+};
+
+struct sensor_drv_data {
+ enum fimc_is_sensor_id id;
+ /* sensor open timeout in ms */
+ unsigned short open_timeout;
+ char *setfile_name;
+};
+
+/**
+ * struct fimc_is_sensor - fimc-is sensor data structure
+ * @drvdata: a pointer to the sensor's parameters data structure
+ * @i2c_bus: ISP I2C bus index (0...1)
+ * @width: sensor active width
+ * @height: sensor active height
+ * @pixel_width: sensor effective pixel width (width + padding)
+ * @pixel_height: sensor effective pixel height (height + padding)
+ */
+struct fimc_is_sensor {
+ const struct sensor_drv_data *drvdata;
+ unsigned int i2c_bus;
+ unsigned int width;
+ unsigned int height;
+ unsigned int pixel_width;
+ unsigned int pixel_height;
+};
+
+const struct sensor_drv_data *exynos5_is_sensor_get_drvdata(
+ struct device_node *node);
+
+#endif /* FIMC_IS_SENSOR_H_ */
--
1.7.9.5
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[PATCH v7 11/13] [media] exynos5-is: Add Kconfig and Makefile
Adds Kconfig and Makefile for exynos5-is driver files. Signed-off-by: Shaik Ameer Basha Signed-off-by: Arun Kumar K Reviewed-by: Sylwester Nawrocki --- drivers/media/platform/Kconfig |1 + drivers/media/platform/Makefile|1 + drivers/media/platform/exynos5-is/Kconfig | 20 drivers/media/platform/exynos5-is/Makefile |7 +++ 4 files changed, 29 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/Kconfig create mode 100644 drivers/media/platform/exynos5-is/Makefile diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 08de865..4b0475e 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -123,6 +123,7 @@ config VIDEO_S3C_CAMIF source "drivers/media/platform/soc_camera/Kconfig" source "drivers/media/platform/exynos4-is/Kconfig" +source "drivers/media/platform/exynos5-is/Kconfig" source "drivers/media/platform/s5p-tv/Kconfig" endif # V4L_PLATFORM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index eee28dd..40bf09f 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV)+= s5p-tv/ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D)+= s5p-g2d/ obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/ +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos5-is/ obj-$(CONFIG_BLACKFIN) += blackfin/ diff --git a/drivers/media/platform/exynos5-is/Kconfig b/drivers/media/platform/exynos5-is/Kconfig new file mode 100644 index 000..b67d11a --- /dev/null +++ b/drivers/media/platform/exynos5-is/Kconfig @@ -0,0 +1,20 @@ +config VIDEO_SAMSUNG_EXYNOS5_CAMERA + bool "Samsung Exynos5 SoC Camera Media Device driver" + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME + depends on VIDEO_SAMSUNG_EXYNOS4_IS + help + This is a V4L2 media device driver for Exynos5 SoC series + camera subsystem. + +if VIDEO_SAMSUNG_EXYNOS5_CAMERA + +config VIDEO_SAMSUNG_EXYNOS5_FIMC_IS + tristate "Samsung Exynos5 SoC FIMC-IS driver" + depends on I2C && OF + depends on VIDEO_EXYNOS4_FIMC_IS + select VIDEOBUF2_DMA_CONTIG + help + This is a V4L2 driver for Samsung Exynos5 SoC series Imaging + Subsystem known as FIMC-IS. + +endif #VIDEO_SAMSUNG_EXYNOS5_MDEV diff --git a/drivers/media/platform/exynos5-is/Makefile b/drivers/media/platform/exynos5-is/Makefile new file mode 100644 index 000..6cdb037 --- /dev/null +++ b/drivers/media/platform/exynos5-is/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -Idrivers/media/platform/exynos4-is +exynos5-fimc-is-objs := fimc-is-core.o fimc-is-isp.o fimc-is-scaler.o +exynos5-fimc-is-objs += fimc-is-pipeline.o fimc-is-interface.o fimc-is-sensor.o +exynos-mdevice-objs := exynos5-mdev.o + +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_FIMC_IS) += exynos5-fimc-is.o +obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS5_CAMERA) += exynos-mdevice.o -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 10/13] [media] exynos5-fimc-is: Add the hardware interface module
The hardware interface module finally sends the commands to the
FIMC-IS firmware and runs the interrupt handler for getting the
responses.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
Reviewed-by: Sylwester Nawrocki
---
.../media/platform/exynos5-is/fimc-is-interface.c | 810
.../media/platform/exynos5-is/fimc-is-interface.h | 125 +++
2 files changed, 935 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-interface.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-interface.c
b/drivers/media/platform/exynos5-is/fimc-is-interface.c
new file mode 100644
index 000..c5da6ff
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-interface.c
@@ -0,0 +1,810 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Kil-yeon Lim
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include "fimc-is.h"
+#include "fimc-is-cmd.h"
+#include "fimc-is-regs.h"
+
+#define init_request_barrier(itf) mutex_init(&itf->request_barrier)
+#define enter_request_barrier(itf) mutex_lock(&itf->request_barrier)
+#define exit_request_barrier(itf) mutex_unlock(&itf->request_barrier)
+
+static inline void itf_get_cmd(struct fimc_is_interface *itf,
+ struct fimc_is_msg *msg, unsigned int index)
+{
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ memset(msg, 0, sizeof(*msg));
+
+ switch (index) {
+ case INTR_GENERAL:
+ msg->command = com_regs->ihcmd;
+ msg->instance = com_regs->ihc_sensorid;
+ memcpy(msg->param, com_regs->ihc_param,
+ 4 * sizeof(msg->param[0]));
+ break;
+ case INTR_SCC_FDONE:
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scc_sensor_id;
+ memcpy(msg->param, com_regs->scc_param,
+ 3 * sizeof(msg->param[0]));
+ break;
+ case INTR_SCP_FDONE:
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->scp_sensor_id;
+ memcpy(msg->param, com_regs->scp_param,
+ 3 * sizeof(msg->param[0]));
+ break;
+ case INTR_META_DONE:
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->meta_sensor_id;
+ msg->param[0] = com_regs->meta_param1;
+ break;
+ case INTR_SHOT_DONE:
+ msg->command = IHC_FRAME_DONE;
+ msg->instance = com_regs->shot_sensor_id;
+ memcpy(msg->param, com_regs->shot_param,
+ 2 * sizeof(msg->param[0]));
+ break;
+ default:
+ dev_err(itf->dev, "%s Unknown command\n", __func__);
+ break;
+ }
+}
+
+static inline unsigned int itf_get_intr(struct fimc_is_interface *itf)
+{
+ unsigned int status;
+ struct is_common_reg __iomem *com_regs = itf->com_regs;
+
+ status = readl(itf->regs + INTMSR1) | com_regs->ihcmd_iflag |
+ com_regs->scc_iflag |
+ com_regs->scp_iflag |
+ com_regs->meta_iflag |
+ com_regs->shot_iflag;
+
+ return status;
+}
+
+static void itf_set_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ __set_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static void itf_clr_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&itf->slock_state, flags);
+ __clear_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+}
+
+static int itf_get_state(struct fimc_is_interface *itf,
+ unsigned long state)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&itf->slock_state, flags);
+ ret = test_bit(state, &itf->state);
+ spin_unlock_irqrestore(&itf->slock_state, flags);
+ return ret;
+}
+
+static void itf_init_wakeup(struct fimc_is_interface *itf)
+{
+ itf_set_state(itf, IS_IF_STATE_INIT);
+ wake_up(&itf->irq_queue);
+}
+
+void itf_busy_wakeup(struct fimc_is_interface *itf)
+{
+ itf_clr_state(itf, IS_IF_STATE_BUSY);
+ wake_up(&itf->irq_queue);
+}
+
+static int itf_wait_hw_ready(struct fimc_is_interface *itf)
+{
+ int t;
+ for (t = TRY_RECV_AWARE_COUNT; t >= 0; t--) {
+ unsigned int cfg = readl(itf->regs + INTMSR0);
+ if (INTMSR0_GET_INTMSD(0, cfg) == 0)
+
[PATCH v7 07/13] [media] exynos5-fimc-is: Add scaler subdev
FIMC-IS has two hardware scalers named as scaler-codec and
scaler-preview. This patch adds the common code handling the
video nodes and subdevs of both the scalers.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
Reviewed-by: Sylwester Nawrocki
---
drivers/media/platform/exynos5-is/fimc-is-scaler.c | 472
drivers/media/platform/exynos5-is/fimc-is-scaler.h | 106 +
2 files changed, 578 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-scaler.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-scaler.c
b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
new file mode 100644
index 000..82ba867
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-scaler.c
@@ -0,0 +1,472 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+
+#include "fimc-is.h"
+
+#define IS_SCALER_DRV_NAME "fimc-is-scaler"
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = "YUV 4:2:0 3p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_YUV420M,
+ .depth = {8, 2, 2},
+ .num_planes = 3,
+ },
+ {
+ .name = "YUV 4:2:0 2p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .depth = {8, 4},
+ .num_planes = 2,
+ },
+ {
+ .name = "YUV 4:2:2 1p MultiPlanar",
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .depth = {16},
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ }
+ return NULL;
+}
+
+static int scaler_video_capture_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_start(ctx->pipeline,
+ ctx->scaler_id,
+ vq->num_buffers,
+ ctx->fmt->num_planes);
+ if (ret) {
+ v4l2_err(&ctx->subdev, "Scaler start failed.\n");
+ return -EINVAL;
+ }
+
+ set_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+ int ret;
+
+ ret = fimc_is_pipeline_scaler_stop(ctx->pipeline, ctx->scaler_id);
+ if (ret)
+ v4l2_info(&ctx->subdev, "Scaler already stopped.\n");
+
+ /* Release un-used buffers */
+ while (!list_empty(&ctx->wait_queue)) {
+ buf = fimc_is_scaler_wait_queue_get(ctx);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(&ctx->run_queue)) {
+ buf = fimc_is_scaler_run_queue_get(ctx);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, &ctx->capture_state);
+ return 0;
+}
+
+static int scaler_video_capture_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = ctx->fmt;
+ unsigned int wh;
+ int i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = ctx->width * ctx->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = ctx->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int scaler_video_capture_buffer_init(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_scaler *ctx = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+ const struct fimc_is_fmt *fmt;
+ int i;
+
+ fmt = ctx->fmt;
+ for (i = 0; i < fmt->num_planes; i++)
+ buf->paddr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+ return 0;
+}
+
+static int scaler_video_capture_buffer_prepare(struct vb2_buffer
[PATCH v7 05/13] [media] exynos5-fimc-is: Add register definition and context header
This patch adds the register definition file for the fimc-is driver and also the header file containing the main context for the driver. Signed-off-by: Arun Kumar K Signed-off-by: Kilyeon Im Reviewed-by: Sylwester Nawrocki --- drivers/media/platform/exynos5-is/fimc-is-regs.h | 105 ++ drivers/media/platform/exynos5-is/fimc-is.h | 160 ++ 2 files changed, 265 insertions(+) create mode 100644 drivers/media/platform/exynos5-is/fimc-is-regs.h create mode 100644 drivers/media/platform/exynos5-is/fimc-is.h diff --git a/drivers/media/platform/exynos5-is/fimc-is-regs.h b/drivers/media/platform/exynos5-is/fimc-is-regs.h new file mode 100644 index 000..06aa466 --- /dev/null +++ b/drivers/media/platform/exynos5-is/fimc-is-regs.h @@ -0,0 +1,105 @@ +/* + * Samsung Exynos5 SoC series FIMC-IS driver + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd + * Arun Kumar K + * Kil-yeon Lim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef FIMC_IS_REGS_H +#define FIMC_IS_REGS_H + +/* WDT_ISP register */ +#define WDT0x0017 +/* MCUCTL register */ +#define MCUCTL 0x0018 +/* MCU Controller Register */ +#define MCUCTLR(MCUCTL+0x00) +#define MCUCTLR_AXI_ISPX_AWCACHE(x)((x) << 16) +#define MCUCTLR_AXI_ISPX_ARCACHE(x)((x) << 12) +#define MCUCTLR_MSWRST (1 << 0) +/* Boot Base OFfset Address Register */ +#define BBOAR (MCUCTL+0x04) +#define BBOAR_BBOA(x) ((x) << 0) + +/* Interrupt Generation Register 0 from Host CPU to VIC */ +#define INTGR0 (MCUCTL+0x08) +#define INTGR0_INTGC(n)(1 << ((n) + 16)) +#define INTGR0_INTGD(n)(1 << (n)) + +/* Interrupt Clear Register 0 from Host CPU to VIC */ +#define INTCR0 (MCUCTL+0x0c) +#define INTCR0_INTCC(n)(1 << ((n) + 16)) +#define INTCR0_INTCD(n)(1 << (n)) + +/* Interrupt Mask Register 0 from Host CPU to VIC */ +#define INTMR0 (MCUCTL+0x10) +#define INTMR0_INTMC(n)(1 << ((n) + 16)) +#define INTMR0_INTMD(n)(1 << (n)) + +/* Interrupt Status Register 0 from Host CPU to VIC */ +#define INTSR0 (MCUCTL+0x14) +#define INTSR0_GET_INTSD(n, x) (((x) >> (n)) & 0x1) +#define INTSR0_GET_INTSC(n, x) (((x) >> ((n) + 16)) & 0x1) + +/* Interrupt Mask Status Register 0 from Host CPU to VIC */ +#define INTMSR0(MCUCTL+0x18) +#define INTMSR0_GET_INTMSD(n, x) (((x) >> (n)) & 0x1) +#define INTMSR0_GET_INTMSC(n, x) (((x) >> ((n) + 16)) & 0x1) + +/* Interrupt Generation Register 1 from ISP CPU to Host IC */ +#define INTGR1 (MCUCTL+0x1c) +#define INTGR1_INTGC(n)(1 << (n)) + +/* Interrupt Clear Register 1 from ISP CPU to Host IC */ +#define INTCR1 (MCUCTL+0x20) +#define INTCR1_INTCC(n)(1 << (n)) + +/* Interrupt Mask Register 1 from ISP CPU to Host IC */ +#define INTMR1 (MCUCTL+0x24) +#define INTMR1_INTMC(n)(1 << (n)) + +/* Interrupt Status Register 1 from ISP CPU to Host IC */ +#define INTSR1 (MCUCTL+0x28) +/* Interrupt Mask Status Register 1 from ISP CPU to Host IC */ +#define INTMSR1(MCUCTL+0x2c) +/* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */ +#define INTCR2 (MCUCTL+0x30) +#define INTCR2_INTCC(n)(1 << (n)) + +/* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMR2 (MCUCTL+0x34) +#define INTMR2_INTMCIS(n) (1 << (n)) + +/* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTSR2 (MCUCTL+0x38) +/* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */ +#define INTMSR2(MCUCTL+0x3c) +/* General Purpose Output Control Register (0~17) */ +#define GPOCTLR(MCUCTL+0x40) +#define GPOCTLR_GPOG(n, x) ((x) << (n)) + +/* General Purpose Pad Output Enable Register (0~17) */ +#define GPOENCTLR (MCUCTL+0x44) +#define GPOENCTLR_GPOEN0(n, x) ((x) << (n)) + +/* General Purpose Input Control Register (0~17) */ +#define GPICTLR(MCUCTL+0x48) + +/* IS Shared Registers between ISP CPU and HOST CPU */ +#define ISSR(n)(MCUCTL + 0x80 + (n)) + +/* PMU for FIMC-IS*/ +#define PMUREG_CMU_RESET_ISP_SYS_PWR_REG 0x1584 +#define PMUREG_ISP_ARM_CONFIGURA
[PATCH v7 00/13] Exynos5 IS driver
The patch series add support for Exynos5 camera subsystem. It re-uses mipi-csis and fimc-lite from exynos4-is and adds a new media device and fimc-is device drivers for exynos5. The media device supports asynchronos subdev registration for the fimc-is sensors and is tested on top of the patch series from Sylwester for exynos4-is [1]. [1] http://www.mail-archive.com/linux-media@vger.kernel.org/msg64653.html Changes from v6 --- - Addressed DT binding doc review comments from Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg65771.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg65772.html Changes from v5 --- - Addressed review comments from Sylwester http://www.mail-archive.com/linux-media@vger.kernel.org/msg65578.html http://www.mail-archive.com/linux-media@vger.kernel.org/msg65605.html Changes from v4 --- - Addressed all review comments from Sylwester - Added separate PMU node as suggested by Stephen Warren - Added phandle based discovery of subdevs instead of node name Changes from v3 --- - Dropped the RFC tag - Addressed all review comments from Sylwester and Sachin - Removed clock provider for media dev - Added s5k4e5 sensor devicetree binding doc Changes from v2 --- - Added exynos5 media device driver from Shaik to this series - Added ISP pipeline support in media device driver - Based on Sylwester's latest exynos4-is development - Asynchronos registration of sensor subdevs - Made independent IS-sensor support - Add s5k4e5 sensor driver - Addressed review comments from Sylwester, Hans, Andrzej, Sachin Changes from v1 --- - Addressed all review comments from Sylwester - Made sensor subdevs as independent i2c devices - Lots of cleanup - Debugfs support added - Removed PMU global register access Arun Kumar K (12): [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation [media] exynos5-fimc-is: Add driver core files [media] exynos5-fimc-is: Add common driver header files [media] exynos5-fimc-is: Add register definition and context header [media] exynos5-fimc-is: Add isp subdev [media] exynos5-fimc-is: Add scaler subdev [media] exynos5-fimc-is: Add sensor interface [media] exynos5-fimc-is: Add the hardware pipeline control [media] exynos5-fimc-is: Add the hardware interface module [media] exynos5-is: Add Kconfig and Makefile V4L: s5k6a3: Change sensor min/max resolutions V4L: Add driver for s5k4e5 image sensor Shaik Ameer Basha (1): [media] exynos5-is: Adding media device driver for exynos5 .../devicetree/bindings/media/exynos5-fimc-is.txt | 46 + .../bindings/media/exynos5250-camera.txt | 126 ++ .../devicetree/bindings/media/i2c/s5k4e5.txt | 43 + drivers/media/i2c/Kconfig |8 + drivers/media/i2c/Makefile |1 + drivers/media/i2c/s5k4e5.c | 361 + drivers/media/i2c/s5k6a3.c | 19 +- drivers/media/platform/Kconfig |1 + drivers/media/platform/Makefile|1 + drivers/media/platform/exynos5-is/Kconfig | 20 + drivers/media/platform/exynos5-is/Makefile |7 + drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210 ++ drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++ drivers/media/platform/exynos5-is/fimc-is-cmd.h| 187 +++ drivers/media/platform/exynos5-is/fimc-is-core.c | 413 + drivers/media/platform/exynos5-is/fimc-is-core.h | 132 ++ drivers/media/platform/exynos5-is/fimc-is-err.h| 257 +++ .../media/platform/exynos5-is/fimc-is-interface.c | 810 ++ .../media/platform/exynos5-is/fimc-is-interface.h | 125 ++ drivers/media/platform/exynos5-is/fimc-is-isp.c| 534 ++ drivers/media/platform/exynos5-is/fimc-is-isp.h| 90 ++ .../media/platform/exynos5-is/fimc-is-metadata.h | 767 + drivers/media/platform/exynos5-is/fimc-is-param.h | 1159 ++ .../media/platform/exynos5-is/fimc-is-pipeline.c | 1692 .../media/platform/exynos5-is/fimc-is-pipeline.h | 128 ++ drivers/media/platform/exynos5-is/fimc-is-regs.h | 105 ++ drivers/media/platform/exynos5-is/fimc-is-scaler.c | 472 ++ drivers/media/platform/exynos5-is/fimc-is-scaler.h | 106 ++ drivers/media/platform/exynos5-is/fimc-is-sensor.c | 45 + drivers/media/platform/exynos5-is/fimc-is-sensor.h | 65 + drivers/media/platform/exynos5-is/fimc-is.h| 160 ++ 31 files changed, 9208 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt create mode 100644 Documentation/devicetree/bindings/media/exynos5250-camera.txt create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt create mode 100644 drivers/media/i2c/s5k4e5.c create mode 100644 drivers/media/platform/exynos5-is/Kconfig create mo
[PATCH v7 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation
The patch adds the DT binding documentation for Samsung Exynos5 SoC series imaging subsystem (FIMC-IS). Signed-off-by: Arun Kumar K Reviewed-by: Sylwester Nawrocki --- .../devicetree/bindings/media/exynos5-fimc-is.txt | 46 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt new file mode 100644 index 000..5611401 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt @@ -0,0 +1,46 @@ +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS) +-- + +The camera subsystem on Samsung Exynos5 SoC has some changes relative +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and +FIMC-LITE IPs but has a much improved version of FIMC-IS which can +handle sensor controls and camera post-processing operations. The +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two +dedicated scalers (SCC and SCP). + +fimc-is node + + +Required properties: + +- compatible: must be "samsung,exynos5250-fimc-is" +- reg : physical base address and size of the memory mapped + registers +- interrupt-parent : parent interrupt controller +- interrupts: fimc-is interrupt to the parent interrupt controller +- clocks: list of clock specifiers, corresponding to entries in + clock-names property +- clock-names : must contain "isp", "mcu_isp", "isp_div0", "isp_div1", + "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries, + matching entries in the clocks property +- samsung,pmu : phandle to the Power Management Unit (PMU) node + +i2c-isp (ISP I2C bus controller) nodes +-- + +Required properties: + +- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212, + Exynos4412 and Exynos5250 SoCs +- reg : physical base address and length of the registers set +- clocks : must contain gate clock specifier for this controller +- clock-names : must contain "i2c_isp" entry + +For the i2c-isp node, it is required to specify a pinctrl state named "default", +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. + +Device tree nodes of the image sensors controlled directly by the FIMC-IS +firmware must be child nodes of their corresponding ISP I2C bus controller node. +The data link of these image sensors must be specified using the common video +interfaces bindings, defined in video-interfaces.txt. -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 06/13] [media] exynos5-fimc-is: Add isp subdev
fimc-is driver takes video data input from the ISP video node
which is added in this patch. This node accepts Bayer input
buffers which is given from the IS sensors.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
Reviewed-by: Sylwester Nawrocki
---
drivers/media/platform/exynos5-is/fimc-is-isp.c | 534 +++
drivers/media/platform/exynos5-is/fimc-is-isp.h | 90
2 files changed, 624 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-isp.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-isp.c
b/drivers/media/platform/exynos5-is/fimc-is-isp.c
new file mode 100644
index 000..882c291
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-isp.c
@@ -0,0 +1,534 @@
+/*
+ * Samsung EXYNOS5250 FIMC-IS (Imaging Subsystem) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+
+#include "fimc-is.h"
+
+#define ISP_DRV_NAME "fimc-is-isp"
+
+static const struct fimc_is_fmt formats[] = {
+ {
+ .name = "Bayer GR-BG 8bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .depth = { 8 },
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 10bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+ {
+ .name = "Bayer GR-BG 12bits",
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .depth = { 16 },
+ .num_planes = 1,
+ },
+};
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct fimc_is_fmt *find_format(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++)
+ if (formats[i].fourcc == f->fmt.pix_mp.pixelformat)
+ return &formats[i];
+ return NULL;
+}
+
+static int isp_video_output_start_streaming(struct vb2_queue *vq,
+ unsigned int count)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+
+ set_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_stop_streaming(struct vb2_queue *vq)
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf;
+
+ /* Release unused buffers */
+ while (!list_empty(&isp->wait_queue)) {
+ buf = fimc_is_isp_wait_queue_get(isp);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(&isp->run_queue)) {
+ buf = fimc_is_isp_run_queue_get(isp);
+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
+ }
+
+ clear_bit(STATE_RUNNING, &isp->output_state);
+ return 0;
+}
+
+static int isp_video_output_queue_setup(struct vb2_queue *vq,
+ const struct v4l2_format *pfmt,
+ unsigned int *num_buffers, unsigned int *num_planes,
+ unsigned int sizes[], void *allocators[])
+{
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ const struct fimc_is_fmt *fmt = isp->fmt;
+ unsigned int wh, i;
+
+ if (!fmt)
+ return -EINVAL;
+
+ *num_planes = fmt->num_planes;
+ wh = isp->width * isp->height;
+
+ for (i = 0; i < *num_planes; i++) {
+ allocators[i] = isp->alloc_ctx;
+ sizes[i] = (wh * fmt->depth[i]) / 8;
+ }
+ return 0;
+}
+
+static int isp_video_output_buffer_init(struct vb2_buffer *vb)
+{
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+ buf->paddr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ return 0;
+}
+
+static int isp_video_output_buffer_prepare(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ unsigned long size;
+
+ size = (isp->width * isp->height * isp->fmt->depth[0]) / 8;
+ if (vb2_plane_size(vb, 0) < size) {
+ v4l2_err(&isp->subdev, "User buffer too small (%ld < %ld)\n",
+vb2_plane_size(vb, 0), size);
+ return -EINVAL;
+ }
+ vb2_set_plane_payload(vb, 0, size);
+
+ return 0;
+}
+
+static void isp_video_output_buffer_queue(struct vb2_buffer *vb)
+{
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct fimc_is_isp *isp = vb2_get_drv_priv(vq);
+ struct fimc_is_buf *buf = container_of(vb, struct fimc_is_buf, vb);
+
+ fimc_is_pipeline_buf_lock(isp->pipeline);
+ fimc_is_isp_wait_queue_add(isp, buf);
+ fimc_is_pi
[PATCH v7 03/13] [media] exynos5-fimc-is: Add driver core files
This driver is for the FIMC-IS IP available in Samsung Exynos5
SoC onwards. This patch adds the core files for the new driver.
Signed-off-by: Arun Kumar K
Signed-off-by: Kilyeon Im
Reviewed-by: Sylwester Nawrocki
---
drivers/media/platform/exynos5-is/fimc-is-core.c | 413 ++
drivers/media/platform/exynos5-is/fimc-is-core.h | 132 +++
2 files changed, 545 insertions(+)
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.c
create mode 100644 drivers/media/platform/exynos5-is/fimc-is-core.h
diff --git a/drivers/media/platform/exynos5-is/fimc-is-core.c
b/drivers/media/platform/exynos5-is/fimc-is-core.c
new file mode 100644
index 000..6910581
--- /dev/null
+++ b/drivers/media/platform/exynos5-is/fimc-is-core.c
@@ -0,0 +1,413 @@
+/*
+ * Samsung EXYNOS5 FIMC-IS (Imaging Subsystem) driver
+*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Arun Kumar K
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "fimc-is.h"
+#include "fimc-is-i2c.h"
+
+#define CLK_MCU_ISP_DIV0_FREQ (200 * 100)
+#define CLK_MCU_ISP_DIV1_FREQ (100 * 100)
+#define CLK_ISP_DIV0_FREQ (134 * 100)
+#define CLK_ISP_DIV1_FREQ (68 * 100)
+#define CLK_ISP_DIVMPWM_FREQ (34 * 100)
+
+static const char * const fimc_is_clock_name[] = {
+ [IS_CLK_ISP]= "isp",
+ [IS_CLK_MCU_ISP]= "mcu_isp",
+ [IS_CLK_ISP_DIV0] = "isp_div0",
+ [IS_CLK_ISP_DIV1] = "isp_div1",
+ [IS_CLK_ISP_DIVMPWM]= "isp_divmpwm",
+ [IS_CLK_MCU_ISP_DIV0] = "mcu_isp_div0",
+ [IS_CLK_MCU_ISP_DIV1] = "mcu_isp_div1",
+};
+
+static void fimc_is_put_clocks(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+ if (IS_ERR(is->clock[i]))
+ continue;
+ clk_unprepare(is->clock[i]);
+ clk_put(is->clock[i]);
+ is->clock[i] = ERR_PTR(-EINVAL);
+ }
+}
+
+static int fimc_is_get_clocks(struct fimc_is *is)
+{
+ struct device *dev = &is->pdev->dev;
+ int i, ret;
+
+ for (i = 0; i < IS_CLK_MAX_NUM; i++) {
+ is->clock[i] = clk_get(dev, fimc_is_clock_name[i]);
+ if (IS_ERR(is->clock[i]))
+ goto err;
+ ret = clk_prepare(is->clock[i]);
+ if (ret < 0) {
+ clk_put(is->clock[i]);
+ is->clock[i] = ERR_PTR(-EINVAL);
+ goto err;
+ }
+ }
+ return 0;
+err:
+ fimc_is_put_clocks(is);
+ pr_err("Failed to get clock: %s\n", fimc_is_clock_name[i]);
+ return -ENXIO;
+}
+
+static int fimc_is_configure_clocks(struct fimc_is *is)
+{
+ int i, ret;
+
+ for (i = 0; i < IS_CLK_MAX_NUM; i++)
+ is->clock[i] = ERR_PTR(-EINVAL);
+
+ ret = fimc_is_get_clocks(is);
+ if (ret)
+ return ret;
+
+ /* Set rates */
+ ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV0],
+ CLK_MCU_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is->clock[IS_CLK_MCU_ISP_DIV1],
+ CLK_MCU_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV0], CLK_ISP_DIV0_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is->clock[IS_CLK_ISP_DIV1], CLK_ISP_DIV1_FREQ);
+ if (ret)
+ return ret;
+ ret = clk_set_rate(is->clock[IS_CLK_ISP_DIVMPWM],
+ CLK_ISP_DIVMPWM_FREQ);
+ return ret;
+}
+
+static void fimc_is_pipelines_destroy(struct fimc_is *is)
+{
+ int i;
+
+ for (i = 0; i < is->drvdata->num_instances; i++)
+ fimc_is_pipeline_destroy(&is->pipeline[i]);
+}
+
+static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
+ struct device_node *node)
+{
+ struct fimc_is_sensor *sensor = &is->sensor[index];
+ u32 tmp = 0;
+ int ret;
+
+ sensor->drvdata = exynos5_is_sensor_get_drvdata(node);
+ if (!sensor->drvdata) {
+ dev_err(&is->pdev->dev, "no driver data found for: %s\n",
+node->full_name);
+ return -EINVAL;
+ }
+
+ node = v4l2_of_get_next_endpoint(node, NULL);
+ if (!node)
+ return -EN
[PATCH v7 01/13] [media] exynos5-is: Adding media device driver for exynos5
From: Shaik Ameer Basha
This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.
* MIPI-CSIS
Support interconnection(subdev interface) between devices
* FIMC-LITE
Support capture interface from device(Sensor, MIPI-CSIS) to memory
Support interconnection(subdev interface) between devices
* FIMC-IS
Camera post-processing IP having multiple sub-nodes.
G-Scaler will be added later to the current media device.
The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.
Pipeline0
++ +---+ +---+ ++
| Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
++ +---+ +---+ ++
Pipeline1
++ ++ +---+ +---+
| Memory | --> | ISP | --> |SCC| --> |SCP|
++ ++ +---+ +---+
Signed-off-by: Shaik Ameer Basha
Signed-off-by: Arun Kumar K
---
.../bindings/media/exynos5250-camera.txt | 126 ++
drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210
drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++
3 files changed, 1462 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/exynos5250-camera.txt
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
diff --git a/Documentation/devicetree/bindings/media/exynos5250-camera.txt
b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
new file mode 100644
index 000..09420ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
@@ -0,0 +1,126 @@
+Samsung EXYNOS5 SoC Camera Subsystem
+
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-device nodes are referenced using phandles in the common 'camera' node
+which also includes common properties of the whole subsystem not really
+specific to any single sub-device, like common camera port pins or the common
+camera bus clocks.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible : must be "samsung,exynos5250-fimc"
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property
+- clock-names : must contain "sclk_bayer" entry
+- samsung,csis : list of phandles to the mipi-csis device nodes
+- samsung,fimc-lite: list of phandles to the fimc-lite device nodes
+- samsung,fimc-is : phandle to the fimc-is device node
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named "default".
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A, camera B and RGB bay inputs.
+'reg' property in the port nodes specifies the input type:
+ 1 - parallel camport A
+ 2 - parallel camport B
+ 5 - RGB camera bay
+
+3, 4 are for MIPI CSI-2 bus and are already described in samsung-mipi-csis.txt
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ aliases {
+ fimc-lite0 = &fimc_lite_0
+ };
+
+ /* Parallel bus IF sensor */
+ i2c_0: i2c@1386 {
+ s5k6aa: sensor@3c {
+ compatible = "samsung,s5k6aafx";
+ reg = <0x3c>;
+ vddio-supply = <...>;
+
+ clock-frequency = <2400>;
+ clocks = <...>;
+ clock-names = "mclk";
+
+ port {
+ s5k6aa_ep: endpoint {
+ remote-endpoint = <&fimc0_ep>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <1>;
+ pclk-sample = <1>;
+ };
+ };
+ };
+ };
+
+ /* MIPI CSI-2 bus IF sensor */
+ s5c73m3: sensor@1a {
+ compatible = "samsung,s5c73m3";
+
[PATCH v11 0/8] PHY framework
Added a generic PHY framework that provides a set of APIs for the PHY drivers to create/destroy a PHY and APIs for the PHY users to obtain a reference to the PHY with or without using phandle. This framework will be of use only to devices that uses external PHY (PHY functionality is not embedded within the controller). The intention of creating this framework is to bring the phy drivers spread all over the Linux kernel to drivers/phy to increase code re-use and to increase code maintainability. Comments to make PHY as bus wasn't done because PHY devices can be part of other bus and making a same device attached to multiple bus leads to bad design. If the PHY driver has to send notification on connect/disconnect, the PHY driver should make use of the extcon framework. Using this susbsystem to use extcon framwork will have to be analysed. You can find this patch series @ git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git testing I'll create a new branch *next* once this patch series is finalized. All the PHY driver development that depends on PHY framework can be based on this branch. Did USB enumeration testing in panda and beagle after applying [1] [1] -> https://lkml.org/lkml/2013/7/26/88 Changes from v10: * fixed a mistake in devm_of_phy_provider_register macro which was carried over from earlier version. * used ida_simple_get for obtaining the id. Changes from v9: * Fixed Greg's concern on having *find PHY by string* and changed it to Tomasz pseudo code. * move omap-usb2 phy and twl4030-usb phy to drivers/phy * made all the dependent drivers select GENERIC_PHY instead of having depends on * Made PHY core to assign the id's (so changed the phy_create API). * Adapted twl4030-usb to the new design. Changes from v8: * Added phy_set_drvdata and phy_get_drvdata in phy.h. * Changed phy_create API not to take void *priv. private data should now be set using phy_set_drvdata now. Changes from v7: * Fixed Documentation * Added to_phy, of_phy_provider_register and devm_of_phy_provider_register * modified runtime_pm usage in phy_init, phy_exit, phy_power_on and phy_power_off. Now phy_power_on will enable the clocks and phy_power_off will disable the clocks. * pm_runtime_no_callbacks() is added so that pm_runtime_get_sync doesn't fail * modified other patches to adhere to the changes in the PHY framework * removed usb: phy: twl4030: twl4030 shouldn't be subsys_initcall as it will be merged separately. * reference counting has been added to protect phy ops when the PHY is shared by multiple consumers. Changes from v6 * corrected few typos in Documentation * Changed PHY Subsystem to *bool* in Kconfig (to avoid compilation errors when PHY Subsystem is kept as module and the dependent modules are built-in) * Added if pm_runtime_enabled check before runtime pm calls. Changes from v5: * removed the new sysfs entries as it dint have any new information other than what is already there in /sys/devices/... * removed a bunch of APIs added to get the PHY and now only phy_get and devm_phy_get are used. * Added new APIs to register/unregister the PHY provider. This is needed for dt boot case. * Enabled pm runtime and incorporated the comments given by Alan Stern in a different patch series by Gautam. * Removed the *phy_bind* API. Now the phy binding information should be passed using the platform data to the controller devices. * Fixed a few typos. Changes from v4: * removed of_phy_get_with_args/devm_of_phy_get_with_args. Now the *phy providers* should use their custom implementation of of_xlate or use of_phy_xlate to get *phy instance* from *phy providers*. * Added of_phy_xlate to be used by *phy providers* if it provides only one PHY. * changed phy_core from having subsys_initcall to module_init. * other minor fixes. Changes from v3: * Changed the return value of PHY APIs to ENOSYS * Added APIs of_phy_get_with_args/devm_of_phy_get_with_args to support getting PHYs if the same IP implements multiple PHYs. * modified phy_bind API so that the binding information can now be _updated_. In effect of this removed the binding information added in board files and added only in usb-musb.c. If a particular board uses a different phy binding, it can update it in board file after usb_musb_init(). * Added Documentation/devicetree/bindings/phy/phy-bindings.txt for dt binding information. Changes from v2: * removed phy_descriptor structure completely so changed the APIs which were taking phy_descriptor as parameters * Added 2 more APIs *of_phy_get_byname* and *devm_of_phy_get_byname* to be used by PHY user drivers which has *phy* and *phy-names* binding in the dt data * Fixed a few typos * Removed phy_list and we now use class_dev_iter_init, class_dev_iter_next and class_dev_iter_exit for traversing through the phy list. (Note we still need phy_bind list and phy_bind_mutex). * Changed the sysfs entry name from *bind* to *phy_bind*. Changes from v1: * Added Docum
[PATCH v11 2/8] usb: phy: omap-usb2: use the new generic PHY framework
Used the generic PHY framework API to create the PHY. Now the power off and
power on are done in omap_usb_power_off and omap_usb_power_on respectively.
The omap-usb2 driver is also moved to driver/phy.
However using the old USB PHY library cannot be completely removed
because OTG is intertwined with PHY and moving to the new framework
will break OTG. Once we have a separate OTG state machine, we
can get rid of the USB PHY library.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Sylwester Nawrocki
Acked-by: Felipe Balbi
---
drivers/phy/Kconfig | 12 +
drivers/phy/Makefile |1 +
drivers/{usb => }/phy/phy-omap-usb2.c | 45 ++---
drivers/usb/phy/Kconfig | 10
drivers/usb/phy/Makefile |1 -
5 files changed, 54 insertions(+), 15 deletions(-)
rename drivers/{usb => }/phy/phy-omap-usb2.c (88%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 349bef2..38c3477 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -15,4 +15,16 @@ config GENERIC_PHY
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
+config OMAP_USB2
+ tristate "OMAP USB2 PHY Driver"
+ depends on ARCH_OMAP2PLUS
+ select GENERIC_PHY
+ select USB_PHY
+ select OMAP_CONTROL_USB
+ help
+ Enable this to support the transceiver that is part of SOC. This
+ driver takes care of all the PHY functionality apart from comparator.
+ The USB OTG controller communicates with the comparator using this
+ driver.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9e9560f..ed5b088 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
+obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
diff --git a/drivers/usb/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
similarity index 88%
rename from drivers/usb/phy/phy-omap-usb2.c
rename to drivers/phy/phy-omap-usb2.c
index 844ab68..25e0f3c 100644
--- a/drivers/usb/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
/**
* omap_usb2_set_comparator - links the comparator present in the sytem with
@@ -119,10 +120,36 @@ static int omap_usb2_suspend(struct usb_phy *x, int
suspend)
return 0;
}
+static int omap_usb_power_off(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+
+ omap_control_usb_phy_power(phy->control_dev, 0);
+
+ return 0;
+}
+
+static int omap_usb_power_on(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+
+ omap_control_usb_phy_power(phy->control_dev, 1);
+
+ return 0;
+}
+
+static struct phy_ops ops = {
+ .power_on = omap_usb_power_on,
+ .power_off = omap_usb_power_off,
+ .owner = THIS_MODULE,
+};
+
static int omap_usb2_probe(struct platform_device *pdev)
{
struct omap_usb *phy;
+ struct phy *generic_phy;
struct usb_otg *otg;
+ struct phy_provider *phy_provider;
phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
@@ -144,6 +171,11 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy->phy.otg= otg;
phy->phy.type = USB_PHY_TYPE_USB2;
+ phy_provider = devm_of_phy_provider_register(phy->dev,
+ of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return PTR_ERR(phy_provider);
+
phy->control_dev = omap_get_control_dev();
if (IS_ERR(phy->control_dev)) {
dev_dbg(&pdev->dev, "Failed to get control device\n");
@@ -159,6 +191,15 @@ static int omap_usb2_probe(struct platform_device *pdev)
otg->start_srp = omap_usb_start_srp;
otg->phy= &phy->phy;
+ platform_set_drvdata(pdev, phy);
+ pm_runtime_enable(phy->dev);
+
+ generic_phy = devm_phy_create(phy->dev, &ops, NULL);
+ if (IS_ERR(generic_phy))
+ return PTR_ERR(generic_phy);
+
+ phy_set_drvdata(generic_phy, phy);
+
phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
if (IS_ERR(phy->wkupclk)) {
dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
@@ -174,10 +215,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
usb_add_phy_dev(&phy->phy);
- platform_set_drvdata(pdev, phy);
-
- pm_runtime_enable(phy->dev);
-
return 0;
}
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 3622fff..7813238 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -72,16 +72,6 @@ config OMAP_CONTROL_USB
power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 ha
[PATCH v11 3/8] usb: phy: twl4030: use the new generic PHY framework
Used the generic PHY framework API to create the PHY. For powering on
and powering off the PHY, power_on and power_off ops are used. Once the
MUSB OMAP glue is adapted to the new framework, the suspend and resume
ops of usb phy library will be removed. Also twl4030-usb driver is moved
to drivers/phy/.
However using the old usb phy library cannot be completely removed
because otg is intertwined with phy and moving to the new
framework completely will break otg. Once we have a separate otg state machine,
we can get rid of the usb phy library.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Felipe Balbi
Reviewed-by: Sylwester Nawrocki
---
drivers/phy/Kconfig | 11 ++
drivers/phy/Makefile|1 +
drivers/{usb => }/phy/phy-twl4030-usb.c | 56 +--
drivers/usb/phy/Kconfig |9 -
drivers/usb/phy/Makefile|1 -
include/linux/i2c/twl.h |2 ++
6 files changed, 67 insertions(+), 13 deletions(-)
rename drivers/{usb => }/phy/phy-twl4030-usb.c (95%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 38c3477..ac239ac 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -27,4 +27,15 @@ config OMAP_USB2
The USB OTG controller communicates with the comparator using this
driver.
+config TWL4030_USB
+ tristate "TWL4030 USB Transceiver Driver"
+ depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
+ select GENERIC_PHY
+ select USB_PHY
+ help
+ Enable this to support the USB OTG transceiver on TWL4030
+ family chips (including the TWL5030 and TPS659x0 devices).
+ This transceiver supports high and full speed devices plus,
+ in host mode, low speed.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ed5b088..0dd8a98 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -4,3 +4,4 @@
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
+obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
similarity index 95%
rename from drivers/usb/phy/phy-twl4030-usb.c
rename to drivers/phy/phy-twl4030-usb.c
index 8f78d2d..494f107 100644
--- a/drivers/usb/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -431,6 +432,14 @@ static void twl4030_phy_suspend(struct twl4030_usb *twl,
int controller_off)
dev_dbg(twl->dev, "%s\n", __func__);
}
+static int twl4030_phy_power_off(struct phy *phy)
+{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
+ twl4030_phy_suspend(twl, 0);
+ return 0;
+}
+
static void __twl4030_phy_resume(struct twl4030_usb *twl)
{
twl4030_phy_power(twl, 1);
@@ -459,6 +468,14 @@ static void twl4030_phy_resume(struct twl4030_usb *twl)
}
}
+static int twl4030_phy_power_on(struct phy *phy)
+{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
+ twl4030_phy_resume(twl);
+ return 0;
+}
+
static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
{
/* Enable writing to power configuration registers */
@@ -602,13 +619,22 @@ static int twl4030_usb_phy_init(struct usb_phy *phy)
status = twl4030_usb_linkstat(twl);
twl->linkstat = status;
- if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID)
+ if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) {
omap_musb_mailbox(twl->linkstat);
+ twl4030_phy_resume(twl);
+ }
sysfs_notify(&twl->dev->kobj, NULL, "vbus");
return 0;
}
+static int twl4030_phy_init(struct phy *phy)
+{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
+ return twl4030_usb_phy_init(&twl->phy);
+}
+
static int twl4030_set_suspend(struct usb_phy *x, int suspend)
{
struct twl4030_usb *twl = phy_to_twl(x);
@@ -646,13 +672,23 @@ static int twl4030_set_host(struct usb_otg *otg, struct
usb_bus *host)
return 0;
}
+static const struct phy_ops ops = {
+ .init = twl4030_phy_init,
+ .power_on = twl4030_phy_power_on,
+ .power_off = twl4030_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
static int twl4030_usb_probe(struct platform_device *pdev)
{
struct twl4030_usb_data *pdata = pdev->dev.platform_data;
struct twl4030_usb *twl;
+ struct phy *phy;
int status, err;
struct usb_otg *otg;
struct device_node *np = pdev->dev.of_node;
+ struct phy_provider *phy_provider;
+ struct phy_init_data*init_data = NULL;
twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
if (!twl)
@@ -661,9 +697,10 @@ static int twl4
[PATCH v11 6/8] usb: musb: omap2430: use the new generic PHY framework
Use the generic PHY framework API to get the PHY. The usb_phy_set_resume
and usb_phy_set_suspend is replaced with power_on and
power_off to align with the new PHY framework.
musb->xceiv can't be removed as of now because musb core uses xceiv.state and
xceiv.otg. Once there is a separate state machine to handle otg, these can be
moved out of xceiv and then we can start using the generic PHY framework.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Sylwester Nawrocki
Acked-by: Felipe Balbi
---
drivers/usb/musb/Kconfig |1 +
drivers/usb/musb/musb_core.h |2 ++
drivers/usb/musb/omap2430.c | 26 --
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 797e3fd..25e2e57 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -76,6 +76,7 @@ config USB_MUSB_TUSB6010
config USB_MUSB_OMAP2PLUS
tristate "OMAP2430 and onwards"
depends on ARCH_OMAP2PLUS
+ select GENERIC_PHY
config USB_MUSB_AM35X
tristate "AM35x"
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 7d341c3..6e567bd 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -46,6 +46,7 @@
#include
#include
#include
+#include
struct musb;
struct musb_hw_ep;
@@ -346,6 +347,7 @@ struct musb {
u16 int_tx;
struct usb_phy *xceiv;
+ struct phy *phy;
int nIrq;
unsignedirq_wake:1;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index f44e8b5..063773a 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -348,11 +348,21 @@ static int omap2430_musb_init(struct musb *musb)
* up through ULPI. TWL4030-family PMICs include one,
* which needs a driver, drivers aren't always needed.
*/
- if (dev->parent->of_node)
+ if (dev->parent->of_node) {
+ musb->phy = devm_phy_get(dev->parent, "usb2-phy");
+
+ /* We can't totally remove musb->xceiv as of now because
+* musb core uses xceiv.state and xceiv.otg. Once we have
+* a separate state machine to handle otg, these can be moved
+* out of xceiv and then we can start using the generic PHY
+* framework
+*/
musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent,
"usb-phy", 0);
- else
+ } else {
musb->xceiv = devm_usb_get_phy_dev(dev, 0);
+ musb->phy = devm_phy_get(dev, "usb");
+ }
if (IS_ERR(musb->xceiv)) {
status = PTR_ERR(musb->xceiv);
@@ -364,6 +374,10 @@ static int omap2430_musb_init(struct musb *musb)
return -EPROBE_DEFER;
}
+ if (IS_ERR(musb->phy)) {
+ pr_err("HS USB OTG: no PHY configured\n");
+ return PTR_ERR(musb->phy);
+ }
musb->isr = omap2430_musb_interrupt;
status = pm_runtime_get_sync(dev);
@@ -397,7 +411,7 @@ static int omap2430_musb_init(struct musb *musb)
if (glue->status != OMAP_MUSB_UNKNOWN)
omap_musb_set_mailbox(glue);
- usb_phy_init(musb->xceiv);
+ phy_init(musb->phy);
pm_runtime_put_noidle(musb->controller);
return 0;
@@ -460,6 +474,7 @@ static int omap2430_musb_exit(struct musb *musb)
del_timer_sync(&musb_idle_timer);
omap2430_low_level_exit(musb);
+ phy_exit(musb->phy);
return 0;
}
@@ -638,7 +653,7 @@ static int omap2430_runtime_suspend(struct device *dev)
OTG_INTERFSEL);
omap2430_low_level_exit(musb);
- usb_phy_set_suspend(musb->xceiv, 1);
+ phy_power_off(musb->phy);
}
return 0;
@@ -653,8 +668,7 @@ static int omap2430_runtime_resume(struct device *dev)
omap2430_low_level_init(musb);
musb_writel(musb->mregs, OTG_INTERFSEL,
musb->context.otg_interfsel);
-
- usb_phy_set_suspend(musb->xceiv, 0);
+ phy_power_on(musb->phy);
}
return 0;
--
1.7.10.4
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[PATCH v11 1/8] drivers: phy: add generic PHY framework
The PHY framework provides a set of APIs for the PHY drivers to
create/destroy a PHY and APIs for the PHY users to obtain a reference to the
PHY with or without using phandle. For dt-boot, the PHY drivers should
also register *PHY provider* with the framework.
PHY drivers should create the PHY by passing id and ops like init, exit,
power_on and power_off. This framework is also pm runtime enabled.
The documentation for the generic PHY framework is added in
Documentation/phy.txt and the documentation for dt binding can be found at
Documentation/devicetree/bindings/phy/phy-bindings.txt
Cc: Tomasz Figa
Cc: Greg Kroah-Hartman
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Felipe Balbi
Tested-by: Sylwester Nawrocki
---
.../devicetree/bindings/phy/phy-bindings.txt | 66 ++
Documentation/phy.txt | 166 +
MAINTAINERS|8 +
drivers/Kconfig|2 +
drivers/Makefile |2 +
drivers/phy/Kconfig| 18 +
drivers/phy/Makefile |5 +
drivers/phy/phy-core.c | 698
include/linux/phy/phy.h| 270
9 files changed, 1235 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-bindings.txt
create mode 100644 Documentation/phy.txt
create mode 100644 drivers/phy/Kconfig
create mode 100644 drivers/phy/Makefile
create mode 100644 drivers/phy/phy-core.c
create mode 100644 include/linux/phy/phy.h
diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt
b/Documentation/devicetree/bindings/phy/phy-bindings.txt
new file mode 100644
index 000..8ae844f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
@@ -0,0 +1,66 @@
+This document explains only the device tree data binding. For general
+information about PHY subsystem refer to Documentation/phy.txt
+
+PHY device node
+===
+
+Required Properties:
+#phy-cells:Number of cells in a PHY specifier; The meaning of all those
+ cells is defined by the binding for the phy node. The PHY
+ provider can use the values in cells to find the appropriate
+ PHY.
+
+For example:
+
+phys: phy {
+compatible = "xxx";
+reg = <...>;
+.
+.
+#phy-cells = <1>;
+.
+.
+};
+
+That node describes an IP block (PHY provider) that implements 2 different
PHYs.
+In order to differentiate between these 2 PHYs, an additonal specifier should
be
+given while trying to get a reference to it.
+
+PHY user node
+=
+
+Required Properties:
+phys : the phandle for the PHY device (used by the PHY subsystem)
+phy-names : the names of the PHY corresponding to the PHYs present in the
+ *phys* phandle
+
+Example 1:
+usb1: usb_otg_ss@xxx {
+compatible = "xxx";
+reg = ;
+.
+.
+phys = <&usb2_phy>, <&usb3_phy>;
+phy-names = "usb2phy", "usb3phy";
+.
+.
+};
+
+This node represents a controller that uses two PHYs, one for usb2 and one for
+usb3.
+
+Example 2:
+usb2: usb_otg_ss@xxx {
+compatible = "xxx";
+reg = ;
+.
+.
+phys = <&phys 1>;
+phy-names = "usbphy";
+.
+.
+};
+
+This node represents a controller that uses one of the PHYs of the PHY provider
+device defined previously. Note that the phy handle has an additional specifier
+"1" to differentiate between the two PHYs.
diff --git a/Documentation/phy.txt b/Documentation/phy.txt
new file mode 100644
index 000..0103e4b
--- /dev/null
+++ b/Documentation/phy.txt
@@ -0,0 +1,166 @@
+ PHY SUBSYSTEM
+ Kishon Vijay Abraham I
+
+This document explains the Generic PHY Framework along with the APIs provided,
+and how-to-use.
+
+1. Introduction
+
+*PHY* is the abbreviation for physical layer. It is used to connect a device
+to the physical medium e.g., the USB controller has a PHY to provide functions
+such as serialization, de-serialization, encoding, decoding and is responsible
+for obtaining the required data transmission rate. Note that some USB
+controllers have PHY functionality embedded into it and others use an external
+PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
+SATA etc.
+
+The intention of creating this framework is to bring the PHY drivers spread
+all over the Linux kernel to drivers/phy to increase code re-use and for
+better code maintainability.
+
+This framework will be of use only to devices that use external PHY (PHY
+functionality is not embedded within the controller).
+
+2. Registering/Unregistering the PHY provider
+
+PHY provider refers to an entity that implements one or more PHY instances.
+For the simple case where the PHY provider implements only a single instance of
+the PHY, the framework provides its own implementation of of_xlate in
+of_phy_simple_xla
[PATCH v11 5/8] ARM: dts: omap: update usb_otg_hs data
Updated the usb_otg_hs dt data to include the *phy* and *phy-names*
binding in order for the driver to use the new generic PHY framework.
Also updated the Documentation to include the binding information.
The PHY binding information can be found at
Documentation/devicetree/bindings/phy/phy-bindings.txt
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Felipe Balbi
Acked-by: Tony Lindgren
Reviewed-by: Sylwester Nawrocki
---
Documentation/devicetree/bindings/usb/omap-usb.txt |5 +
Documentation/devicetree/bindings/usb/usb-phy.txt |6 ++
arch/arm/boot/dts/omap3-beagle-xm.dts |2 ++
arch/arm/boot/dts/omap3-evm.dts|2 ++
arch/arm/boot/dts/omap3-overo.dtsi |2 ++
arch/arm/boot/dts/omap4.dtsi |3 +++
arch/arm/boot/dts/twl4030.dtsi |1 +
7 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 57e71f6..825790d 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -19,6 +19,9 @@ OMAP MUSB GLUE
- power : Should be "50". This signifies the controller can supply up to
100mA when operating in host mode.
- usb-phy : the phandle for the PHY device
+ - phys : the phandle for the PHY device (used by generic PHY framework)
+ - phy-names : the names of the PHY corresponding to the PHYs present in the
+ *phy* phandle.
Optional properties:
- ctrl-module : phandle of the control module this glue uses to write to
@@ -33,6 +36,8 @@ usb_otg_hs: usb_otg_hs@4a0ab000 {
num-eps = <16>;
ram-bits = <12>;
ctrl-module = <&omap_control_usb>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
};
Board specific device node entry
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index 61496f5..c0245c8 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -5,6 +5,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be "ti,omap-usb2"
- reg : Address and length of the register set for the device.
+ - #phy-cells: determine the number of cells that should be given in the
+ phandle while referencing this phy.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -16,6 +18,7 @@ usb2phy@4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb>;
+ #phy-cells = <0>;
};
OMAP USB3 PHY
@@ -25,6 +28,8 @@ Required properties:
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in "reg".
+ - #phy-cells: determine the number of cells that should be given in the
+ phandle while referencing this phy.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -39,4 +44,5 @@ usb3phy@4a084400 {
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb>;
+ #phy-cells = <0>;
};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index afdb164..533b2da 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -144,6 +144,8 @@
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 7d4329d..4134dd0 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -70,6 +70,8 @@
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi
b/arch/arm/boot/dts/omap3-overo.dtsi
index 8f1abec..a461d2f 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -76,6 +76,8 @@
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
+ phys = <&usb2_phy>;
+ phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 22d9f2b..1e8e2fe 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -520,6 +520,7 @@
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb>;
+ #phy-cells = <0>;
};
};
@@
[PATCH v11 7/8] usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2
Now that omap-usb2 is adapted to the new generic PHY framework,
*set_suspend* ops can be removed from omap-usb2 driver.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Felipe Balbi
Reviewed-by: Sylwester Nawrocki
---
drivers/phy/phy-omap-usb2.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 25e0f3c..dec3fab 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -97,29 +97,6 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb2_suspend(struct usb_phy *x, int suspend)
-{
- u32 ret;
- struct omap_usb *phy = phy_to_omapusb(x);
-
- if (suspend && !phy->is_suspended) {
- omap_control_usb_phy_power(phy->control_dev, 0);
- pm_runtime_put_sync(phy->dev);
- phy->is_suspended = 1;
- } else if (!suspend && phy->is_suspended) {
- ret = pm_runtime_get_sync(phy->dev);
- if (ret < 0) {
- dev_err(phy->dev, "get_sync failed with err %d\n",
- ret);
- return ret;
- }
- omap_control_usb_phy_power(phy->control_dev, 1);
- phy->is_suspended = 0;
- }
-
- return 0;
-}
-
static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
@@ -167,7 +144,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy->phy.dev= phy->dev;
phy->phy.label = "omap-usb2";
- phy->phy.set_suspend= omap_usb2_suspend;
phy->phy.otg= otg;
phy->phy.type = USB_PHY_TYPE_USB2;
@@ -182,7 +158,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
return -ENODEV;
}
- phy->is_suspended = 1;
omap_control_usb_phy_power(phy->control_dev, 0);
otg->set_host = omap_usb_set_host;
--
1.7.10.4
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[PATCH v11 4/8] arm: omap3: twl: add phy consumer data in twl4030_usb_data
The PHY framework uses the phy consumer data populated in platform data in the
case of non-dt boot to return the reference to the PHY when the controller
(PHY consumer) requests for it. So populated the phy consumer data in the
platform
data of twl usb.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/mach-omap2/twl-common.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index c05898f..b0d54da 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -90,8 +91,18 @@ void __init omap_pmic_late_init(void)
}
#if defined(CONFIG_ARCH_OMAP3)
+struct phy_consumer consumers[] = {
+ PHY_CONSUMER("musb-hdrc.0", "usb"),
+};
+
+struct phy_init_data init_data = {
+ .consumers = consumers,
+ .num_consumers = ARRAY_SIZE(consumers),
+};
+
static struct twl4030_usb_data omap3_usb_pdata = {
.usb_mode = T2_USB_MODE_ULPI,
+ .init_data = &init_data,
};
static int omap3_batt_table[] = {
--
1.7.10.4
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[PATCH v11 8/8] usb: phy: twl4030-usb: remove *set_suspend* and *phy_init* ops
Now that twl4030-usb is adapted to the new generic PHY framework,
*set_suspend* and *phy_init* ops can be removed from twl4030-usb driver.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Felipe Balbi
Reviewed-by: Sylwester Nawrocki
---
drivers/phy/phy-twl4030-usb.c | 57 ++---
1 file changed, 13 insertions(+), 44 deletions(-)
diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
index 494f107..c437211 100644
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -422,25 +422,20 @@ static void twl4030_phy_power(struct twl4030_usb *twl,
int on)
}
}
-static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
+static int twl4030_phy_power_off(struct phy *phy)
{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
if (twl->asleep)
- return;
+ return 0;
twl4030_phy_power(twl, 0);
twl->asleep = 1;
dev_dbg(twl->dev, "%s\n", __func__);
-}
-
-static int twl4030_phy_power_off(struct phy *phy)
-{
- struct twl4030_usb *twl = phy_get_drvdata(phy);
-
- twl4030_phy_suspend(twl, 0);
return 0;
}
-static void __twl4030_phy_resume(struct twl4030_usb *twl)
+static void __twl4030_phy_power_on(struct twl4030_usb *twl)
{
twl4030_phy_power(twl, 1);
twl4030_i2c_access(twl, 1);
@@ -449,11 +444,13 @@ static void __twl4030_phy_resume(struct twl4030_usb *twl)
twl4030_i2c_access(twl, 0);
}
-static void twl4030_phy_resume(struct twl4030_usb *twl)
+static int twl4030_phy_power_on(struct phy *phy)
{
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
+
if (!twl->asleep)
- return;
- __twl4030_phy_resume(twl);
+ return 0;
+ __twl4030_phy_power_on(twl);
twl->asleep = 0;
dev_dbg(twl->dev, "%s\n", __func__);
@@ -466,13 +463,6 @@ static void twl4030_phy_resume(struct twl4030_usb *twl)
cancel_delayed_work(&twl->id_workaround_work);
schedule_delayed_work(&twl->id_workaround_work, HZ);
}
-}
-
-static int twl4030_phy_power_on(struct phy *phy)
-{
- struct twl4030_usb *twl = phy_get_drvdata(phy);
-
- twl4030_phy_resume(twl);
return 0;
}
@@ -604,9 +594,9 @@ static void twl4030_id_workaround_work(struct work_struct
*work)
}
}
-static int twl4030_usb_phy_init(struct usb_phy *phy)
+static int twl4030_phy_init(struct phy *phy)
{
- struct twl4030_usb *twl = phy_to_twl(phy);
+ struct twl4030_usb *twl = phy_get_drvdata(phy);
enum omap_musb_vbus_id_status status;
/*
@@ -621,32 +611,13 @@ static int twl4030_usb_phy_init(struct usb_phy *phy)
if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) {
omap_musb_mailbox(twl->linkstat);
- twl4030_phy_resume(twl);
+ twl4030_phy_power_on(phy);
}
sysfs_notify(&twl->dev->kobj, NULL, "vbus");
return 0;
}
-static int twl4030_phy_init(struct phy *phy)
-{
- struct twl4030_usb *twl = phy_get_drvdata(phy);
-
- return twl4030_usb_phy_init(&twl->phy);
-}
-
-static int twl4030_set_suspend(struct usb_phy *x, int suspend)
-{
- struct twl4030_usb *twl = phy_to_twl(x);
-
- if (suspend)
- twl4030_phy_suspend(twl, 1);
- else
- twl4030_phy_resume(twl);
-
- return 0;
-}
-
static int twl4030_set_peripheral(struct usb_otg *otg,
struct usb_gadget *gadget)
{
@@ -719,8 +690,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
twl->phy.label = "twl4030";
twl->phy.otg= otg;
twl->phy.type = USB_PHY_TYPE_USB2;
- twl->phy.set_suspend= twl4030_set_suspend;
- twl->phy.init = twl4030_usb_phy_init;
otg->phy= &twl->phy;
otg->set_host = twl4030_set_host;
--
1.7.10.4
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[PATCH] clk: samsung: pll: Use new registration method for PLL6552 and PLL6553
This patch modifies PLL6552 and PLL6553 clock drivers to use recently
added common Samsung PLL registration method.
Signed-off-by: Tomasz Figa
---
drivers/clk/samsung/clk-pll.c | 105 +-
drivers/clk/samsung/clk-pll.h | 6 +--
2 files changed, 13 insertions(+), 98 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0775554..7572d1d 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -441,9 +441,6 @@ struct clk * __init samsung_clk_register_pll46xx(const char
*name,
* PLL6552 Clock Type
*/
-#define PLL6552_LOCK_REG 0x00
-#define PLL6552_CON_REG0x0c
-
#define PLL6552_MDIV_MASK 0x3ff
#define PLL6552_PDIV_MASK 0x3f
#define PLL6552_SDIV_MASK 0x7
@@ -451,21 +448,14 @@ struct clk * __init samsung_clk_register_pll46xx(const
char *name,
#define PLL6552_PDIV_SHIFT 8
#define PLL6552_SDIV_SHIFT 0
-struct samsung_clk_pll6552 {
- struct clk_hw hw;
- void __iomem *reg_base;
-};
-
-#define to_clk_pll6552(_hw) container_of(_hw, struct samsung_clk_pll6552, hw)
-
static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll6552 *pll = to_clk_pll6552(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->reg_base + PLL6552_CON_REG);
+ pll_con = __raw_readl(pll->con_reg);
mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
@@ -480,48 +470,10 @@ static const struct clk_ops samsung_pll6552_clk_ops = {
.recalc_rate = samsung_pll6552_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll6552(const char *name,
- const char *pname, void __iomem *base)
-{
- struct samsung_clk_pll6552 *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err("%s: could not allocate pll clk %s\n", __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = &samsung_pll6552_clk_ops;
- init.parent_names = &pname;
- init.num_parents = 1;
-
- pll->hw.init = &init;
- pll->reg_base = base;
-
- clk = clk_register(NULL, &pll->hw);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register pll clock %s\n", __func__,
- name);
- kfree(pll);
- }
-
- if (clk_register_clkdev(clk, name, NULL))
- pr_err("%s: failed to register lookup for %s", __func__, name);
-
- return clk;
-}
-
/*
* PLL6553 Clock Type
*/
-#define PLL6553_LOCK_REG 0x00
-#define PLL6553_CON0_REG 0x0c
-#define PLL6553_CON1_REG 0x10
-
#define PLL6553_MDIV_MASK 0xff
#define PLL6553_PDIV_MASK 0x3f
#define PLL6553_SDIV_MASK 0x7
@@ -531,22 +483,15 @@ struct clk * __init samsung_clk_register_pll6552(const
char *name,
#define PLL6553_SDIV_SHIFT 0
#define PLL6553_KDIV_SHIFT 0
-struct samsung_clk_pll6553 {
- struct clk_hw hw;
- void __iomem *reg_base;
-};
-
-#define to_clk_pll6553(_hw) container_of(_hw, struct samsung_clk_pll6553, hw)
-
static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll6553 *pll = to_clk_pll6553(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->reg_base + PLL6553_CON0_REG);
- pll_con1 = __raw_readl(pll->reg_base + PLL6553_CON1_REG);
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con1 = __raw_readl(pll->con_reg + 0x4);
mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -563,40 +508,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = {
.recalc_rate = samsung_pll6553_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll6553(const char *name,
- const char *pname, void __iomem *base)
-{
- struct samsung_clk_pll6553 *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err("%s: could not allocate pll clk %s\n", __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = &samsung_pll6553_clk_ops;
- init
Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On 08/21, Tomasz Figa wrote: > On Tuesday 20 of August 2013 22:14:42 Russell King - ARM Linux wrote: > > On Tue, Aug 20, 2013 at 06:11:10PM +0200, Tomasz Figa wrote: > > > Sometimes it is necessary to fix interrupt affinity to an offline CPU, > > > for example in initialization of local timers. This patch modifies > > > .set_affinity() operation of irq-gic driver to fall back to any > > > possible CPU if no online CPU can be found in requested CPU mask. > > > > Err, this is a bad idea. If a CPU is offline, then it must not respond > > to interrupts. If you bind an interrupt to an offline CPU, and that > > device asserts its interrupt, what happens? It doesn't get serviced > > until that CPU comes back online, which may be a very long time. > > > > If, for example, that is your network device, it would mean your > > network stops operating. Worse, the network layer will time out and > > reset the ethernet device, trying to get things working (which it > > won't.) > > > > I think how I used to handle this case prior to genirq is that I fell > > back to any online CPU if the interrupt ended up only routed to offline > > CPUs, but when an offline CPU comes back, it could then be re-routed > > back to that CPU. In other words, the mask change was non-destructive. > > > > I think with genirq, such mask changes are destructive. > > Yes, that's correct. Although if you _explicitly_ request the interrupt to > be routed to an offline CPU (i.e. only offline CPUs have bits set in > passed cpumask), is it an error? > > There is at least one irqchip that does not check received cpumask for > this (metag) and I don't see any documentation saying what should happen > in this case in .set_affinity operation. > > Still, if you have any better solution for the original problem (broken > Exynos4210 local timers, due to failing irq_set_affinity()), then I'd > appreciate it, as I don't like the one from this patch too much either. > One "solution" might be to change the irq affinity after the CPU is marked online via the hotplug notifier chain. For a short period of time the timer interrupt will go to a different CPU but I don't see how that is a problem. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/16] pwm: samsung: Update DT bindings documentation to cover clocks
On Tuesday 20 of August 2013 14:34:30 Stephen Warren wrote: > On 08/20/2013 11:31 AM, Tomasz Figa wrote: > > PWM driver consumes at least one and up to three clocks, which need to > > be specified in device tree when used. This patch updates bindings > > documentation to add information about clocks. > > > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > > b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > > > > +- clock-names: should contain all following required clock names: > > +- "timers" - PWM base clock used to generate PWM signals, > > + and any subset of following optional clock names: > > +- "pwm-tclk0" - first external PWM clock source, > > +- "pwm-tclk1" - second external PWM clock source. > > + Note that not all IP variants allow using all external clock > > sources. + Refer to SoC documentation to learn which clock source > > configurations + are available. > > It might be nice to explicitly enumerate which variants (or rather, I > suppose which exact compatible values) support which optional clocks. > However, I suppose it's fine to just say "go read the HW manual" > instead. I don't have enough information about some of the variants, so I decided to put it this way, instead of making an incomplete list or speculating about things. > So, this patch, > Acked-by: Stephen Warren Thanks. > (although this patch isn't backwards-compatible since before now, DT > nodes didn't need to provide any entries in clocks) The thing is that the clocks were supposed to be there from the beginning, but in a hurry I forgot to specify them in original bindings documentation and things were running over compatibility clkdev aliases anyway, so nobody (including me) noticed. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/8] Documentation: devicetree: Update Exynos MCT bindings description
On Tuesday 20 of August 2013 14:41:15 Stephen Warren wrote:
> On 08/20/2013 11:12 AM, Tomasz Figa wrote:
> > On Tuesday 20 of August 2013 11:00:53 Stephen Warren wrote:
> >> On 08/20/2013 07:52 AM, Tomasz Figa wrote:
> >>> This patch updates description of device tree bindings for Exynos
> >>> MCT
> >>>
> >>> (multicore timers). Namely:
> >>> - added note about simplified specification of local timer
> >>> interrupts,
> >>>
> >>>when using single per-processor interrupt for all local timers,
> >>>
> >>> - changed first example that was incorrectly suggesting that global
> >>>
> >>>timer interrupts are optional,
> >>>
> >>> - simplified example interrupt map,
> >>> - added example showing simplified local timer interrupt
> >>> specification.
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> >>> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> >>>
> >>> -Example 1: In this example, the system uses only the first global
> >>> timer
> >>> -interrupt generated by MCT and the remaining three global timer
> >>> -interrupts are unused. Two local timer interrupts have been
> >>> -specified.
> >>> + For MCT block that uses a per-processor interrupt for local
> >>> timers,
> >>> such + as ones compatible with "samusng,exynos4412-mct", only one
> >>> local timer
> >>
> >> samsung is typo'd there.
> >
> > Oops. ;)
> >
> >>> +Example 2: In this example, the timer interrupts are connected to
> >>> two
> >>> separate + interrupt controllers. Hence, an interrupt-map
is
> >>> created to map + the interrupts to the respective interrupt
> >>> controllers.
> >>>
> >>> mct@101C {
> >>>
> >>> compatible = "samsung,exynos4210-mct";
> >>> reg = <0x101C 0x800>;
> >>>
> >>> - interrupt-controller;
> >>> - #interrups-cells = <2>;
> >>>
> >>> interrupt-parent = <&mct_map>;
> >>>
> >>> - interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
> >>> - <4 0>, <5 0>;
> >>> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
> >>>
> >>> mct_map: mct-map {
> >>>
> >>> - #interrupt-cells = <2>;
> >>> + #interrupt-cells = <1>;
> >>>
> >>> #address-cells = <0>;
> >>> #size-cells = <0>;
> >>
> >> I don't believe you need either of those two properties in a node
> >> solely used as an interrupt map.
> >
> > Well, you don't need #size-cells, as it is not used for interrupt-map
> > property.
> >
> > As for #address-cell property, you need it, as it defines how many
> > cells are used in interrupt map specifier for unit address. See ePAPR
> > 2.4.3.1 or [1] for a description of interrupt-map property format.
> >
> > [1] -
> > http://devicetree.org/Device_Tree_Usage#Advanced_Interrupt_Mapping
> Uggh. Yes, you're right.
>
> >> Also, why not put the interrupt-map property directly into the main
> >> mct
> >> node; I don't believe there's any requirement nor advantage to it
> >> being
> >> a separate node.
> >
> > It is more readable, as you don't mix virtual (helper) properties,
> > with
> > those describing the hardware. Otherwise both ways are technically
> > correct, but not for all cases, i.e. only when #address-cells and
> > #interrupt-cells properties aren't used for device's own purposes.
>
> Hmm. I see the argument.
>
> >>> +Example 3: In this example, the IP contains four local timers, but
> >>> using + a per-processor interrupt to handle them. Either all
the
> >>> local + timer interrupts can be specified, with the same
> >>> interrupt
> >>> specifier + value or just the first one.
> >>
> >> That sounds like it should be two separate examples.
> >>
> >> Actually, there's already a 2-timer example above using separate
> >> interrupts, so why not make this example *just* be for the
> >> single-interrupt case?
> >
> > Well, I wanted to show that both ways of specification would be
> > equivalent here. If you insist on making it a single example, then I
> > can send next version with this changed.
>
> Oh! I didn't see the /* */ at all in the third example...
>
> I think it'd be more obvious if you wrote the whole property out twice:
>
> + interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> + <0 42 0>/*, <0 42 0>, <0 42 0>, <0 42 0>*/;
> + /* or: */
> + interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> + <0 42 0>;
That's a good idea. I will send new version with the typo above fixed and
this example done the way you proposed.
Best regards,
Tomasz
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Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On Tuesday 20 of August 2013 22:14:42 Russell King - ARM Linux wrote: > On Tue, Aug 20, 2013 at 06:11:10PM +0200, Tomasz Figa wrote: > > Sometimes it is necessary to fix interrupt affinity to an offline CPU, > > for example in initialization of local timers. This patch modifies > > .set_affinity() operation of irq-gic driver to fall back to any > > possible CPU if no online CPU can be found in requested CPU mask. > > Err, this is a bad idea. If a CPU is offline, then it must not respond > to interrupts. If you bind an interrupt to an offline CPU, and that > device asserts its interrupt, what happens? It doesn't get serviced > until that CPU comes back online, which may be a very long time. > > If, for example, that is your network device, it would mean your > network stops operating. Worse, the network layer will time out and > reset the ethernet device, trying to get things working (which it > won't.) > > I think how I used to handle this case prior to genirq is that I fell > back to any online CPU if the interrupt ended up only routed to offline > CPUs, but when an offline CPU comes back, it could then be re-routed > back to that CPU. In other words, the mask change was non-destructive. > > I think with genirq, such mask changes are destructive. Yes, that's correct. Although if you _explicitly_ request the interrupt to be routed to an offline CPU (i.e. only offline CPUs have bits set in passed cpumask), is it an error? There is at least one irqchip that does not check received cpumask for this (metag) and I don't see any documentation saying what should happen in this case in .set_affinity operation. Still, if you have any better solution for the original problem (broken Exynos4210 local timers, due to failing irq_set_affinity()), then I'd appreciate it, as I don't like the one from this patch too much either. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On Tue, Aug 20, 2013 at 06:11:10PM +0200, Tomasz Figa wrote: > Sometimes it is necessary to fix interrupt affinity to an offline CPU, > for example in initialization of local timers. This patch modifies > .set_affinity() operation of irq-gic driver to fall back to any possible > CPU if no online CPU can be found in requested CPU mask. Err, this is a bad idea. If a CPU is offline, then it must not respond to interrupts. If you bind an interrupt to an offline CPU, and that device asserts its interrupt, what happens? It doesn't get serviced until that CPU comes back online, which may be a very long time. If, for example, that is your network device, it would mean your network stops operating. Worse, the network layer will time out and reset the ethernet device, trying to get things working (which it won't.) I think how I used to handle this case prior to genirq is that I fell back to any online CPU if the interrupt ended up only routed to offline CPUs, but when an offline CPU comes back, it could then be re-routed back to that CPU. In other words, the mask change was non-destructive. I think with genirq, such mask changes are destructive. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6] s5k5baf: add camera sensor driver
On 08/20/2013 10:03 AM, Andrzej Hajda wrote: > Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor > with embedded SoC ISP. > The driver exposes the sensor as two V4L2 subdevices: > - S5K5BAF-CIS - pure CMOS Image Sensor, fixed 1600x1200 format, > no controls. > - S5K5BAF-ISP - Image Signal Processor, formats up to 1600x1200, > pre/post ISP cropping, downscaling via selection API, controls. > diff --git a/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt > b/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt > +Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP > + > + > +Required properties: > + > +- compatible : "samsung,s5k5baf"; > +- reg : I2C slave address of the sensor; > +- vdda-supply : analog power supply 2.8V (2.6V to 3.0V); > +- vddreg-supply: regulator input power supply 1.8V (1.7V to 1.9V) > + or 2.8V (2.6V to 3.0); > +- vddio-supply : I/O power supply 1.8V (1.65V to 1.95V) > + or 2.8V (2.5V to 3.1V); > +- stbyn-gpios : GPIO connected to STDBYN pin; > +- rstn-gpios : GPIO connected to RSTN pin; > +- clocks : the sensor's master clock specifier (from the common > + clock bindings); > +- clock-names : must be "mclk"; That all looks sane. > +Optional properties: > + > +- clock-frequency : master clock frequency in Hz; if this property is > + not specified default 24 MHz value will be used. I /think/ the explanation you gave Mark on this property makes sense. However, it's not clear from the description what this does; in many other cases a clock-frequency describes a fixed/actual input clock rate to a device, rather than a frequency which the device believes it should operate at, and hence the driver should request. Perhaps the following would describe this: - clock-frequency : The frequency at which the "mclk" clock should be configured to operate, in Hz. If this property is not specified default 24 MHz value will be used. To me, this more strongly implies that the user of the node should configure the clock, rather than the property reporting the rate at which the clock is already configured to operate. I think the rest of the binding doc (below this point) seems reasonable too. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/8] Documentation: devicetree: Update Exynos MCT bindings description
On 08/20/2013 11:12 AM, Tomasz Figa wrote:
> On Tuesday 20 of August 2013 11:00:53 Stephen Warren wrote:
>> On 08/20/2013 07:52 AM, Tomasz Figa wrote:
>>> This patch updates description of device tree bindings for Exynos MCT
>>>
>>> (multicore timers). Namely:
>>> - added note about simplified specification of local timer interrupts,
>>>
>>>when using single per-processor interrupt for all local timers,
>>>
>>> - changed first example that was incorrectly suggesting that global
>>>
>>>timer interrupts are optional,
>>>
>>> - simplified example interrupt map,
>>> - added example showing simplified local timer interrupt
>>> specification.
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>>> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
>>>
>>> -Example 1: In this example, the system uses only the first global
>>> timer
>>> - interrupt generated by MCT and the remaining three global timer
>>> - interrupts are unused. Two local timer interrupts have been
>>> - specified.
>>> + For MCT block that uses a per-processor interrupt for local timers,
>>> such + as ones compatible with "samusng,exynos4412-mct", only one
>>> local timer
>> samsung is typo'd there.
>
> Oops. ;)
>
>>> +Example 2: In this example, the timer interrupts are connected to two
>>> separate + interrupt controllers. Hence, an interrupt-map is
>>> created to map + the interrupts to the respective interrupt
>>> controllers.
>>>
>>> mct@101C {
>>>
>>> compatible = "samsung,exynos4210-mct";
>>> reg = <0x101C 0x800>;
>>>
>>> - interrupt-controller;
>>> - #interrups-cells = <2>;
>>>
>>> interrupt-parent = <&mct_map>;
>>>
>>> - interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
>>> -<4 0>, <5 0>;
>>> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
>>>
>>> mct_map: mct-map {
>>>
>>> - #interrupt-cells = <2>;
>>> + #interrupt-cells = <1>;
>>>
>>> #address-cells = <0>;
>>> #size-cells = <0>;
>>
>> I don't believe you need either of those two properties in a node solely
>> used as an interrupt map.
>
> Well, you don't need #size-cells, as it is not used for interrupt-map
> property.
>
> As for #address-cell property, you need it, as it defines how many cells
> are used in interrupt map specifier for unit address. See ePAPR 2.4.3.1 or
> [1] for a description of interrupt-map property format.
>
> [1] - http://devicetree.org/Device_Tree_Usage#Advanced_Interrupt_Mapping
Uggh. Yes, you're right.
>> Also, why not put the interrupt-map property directly into the main mct
>> node; I don't believe there's any requirement nor advantage to it being
>> a separate node.
>
> It is more readable, as you don't mix virtual (helper) properties, with
> those describing the hardware. Otherwise both ways are technically correct,
> but not for all cases, i.e. only when #address-cells and #interrupt-cells
> properties aren't used for device's own purposes.
Hmm. I see the argument.
>>> +Example 3: In this example, the IP contains four local timers, but
>>> using +a per-processor interrupt to handle them. Either all the
>>> local +timer interrupts can be specified, with the same interrupt
>>> specifier +value or just the first one.
>>
>> That sounds like it should be two separate examples.
>>
>> Actually, there's already a 2-timer example above using separate
>> interrupts, so why not make this example *just* be for the
>> single-interrupt case?
>
> Well, I wanted to show that both ways of specification would be equivalent
> here. If you insist on making it a single example, then I can send next
> version with this changed.
Oh! I didn't see the /* */ at all in the third example...
I think it'd be more obvious if you wrote the whole property out twice:
+ interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+<0 42 0>/*, <0 42 0>, <0 42 0>, <0 42 0>*/;
+ /* or: */
+ interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+<0 42 0>;
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Re: [PATCH 01/16] pwm: samsung: Update DT bindings documentation to cover clocks
On 08/20/2013 11:31 AM, Tomasz Figa wrote: > PWM driver consumes at least one and up to three clocks, which need to be > specified in device tree when used. This patch updates bindings > documentation to add information about clocks. > diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt > +- clock-names: should contain all following required clock names: > +- "timers" - PWM base clock used to generate PWM signals, > + and any subset of following optional clock names: > +- "pwm-tclk0" - first external PWM clock source, > +- "pwm-tclk1" - second external PWM clock source. > + Note that not all IP variants allow using all external clock sources. > + Refer to SoC documentation to learn which clock source configurations > + are available. It might be nice to explicitly enumerate which variants (or rather, I suppose which exact compatible values) support which optional clocks. However, I suppose it's fine to just say "go read the HW manual" instead. So, this patch, Acked-by: Stephen Warren (although this patch isn't backwards-compatible since before now, DT nodes didn't need to provide any entries in clocks) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] ARM: dts: exynos4210: Work around lack of cpufreq regulator lookup
Exynos cpufreq drivers does not support device tree based regulator
lookup, so it can get the VDD ARM regulator only by its name. To get
cpufreq working for now, this patch works this around by renaming the
regulator in board dts files to vdd_arm, which is the name expected by
the driver.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4210-origen.dts | 7 ++-
arch/arm/boot/dts/exynos4210-trats.dts | 7 ++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index 382d8c7..46378fe 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -192,7 +192,12 @@
};
buck1_reg: BUCK1 {
- regulator-name = "VDD_ARM_1.2V";
+ /*
+ * HACK: The real name is VDD_ARM_1.2V,
+ * but exynos-cpufreq does not support
+ * DT-based regulator lookup yet.
+ */
+ regulator-name = "vdd_arm";
regulator-min-microvolt = <95>;
regulator-max-microvolt = <135>;
regulator-always-on;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 1c164f2..63cc571 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -290,7 +290,12 @@
};
varm_breg: BUCK1 {
-regulator-name = "VARM_1.2V_C210";
+/*
+ * HACK: The real name is VARM_1.2V_C210,
+ * but exynos-cpufreq does not support
+ * DT-based regulator lookup yet.
+ */
+regulator-name = "vdd_arm";
regulator-min-microvolt = <90>;
regulator-max-microvolt = <135>;
regulator-always-on;
--
1.8.3.2
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[PATCH 00/16] Exynos clock clean-up for 3.12
This series fixes various functional and non-functional (e.g. stylistic) issues in Common Clock Framework drivers for Samsung Exynos SoCs. See particular patches for more detailed descriptions. Tomasz Figa (16): pwm: samsung: Update DT bindings documentation to cover clocks ARM: dts: exynos4: Specify PWM clocks in PWM node clocksource: samsung_pwm_timer: Get clock from device tree clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos5250: Simplify registration of PLL rate tables .../devicetree/bindings/pwm/pwm-samsung.txt| 12 + arch/arm/boot/dts/exynos4.dtsi | 2 + drivers/clk/samsung/clk-exynos4.c | 539 - drivers/clk/samsung/clk-exynos5250.c | 12 +- drivers/clk/samsung/clk-exynos5440.c | 2 +- drivers/clk/samsung/clk-pll.c | 284 --- drivers/clk/samsung/clk-pll.h | 59 ++- drivers/clk/samsung/clk.c | 10 +- drivers/clocksource/samsung_pwm_timer.c| 12 +- 9 files changed, 601 insertions(+), 331 deletions(-) -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/16] pwm: samsung: Update DT bindings documentation to cover clocks
PWM driver consumes at least one and up to three clocks, which need to be specified in device tree when used. This patch updates bindings documentation to add information about clocks. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- Documentation/devicetree/bindings/pwm/pwm-samsung.txt | 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt index 4caa1a7..d61fccd 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt @@ -19,6 +19,16 @@ Required properties: - reg: base address and size of register area - interrupts: list of timer interrupts (one interrupt per timer, starting at timer 0) +- clock-names: should contain all following required clock names: +- "timers" - PWM base clock used to generate PWM signals, + and any subset of following optional clock names: +- "pwm-tclk0" - first external PWM clock source, +- "pwm-tclk1" - second external PWM clock source. + Note that not all IP variants allow using all external clock sources. + Refer to SoC documentation to learn which clock source configurations + are available. +- clocks: should contain clock specifiers of all clocks, which input names + have been specified in clock-names property, in same order. - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -34,6 +44,8 @@ Example: reg = <0x7f006000 0x1000>; interrupt-parent = <&vic0>; interrupts = <23>, <24>, <25>, <27>, <28>; + clocks = <&clock 67>; + clock-names = "timers"; samsung,pwm-outputs = <0>, <1>; #pwm-cells = <3>; } -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 02/16] ARM: dts: exynos4: Specify PWM clocks in PWM node
Since pwm-samsung bindings require at least one clock to be specified, this patch adds the missing clocks and clock-names properties to specify clocks used by PWM block on Exynos4 SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- arch/arm/boot/dts/exynos4.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 93c2501..caadc02 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -448,6 +448,8 @@ compatible = "samsung,exynos4210-pwm"; reg = <0x139D 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; + clocks = <&clock 336>; + clock-names = "timers"; #pwm-cells = <2>; status = "disabled"; }; -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/16] clk: samsung: Modify _get_rate() helper to use __clk_lookup()
There is no need to use clkdev inside the clock driver to retrieve the
clocks for internal use. Instead __clk_lookup() helper can be used to
look up clocks by their platform name.
This patch modifies the behavior of _get_rate() helper to look up clocks
by platform name and adjusts all users of it to pass platform names
instead of clkdev aliases.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c| 4 ++--
drivers/clk/samsung/clk-exynos5440.c | 2 +-
drivers/clk/samsung/clk.c| 10 --
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 7de0769..a974a56 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1096,9 +1096,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
- _get_rate("sclk_apll"), _get_rate("mout_mpll"),
+ _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
- _get_rate("armclk"));
+ _get_rate("arm_clk"));
}
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index 4ef38e0..f865894 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -132,7 +132,7 @@ static void __init exynos5440_clk_init(struct device_node
*np)
samsung_clk_register_gate(exynos5440_gate_clks,
ARRAY_SIZE(exynos5440_gate_clks));
- pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
+ pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
pr_info("exynos5440 clock initialization complete\n");
}
CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock",
exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index cd3c40a..f503f32 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -307,14 +307,12 @@ void __init samsung_clk_of_register_fixed_ext(
unsigned long _get_rate(const char *clk_name)
{
struct clk *clk;
- unsigned long rate;
- clk = clk_get(NULL, clk_name);
- if (IS_ERR(clk)) {
+ clk = __clk_lookup(clk_name);
+ if (!clk) {
pr_err("%s: could not find clock %s\n", __func__, clk_name);
return 0;
}
- rate = clk_get_rate(clk);
- clk_put(clk);
- return rate;
+
+ return clk_get_rate(clk);
}
--
1.8.3.2
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[PATCH 03/16] clocksource: samsung_pwm_timer: Get clock from device tree
When booting with device tree static clkdev aliases should not be used.
This patch modifies the samsung_pwm_timer driver to use DT-based clock
lookup when booting with device tree.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clocksource/samsung_pwm_timer.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/samsung_pwm_timer.c
b/drivers/clocksource/samsung_pwm_timer.c
index ac60f8b..ab29476 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -368,10 +368,6 @@ static void __init samsung_clocksource_init(void)
static void __init samsung_timer_resources(void)
{
- pwm.timerclk = clk_get(NULL, "timers");
- if (IS_ERR(pwm.timerclk))
- panic("failed to get timers clock for timer");
-
clk_prepare_enable(pwm.timerclk);
pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
@@ -416,6 +412,10 @@ void __init samsung_pwm_clocksource_init(void __iomem
*base,
memcpy(&pwm.variant, variant, sizeof(pwm.variant));
memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
+ pwm.timerclk = clk_get(NULL, "timers");
+ if (IS_ERR(pwm.timerclk))
+ panic("failed to get timers clock for timer");
+
_samsung_pwm_clocksource_init();
}
@@ -447,6 +447,10 @@ static void __init samsung_pwm_alloc(struct device_node
*np,
return;
}
+ pwm.timerclk = of_clk_get_by_name(np, "timers");
+ if (IS_ERR(pwm.timerclk))
+ panic("failed to get timers clock for timer");
+
_samsung_pwm_clocksource_init();
}
--
1.8.3.2
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[PATCH 04/16] clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
Exynos cpufreq driver is the only remaining piece of code that needs
static clkdev aliases for operation, because it can not do device tree
based clock lookups yet.
This patch moves clock alias definitions for those clocks to separate
arrays that can be used with samsung_clk_register_alias() helper.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index f53658b..7de0769 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -392,9 +392,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
- MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"),
- MUX_A(mout_core, "mout_core", mout_core_p4210,
- SRC_CPU, 16, 1, "moutcore"),
+ MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
+ MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
SRC_TOP0, 8, 1, "sclk_vpll"),
MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
@@ -431,8 +430,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
/* list of mux clocks supported in exynos4x12 soc */
static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
- MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
- SRC_CPU, 24, 1, "mout_mpll"),
+ MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
+ SRC_CPU, 24, 1),
MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
@@ -456,8 +455,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
SRC_DMC, 12, 1, "sclk_mpll"),
MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
SRC_TOP0, 8, 1, "sclk_vpll"),
- MUX_A(mout_core, "mout_core", mout_core_p4x12,
- SRC_CPU, 16, 1, "moutcore"),
+ MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
@@ -545,7 +543,7 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
- DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"),
+ DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
DIV_A(sclk_apll, "sclk_apll", "mout_apll",
DIV_CPU0, 24, 3, "sclk_apll"),
DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
@@ -930,6 +928,20 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0),
};
+static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+ ALIAS(mout_core, NULL, "moutcore"),
+ ALIAS(arm_clk, NULL, "armclk"),
+ ALIAS(sclk_apll, NULL, "mout_apll"),
+};
+
+static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
+ ALIAS(sclk_mpll, NULL, "mout_mpll"),
+};
+
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
+ ALIAS(mout_mpll_user_c, NULL, "mout_mpll"),
+};
+
/*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory
@@ -1065,6 +1077,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks));
+ samsung_clk_register_alias(exynos4210_aliases,
+ ARRAY_SIZE(exynos4210_aliases));
} else {
samsung_clk_register_mux(exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1072,8 +1086,13 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_div_clks));
samsung_clk_register_gate(exynos4x12_gate_clks,
ARRAY_SIZE(exynos4x12_gate_clks));
+ samsung_clk_register_alias(exynos
[PATCH 16/16] clk: samsung: exynos5250: Simplify registration of PLL rate tables
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos5250.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index a9916a4..00a80e4 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -543,8 +543,6 @@ static struct of_device_id ext_clk_match[] __initdata = {
static void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
- struct clk *vpllsrc;
- unsigned long fin_pll_rate, mout_vpllsrc_rate = 0;
if (np) {
reg_base = of_iomap(np, 0);
@@ -563,16 +561,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
- fin_pll_rate = _get_rate("fin_pll");
-
- if (fin_pll_rate == 24 * MHZ)
+ if (_get_rate("fin_pll") == 24 * MHZ)
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
- vpllsrc = __clk_lookup("mout_vpllsrc");
- if (vpllsrc)
- mout_vpllsrc_rate = clk_get_rate(vpllsrc);
-
- if (mout_vpllsrc_rate == 24 * MHZ)
+ if (_get_rate("mout_vpllsrc") == 24 * MHZ)
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
--
1.8.3.2
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[PATCH 06/16] clk: samsung: exynos4: Remove unused static clkdev aliases
Since Exynos does not support legacy non-DT boot anymore, most of clock
lookups happen using device tree, so most of static clkdev aliases are no
longer necessary. This patch removes them.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 356 ++
1 file changed, 172 insertions(+), 184 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index a974a56..457b15a 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -374,7 +374,7 @@ static struct samsung_mux_clock exynos4_mux_clks[]
__initdata = {
CLK_SET_RATE_PARENT, 0),
MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
- MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
+ MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
};
@@ -394,8 +394,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
- MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
- SRC_TOP0, 8, 1, "sclk_vpll"),
+ MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
@@ -451,10 +450,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
- MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
- SRC_DMC, 12, 1, "sclk_mpll"),
- MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
- SRC_TOP0, 8, 1, "sclk_vpll"),
+ MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
+ MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
@@ -544,8 +541,7 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3),
- DIV_A(sclk_apll, "sclk_apll", "mout_apll",
- DIV_CPU0, 24, 3, "sclk_apll"),
+ DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
@@ -634,160 +630,147 @@ static struct samsung_gate_clock exynos4_gate_clks[]
__initdata = {
CLK_SET_RATE_PARENT, 0),
GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
CLK_SET_RATE_PARENT, 0),
- GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
- GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
- GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
- GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
- GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
- GATE_A(usb_host, "usb_host", "aclk133",
- GATE_IP_FSYS, 12, 0, 0, "usbhost"),
- GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
- SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
- GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
- SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
- GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
- SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
- GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
- SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
- GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
- SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
- GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
- SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
- GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
- SRC_
[PATCH 13/16] clk: samsung: exynos4: Reorder registration of mout_vpllsrc
Since PLL input frequency must be known before PLL registration,
mout_vpllsrc clock which is a reference clock of VPLL must be registered
before VPLL.
This patch reorders clock registration to register mout_vpllsrc before
VPLL.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 42a4001..34474ce 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -380,12 +380,15 @@ static struct samsung_mux_clock exynos4_mux_clks[]
__initdata = {
};
/* list of mux clocks supported in exynos4210 soc */
+static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
+ MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+};
+
static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
- MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
@@ -1036,6 +1039,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
+ samsung_clk_register_mux(exynos4210_mux_early,
+ ARRAY_SIZE(exynos4210_mux_early));
+
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
--
1.8.3.2
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[PATCH 08/16] clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
This array defines PLLs specific to Exynos 4x12 SoCs and not for all
Exynos 4 SoCs, so the name should represent that.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index f1b61fe..febdce2 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -988,7 +988,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
-static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
+static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
@@ -1040,8 +1040,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
- samsung_clk_register_pll(exynos4_plls,
- ARRAY_SIZE(exynos4_plls), reg_base);
+ samsung_clk_register_pll(exynos4x12_plls,
+ ARRAY_SIZE(exynos4x12_plls), reg_base);
}
samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
--
1.8.3.2
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[PATCH 07/16] clk: samsung: exynos4: Remove checks for DT node
Exynos 4 supports only DT based bootup, so non-DT cases does not need to
be handled anymore.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 457b15a..f1b61fe 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1006,11 +1006,9 @@ static void __init exynos4_clk_init(struct device_node
*np,
{
struct clk *apll, *mpll, *epll, *vpll;
- if (np) {
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic("%s: failed to map registers\n", __func__);
- }
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
if (exynos4_soc == EXYNOS4210)
samsung_clk_init(np, reg_base, nr_clks,
@@ -1021,8 +1019,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
- if (np)
- samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
--
1.8.3.2
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[PATCH 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx
This patch implements round_rate and set_rate callbacks of PLL45xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-pll.c | 109 +-
drivers/clk/samsung/clk-pll.h | 10
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b0398d2..cb971cb 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -10,9 +10,12 @@
*/
#include
+#include
#include "clk.h"
#include "clk-pll.h"
+#define PLL_TIMEOUT_MS 10
+
struct samsung_clk_pll {
struct clk_hw hw;
void __iomem*lock_reg;
@@ -272,13 +275,20 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops =
{
/*
* PLL45xx Clock Type
*/
+#define PLL4502_LOCK_FACTOR400
+#define PLL4508_LOCK_FACTOR240
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
+#define PLL45XX_AFC_MASK (0x1F)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
+#define PLL45XX_AFC_SHIFT (0)
+
+#define PLL45XX_ENABLE BIT(31)
+#define PLL45XX_LOCKED BIT(29)
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -301,8 +311,100 @@ static unsigned long samsung_pll45xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_afc;
+
+ old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+ old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
+
+ return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv);
+}
+
+static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll->con_reg);
+ con1 = __raw_readl(pll->con_reg + 0x4);
+
+ if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
+ con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
+ __raw_writel(con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL PMS values. */
+ con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
+ (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
+ (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
+ con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL45XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL45XX_SDIV_SHIFT);
+
+ /* Set PLL AFC value. */
+ con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
+ con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
+
+ /* Set PLL lock time. */
+ switch (pll->type) {
+ case pll_4502:
+ __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
+ break;
+ case pll_4508:
+ __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
+ break;
+ default:
+ break;
+ };
+
+ /* Set new configuration. */
+ __raw_writel(con1, pll->con_reg + 0x4);
+ __raw_writel(con0, pll->con_reg);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
+ pr_err("%s: could not lock PLL %s\n",
+ __func__, __clk_get_name(hw->clk));
+ return -EFAULT;
+ }
+
+ cpu_relax();
+ }
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll45xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll45xx_clk_min_ops = {
+ .recalc_rate
[PATCH 09/16] clk: samsung: pll: Use new registration method for PLL45xx
This patch modifies PLL45xx support code and its users to use the
recently introduced common PLL registration helper.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 18 --
drivers/clk/samsung/clk-pll.c | 52 +--
drivers/clk/samsung/clk-pll.h | 12 +++--
3 files changed, 20 insertions(+), 62 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index febdce2..6036fdf 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -104,6 +104,7 @@
#define DIV_DMC1 0x10504
#define GATE_IP_DMC0x10900
#define APLL_LOCK 0x14000
+#define E4210_MPLL_LOCK0x14008
#define APLL_CON0 0x14100
#define E4210_MPLL_CON00x14108
#define SRC_CPU0x14200
@@ -988,6 +989,13 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
+static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = {
+ [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, "fout_apll", NULL),
+ [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll",
+ E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
+};
+
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
@@ -1004,7 +1012,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
enum exynos4_soc exynos4_soc,
void __iomem *reg_base, unsigned long xom)
{
- struct clk *apll, *mpll, *epll, *vpll;
+ struct clk *epll, *vpll;
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -1026,17 +1034,13 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
- apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
- reg_base + APLL_CON0, pll_4508);
- mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
- reg_base + E4210_MPLL_CON0, pll_4508);
+ samsung_clk_register_pll(exynos4210_plls,
+ ARRAY_SIZE(exynos4210_plls), reg_base);
epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
reg_base + EPLL_CON0, pll_4600);
vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
reg_base + VPLL_CON0, pll_4650c);
- samsung_clk_add_lookup(apll, fout_apll);
- samsung_clk_add_lookup(mpll, fout_mpll);
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0775554..b0398d2 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -280,18 +280,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops =
{
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
-struct samsung_clk_pll45xx {
- struct clk_hw hw;
- enum pll45xx_type type;
- const void __iomem *con_reg;
-};
-
-#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
-
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
@@ -313,43 +305,6 @@ static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll45xx(const char *name,
- const char *pname, const void __iomem *con_reg,
- enum pll45xx_type type)
-{
- struct samsung_clk_pll45xx *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err("%s: could not allocate pll clk %s\n", __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = &samsung_pll45xx_clk_ops;
- init.flags = CLK_GET_RATE_NOCACHE;
- init.parent_names = &pname;
- init.num_parents = 1;
-
- pll->hw.init = &init;
- pll->con_reg = con_reg;
- pll->type = type;
-
- clk = clk_register(NULL, &pll->hw);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register
[PATCH 11/16] clk: samsung: pll: Use new registration method for PLL46xx
This patch modifies PLL46xx support code and its users to use the
recently introduced common PLL registration helper.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 13 +++---
drivers/clk/samsung/clk-pll.c | 52 +--
drivers/clk/samsung/clk-pll.h | 14 +++
3 files changed, 14 insertions(+), 65 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 6036fdf..42a4001 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -994,6 +994,10 @@ static struct __initdata samsung_pll_clock
exynos4210_plls[nr_plls] = {
APLL_CON0, "fout_apll", NULL),
[mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll",
E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
+ [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
+ EPLL_CON0, "fout_epll", NULL),
+ [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc",
+ VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
};
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1012,8 +1016,6 @@ static void __init exynos4_clk_init(struct device_node
*np,
enum exynos4_soc exynos4_soc,
void __iomem *reg_base, unsigned long xom)
{
- struct clk *epll, *vpll;
-
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
@@ -1036,13 +1038,6 @@ static void __init exynos4_clk_init(struct device_node
*np,
if (exynos4_soc == EXYNOS4210) {
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
- epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
- reg_base + EPLL_CON0, pll_4600);
- vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
- reg_base + VPLL_CON0, pll_4650c);
-
- samsung_clk_add_lookup(epll, fout_epll);
- samsung_clk_add_lookup(vpll, fout_vpll);
} else {
samsung_clk_register_pll(exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index cb971cb..8a008ca 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -422,18 +422,10 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops =
{
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_KDIV_SHIFT (0)
-struct samsung_clk_pll46xx {
- struct clk_hw hw;
- enum pll46xx_type type;
- const void __iomem *con_reg;
-};
-
-#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
-
static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
u64 fvco = parent_rate;
@@ -457,43 +449,6 @@ static const struct clk_ops samsung_pll46xx_clk_ops = {
.recalc_rate = samsung_pll46xx_recalc_rate,
};
-struct clk * __init samsung_clk_register_pll46xx(const char *name,
- const char *pname, const void __iomem *con_reg,
- enum pll46xx_type type)
-{
- struct samsung_clk_pll46xx *pll;
- struct clk *clk;
- struct clk_init_data init;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll) {
- pr_err("%s: could not allocate pll clk %s\n", __func__, name);
- return NULL;
- }
-
- init.name = name;
- init.ops = &samsung_pll46xx_clk_ops;
- init.flags = CLK_GET_RATE_NOCACHE;
- init.parent_names = &pname;
- init.num_parents = 1;
-
- pll->hw.init = &init;
- pll->con_reg = con_reg;
- pll->type = type;
-
- clk = clk_register(NULL, &pll->hw);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register pll clock %s\n", __func__,
- name);
- kfree(pll);
- }
-
- if (clk_register_clkdev(clk, name, NULL))
- pr_err("%s: failed to register lookup for %s", __func__, name);
-
- return clk;
-}
-
/*
* PLL6552 Clock Type
*/
@@ -799,6 +754,11 @@ static void __init _samsung_clk_register_pll(struct
samsung_pll_clock *pll_clk,
else
init.ops = &samsung_pll36xx_clk_ops;
break;
+ case pll_4600:
+ case pll_4650:
+ case pll_4650c:
+ init.ops = &samsung_pll46xx_clk_
[PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx
This patch implements round_rate and set_rate callbacks of PLL46xx
driver to allow reconfiguration of PLL at runtime.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-pll.c | 111 +-
drivers/clk/samsung/clk-pll.h | 25 ++
2 files changed, 135 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 8a008ca..c1f1c87 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -410,10 +410,13 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops =
{
/*
* PLL46xx Clock Type
*/
+#define PLL46XX_LOCK_FACTOR3000
+#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
+#define PLL46XX_VSEL_SHIFT (27)
#define PLL46XX_MDIV_SHIFT (16)
#define PLL46XX_PDIV_SHIFT (8)
#define PLL46XX_SDIV_SHIFT (0)
@@ -421,6 +424,15 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_KDIV_MASK (0x)
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_MASK (0x3F)
+#define PLL46XX_MRR_MASK (0x1F)
+#define PLL46XX_KDIV_SHIFT (0)
+#define PLL46XX_MFR_SHIFT (16)
+#define PLL46XX_MRR_SHIFT (24)
+
+#define PLL46XX_ENABLE BIT(31)
+#define PLL46XX_LOCKED BIT(29)
+#define PLL46XX_VSEL BIT(27)
static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -445,8 +457,102 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
+ const struct samsung_pll_rate_table *rate)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+ old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+ old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
+
+ return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
+ || old_kdiv != rate->kdiv);
+}
+
+static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 con0, con1, lock;
+ ktime_t start;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ con0 = __raw_readl(pll->con_reg);
+ con1 = __raw_readl(pll->con_reg + 0x4);
+
+ if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
+ /* If only s change, change just s value only*/
+ con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+ con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
+ __raw_writel(con0, pll->con_reg);
+
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
+ if (lock > 0x)
+ /* Maximum lock time bitfield is 16-bit. */
+ lock = 0x;
+
+ /* Set PLL PMS and VSEL values. */
+ con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
+ (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
+ con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL46XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL46XX_SDIV_SHIFT) |
+ (rate->vsel << PLL46XX_VSEL_SHIFT);
+
+ /* Set PLL AFC, MFR and MRR values. */
+ con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
+ (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
+ (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
+ con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
+ (rate->mfr << PLL46XX_MFR_SHIFT) |
+ (rate->mrr << PLL46XX_MRR_SHIFT);
+
+ /* Write configuration to PLL */
+ __raw_writel(lock, pll->lock_reg);
+ __raw_writel(con0, pll->con_reg);
+ __raw_writel(con1, pll->con_reg + 0x4);
+
+ /* Wait for locking. */
+ start = ktime_get();
+ while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
+ ktime_t delta = ktime_sub(ktime_get(), start);
+
+ if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
+ pr_err("%s: coul
[PATCH 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 34474ce..e18cfae 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
+/* PLLs PMS values */
+static struct samsung_pll_rate_table exynos4210_apll_rates[] = {
+ PLL_45XX_RATE(12, 150, 3, 1, 28),
+ PLL_45XX_RATE(10, 250, 6, 1, 28),
+ PLL_45XX_RATE( 8, 200, 6, 1, 28),
+ PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
+ PLL_45XX_RATE( 6, 100, 4, 1, 13),
+ PLL_45XX_RATE( 53300, 533, 24, 1, 5),
+ PLL_45XX_RATE( 5, 250, 6, 2, 28),
+ PLL_45XX_RATE( 4, 200, 6, 2, 28),
+ PLL_45XX_RATE( 2, 200, 6, 3, 28),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4210_epll_rates[] = {
+ PLL_4600_RATE(19200, 48, 3, 1, 0, 0),
+ PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
+ PLL_4600_RATE(18000, 45, 3, 1, 0, 0),
+ PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
+ PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
+ PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0),
+ PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4210_vpll_rates[] = {
+ PLL_4650_RATE(36000, 44, 3, 0, 1024, 0, 14, 0),
+ PLL_4650_RATE(32400, 53, 2, 1, 1024, 1, 1, 1),
+ PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
+ PLL_4650_RATE(11000, 53, 3, 2, 2048, 0, 17, 0),
+ PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
+ { /* sentinel */ }
+};
+
static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = {
[apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, "fout_apll", NULL),
@@ -1042,6 +1076,17 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_mux(exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
+ if (_get_rate("fin_pll") == 2400) {
+ exynos4210_plls[apll].rate_table =
+ exynos4210_apll_rates;
+ exynos4210_plls[epll].rate_table =
+ exynos4210_epll_rates;
+ }
+
+ if (_get_rate("mout_vpllsrc") == 2400)
+ exynos4210_plls[vpll].rate_table =
+ exynos4210_vpll_rates;
+
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
--
1.8.3.2
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[PATCH 15/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos4.c | 49 +++
1 file changed, 49 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index e18cfae..8ab86f8 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1026,6 +1026,46 @@ static struct samsung_pll_rate_table
exynos4210_vpll_rates[] = {
{ /* sentinel */ }
};
+static struct samsung_pll_rate_table exynos4x12_apll_rates[] = {
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 4, 0),
+ PLL_35XX_RATE(11, 275, 6, 0),
+ PLL_35XX_RATE(10, 125, 3, 0),
+ PLL_35XX_RATE( 9, 150, 4, 0),
+ PLL_35XX_RATE( 8, 100, 3, 0),
+ PLL_35XX_RATE( 7, 175, 3, 1),
+ PLL_35XX_RATE( 6, 200, 4, 1),
+ PLL_35XX_RATE( 5, 125, 3, 1),
+ PLL_35XX_RATE( 4, 100, 3, 1),
+ PLL_35XX_RATE( 3, 200, 4, 2),
+ PLL_35XX_RATE( 2, 100, 3, 2),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4x12_epll_rates[] = {
+ PLL_36XX_RATE(19200, 48, 3, 1, 0),
+ PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
+ PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
+ PLL_36XX_RATE( 49151992, 49, 3, 3, 9961),
+ PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
+ { /* sentinel */ }
+};
+
+static struct samsung_pll_rate_table exynos4x12_vpll_rates[] = {
+ PLL_36XX_RATE(53300, 133, 3, 1, 16384),
+ PLL_36XX_RATE(44000, 110, 3, 1, 0),
+ PLL_36XX_RATE(35000, 175, 3, 2, 0),
+ PLL_36XX_RATE(26600, 133, 3, 2, 0),
+ PLL_36XX_RATE(16000, 160, 3, 3, 0),
+ PLL_36XX_RATE(106031250, 53, 3, 2, 1024),
+ PLL_36XX_RATE( 53015625, 53, 3, 3, 1024),
+ { /* sentinel */ }
+};
+
static struct __initdata samsung_pll_clock exynos4210_plls[nr_plls] = {
[apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, "fout_apll", NULL),
@@ -1090,6 +1130,15 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
+ if (_get_rate("fin_pll") == 2400) {
+ exynos4x12_plls[apll].rate_table =
+ exynos4x12_apll_rates;
+ exynos4x12_plls[epll].rate_table =
+ exynos4x12_epll_rates;
+ exynos4x12_plls[vpll].rate_table =
+ exynos4x12_vpll_rates;
+ }
+
samsung_clk_register_pll(exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
}
--
1.8.3.2
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Re: [PATCH 1/8] Documentation: devicetree: Update Exynos MCT bindings description
On Tuesday 20 of August 2013 11:00:53 Stephen Warren wrote:
> On 08/20/2013 07:52 AM, Tomasz Figa wrote:
> > This patch updates description of device tree bindings for Exynos MCT
> >
> > (multicore timers). Namely:
> > - added note about simplified specification of local timer interrupts,
> >
> >when using single per-processor interrupt for all local timers,
> >
> > - changed first example that was incorrectly suggesting that global
> >
> >timer interrupts are optional,
> >
> > - simplified example interrupt map,
> > - added example showing simplified local timer interrupt
> > specification.
> >
> > diff --git
> > a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> > b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> >
> > -Example 1: In this example, the system uses only the first global
> > timer
> > - interrupt generated by MCT and the remaining three global timer
> > - interrupts are unused. Two local timer interrupts have been
> > - specified.
> > + For MCT block that uses a per-processor interrupt for local timers,
> > such + as ones compatible with "samusng,exynos4412-mct", only one
> > local timer
> samsung is typo'd there.
Oops. ;)
> > +Example 2: In this example, the timer interrupts are connected to two
> > separate + interrupt controllers. Hence, an interrupt-map is
> > created to map + the interrupts to the respective interrupt
> > controllers.
> >
> > mct@101C {
> >
> > compatible = "samsung,exynos4210-mct";
> > reg = <0x101C 0x800>;
> >
> > - interrupt-controller;
> > - #interrups-cells = <2>;
> >
> > interrupt-parent = <&mct_map>;
> >
> > - interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
> > -<4 0>, <5 0>;
> > + interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
> >
> > mct_map: mct-map {
> >
> > - #interrupt-cells = <2>;
> > + #interrupt-cells = <1>;
> >
> > #address-cells = <0>;
> > #size-cells = <0>;
>
> I don't believe you need either of those two properties in a node solely
> used as an interrupt map.
Well, you don't need #size-cells, as it is not used for interrupt-map
property.
As for #address-cell property, you need it, as it defines how many cells
are used in interrupt map specifier for unit address. See ePAPR 2.4.3.1 or
[1] for a description of interrupt-map property format.
[1] - http://devicetree.org/Device_Tree_Usage#Advanced_Interrupt_Mapping
> Also, why not put the interrupt-map property directly into the main mct
> node; I don't believe there's any requirement nor advantage to it being
> a separate node.
It is more readable, as you don't mix virtual (helper) properties, with
those describing the hardware. Otherwise both ways are technically correct,
but not for all cases, i.e. only when #address-cells and #interrupt-cells
properties aren't used for device's own purposes.
> > - interrupt-map = <0x0 0 &combiner 23 3>,
> > - <0x4 0 &gic 0 120 0>,
> > - <0x5 0 &gic 0 121 0>;
> > + interrupt-map = <0 &gic 0 57 0>,
> > + <1 &gic 0 69 0>,
> > + <2 &combiner 12 6>,
> > + <3 &combiner 12 7>,
> > + <4 &gic 0 42 0>,
> > + <5 &gic 0 48 0>;
> >
> > };
> >
> > };
> >
> > +Example 3: In this example, the IP contains four local timers, but
> > using +a per-processor interrupt to handle them. Either all the
> > local +timer interrupts can be specified, with the same interrupt
> > specifier +value or just the first one.
>
> That sounds like it should be two separate examples.
>
> Actually, there's already a 2-timer example above using separate
> interrupts, so why not make this example *just* be for the
> single-interrupt case?
Well, I wanted to show that both ways of specification would be equivalent
here. If you insist on making it a single example, then I can send next
version with this changed.
Best regards,
Tomasz
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Re: [PATCH 1/8] Documentation: devicetree: Update Exynos MCT bindings description
On 08/20/2013 07:52 AM, Tomasz Figa wrote:
> This patch updates description of device tree bindings for Exynos MCT
> (multicore timers). Namely:
> - added note about simplified specification of local timer interrupts,
>when using single per-processor interrupt for all local timers,
> - changed first example that was incorrectly suggesting that global
>timer interrupts are optional,
> - simplified example interrupt map,
> - added example showing simplified local timer interrupt specification.
> diff --git
> a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> -Example 1: In this example, the system uses only the first global timer
> -interrupt generated by MCT and the remaining three global timer
> -interrupts are unused. Two local timer interrupts have been
> -specified.
> + For MCT block that uses a per-processor interrupt for local timers, such
> + as ones compatible with "samusng,exynos4412-mct", only one local timer
samsung is typo'd there.
> +Example 2: In this example, the timer interrupts are connected to two
> separate
> +interrupt controllers. Hence, an interrupt-map is created to map
> +the interrupts to the respective interrupt controllers.
>
> mct@101C {
> compatible = "samsung,exynos4210-mct";
> reg = <0x101C 0x800>;
> - interrupt-controller;
> - #interrups-cells = <2>;
> interrupt-parent = <&mct_map>;
> - interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
> - <4 0>, <5 0>;
> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
>
> mct_map: mct-map {
> - #interrupt-cells = <2>;
> + #interrupt-cells = <1>;
> #address-cells = <0>;
> #size-cells = <0>;
I don't believe you need either of those two properties in a node solely
used as an interrupt map.
Also, why not put the interrupt-map property directly into the main mct
node; I don't believe there's any requirement nor advantage to it being
a separate node.
> - interrupt-map = <0x0 0 &combiner 23 3>,
> - <0x4 0 &gic 0 120 0>,
> - <0x5 0 &gic 0 121 0>;
> + interrupt-map = <0 &gic 0 57 0>,
> + <1 &gic 0 69 0>,
> + <2 &combiner 12 6>,
> + <3 &combiner 12 7>,
> + <4 &gic 0 42 0>,
> + <5 &gic 0 48 0>;
> };
> };
> +Example 3: In this example, the IP contains four local timers, but using
> +a per-processor interrupt to handle them. Either all the local
> +timer interrupts can be specified, with the same interrupt specifier
> +value or just the first one.
That sounds like it should be two separate examples.
Actually, there's already a 2-timer example above using separate
interrupts, so why not make this example *just* be for the
single-interrupt case?
> + mct@1005 {
> + compatible = "samsung,exynos4412-mct";
> + reg = <0x1005 0x800>;
> + interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> + <0 42 0>/*, <0 42 0>, <0 42 0>, <0 42 0>*/;
> + };
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Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On Tuesday 20 of August 2013 09:48:25 Stephen Boyd wrote: > On 08/20/13 09:41, Tomasz Figa wrote: > > On Tuesday 20 of August 2013 09:33:31 Stephen Boyd wrote: > >> On 08/20/13 09:11, Tomasz Figa wrote: > >>> Sometimes it is necessary to fix interrupt affinity to an offline > >>> CPU, > >>> for example in initialization of local timers. This patch modifies > >>> .set_affinity() operation of irq-gic driver to fall back to any > >>> possible > >>> CPU if no online CPU can be found in requested CPU mask. > >>> > >>> This fixes broken Exynos4210 support since commit > >>> > >>> ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API > >>> > >>> caused by timer initialization code unable to set affinity for local > >>> timer interrupts. > >> > >> Care to elaborate further? I don't see how the interrupt affinity is > >> set > >> for a CPU that isn't online because the mct code runs on the CPU that > >> the affinity is being set to. > > > > Well, please look at secondary_start_kernel() in arch/arm/kernel/smp.c > > [1]. You can see that notify_cpu_starting() (line 348) that fires the > > notifier registered in MCT driver is called before set_cpu_online() > > (line 359) that marks the CPU as online. Also notice that, originally, > > local timer initialization was happening after set_cpu_online() - see > > line 365. > Great, thank you. Please put this information in the commit text next > time. Right, I could have added a sentence or two about this. > I wonder if we shouldn't make the cpumask_any_and() work on the present > mask instead? If we ever support physical hotplug on ARM I think we > wouldn't want to allow interrupts to go to CPUs that aren't even present > (but still possible). Yes, cpu_present_mask might be better indeed. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On 08/20/13 09:41, Tomasz Figa wrote: > On Tuesday 20 of August 2013 09:33:31 Stephen Boyd wrote: >> On 08/20/13 09:11, Tomasz Figa wrote: >>> Sometimes it is necessary to fix interrupt affinity to an offline CPU, >>> for example in initialization of local timers. This patch modifies >>> .set_affinity() operation of irq-gic driver to fall back to any >>> possible >>> CPU if no online CPU can be found in requested CPU mask. >>> >>> This fixes broken Exynos4210 support since commit >>> >>> ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API >>> >>> caused by timer initialization code unable to set affinity for local >>> timer interrupts. >> Care to elaborate further? I don't see how the interrupt affinity is set >> for a CPU that isn't online because the mct code runs on the CPU that >> the affinity is being set to. > Well, please look at secondary_start_kernel() in arch/arm/kernel/smp.c [1]. > You can see that notify_cpu_starting() (line 348) that fires the notifier > registered in MCT driver is called before set_cpu_online() (line 359) that > marks the CPU as online. Also notice that, originally, local timer > initialization was happening after set_cpu_online() - see line 365. > > Great, thank you. Please put this information in the commit text next time. I wonder if we shouldn't make the cpumask_any_and() work on the present mask instead? If we ever support physical hotplug on ARM I think we wouldn't want to allow interrupts to go to CPUs that aren't even present (but still possible). -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On Tuesday 20 of August 2013 09:33:31 Stephen Boyd wrote: > On 08/20/13 09:11, Tomasz Figa wrote: > > Sometimes it is necessary to fix interrupt affinity to an offline CPU, > > for example in initialization of local timers. This patch modifies > > .set_affinity() operation of irq-gic driver to fall back to any > > possible > > CPU if no online CPU can be found in requested CPU mask. > > > > This fixes broken Exynos4210 support since commit > > > > ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API > > > > caused by timer initialization code unable to set affinity for local > > timer interrupts. > > Care to elaborate further? I don't see how the interrupt affinity is set > for a CPU that isn't online because the mct code runs on the CPU that > the affinity is being set to. Well, please look at secondary_start_kernel() in arch/arm/kernel/smp.c [1]. You can see that notify_cpu_starting() (line 348) that fires the notifier registered in MCT driver is called before set_cpu_online() (line 359) that marks the CPU as online. Also notice that, originally, local timer initialization was happening after set_cpu_online() - see line 365. [1] - http://lxr.free-electrons.com/source/arch/arm/kernel/smp.c?a=arm#L312 Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] irqchip: gic: Allow setting affinity to offline CPUs
On 08/20/13 09:11, Tomasz Figa wrote: > Sometimes it is necessary to fix interrupt affinity to an offline CPU, > for example in initialization of local timers. This patch modifies > .set_affinity() operation of irq-gic driver to fall back to any possible > CPU if no online CPU can be found in requested CPU mask. > > This fixes broken Exynos4210 support since commit > ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API > caused by timer initialization code unable to set affinity for local > timer interrupts. Care to elaborate further? I don't see how the interrupt affinity is set for a CPU that isn't online because the mct code runs on the CPU that the affinity is being set to. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] pinctrl: samsung: Parse pin groups before calling pinctrl_register()
Calling pinctrl_register() means that the driver is fully initialized
and might accept pinmux/pinconf requests, so pin groups must be parsed
before.
This patch fixes this problem by moving device tree parsing before call
to pinctrl_register(). In addition, this fixes support for hogs on
pin controllers handled by pinctrl-samsung driver.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
drivers/pinctrl/pinctrl-samsung.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
b/drivers/pinctrl/pinctrl-samsung.c
index a7fa9e2..439f2ef 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -767,6 +767,10 @@ static int samsung_pinctrl_register(struct platform_device
*pdev,
}
}
+ ret = samsung_pinctrl_parse_dt(pdev, drvdata);
+ if (ret)
+ return ret;
+
drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
if (!drvdata->pctl_dev) {
dev_err(&pdev->dev, "could not register pinctrl driver\n");
@@ -784,12 +788,6 @@ static int samsung_pinctrl_register(struct platform_device
*pdev,
pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange);
}
- ret = samsung_pinctrl_parse_dt(pdev, drvdata);
- if (ret) {
- pinctrl_unregister(drvdata->pctl_dev);
- return ret;
- }
-
return 0;
}
--
1.8.3.2
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[PATCH] irqchip: gic: Allow setting affinity to offline CPUs
Sometimes it is necessary to fix interrupt affinity to an offline CPU, for example in initialization of local timers. This patch modifies .set_affinity() operation of irq-gic driver to fall back to any possible CPU if no online CPU can be found in requested CPU mask. This fixes broken Exynos4210 support since commit ee98d27df6 ARM: EXYNOS4: Divorce mct from local timer API caused by timer initialization code unable to set affinity for local timer interrupts. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/irqchip/irq-gic.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index ee7c503..5f0797e 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -250,6 +250,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); u32 val, mask, bit; + /* +* If no online CPU could be found, fall back to any possible CPU. +* +* This is to allow setting affinity of some interrupts to a CPU +* before it is marked as online, i.e. local timer initialization. +*/ + if (cpu >= nr_cpu_ids) + cpu = cpumask_any_and(mask_val, cpu_possible_mask); + if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) return -EINVAL; -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC v5] s5k5baf: add camera sensor driver
On 08/20/2013 12:57 AM, Stephen Warren wrote: > On 08/19/2013 04:53 PM, Tomasz Figa wrote: >> On Monday 19 of August 2013 16:30:45 Stephen Warren wrote: >>> On 08/19/2013 11:25 AM, Sylwester Nawrocki wrote: On 08/19/2013 03:25 PM, Pawel Moll wrote: > On Mon, 2013-08-19 at 14:18 +0100, Andrzej Hajda wrote: >> +++ b/Documentation/devicetree/bindings/media/samsung-s5k5baf.txt >> @@ -0,0 +1,51 @@ >> +Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC >> ISP >> +- >> + >> +Required properties: >> + >> +- compatible : "samsung,s5k5baf"; >> +- reg: I2C slave address of the sensor; >> +- vdda-supply: analog power supply 2.8V (2.6V to 3.0V); >> +- vddreg-supply : regulator input power supply 1.8V (1.7V >> to 1.9V) +or 2.8V (2.6V to 3.0); >> +- vddio-supply : I/O power supply 1.8V (1.65V to 1.95V) >> +or 2.8V (2.5V to 3.1V); >> +- gpios : GPIOs connected to STDBYN and RSTN pins, >> +in order: STBYN, RSTN; > > You probably want to use the "[-]gpios" convention here (see > Documentation/devicetree/bindings/gpio/gpio.txt), so something like > stbyn-gpios and rstn-gpios. Unless using multiple named properties is really preferred over a single "gpios" property I would like to keep the single property containing a list of GPIOs. ... >>> >>> Yes, a separate property for each type of GPIO is typical. Multiple >>> entries in the same property are allowed if they're used for the same >>> purpose/type, whereas here they're clearly different things. Yes, that's a good argument. Those GPIOs are pretty unrelated. >>> Inconsistent with (some) other properties, admittedly... It might depend on which properties we consider together. >> I'm not really convinced about the superiority of named gpio properties >> over a single gpios property with multiple entries in this case. I'd say >> it's more just a matter of preference. >> >> See the clock or interrupt bindings. They all specify all the clocks and >> interrupts in single property, without any differentiation based on their >> purposes. Also keep in mind that original GPIO bindings used only a single >> "gpios" property and was only extended to allow named ones. > > Well, it's not so much about what's best, but just being consistent with > what's already there. OK, thanks a lot for clarification. We'll rework this to use separate named properties. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/8] Exynos device tree clean-up for 3.12
On 08/20/2013 03:52 PM, Tomasz Figa wrote: > This series intends to fix small problems with Exynos device tree sources > that I spotted during my work on other things. The fixes are mostly > stylistic, without any funtional changes introduced, except patch 6/8, > which makes the mshc node disabled by default, but for all affected > boards it is enabled at board level. > > Tomasz Figa (8): > Documentation: devicetree: Update Exynos MCT bindings description > ARM: dts: exynos4: Drop interrupt controller properties from MCT nodes > ARM: dts: exynos4x12: Move MCT node to exynos4x12.dtsi > ARM: dts: exynos4: Simplify MCT interrupt map > ARM: dts: exynos4x12: Move mshc node to exynos4x12.dtsi > ARM: dts: exynos4x12: Keep mshc node disabled by default > ARM: dts: exynos: Fix missing spaces after labels > ARM: dts: exynos4: Add missing unit-address of sysreg node > > .../bindings/timer/samsung,exynos4210-mct.txt | 49 > ++ > arch/arm/boot/dts/exynos4.dtsi | 6 +-- > arch/arm/boot/dts/exynos4210.dtsi | 23 +- > arch/arm/boot/dts/exynos4212.dtsi | 24 +-- > arch/arm/boot/dts/exynos4412.dtsi | 36 +--- > arch/arm/boot/dts/exynos4x12.dtsi | 29 + > arch/arm/boot/dts/exynos5.dtsi | 4 +- > arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +-- > arch/arm/boot/dts/exynos5440.dtsi | 2 +- > 9 files changed, 82 insertions(+), 97 deletions(-) Thanks Tomasz, for the whole series: Reviewed-by: Sylwester Nawrocki Regards, -- Sylwester Nawrocki Samsung R&D Institute Poland -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/8] ARM: dts: exynos4: Simplify MCT interrupt map
There is no need to use two cells for interrupt specifiers inside the
MCT interrupt map, so this patch simplifies the map to use one cell.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4210.dtsi | 17 -
arch/arm/boot/dts/exynos4x12.dtsi | 14 +++---
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 1a6440ae6..b0fee69 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -52,21 +52,20 @@
compatible = "samsung,exynos4210-mct";
reg = <0x1005 0x800>;
interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-<4 0>, <5 0>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock 3>, <&clock 344>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
- #interrupt-cells = <2>;
+ #interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &gic 0 69 0>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 0 42 0>,
- <0x5 0 &gic 0 48 0>;
+ interrupt-map = <0 &gic 0 57 0>,
+ <1 &gic 0 69 0>,
+ <2 &combiner 12 6>,
+ <3 &combiner 12 7>,
+ <4 &gic 0 42 0>,
+ <5 &gic 0 48 0>;
};
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 5012bc8..3d7182a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -45,19 +45,19 @@
compatible = "samsung,exynos4412-mct";
reg = <0x1005 0x800>;
interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>;
+ interrupts = <0>, <1>, <2>, <3>, <4>;
clocks = <&clock 3>, <&clock 344>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
- #interrupt-cells = <2>;
+ #interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &combiner 12 5>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 1 12 0>;
+ interrupt-map = <0 &gic 0 57 0>,
+ <1 &combiner 12 5>,
+ <2 &combiner 12 6>,
+ <3 &combiner 12 7>,
+ <4 &gic 1 12 0>;
};
};
--
1.8.3.2
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[PATCH 5/8] ARM: dts: exynos4x12: Move mshc node to exynos4x12.dtsi
All SoCs from Exynos4x12 series contain the MSHC block, so its node can
be located in exynos4x12.dtsi.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4412.dtsi | 8
arch/arm/boot/dts/exynos4x12.dtsi | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index 1388ce0..6b0184f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -34,12 +34,4 @@
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
-
- mshc@1255 {
- compatible = "samsung,exynos4412-dw-mshc";
- reg = <0x1255 0x1000>;
- interrupts = <0 77 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 3d7182a..06cef96 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -196,4 +196,12 @@
};
};
};
+
+ mshc@1255 {
+ compatible = "samsung,exynos4412-dw-mshc";
+ reg = <0x1255 0x1000>;
+ interrupts = <0 77 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
--
1.8.3.2
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[PATCH 6/8] ARM: dts: exynos4x12: Keep mshc node disabled by default
MSHC node requires additional board-specific data, so it should be disabled by default. Board dts files already have status override for it, so only the change in exynso4x12.dtsi is needed. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- arch/arm/boot/dts/exynos4x12.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 06cef96..2f243c2 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -203,5 +203,6 @@ interrupts = <0 77 0>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/8] ARM: dts: exynos: Fix missing spaces after labels
For consistency with other device tree nodes, this patch adds missing
spaces after node labels.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4.dtsi| 4 ++--
arch/arm/boot/dts/exynos4210.dtsi | 4 ++--
arch/arm/boot/dts/exynos4212.dtsi | 2 +-
arch/arm/boot/dts/exynos4412.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi| 4 ++--
arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++---
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
7 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 93c2501..892d5ea 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -79,14 +79,14 @@
reg = <0x10023CE0 0x20>;
};
- gic:interrupt-controller@1049 {
+ gic: interrupt-controller@1049 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1049 0x1000>, <0x1048 0x100>;
};
- combiner:interrupt-controller@1044 {
+ combiner: interrupt-controller@1044 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index b0fee69..48ecd7a 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -36,11 +36,11 @@
reg = <0x10023CA0 0x20>;
};
- gic:interrupt-controller@1049 {
+ gic: interrupt-controller@1049 {
cpu-offset = <0x8000>;
};
- combiner:interrupt-controller@1044 {
+ combiner: interrupt-controller@1044 {
samsung,combiner-nr = <16>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index 443b8a2..94a43f9 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,7 +22,7 @@
/ {
compatible = "samsung,exynos4212";
- gic:interrupt-controller@1049 {
+ gic: interrupt-controller@1049 {
cpu-offset = <0x8000>;
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index 6b0184f..5a82f67 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,7 +22,7 @@
/ {
compatible = "samsung,exynos4412";
- gic:interrupt-controller@1049 {
+ gic: interrupt-controller@1049 {
cpu-offset = <0x4000>;
};
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..a25c5ac 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -23,7 +23,7 @@
reg = <0x1000 0x100>;
};
- combiner:interrupt-controller@1044 {
+ combiner: interrupt-controller@1044 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
@@ -39,7 +39,7 @@
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
- gic:interrupt-controller@10481000 {
+ gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..56334d8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,7 +37,7 @@
};
};
- vdd:fixed-regulator@0 {
+ vdd: fixed-regulator@0 {
compatible = "regulator-fixed";
regulator-name = "vdd-supply";
regulator-min-microvolt = <180>;
@@ -45,7 +45,7 @@
regulator-always-on;
};
- dbvdd:fixed-regulator@1 {
+ dbvdd: fixed-regulator@1 {
compatible = "regulator-fixed";
regulator-name = "dbvdd-supply";
regulator-min-microvolt = <330>;
@@ -53,7 +53,7 @@
regulator-always-on;
};
- spkvdd:fixed-regulator@2 {
+ spkvdd: fixed-regulator@2 {
compatible = "regulator-fixed";
regulator-name = "spkvdd-supply";
regulator-min-microvolt = <500>;
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 5d6cf49..799cb77 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -29,7 +29,7 @@
#clock-cells = <1>;
[PATCH 1/8] Documentation: devicetree: Update Exynos MCT bindings description
This patch updates description of device tree bindings for Exynos MCT
(multicore timers). Namely:
- added note about simplified specification of local timer interrupts,
when using single per-processor interrupt for all local timers,
- changed first example that was incorrectly suggesting that global
timer interrupts are optional,
- simplified example interrupt map,
- added example showing simplified local timer interrupt specification.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
.../bindings/timer/samsung,exynos4210-mct.txt | 49 ++
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index b5a86d2..a5d6891f 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -31,38 +31,53 @@ Required properties:
7: ..
i: Local Timer Interrupt n
-Example 1: In this example, the system uses only the first global timer
- interrupt generated by MCT and the remaining three global timer
- interrupts are unused. Two local timer interrupts have been
- specified.
+ For MCT block that uses a per-processor interrupt for local timers, such
+ as ones compatible with "samusng,exynos4412-mct", only one local timer
+ interrupt might be specified, meaning that all local timers use the same
+ per processor interrupt.
+
+Example 1: In this example, the IP contains two local timers, using separate
+ interrupts, so two local timer interrupts have been specified,
+ in addition to four global timer interrupts.
mct@1005 {
compatible = "samsung,exynos4210-mct";
reg = <0x1005 0x800>;
- interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+ interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
<0 42 0>, <0 48 0>;
};
-Example 2: In this example, the MCT global and local timer interrupts are
- connected to two separate interrupt controllers. Hence, an
- interrupt-map is created to map the interrupts to the respective
- interrupt controllers.
+Example 2: In this example, the timer interrupts are connected to two separate
+ interrupt controllers. Hence, an interrupt-map is created to map
+ the interrupts to the respective interrupt controllers.
mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-<4 0>, <5 0>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
mct_map: mct-map {
- #interrupt-cells = <2>;
+ #interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0x0 0 &combiner 23 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
+ interrupt-map = <0 &gic 0 57 0>,
+ <1 &gic 0 69 0>,
+ <2 &combiner 12 6>,
+ <3 &combiner 12 7>,
+ <4 &gic 0 42 0>,
+ <5 &gic 0 48 0>;
};
};
+
+Example 3: In this example, the IP contains four local timers, but using
+ a per-processor interrupt to handle them. Either all the local
+ timer interrupts can be specified, with the same interrupt specifier
+ value or just the first one.
+
+ mct@1005 {
+ compatible = "samsung,exynos4412-mct";
+ reg = <0x1005 0x800>;
+ interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+<0 42 0>/*, <0 42 0>, <0 42 0>, <0 42 0>*/;
+ };
--
1.8.3.2
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[PATCH 8/8] ARM: dts: exynos4: Add missing unit-address of sysreg node
The node contains reg property, so unit-address suffix should be present
in its name.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 892d5ea..92c9d24 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -93,7 +93,7 @@
reg = <0x1044 0x1000>;
};
- sys_reg: sysreg {
+ sys_reg: sysreg@1001 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x1001 0x400>;
};
--
1.8.3.2
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[PATCH 0/8] Exynos device tree clean-up for 3.12
This series intends to fix small problems with Exynos device tree sources that I spotted during my work on other things. The fixes are mostly stylistic, without any funtional changes introduced, except patch 6/8, which makes the mshc node disabled by default, but for all affected boards it is enabled at board level. Tomasz Figa (8): Documentation: devicetree: Update Exynos MCT bindings description ARM: dts: exynos4: Drop interrupt controller properties from MCT nodes ARM: dts: exynos4x12: Move MCT node to exynos4x12.dtsi ARM: dts: exynos4: Simplify MCT interrupt map ARM: dts: exynos4x12: Move mshc node to exynos4x12.dtsi ARM: dts: exynos4x12: Keep mshc node disabled by default ARM: dts: exynos: Fix missing spaces after labels ARM: dts: exynos4: Add missing unit-address of sysreg node .../bindings/timer/samsung,exynos4210-mct.txt | 49 ++ arch/arm/boot/dts/exynos4.dtsi | 6 +-- arch/arm/boot/dts/exynos4210.dtsi | 23 +- arch/arm/boot/dts/exynos4212.dtsi | 24 +-- arch/arm/boot/dts/exynos4412.dtsi | 36 +--- arch/arm/boot/dts/exynos4x12.dtsi | 29 + arch/arm/boot/dts/exynos5.dtsi | 4 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +-- arch/arm/boot/dts/exynos5440.dtsi | 2 +- 9 files changed, 82 insertions(+), 97 deletions(-) -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/8] ARM: dts: exynos4x12: Move MCT node to exynos4x12.dtsi
For MCT block compatible with "samsung,exynos4412-mct", that uses PPI
interrupts for local timers, only one local interrupt needs to be
specified, since it is a per-processor interrupt.
This allows moving MCT node of Exynos4x12 SoCs back to common
exynos4x12.dtsi, since they have the same set of interrupts to be
specified, which was the only difference.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4212.dtsi | 20
arch/arm/boot/dts/exynos4412.dtsi | 24
arch/arm/boot/dts/exynos4x12.dtsi | 20
3 files changed, 20 insertions(+), 44 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index 028752e..443b8a2 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -34,24 +34,4 @@
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>;
};
-
- mct@1005 {
- compatible = "samsung,exynos4412-mct";
- reg = <0x1005 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-<4 0>, <5 0>;
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &combiner 12 5>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 1 12 0>,
- <0x5 0 &gic 1 12 0>;
- };
- };
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index 85d2c26..1388ce0 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -35,30 +35,6 @@
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
};
- mct@1005 {
- compatible = "samsung,exynos4412-mct";
- reg = <0x1005 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-<4 0>, <5 0>, <6 0>, <7 0>;
- clocks = <&clock 3>, <&clock 344>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &combiner 12 5>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 1 12 0>,
- <0x5 0 &gic 1 12 0>,
- <0x6 0 &gic 1 12 0>,
- <0x7 0 &gic 1 12 0>;
- };
- };
-
mshc@1255 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x1255 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe..5012bc8 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -41,6 +41,26 @@
#clock-cells = <1>;
};
+ mct@1005 {
+ compatible = "samsung,exynos4412-mct";
+ reg = <0x1005 0x800>;
+ interrupt-parent = <&mct_map>;
+ interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>;
+ clocks = <&clock 3>, <&clock 344>;
+ clock-names = "fin_pll", "mct";
+
+ mct_map: mct-map {
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0x0 0 &gic 0 57 0>,
+ <0x1 0 &combiner 12 5>,
+ <0x2 0 &combiner 12 6>,
+ <0x3 0 &combiner 12 7>,
+ <0x4 0 &gic 1 12 0>;
+ };
+ };
+
pinctrl_0: pinctrl@1140 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x1140 0x1000>;
--
1.8.3.2
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[PATCH 2/8] ARM: dts: exynos4: Drop interrupt controller properties from MCT nodes
MCT is not an interrupt controller and so there is no point for device
tree nodes representing it to contain interrupt-controller
and #interrupt-cells properties.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4210.dtsi | 2 --
arch/arm/boot/dts/exynos4212.dtsi | 2 --
arch/arm/boot/dts/exynos4412.dtsi | 2 --
3 files changed, 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 057d682..1a6440ae6 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -51,8 +51,6 @@
mct@1005 {
compatible = "samsung,exynos4210-mct";
reg = <0x1005 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index 6f34d7f..028752e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -38,8 +38,6 @@
mct@1005 {
compatible = "samsung,exynos4412-mct";
reg = <0x1005 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index e743e67..85d2c26 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -38,8 +38,6 @@
mct@1005 {
compatible = "samsung,exynos4412-mct";
reg = <0x1005 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>;
--
1.8.3.2
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Re: [PATCH v6 01/13] [media] exynos5-is: Adding media device driver for exynos5
Hi Sylwester,
On Tue, Aug 20, 2013 at 5:29 PM, Sylwester Nawrocki
wrote:
> Cc: Pawel, Kumar
>
> On 08/16/2013 11:20 AM, Arun Kumar K wrote:
>> From: Shaik Ameer Basha
>>
>> This patch adds support for media device for EXYNOS5 SoCs.
>> The current media device supports the following ips to connect
>> through the media controller framework.
>>
>> * MIPI-CSIS
>> Support interconnection(subdev interface) between devices
>>
>> * FIMC-LITE
>> Support capture interface from device(Sensor, MIPI-CSIS) to memory
>> Support interconnection(subdev interface) between devices
>>
>> * FIMC-IS
>> Camera post-processing IP having multiple sub-nodes.
>>
>> G-Scaler will be added later to the current media device.
>>
>> The media device creates two kinds of pipelines for connecting
>> the above mentioned IPs.
>> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
>> image data and dumps to memory.
>> Pipeline1 uses FIMC-IS components for doing post-processing
>> operations on the captured image and give scaled YUV output.
>>
>> Pipeline0
>> ++ +---+ +---+ ++
>> | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
>> ++ +---+ +---+ ++
>>
>> Pipeline1
>> ++ ++ +---+ +---+
>> | Memory | --> | ISP | --> |SCC| --> |SCP|
>> ++ ++ +---+ +---+
>>
>> Signed-off-by: Shaik Ameer Basha
>> Signed-off-by: Arun Kumar K
>> ---
>> .../devicetree/bindings/media/exynos5-mdev.txt | 126 ++
>> drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210
>>
>> drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++
>> 3 files changed, 1462 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
>> create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
>> create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
>>
>> diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt
>> b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
>> new file mode 100644
>> index 000..b1299e2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
>
> Sorry, I missed this previously. How about renaming this file to something
> more specific to the subsystem it describes, e.g. exynos5250-camera.txt ?
>
>> @@ -0,0 +1,126 @@
>> +Samsung EXYNOS5 SoC Camera Subsystem
>> +
>> +
>> +The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
>> +represented by separate device tree nodes. Currently this includes:
>> FIMC-LITE,
>> +MIPI CSIS and FIMC-IS.
>> +
>> +The sub-device nodes are referenced using phandles in the common 'camera'
>> node
>> +which also includes common properties of the whole subsystem not really
>> +specific to any single sub-device, like common camera port pins or the
>> common
>> +camera bus clocks.
>> +
>> +Common 'camera' node
>> +
>> +
>> +Required properties:
>> +
>> +- compatible : must be "samsung,exynos5250-fimc"
>> +- clocks : list of clock specifiers, corresponding to entries in
>> + the clock-names property;
>> +- clock-names: must contain "sclk_bayer" entry
>> +- samsung,csis : list of phandles to the mipi-csis device
>> nodes
>> +- samsung,fimc-lite : list of phandles to the fimc-lite device nodes
>> +- samsung,fimc-is: phandle to the fimc-is device node
>> +
>> +The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
>> +to define a required pinctrl state named "default".
>> +
>> +'parallel-ports' node
>> +-
>> +
>> +This node should contain child 'port' nodes specifying active parallel video
>> +input ports. It includes camera A, camera B and RGB bay inputs.
>> +'reg' property in the port nodes specifies the input type:
>> + 1 - parallel camport A
>> + 2 - parallel camport B
>> + 5 - RGB camera bay
>> +
>> +3, 4 are for MIPI CSI-2 bus and are already described in
>> samsung-mipi-csis.txt
>> +
>> +Image sensor nodes
>> +--
>> +
>> +The sensor device nodes should be added to their control bus controller
>> (e.g.
>> +I2C0) nodes and linked to a port node in the csis or the parallel-ports
>> node,
>> +using the common video interfaces bindings, defined in video-interfaces.txt.
>> +
>> +Example:
>> +
>> + aliases {
>> + fimc-lite0 = &fimc_lite_0
>> + };
>> +
>> + /* Parallel bus IF sensor */
>> + i2c_0: i2c@1386 {
>> + s5k6aa: sensor@3c {
>> + compatible = "samsung,s5k6aafx";
>> + reg = <0x3c>;
>> + vddio-supply = <...>;
>> +
>> + clock-frequency = <2400>;
>> + clocks = <...>;
>> + clock-n
Re: [PATCH 01/15] drivers: phy: add generic PHY framework
Hi, On Mon, Aug 19, 2013 at 10:58:09AM +0530, Kishon Vijay Abraham I wrote: > >> So maybe let's stop solving an already solved problem and just state that > >> you need to explicitly assign device ID to use this framework? > > > > Felipe, > > Can we have it the way I had in my v10 patch series till we find a better > > way? > > I think this *non-dt* stuff shouldn't be blocking as most of the users are > > dt only? I don't have a lot of things against it, but preventing driver authors to use PLATFORM_DEVID_AUTO just to use the framework is likely going to piss some people off. Perhaps we can start with this approach and fix things later ? At least it ungates all the PHY drivers which are depending on this framework (quite a few already). If everybody agrees with this approach, I'd be ok with it too. cheers -- balbi signature.asc Description: Digital signature
Re: [PATCH] ARM: EXYNOS: fix PL330 MDMA1 address in DT for Universal C210 board
Hi Bart,
On Tuesday 20 of August 2013 13:22:45 Bartlomiej Zolnierkiewicz wrote:
> Revision 0 of Exynos4210 SoC (used on Universal C210 board) requires
> 'secure' PL330 MDMA1 address (0x1284) instead of 'non-secure' one
> (0x1285). Fix it by overriding the default PL330 MDMA1 address in
> exynos4210-universal_c210.dts.
>
> This is a Device Tree (DT) version of commit 91280e7 ("ARM: EXYNOS:
> PL330 MDMA1 fix for revision 0 of Exynos4210 SOC") and fixes recent
> regression caused by conversion to DT-only setup on ARM EXYNOS.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/boot/dts/exynos4210-universal_c210.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
> b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 889cdad..d2e3f5f
> 100644
> --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
> +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
> @@ -350,3 +350,7 @@
> status = "okay";
> };
> };
> +
> +&mdma1 {
> + reg = <0x1284 0x1000>;
> +};
Acked-by: Tomasz Figa
As a side note for other reviewers, Universal C210 is the only board based
on Exynos4210 rev0, so board-level dts is the right place for such
override.
Best regards,
Tomasz
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Re: [PATCH v6 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation
Cc: Pawel, Kumar On 08/16/2013 11:20 AM, Arun Kumar K wrote: > The patch adds the DT binding documentation for Samsung > Exynos5 SoC series imaging subsystem (FIMC-IS). > > Signed-off-by: Arun Kumar K > Reviewed-by: Sylwester Nawrocki > --- > .../devicetree/bindings/media/exynos5-fimc-is.txt | 47 > > 1 file changed, 47 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/media/exynos5-fimc-is.txt > > diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt > b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt > new file mode 100644 > index 000..bc279b4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt > @@ -0,0 +1,47 @@ > +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS) > +-- > + > +The camera subsystem on Samsung Exynos5 SoC has some changes relative > +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and > +FIMC-LITE IPs but has a much improved version of FIMC-IS which can > +handle sensor controls and camera post-processing operations. The > +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many > +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two > +dedicated scalers (SCC and SCP). > + > +fimc-is node > + > + > +Required properties: > + > +- compatible: must be "samsung,exynos5250-fimc-is" > +- reg : physical base address and size of the memory mapped > + registers > +- interrupt-parent : parent interrupt controller > +- interrupts: fimc-is interrupt to the parent interrupt controller > +- clocks: list of clock specifiers, corresponding to entries in > + clock-names property; > +- clock-names : must contain "isp", "mcu_isp", "isp_div0", "isp_div1", > + "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries, > + matching entries in the clocks property. > +- samsung,pmu : phandle to the fimc-is pmu node describing the register > + base and size for FIMC-IS PMU. As this is a phandle to the whole SoC Power Management Unit I would amend this to something like: - samsung,pmu : phandle to the Power Management Unit (PMU) node. > + > +i2c-isp (ISP I2C bus controller) nodes > +-- > + > +Required properties: > + > +- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212, > + Exynos4412 and Exynos5250 SoCs; > +- reg: physical base address and length of the registers set; > +- clocks : must contain gate clock specifier for this controller; > +- clock-names: must contain "i2c_isp" entry. > + > +For the i2c-isp node, it is required to specify a pinctrl state named > "default", > +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. > + > +Device tree nodes of the image sensors controlled directly by the FIMC-IS > +firmware must be child nodes of their corresponding ISP I2C bus controller > node. > +The data link of these image sensors must be specified using the common video > +interfaces bindings, defined in video-interfaces.txt. Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 01/13] [media] exynos5-is: Adding media device driver for exynos5
Cc: Pawel, Kumar
On 08/16/2013 11:20 AM, Arun Kumar K wrote:
> From: Shaik Ameer Basha
>
> This patch adds support for media device for EXYNOS5 SoCs.
> The current media device supports the following ips to connect
> through the media controller framework.
>
> * MIPI-CSIS
> Support interconnection(subdev interface) between devices
>
> * FIMC-LITE
> Support capture interface from device(Sensor, MIPI-CSIS) to memory
> Support interconnection(subdev interface) between devices
>
> * FIMC-IS
> Camera post-processing IP having multiple sub-nodes.
>
> G-Scaler will be added later to the current media device.
>
> The media device creates two kinds of pipelines for connecting
> the above mentioned IPs.
> The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
> image data and dumps to memory.
> Pipeline1 uses FIMC-IS components for doing post-processing
> operations on the captured image and give scaled YUV output.
>
> Pipeline0
> ++ +---+ +---+ ++
> | Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
> ++ +---+ +---+ ++
>
> Pipeline1
> ++ ++ +---+ +---+
> | Memory | --> | ISP | --> |SCC| --> |SCP|
> ++ ++ +---+ +---+
>
> Signed-off-by: Shaik Ameer Basha
> Signed-off-by: Arun Kumar K
> ---
> .../devicetree/bindings/media/exynos5-mdev.txt | 126 ++
> drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210
>
> drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++
> 3 files changed, 1462 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/exynos5-mdev.txt
> create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
> create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
>
> diff --git a/Documentation/devicetree/bindings/media/exynos5-mdev.txt
> b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
> new file mode 100644
> index 000..b1299e2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/exynos5-mdev.txt
Sorry, I missed this previously. How about renaming this file to something
more specific to the subsystem it describes, e.g. exynos5250-camera.txt ?
> @@ -0,0 +1,126 @@
> +Samsung EXYNOS5 SoC Camera Subsystem
> +
> +
> +The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
> +represented by separate device tree nodes. Currently this includes:
> FIMC-LITE,
> +MIPI CSIS and FIMC-IS.
> +
> +The sub-device nodes are referenced using phandles in the common 'camera'
> node
> +which also includes common properties of the whole subsystem not really
> +specific to any single sub-device, like common camera port pins or the common
> +camera bus clocks.
> +
> +Common 'camera' node
> +
> +
> +Required properties:
> +
> +- compatible : must be "samsung,exynos5250-fimc"
> +- clocks : list of clock specifiers, corresponding to entries in
> + the clock-names property;
> +- clock-names: must contain "sclk_bayer" entry
> +- samsung,csis : list of phandles to the mipi-csis device nodes
> +- samsung,fimc-lite : list of phandles to the fimc-lite device nodes
> +- samsung,fimc-is: phandle to the fimc-is device node
> +
> +The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
> +to define a required pinctrl state named "default".
> +
> +'parallel-ports' node
> +-
> +
> +This node should contain child 'port' nodes specifying active parallel video
> +input ports. It includes camera A, camera B and RGB bay inputs.
> +'reg' property in the port nodes specifies the input type:
> + 1 - parallel camport A
> + 2 - parallel camport B
> + 5 - RGB camera bay
> +
> +3, 4 are for MIPI CSI-2 bus and are already described in
> samsung-mipi-csis.txt
> +
> +Image sensor nodes
> +--
> +
> +The sensor device nodes should be added to their control bus controller (e.g.
> +I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
> +using the common video interfaces bindings, defined in video-interfaces.txt.
> +
> +Example:
> +
> + aliases {
> + fimc-lite0 = &fimc_lite_0
> + };
> +
> + /* Parallel bus IF sensor */
> + i2c_0: i2c@1386 {
> + s5k6aa: sensor@3c {
> + compatible = "samsung,s5k6aafx";
> + reg = <0x3c>;
> + vddio-supply = <...>;
> +
> + clock-frequency = <2400>;
> + clocks = <...>;
> + clock-names = "mclk";
> +
> + port {
> + s5k6aa_ep: endpoint {
> + remote-endpoint = <&fimc0_ep>;
> +
[PATCH] ARM: EXYNOS: fix PL330 MDMA1 address in DT for Universal C210 board
Revision 0 of Exynos4210 SoC (used on Universal C210 board) requires
'secure' PL330 MDMA1 address (0x1284) instead of 'non-secure' one
(0x1285). Fix it by overriding the default PL330 MDMA1 address in
exynos4210-universal_c210.dts.
This is a Device Tree (DT) version of commit 91280e7 ("ARM: EXYNOS:
PL330 MDMA1 fix for revision 0 of Exynos4210 SOC") and fixes recent
regression caused by conversion to DT-only setup on ARM EXYNOS.
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4210-universal_c210.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 889cdad..d2e3f5f 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -350,3 +350,7 @@
status = "okay";
};
};
+
+&mdma1 {
+ reg = <0x1284 0x1000>;
+};
--
1.8.2.3
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Re: [PATCH v2 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
On Tue, Aug 20, 2013 at 10:23:49AM +0200, Heiko Stübner wrote:
> Hi Vinod,
>
> Am Montag, 19. August 2013, 06:48:12 schrieb Vinod Koul:
> > On Wed, Aug 14, 2013 at 02:00:25PM +0200, Heiko Stübner wrote:
> > > This adds a new driver to support the s3c24xx dma using the dmaengine
> > > and makes the old one in mach-s3c24xx obsolete in the long run.
> > >
> > > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> > > with numerous virtual channels being mapped to a lot less physical ones.
> > > The driver therefore borrows a lot from the amba-pl08x driver in this
> > > regard. Functionality-wise the driver gains a memcpy ability in addition
> > > to the slave_sg one.
> >
> > If that is the case why cant we have this driver supported from pl08x
> > driver? If the delta is only mapping then can that be seprated or both
> > mapping hanlded? Maybe you and Linus have already though about that?
>
> Yes we have ... As Tomasz has already written the hardware itself is very
> much
> different. It's only the concept of mapping virtual channels to physical
> channels that is somehow similar.
>
> It seems my patch message is lacking in making this clearer ;-) .
The above made me believ they are similar contrlllers with differnt mapping!,
hence the question...
> > > +#define DMASKTRIG_STOP (1 << 2)
> > > +#define DMASKTRIG_ON (1 << 1)
> > > +#define DMASKTRIG_SWTRIG (1 << 0)
> > > +
> > > +#define DMAREQSEL(0x24)
> > > +#define DMAREQSEL_HW (1 << 0)
> >
> > This is proper namespacing...
>
> Hmm, I don't understand meaning of this sentence. Is it a suggestion to
> change
> anything?
Sorry above should be read as "this need proper namespacing". The macros like
DMAREQSEL asre farliy egneric and can collide with others. SO the recommendation
is to use something like S3_DMAREQSEL etc
> > > +static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
> > > +{
> > > + struct s3c24xx_dma_phy *phy = data;
> > > + struct s3c24xx_dma_chan *s3cchan = phy->serving;
> > > + struct s3c24xx_txd *txd;
> > > +
> > > + dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n", phy->id);
> > > +
> > > + if (!s3cchan) {
> > > + dev_err(&phy->host->pdev->dev, "interrupt on unused channel
> %d\n",
> > > + phy->id);
> > > + return IRQ_NONE;
> >
> > hmmm, these channles belong to you. So if one of them is behvaing badly,
> > then not handling the interrupt will make things worse...
>
> hmm ... I'm not sure what a valid handling would be for this.
>
> The interrupt is only asserted when a transfer is completed - there are no
> other interrupt-triggers. But when phy->serving is NULL, this also means that
> the clock of the channel is disabled at this time. So this _should_ never
> happen.
if that is the case we dont need above, but you added that just for the small
iota of if
> And as written above, the interrupt is only triggered when a transfer was
> completed and the channel is idle again, so if there is no virtual channel
> being served, there is nothing else to do.
But if we do get such an interrupt, it means:
a) bug in SW
b) erratic hw behaviour
if you handle and dump the issue at least you have recovered. Rather than
returning and controller asserting interrupt again and again as it is not
cleared.
~Vinod
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Re: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-Scaler
On Tue, Aug 20, 2013 at 2:13 PM, Inki Dae wrote:
>
>
>> -Original Message-
>> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
>> ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
>> Sent: Tuesday, August 20, 2013 5:07 PM
>> To: Inki Dae
>> Cc: Shaik Ameer Basha; LMML; linux-samsung-soc@vger.kernel.org;
>> c...@samsung.com; Sylwester Nawrocki; posc...@google.com; Arun Kumar K
>> Subject: Re: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-
>> Scaler
>>
>> Hi Inki Dae,
>>
>> Thanks for the review.
>>
>>
>> On Mon, Aug 19, 2013 at 6:18 PM, Inki Dae wrote:
>> > Just quick review.
>> >
>> >> -Original Message-
>> >> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
>> >> ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
>> >> Sent: Monday, August 19, 2013 7:59 PM
>> >> To: linux-me...@vger.kernel.org; linux-samsung-soc@vger.kernel.org
>> >> Cc: s.nawro...@samsung.com; posc...@google.com; arun...@samsung.com;
>> >> shaik.am...@samsung.com
>> >> Subject: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-
>> Scaler
>> >>
>> >> This patch adds support for M-Scaler (M2M Scaler) device which is a
>> >> new device for scaling, blending, color fill and color space
>> >> conversion on EXYNOS5 SoCs.
>> >>
>> >> This device supports the followings as key feature.
>> >> input image format
>> >> - YCbCr420 2P(UV/VU), 3P
>> >> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
>> >> - YCbCr444 2P(UV,VU), 3P
>> >> - RGB565, ARGB1555, ARGB, ARGB, RGBA
>> >> - Pre-multiplexed ARGB, L8A8 and L8
>> >> output image format
>> >> - YCbCr420 2P(UV/VU), 3P
>> >> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
>> >> - YCbCr444 2P(UV,VU), 3P
>> >> - RGB565, ARGB1555, ARGB, ARGB, RGBA
>> >> - Pre-multiplexed ARGB
>> >> input rotation
>> >> - 0/90/180/270 degree, X/Y/XY Flip
>> >> scale ratio
>> >> - 1/4 scale down to 16 scale up
>> >> color space conversion
>> >> - RGB to YUV / YUV to RGB
>> >> Size
>> >> - Input : 16x16 to 8192x8192
>> >> - Output: 4x4 to 8192x8192
>> >> alpha blending, color fill
>> >>
>> >> Signed-off-by: Shaik Ameer Basha
>> >> ---
>> >> drivers/media/platform/exynos-mscl/mscl-regs.c | 318
>> >>
>> >> drivers/media/platform/exynos-mscl/mscl-regs.h | 282
>> >> +
>> >> 2 files changed, 600 insertions(+)
>> >> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.c
>> >> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.h
>> >>
>> >> diff --git a/drivers/media/platform/exynos-mscl/mscl-regs.c
>> >> b/drivers/media/platform/exynos-mscl/mscl-regs.c
>> >> new file mode 100644
>> >> index 000..9354afc
>> >> --- /dev/null
>> >> +++ b/drivers/media/platform/exynos-mscl/mscl-regs.c
>> >> @@ -0,0 +1,318 @@
>> >> +/*
>> >> + * Copyright (c) 2013 - 2014 Samsung Electronics Co., Ltd.
>> >> + * http://www.samsung.com
>> >> + *
>> >> + * Samsung EXYNOS5 SoC series M-Scaler driver
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or
>> modify
>> >> + * it under the terms of the GNU General Public License as published
>> >> + * by the Free Software Foundation, either version 2 of the License,
>> >> + * or (at your option) any later version.
>> >> + */
>> >> +
>> >> +#include
>> >> +#include
>> >> +
>> >> +#include "mscl-core.h"
>> >> +
>> >> +void mscl_hw_set_sw_reset(struct mscl_dev *dev)
>> >> +{
>> >> + u32 cfg;
>> >> +
>> >> + cfg = readl(dev->regs + MSCL_CFG);
>> >> + cfg |= MSCL_CFG_SOFT_RESET;
>> >> +
>> >> + writel(cfg, dev->regs + MSCL_CFG);
>> >> +}
>> >> +
>> >> +int mscl_wait_reset(struct mscl_dev *dev)
>> >> +{
>> >> + unsigned long end = jiffies + msecs_to_jiffies(50);
>> >
>> > What does 50 mean?
>> >
>> >> + u32 cfg, reset_done = 0;
>> >> +
>> >
>> > Please describe why the below codes are needed.
>>
>>
>> As per the Documentation,
>>
>> " SOFT RESET: Writing "1" to this bit generates software reset. To
>> check the completion of the reset, wait until this
>> field becomes zero, then wrie an arbitrary value to any of RW
>> registers and read it. If the read data matches the written data,
>> it means SW reset succeeded. Otherwise, repeat write & read until
>> matched."
>>
>>
>> Thie below code tries to do the same (as per user manual). and in the
>> above msec_to_jiffies(50), 50 is the 50msec wait. before
>> checking the SOFT RESET is really done.
>>
>> Is it good to ignore this checks?
>>
>
> No, I mean that someone may want to understand your codes so leave comments
> enough for them.
Ok. thanks. I will add more comments. :)
Regards,
Shaik Ameer Basha
>
> Thanks,
> Inki Dae
>
>>
>>
>> >
>> >> + while (time_before(jiffies, end)) {
>> >> + cfg = readl(dev->regs + MSCL_CFG);
>> >> + if (!(cfg & MSCL_CFG_SOFT_
RE: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-Scaler
> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
> Sent: Tuesday, August 20, 2013 5:07 PM
> To: Inki Dae
> Cc: Shaik Ameer Basha; LMML; linux-samsung-soc@vger.kernel.org;
> c...@samsung.com; Sylwester Nawrocki; posc...@google.com; Arun Kumar K
> Subject: Re: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-
> Scaler
>
> Hi Inki Dae,
>
> Thanks for the review.
>
>
> On Mon, Aug 19, 2013 at 6:18 PM, Inki Dae wrote:
> > Just quick review.
> >
> >> -Original Message-
> >> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> >> ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
> >> Sent: Monday, August 19, 2013 7:59 PM
> >> To: linux-me...@vger.kernel.org; linux-samsung-soc@vger.kernel.org
> >> Cc: s.nawro...@samsung.com; posc...@google.com; arun...@samsung.com;
> >> shaik.am...@samsung.com
> >> Subject: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-
> Scaler
> >>
> >> This patch adds support for M-Scaler (M2M Scaler) device which is a
> >> new device for scaling, blending, color fill and color space
> >> conversion on EXYNOS5 SoCs.
> >>
> >> This device supports the followings as key feature.
> >> input image format
> >> - YCbCr420 2P(UV/VU), 3P
> >> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
> >> - YCbCr444 2P(UV,VU), 3P
> >> - RGB565, ARGB1555, ARGB, ARGB, RGBA
> >> - Pre-multiplexed ARGB, L8A8 and L8
> >> output image format
> >> - YCbCr420 2P(UV/VU), 3P
> >> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
> >> - YCbCr444 2P(UV,VU), 3P
> >> - RGB565, ARGB1555, ARGB, ARGB, RGBA
> >> - Pre-multiplexed ARGB
> >> input rotation
> >> - 0/90/180/270 degree, X/Y/XY Flip
> >> scale ratio
> >> - 1/4 scale down to 16 scale up
> >> color space conversion
> >> - RGB to YUV / YUV to RGB
> >> Size
> >> - Input : 16x16 to 8192x8192
> >> - Output: 4x4 to 8192x8192
> >> alpha blending, color fill
> >>
> >> Signed-off-by: Shaik Ameer Basha
> >> ---
> >> drivers/media/platform/exynos-mscl/mscl-regs.c | 318
> >>
> >> drivers/media/platform/exynos-mscl/mscl-regs.h | 282
> >> +
> >> 2 files changed, 600 insertions(+)
> >> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.c
> >> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.h
> >>
> >> diff --git a/drivers/media/platform/exynos-mscl/mscl-regs.c
> >> b/drivers/media/platform/exynos-mscl/mscl-regs.c
> >> new file mode 100644
> >> index 000..9354afc
> >> --- /dev/null
> >> +++ b/drivers/media/platform/exynos-mscl/mscl-regs.c
> >> @@ -0,0 +1,318 @@
> >> +/*
> >> + * Copyright (c) 2013 - 2014 Samsung Electronics Co., Ltd.
> >> + * http://www.samsung.com
> >> + *
> >> + * Samsung EXYNOS5 SoC series M-Scaler driver
> >> + *
> >> + * This program is free software; you can redistribute it and/or
> modify
> >> + * it under the terms of the GNU General Public License as published
> >> + * by the Free Software Foundation, either version 2 of the License,
> >> + * or (at your option) any later version.
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +
> >> +#include "mscl-core.h"
> >> +
> >> +void mscl_hw_set_sw_reset(struct mscl_dev *dev)
> >> +{
> >> + u32 cfg;
> >> +
> >> + cfg = readl(dev->regs + MSCL_CFG);
> >> + cfg |= MSCL_CFG_SOFT_RESET;
> >> +
> >> + writel(cfg, dev->regs + MSCL_CFG);
> >> +}
> >> +
> >> +int mscl_wait_reset(struct mscl_dev *dev)
> >> +{
> >> + unsigned long end = jiffies + msecs_to_jiffies(50);
> >
> > What does 50 mean?
> >
> >> + u32 cfg, reset_done = 0;
> >> +
> >
> > Please describe why the below codes are needed.
>
>
> As per the Documentation,
>
> " SOFT RESET: Writing "1" to this bit generates software reset. To
> check the completion of the reset, wait until this
> field becomes zero, then wrie an arbitrary value to any of RW
> registers and read it. If the read data matches the written data,
> it means SW reset succeeded. Otherwise, repeat write & read until
> matched."
>
>
> Thie below code tries to do the same (as per user manual). and in the
> above msec_to_jiffies(50), 50 is the 50msec wait. before
> checking the SOFT RESET is really done.
>
> Is it good to ignore this checks?
>
No, I mean that someone may want to understand your codes so leave comments
enough for them.
Thanks,
Inki Dae
>
>
> >
> >> + while (time_before(jiffies, end)) {
> >> + cfg = readl(dev->regs + MSCL_CFG);
> >> + if (!(cfg & MSCL_CFG_SOFT_RESET)) {
> >> + reset_done = 1;
> >> + break;
> >> + }
> >> + usleep_range(10, 20);
> >> + }
> >> +
> >> + /* write any value to r/w reg and read it back */
> >> + while (reset_don
Re: [PATCH v2 2/4] dmaengine: add driver for Samsung s3c24xx SoCs
Hi Vinod,
Am Montag, 19. August 2013, 06:48:12 schrieb Vinod Koul:
> On Wed, Aug 14, 2013 at 02:00:25PM +0200, Heiko Stübner wrote:
> > This adds a new driver to support the s3c24xx dma using the dmaengine
> > and makes the old one in mach-s3c24xx obsolete in the long run.
> >
> > Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
> > with numerous virtual channels being mapped to a lot less physical ones.
> > The driver therefore borrows a lot from the amba-pl08x driver in this
> > regard. Functionality-wise the driver gains a memcpy ability in addition
> > to the slave_sg one.
>
> If that is the case why cant we have this driver supported from pl08x
> driver? If the delta is only mapping then can that be seprated or both
> mapping hanlded? Maybe you and Linus have already though about that?
Yes we have ... As Tomasz has already written the hardware itself is very much
different. It's only the concept of mapping virtual channels to physical
channels that is somehow similar.
It seems my patch message is lacking in making this clearer ;-) .
> > The driver supports both the method for requesting the peripheral used
> > by SoCs before the S3C2443 and the different method for S3C2443 and
> > later.
> >
> > On earlier SoCs the hardware channels usable for specific peripherals is
> > constrainted while on later SoCs all channels can be used for any
> > peripheral.
> >
> > Tested on a s3c2416-based board, memcpy using the dmatest module and
> > slave_sg partially using the spi-s3c64xx driver.
> >
> > Signed-off-by: Heiko Stuebner
> >
> > +#define DISRC (0x00)
> > +#define DISRCC (0x04)
> > +#define DISRCC_INC_INCREMENT (0 << 0)
> > +#define DISRCC_INC_FIXED (1 << 0)
> > +#define DISRCC_LOC_AHB (0 << 1)
> > +#define DISRCC_LOC_APB (1 << 1)
> > +
> > +#define DIDST (0x08)
> > +#define DIDSTC (0x0C)
> > +#define DIDSTC_INC_INCREMENT (0 << 0)
> > +#define DIDSTC_INC_FIXED (1 << 0)
> > +#define DIDSTC_LOC_AHB (0 << 1)
> > +#define DIDSTC_LOC_APB (1 << 1)
> > +#define DIDSTC_INT_TC0 (0 << 2)
> > +#define DIDSTC_INT_RELOAD (1 << 2)
> > +
> > +#define DCON (0x10)
> > +
> > +#define DCON_TC_MASK 0xf
> > +#define DCON_DSZ_BYTE (0 << 20)
> > +#define DCON_DSZ_HALFWORD (1 << 20)
> > +#define DCON_DSZ_WORD (2 << 20)
> > +#define DCON_DSZ_MASK (3 << 20)
> > +#define DCON_DSZ_SHIFT 20
> > +#define DCON_AUTORELOAD(0 << 22)
> > +#define DCON_NORELOAD (1 << 22)
> > +#define DCON_HWTRIG(1 << 23)
> > +#define DCON_HWSRC_SHIFT 24
> > +#define DCON_SERV_SINGLE (0 << 27)
> > +#define DCON_SERV_WHOLE(1 << 27)
> > +#define DCON_TSZ_UNIT (0 << 28)
> > +#define DCON_TSZ_BURST4(1 << 28)
> > +#define DCON_INT (1 << 29)
> > +#define DCON_SYNC_PCLK (0 << 30)
> > +#define DCON_SYNC_HCLK (1 << 30)
> > +#define DCON_DEMAND(0 << 31)
> > +#define DCON_HANDSHAKE (1 << 31)
> > +
> > +#define DSTAT (0x14)
> > +#define DSTAT_STAT_BUSY(1 << 20)
> > +#define DSTAT_CURRTC_MASK 0xf
> > +
> > +#define DMASKTRIG (0x20)
> > +#define DMASKTRIG_STOP (1 << 2)
> > +#define DMASKTRIG_ON (1 << 1)
> > +#define DMASKTRIG_SWTRIG (1 << 0)
> > +
> > +#define DMAREQSEL (0x24)
> > +#define DMAREQSEL_HW (1 << 0)
>
> This is proper namespacing...
Hmm, I don't understand meaning of this sentence. Is it a suggestion to change
anything?
> > +static int s3c24xx_dma_set_runtime_config(struct s3c24xx_dma_chan
> > *s3cchan, + struct dma_slave_config *config)
> > +{
> > + if (!s3cchan->slave)
> > + return -EINVAL;
> > +
> > + /* Reject definitely invalid configurations */
> > + if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
> > + config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > + return -EINVAL;
> > +
> > + s3cchan->cfg = *config;
>
> you are takinga ref to client pointer without a clue on when that would be
> freed. I dont think its a good idea!
hmm, the config pointer is dereferenced here and its data thus copyied into
s3cchan->cfg, so no reference to the origial config pointer is kept.
> > +static irqreturn_t s3c24xx_dma_irq(int irq, void *data)
> > +{
> > + struct s3c24xx_dma_phy *phy = data;
> > + struct s3c24xx_dma_chan *s3cchan = phy->serving;
> > + struct s3c24xx_txd *txd;
> > +
> > + dev_dbg(&phy->host->pdev->dev, "interrupt on channel %d\n", phy->id);
> > +
> > + if (!s3cchan) {
> > + dev_err(&phy->host->pdev->dev, "interrupt on unused channel
%d\n",
> > + phy->id);
> > + return IRQ_NONE;
>
> hmmm, these channles
Re: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-Scaler
Hi Inki Dae,
Thanks for the review.
On Mon, Aug 19, 2013 at 6:18 PM, Inki Dae wrote:
> Just quick review.
>
>> -Original Message-
>> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
>> ow...@vger.kernel.org] On Behalf Of Shaik Ameer Basha
>> Sent: Monday, August 19, 2013 7:59 PM
>> To: linux-me...@vger.kernel.org; linux-samsung-soc@vger.kernel.org
>> Cc: s.nawro...@samsung.com; posc...@google.com; arun...@samsung.com;
>> shaik.am...@samsung.com
>> Subject: [PATCH v2 1/5] [media] exynos-mscl: Add new driver for M-Scaler
>>
>> This patch adds support for M-Scaler (M2M Scaler) device which is a
>> new device for scaling, blending, color fill and color space
>> conversion on EXYNOS5 SoCs.
>>
>> This device supports the followings as key feature.
>> input image format
>> - YCbCr420 2P(UV/VU), 3P
>> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
>> - YCbCr444 2P(UV,VU), 3P
>> - RGB565, ARGB1555, ARGB, ARGB, RGBA
>> - Pre-multiplexed ARGB, L8A8 and L8
>> output image format
>> - YCbCr420 2P(UV/VU), 3P
>> - YCbCr422 1P(YUYV/UYVY/YVYU), 2P(UV,VU), 3P
>> - YCbCr444 2P(UV,VU), 3P
>> - RGB565, ARGB1555, ARGB, ARGB, RGBA
>> - Pre-multiplexed ARGB
>> input rotation
>> - 0/90/180/270 degree, X/Y/XY Flip
>> scale ratio
>> - 1/4 scale down to 16 scale up
>> color space conversion
>> - RGB to YUV / YUV to RGB
>> Size
>> - Input : 16x16 to 8192x8192
>> - Output: 4x4 to 8192x8192
>> alpha blending, color fill
>>
>> Signed-off-by: Shaik Ameer Basha
>> ---
>> drivers/media/platform/exynos-mscl/mscl-regs.c | 318
>>
>> drivers/media/platform/exynos-mscl/mscl-regs.h | 282
>> +
>> 2 files changed, 600 insertions(+)
>> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.c
>> create mode 100644 drivers/media/platform/exynos-mscl/mscl-regs.h
>>
>> diff --git a/drivers/media/platform/exynos-mscl/mscl-regs.c
>> b/drivers/media/platform/exynos-mscl/mscl-regs.c
>> new file mode 100644
>> index 000..9354afc
>> --- /dev/null
>> +++ b/drivers/media/platform/exynos-mscl/mscl-regs.c
>> @@ -0,0 +1,318 @@
>> +/*
>> + * Copyright (c) 2013 - 2014 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Samsung EXYNOS5 SoC series M-Scaler driver
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published
>> + * by the Free Software Foundation, either version 2 of the License,
>> + * or (at your option) any later version.
>> + */
>> +
>> +#include
>> +#include
>> +
>> +#include "mscl-core.h"
>> +
>> +void mscl_hw_set_sw_reset(struct mscl_dev *dev)
>> +{
>> + u32 cfg;
>> +
>> + cfg = readl(dev->regs + MSCL_CFG);
>> + cfg |= MSCL_CFG_SOFT_RESET;
>> +
>> + writel(cfg, dev->regs + MSCL_CFG);
>> +}
>> +
>> +int mscl_wait_reset(struct mscl_dev *dev)
>> +{
>> + unsigned long end = jiffies + msecs_to_jiffies(50);
>
> What does 50 mean?
>
>> + u32 cfg, reset_done = 0;
>> +
>
> Please describe why the below codes are needed.
As per the Documentation,
" SOFT RESET: Writing "1" to this bit generates software reset. To
check the completion of the reset, wait until this
field becomes zero, then wrie an arbitrary value to any of RW
registers and read it. If the read data matches the written data,
it means SW reset succeeded. Otherwise, repeat write & read until matched."
Thie below code tries to do the same (as per user manual). and in the
above msec_to_jiffies(50), 50 is the 50msec wait. before
checking the SOFT RESET is really done.
Is it good to ignore this checks?
>
>> + while (time_before(jiffies, end)) {
>> + cfg = readl(dev->regs + MSCL_CFG);
>> + if (!(cfg & MSCL_CFG_SOFT_RESET)) {
>> + reset_done = 1;
>> + break;
>> + }
>> + usleep_range(10, 20);
>> + }
>> +
>> + /* write any value to r/w reg and read it back */
>> + while (reset_done) {
>> +
>> + /* [TBD] need to define number of tries before returning
>> + * -EBUSY to the caller
>> + */
>> +
>> + writel(MSCL_CFG_SOFT_RESET_CHECK_VAL,
>> + dev->regs + MSCL_CFG_SOFT_RESET_CHECK_REG);
>> + if (MSCL_CFG_SOFT_RESET_CHECK_VAL ==
>> + readl(dev->regs + MSCL_CFG_SOFT_RESET_CHECK_REG))
>> + return 0;
>> + }
>> +
>> + return -EBUSY;
>> +}
>> +
>> +void mscl_hw_set_irq_mask(struct mscl_dev *dev, int interrupt, bool mask)
>> +{
>> + u32 cfg;
>> +
>> + switch (interrupt) {
>> + case MSCL_INT_TIMEOUT:
>> + case MSCL_INT_ILLEGAL_BLEND:
>> + case MSCL_INT_ILLEGAL_RATIO:
>> + case MSCL_INT_ILLEGAL_DST_HEIGHT:
>> + case MSCL_INT_IL
Re: [PATCH v2 2/5] [media] exynos-mscl: Add core functionality for the M-Scaler driver
On Tue, Aug 20, 2013 at 11:57 AM, Hans Verkuil wrote:
> On 08/20/2013 07:43 AM, Shaik Ameer Basha wrote:
>> + linux-media, linux-samsung-soc
>>
>> Hi Hans,
>>
>> Thanks for the review.
>> Will address all your comments in v3.
>>
>> I have only one doubt regarding try_ctrl... (addressed inline)
>>
>>
>> On Mon, Aug 19, 2013 at 6:36 PM, Hans Verkuil wrote:
>>>
>>> On 08/19/2013 12:58 PM, Shaik Ameer Basha wrote:
This patch adds the core functionality for the M-Scaler driver.
>>>
>>> Some more comments below...
>>>
Signed-off-by: Shaik Ameer Basha
---
drivers/media/platform/exynos-mscl/mscl-core.c | 1312
drivers/media/platform/exynos-mscl/mscl-core.h | 549 ++
2 files changed, 1861 insertions(+)
create mode 100644 drivers/media/platform/exynos-mscl/mscl-core.c
create mode 100644 drivers/media/platform/exynos-mscl/mscl-core.h
diff --git a/drivers/media/platform/exynos-mscl/mscl-core.c
b/drivers/media/platform/exynos-mscl/mscl-core.c
new file mode 100644
index 000..4a3a851
--- /dev/null
+++ b/drivers/media/platform/exynos-mscl/mscl-core.c
@@ -0,0 +1,1312 @@
+/*
+ * Copyright (c) 2013 - 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung EXYNOS5 SoC series M-Scaler driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundation, either version 2 of the License,
+ * or (at your option) any later version.
+ */
+
+#include
+#include
>>
>> [snip]
>>
+
+static int __mscl_s_ctrl(struct mscl_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ struct mscl_dev *mscl = ctx->mscl_dev;
+ struct mscl_variant *variant = mscl->variant;
+ unsigned int flags = MSCL_DST_FMT | MSCL_SRC_FMT;
+ int ret = 0;
+
+ if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
+ return 0;
>>>
>>> Why would you want to do this check?
>>
>> Will remove this. seems no such check is required for this driver.
>>
>>>
+
+ switch (ctrl->id) {
+ case V4L2_CID_HFLIP:
+ ctx->hflip = ctrl->val;
+ break;
+
+ case V4L2_CID_VFLIP:
+ ctx->vflip = ctrl->val;
+ break;
+
+ case V4L2_CID_ROTATE:
+ if ((ctx->state & flags) == flags) {
+ ret = mscl_check_scaler_ratio(variant,
+ ctx->s_frame.crop.width,
+ ctx->s_frame.crop.height,
+ ctx->d_frame.crop.width,
+ ctx->d_frame.crop.height,
+ ctx->ctrls_mscl.rotate->val);
+
+ if (ret)
+ return -EINVAL;
+ }
>>>
>>> I think it would be good if the try_ctrl op is implemented so you can call
>>> VIDIOC_EXT_TRY_CTRLS in the application to check if the ROTATE control can
>>> be
>>> set.
>>
>> * @try_ctrl: Test whether the control's value is valid. Only relevant when
>> * the usual min/max/step checks are not sufficient.
>>
>> As we support only 0,90,270 and the min, max and step can address these
>> values,
>> does it really relevant to have try_ctrl op here ???
>
> Well, you seem to have an additional mscl_check_scaler_ratio check here that
> can
> make it fail, in other words: the min/max/step checks aren't sufficient.
Ok. Thanks for the explanation. Will implement that.
Regards,
Shaik Ameer Basha
>
> Regards,
>
> Hans
>
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RE: RE: [PATCH v2 0/8] Common Clock Framework support for Samsung S3C64xx
Mike Turquette wrote: > [...] > > OK, if new branch is ready, I will replace with that or if re-merge is > > required, I will. Either way, I'm fine and can handle. Mike, let me know > > your choice :-) > > Since I have already published it let's just go with the delta patch. I > can create another stable branch named clk-next-s3c64xx-delta that just > has this patch on top of clk-next-s3c64xx OR I can apply it on top of > the existing clk-next-s3c64xx and re-merge it. > Sounds good to me. If the branch for the delta is ready, let me know. > I'm trying to think on whether there are any weird git corner cases with > re-merging clk-next-s3c64xx. Let me know if re-merging is somehow unsafe > (makes history weird, or whatever). > I don't think it causes some problem. > Let me know what option is better for you. I'll publish as soon as I get > the delta patch. Apologies again for creating some extra work! > No problem. Thanks, Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
