[PATCH 1/2] clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
Exynos5420 is octacore SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dt entries for 8 interrupts.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi |9 +++--
drivers/clocksource/exynos_mct.c |4
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ce2f94..e97c87b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -69,7 +69,8 @@
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
clocks = <&clock 1>, <&clock 315>;
clock-names = "fin_pll", "mct";
@@ -84,7 +85,11 @@
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
- <7 &gic 0 123 0>;
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
};
};
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index b2bbc41..ff4711e 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
+ MCT_L4_IRQ,
+ MCT_L5_IRQ,
+ MCT_L6_IRQ,
+ MCT_L7_IRQ,
MCT_NR_IRQS,
};
--
1.7.9.5
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[PATCH 0/2] Enable all cpus in Exynos5420
Exynos5420 is an octacore SoC. This patch series enables the remaining 4 cores. Chander Kashyap (2): clocksource: mct: extend mct to support 8 local interrupts for Exynos5420 arm: dt: Exynos5420: populate cpu node enteries to 8 cpus arch/arm/boot/dts/exynos5420.dtsi | 37 +++-- drivers/clocksource/exynos_mct.c |4 2 files changed, 39 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Exynos5420 is octacore SoC from samsung.
Hence populate all the cpu node enteries.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e97c87b..59489f6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -57,6 +57,34 @@
reg = <0x3>;
clock-frequency = <18>;
};
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <10>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <10>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <10>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <10>;
+ };
};
clock: clock-controller@0x1001 {
--
1.7.9.5
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Re: [PATCH 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Hi Chander,
On Thursday 05 of September 2013 14:54:46 Chander Kashyap wrote:
> Exynos5420 is octacore SoC from samsung.
> Hence populate all the cpu node enteries.
>
> Signed-off-by: Chander Kashyap
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi index e97c87b..59489f6 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -57,6 +57,34 @@
> reg = <0x3>;
> clock-frequency = <18>;
> };
> +
> + cpu4: cpu@4 {
I believe this is a typo. The @unit-address suffix should match the value
of reg property.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + clock-frequency = <10>;
> + };
> +
> + cpu5: cpu@5 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + clock-frequency = <10>;
> + };
> +
> + cpu6: cpu@6 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + clock-frequency = <10>;
> + };
> +
> + cpu7: cpu@7 {
Ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + clock-frequency = <10>;
> + };
> };
Best regards,
Tomasz
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Re: [PATCH 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Hi Tomasz,
On 5 September 2013 15:25, Tomasz Figa wrote:
> Hi Chander,
>
> On Thursday 05 of September 2013 14:54:46 Chander Kashyap wrote:
>> Exynos5420 is octacore SoC from samsung.
>> Hence populate all the cpu node enteries.
>>
>> Signed-off-by: Chander Kashyap
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 28
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi index e97c87b..59489f6 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -57,6 +57,34 @@
>> reg = <0x3>;
>> clock-frequency = <18>;
>> };
>> +
>> + cpu4: cpu@4 {
>
> I believe this is a typo. The @unit-address suffix should match the value
> of reg property.
No this is not typo. It is the MPIDR value of the cpu. (24 bits of
MPIDR register).
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x100>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu5: cpu@5 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x101>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu6: cpu@6 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x102>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu7: cpu@7 {
>
> Ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x103>;
>> + clock-frequency = <10>;
>> + };
>> };
>
> Best regards,
> Tomasz
>
--
with warm regards,
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Re: [PATCH 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
On Thursday 05 of September 2013 15:33:17 Chander Kashyap wrote:
> Hi Tomasz,
>
> On 5 September 2013 15:25, Tomasz Figa wrote:
> > Hi Chander,
> >
> > On Thursday 05 of September 2013 14:54:46 Chander Kashyap wrote:
> >> Exynos5420 is octacore SoC from samsung.
> >> Hence populate all the cpu node enteries.
> >>
> >> Signed-off-by: Chander Kashyap
> >> ---
> >>
> >> arch/arm/boot/dts/exynos5420.dtsi | 28
> >> 1 file changed, 28 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> >> b/arch/arm/boot/dts/exynos5420.dtsi index e97c87b..59489f6 100644
> >> --- a/arch/arm/boot/dts/exynos5420.dtsi
> >> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> >> @@ -57,6 +57,34 @@
> >>
> >> reg = <0x3>;
> >> clock-frequency = <18>;
> >>
> >> };
> >>
> >> +
> >> + cpu4: cpu@4 {
> >
> > I believe this is a typo. The @unit-address suffix should match the
> > value of reg property.
>
> No this is not typo. It is the MPIDR value of the cpu. (24 bits of
> MPIDR register).
Right. This is what the reg property should be set to. However, the @unit-
address prefix of node name should match the value of reg property, so if
the value of reg property is 0x100, then the node should be named cpu@100.
Best regards,
Tomasz
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Re: [PATCH 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
On 5 September 2013 15:40, Tomasz Figa wrote:
> On Thursday 05 of September 2013 15:33:17 Chander Kashyap wrote:
>> Hi Tomasz,
>>
>> On 5 September 2013 15:25, Tomasz Figa wrote:
>> > Hi Chander,
>> >
>> > On Thursday 05 of September 2013 14:54:46 Chander Kashyap wrote:
>> >> Exynos5420 is octacore SoC from samsung.
>> >> Hence populate all the cpu node enteries.
>> >>
>> >> Signed-off-by: Chander Kashyap
>> >> ---
>> >>
>> >> arch/arm/boot/dts/exynos5420.dtsi | 28
>> >> 1 file changed, 28 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> >> b/arch/arm/boot/dts/exynos5420.dtsi index e97c87b..59489f6 100644
>> >> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> >> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> >> @@ -57,6 +57,34 @@
>> >>
>> >> reg = <0x3>;
>> >> clock-frequency = <18>;
>> >>
>> >> };
>> >>
>> >> +
>> >> + cpu4: cpu@4 {
>> >
>> > I believe this is a typo. The @unit-address suffix should match the
>> > value of reg property.
>>
>> No this is not typo. It is the MPIDR value of the cpu. (24 bits of
>> MPIDR register).
>
> Right. This is what the reg property should be set to. However, the @unit-
> address prefix of node name should match the value of reg property, so if
> the value of reg property is 0x100, then the node should be named cpu@100.
Ah ok,
Thanks. I will spin out a new version and send
>
> Best regards,
> Tomasz
>
--
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[PATCH v2 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Exynos5420 is octacore SoC from samsung.
Hence populate all the cpu node enteries.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e97c87b..0bd1a40 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -57,6 +57,34 @@
reg = <0x3>;
clock-frequency = <18>;
};
+
+ cpu4: cpu@0x100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <10>;
+ };
+
+ cpu5: cpu@0x101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <10>;
+ };
+
+ cpu6: cpu@0x102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <10>;
+ };
+
+ cpu7: cpu@0x103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <10>;
+ };
};
clock: clock-controller@0x1001 {
--
1.7.9.5
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[PATCH v2 0/2] Enable all cpus in Exynos5420
Exynos5420 is an octacore SoC. This patch series enables the remaining 4 cores. Changes in v2: - Changed the cpu node @unit-address value to reg property value. Chander Kashyap (2): clocksource: mct: extend mct to support 8 local interrupts for Exynos5420 arm: dt: Exynos5420: populate cpu node enteries to 8 cpus arch/arm/boot/dts/exynos5420.dtsi | 37 +++-- drivers/clocksource/exynos_mct.c |4 2 files changed, 39 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
Exynos5420 is octacore SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dt entries for 8 interrupts.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi |9 +++--
drivers/clocksource/exynos_mct.c |4
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ce2f94..e97c87b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -69,7 +69,8 @@
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
clocks = <&clock 1>, <&clock 315>;
clock-names = "fin_pll", "mct";
@@ -84,7 +85,11 @@
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
- <7 &gic 0 123 0>;
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
};
};
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index b2bbc41..ff4711e 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
+ MCT_L4_IRQ,
+ MCT_L5_IRQ,
+ MCT_L6_IRQ,
+ MCT_L7_IRQ,
MCT_NR_IRQS,
};
--
1.7.9.5
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Re: [PATCH v2 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Hi Chander,
On Thu, Sep 5, 2013 at 3:52 PM, Chander Kashyap
wrote:
> Exynos5420 is octacore SoC from samsung.
> Hence populate all the cpu node enteries.
>
> Signed-off-by: Chander Kashyap
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi
> index e97c87b..0bd1a40 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -57,6 +57,34 @@
> reg = <0x3>;
> clock-frequency = <18>;
> };
> +
> + cpu4: cpu@0x100 {
you are NOT suppose to use '0x' in dt node name.
it should be cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + clock-frequency = <10>;
> + };
> +
> + cpu5: cpu@0x101 {
ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + clock-frequency = <10>;
> + };
> +
> + cpu6: cpu@0x102 {
ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + clock-frequency = <10>;
> + };
> +
> + cpu7: cpu@0x103 {
ditto.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + clock-frequency = <10>;
> + };
> };
>
> clock: clock-controller@0x1001 {
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majord...@vger.kernel.org
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Re: [PATCH v2 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Hi Vikas,
On 5 September 2013 16:09, Vikas Sajjan wrote:
> Hi Chander,
>
> On Thu, Sep 5, 2013 at 3:52 PM, Chander Kashyap
> wrote:
>> Exynos5420 is octacore SoC from samsung.
>> Hence populate all the cpu node enteries.
>>
>> Signed-off-by: Chander Kashyap
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 28
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi
>> index e97c87b..0bd1a40 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -57,6 +57,34 @@
>> reg = <0x3>;
>> clock-frequency = <18>;
>> };
>> +
>> + cpu4: cpu@0x100 {
>
>
> you are NOT suppose to use '0x' in dt node name.
> it should be cpu4: cpu@100 {
Ok, I will fix it.
>
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x100>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu5: cpu@0x101 {
>
> ditto.
>
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x101>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu6: cpu@0x102 {
>
> ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x102>;
>> + clock-frequency = <10>;
>> + };
>> +
>> + cpu7: cpu@0x103 {
>
> ditto.
>
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a7";
>> + reg = <0x103>;
>> + clock-frequency = <10>;
>> + };
>> };
>>
>> clock: clock-controller@0x1001 {
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
>> in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
with warm regards,
Chander Kashyap
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[PATCH v3 0/2] Enable all cpus in Exynos5420
Exynos5420 is an octacore SoC. This patch series enables the remaining 4 cores. Changes in v2: - Changed the cpu node @unit-address value to reg property value. Changes in v3: - Removed leading 0x from @unit-address value. Chander Kashyap (2): clocksource: mct: extend mct to support 8 local interrupts for Exynos5420 arm: dt: Exynos5420: populate cpu node enteries to 8 cpus arch/arm/boot/dts/exynos5420.dtsi | 37 +++-- drivers/clocksource/exynos_mct.c |4 2 files changed, 39 insertions(+), 2 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
Exynos5420 is octacore SoC from samsung.
Hence populate all the cpu node enteries.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e97c87b..0bd1a40 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -57,6 +57,34 @@
reg = <0x3>;
clock-frequency = <18>;
};
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <10>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <10>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <10>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <10>;
+ };
};
clock: clock-controller@0x1001 {
--
1.7.9.5
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[PATCH v3 1/2] clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
Exynos5420 is octacore SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dt entries for 8 interrupts.
Signed-off-by: Chander Kashyap
---
arch/arm/boot/dts/exynos5420.dtsi |9 +++--
drivers/clocksource/exynos_mct.c |4
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 6ce2f94..e97c87b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -69,7 +69,8 @@
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>;
clocks = <&clock 1>, <&clock 315>;
clock-names = "fin_pll", "mct";
@@ -84,7 +85,11 @@
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
- <7 &gic 0 123 0>;
+ <7 &gic 0 123 0>,
+ <8 &gic 0 128 0>,
+ <9 &gic 0 129 0>,
+ <10 &gic 0 130 0>,
+ <11 &gic 0 131 0>;
};
};
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index b2bbc41..ff4711e 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
+ MCT_L4_IRQ,
+ MCT_L5_IRQ,
+ MCT_L6_IRQ,
+ MCT_L7_IRQ,
MCT_NR_IRQS,
};
--
1.7.9.5
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[PATCH 08/12] ARM: dts: exynos5420: convert magic numbers to macros in clock bindings
The patch replaces magic numbers with macros defined in DT header in exynos5420 clock bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 + arch/arm/boot/dts/exynos5420.dtsi | 13 +- 2 files changed, 13 insertions(+), 184 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 32aa34e..785162a 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -13,184 +13,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. - - [Core Clocks] - - ClockID - - - fin_pll 1 - - [Clock Gate for Special Clocks] - - ClockID - - sclk_uart0 128 - sclk_uart1 129 - sclk_uart2 130 - sclk_uart3 131 - sclk_mmc0132 - sclk_mmc1133 - sclk_mmc2134 - sclk_spi0135 - sclk_spi1136 - sclk_spi2137 - sclk_i2s1138 - sclk_i2s2139 - sclk_pcm1140 - sclk_pcm2141 - sclk_spdif 142 - sclk_hdmi143 - sclk_pixel 144 - sclk_dp1 145 - sclk_mipi1 146 - sclk_fimd1 147 - sclk_maudio0 148 - sclk_maupcm0 149 - sclk_usbd300 150 - sclk_usbd301 151 - sclk_usbphy300 152 - sclk_usbphy301 153 - sclk_unipro 154 - sclk_pwm 155 - sclk_gscl_wa 156 - sclk_gscl_wb 157 - sclk_hdmiphy 158 - - [Peripheral Clock Gates] - - ClockID - - - aclk66_peric 256 - uart0257 - uart1258 - uart2259 - uart3260 - i2c0 261 - i2c1 262 - i2c2 263 - i2c3 264 - i2c4 265 - i2c5 266 - i2c6 267 - i2c7 268 - i2c_hdmi 269 - tsadc270 - spi0 271 - spi1 272 - spi2 273 - keyif274 - i2s1 275 - i2s2 276 - pcm1 277 - pcm2 278 - pwm 279 - spdif280 - i2c8 281 - i2c9 282 - i2c10283 - aclk66_psgen 300 - chipid 301 - sysreg 302 - tzpc0303 - tzpc1304 - tzpc2305 - tzpc3306 - tzpc4307 - tzpc5308 - tzpc6309 - tzpc7310 - tzpc8311 - tzpc9312 - hdmi_cec 313 - seckey 314 - mct 315 - wdt 316 - rtc 317 - tmu 318 - tmu_gpu 319 - pclk66_gpio 330 - aclk200_fsys2350 - mmc0 351 - mmc1 352 - mmc2 353 - sromc354 - ufs 355 - aclk200_fsys 360 - tsi 361 - pdma0362 - pdma1363 - rtic 364 - usbh20 365 - usbd300 366 - usbd301 377 - aclk400_mscl 380 - mscl0381 - mscl1382 - mscl2383 - smmu_mscl0 384 - smmu_mscl1 385 - smmu_mscl2 386 - aclk333 400 - mfc 401 - smmu_mfcl402 - smmu_mfcr403 - aclk200_disp1410 - dsim1411 - dp1 412 - hdmi 413 - aclk300_disp1420 - fimd1421 - smmu_fimd1 422 - aclk166 430 - mixer431 - aclk266 440 - rotator 441 - mdma1442 - smmu_rotator 443 - smmu_mdma1 444 - aclk300_jpeg 450 - jpeg
[PATCH 12/12] clk: exynos5440: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos5440.c | 81 +++-
1 file changed, 34 insertions(+), 47 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5440.c
b/drivers/clk/samsung/clk-exynos5440.c
index 4ef38e0..7a08b2d 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -9,6 +9,7 @@
* Common Clock Framework support for Exynos5440 SoC.
*/
+#include
#include
#include
#include
@@ -22,79 +23,65 @@
#define CPU_CLK_STATUS 0xfc
#define MISC_DOUT1 0x558
-/*
- * Let each supported clock get a unique id. This id is used to lookup the
clock
- * for device tree based platforms.
- */
-enum exynos5440_clks {
- none, xtal, arm_clk,
-
- spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
- usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
- b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
-
- nr_clks,
-};
-
/* parent clock name list */
PNAME(mout_armclk_p) = { "cplla", "cpllb" };
PNAME(mout_spi_p) = { "div125", "div200" };
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[]
__initdata = {
- FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
+ FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks */
static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata
= {
- FRATE(none, "ppll", NULL, CLK_IS_ROOT, 10),
- FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 6000),
- FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 6000),
- FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 1200),
- FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 4800),
+ FRATE(0, "ppll", NULL, CLK_IS_ROOT, 10),
+ FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 6000),
+ FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 6000),
+ FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 1200),
+ FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 4800),
};
/* fixed factor clocks */
static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[]
__initdata = {
- FFACTOR(none, "div250", "ppll", 1, 4, 0),
- FFACTOR(none, "div200", "ppll", 1, 5, 0),
- FFACTOR(none, "div125", "div250", 1, 2, 0),
+ FFACTOR(0, "div250", "ppll", 1, 4, 0),
+ FFACTOR(0, "div200", "ppll", 1, 5, 0),
+ FFACTOR(0, "div125", "div250", 1, 2, 0),
};
/* mux clocks */
static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
- MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
- MUX_A(arm_clk, "arm_clk", mout_armclk_p,
+ MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
+ MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
CPU_CLK_STATUS, 0, 1, "armclk"),
};
/* divider clocks */
static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
- DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
+ DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
};
/* gate clocks */
static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
- GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
- GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
- GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
- GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
- GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
- GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
- GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
- GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
- GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
- GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
- GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
- GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
- GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
- GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
- GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
- GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
- GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
- GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
- GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
- GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
+ GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
+ GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
+ GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
+ GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
+ GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0,
[PATCH 06/12] clk: exynos5250: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos5250.c | 501 ---
1 file changed, 229 insertions(+), 272 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index d90e593..61de289 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -10,6 +10,7 @@
* Common Clock Framework support for Exynos5250 SoC.
*/
+#include
#include
#include
#include
@@ -84,51 +85,6 @@ enum exynos5250_plls {
};
/*
- * Let each supported clock get a unique id. This id is used to lookup the
clock
- * for device tree based platforms. The clocks are categorized into three
- * sections: core, sclk gate and bus interface gate clocks.
- *
- * When adding a new clock to this list, it is advised to choose a clock
- * category and add it to the end of that category. That is because the the
- * device tree source file is referring to these ids and any change in the
- * sequence number of existing clocks will require corresponding change in the
- * device tree files. This limitation would go away when pre-processor support
- * for dtc would be available.
- */
-enum exynos5250_clks {
- none,
-
- /* core clocks */
- fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
- fout_epll, fout_vpll,
-
- /* gate for special clocks (sclk) */
- sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
- sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
- sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
- sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
- sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
- div_i2s1, div_i2s2, sclk_hdmiphy,
-
- /* gate clocks */
- gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
- smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
- jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
- usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
- sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
- i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
- spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
- hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
- tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
- wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
-
- /* mux clocks */
- mout_hdmi = 1024,
-
- nr_clks,
-};
-
-/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
@@ -217,281 +173,282 @@ PNAME(mout_spdif_p) = { "sclk_audio0",
"sclk_audio1", "sclk_audio2",
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[]
__initdata = {
- FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+ FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata
= {
- FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2400),
- FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 2700),
- FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 2400),
- FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 4800),
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2400),
+ FRATE(0, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 2700),
+ FRATE(0, "sclk_dptxphy", NULL, CLK_IS_ROOT, 2400),
+ FRATE(0, "sclk_uhostphy", NULL, CLK_IS_ROOT, 4800),
};
static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[]
__initdata = {
- FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
- FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
+ FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
+ FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
};
static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
- MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+ MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
};
static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
- MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
- MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
- MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
- MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
- MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
- MUX(none, "scl
[PATCH 01/12] ARM: exynos4: create a DT header defining CLK IDs
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- include/dt-bindings/clock/exynos4.h | 231 1 file changed, 231 insertions(+) create mode 100644 include/dt-bindings/clock/exynos4.h diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h new file mode 100644 index 000..deb5428 --- /dev/null +++ b/include/dt-bindings/clock/exynos4.h @@ -0,0 +1,231 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H +#define _DT_BINDINGS_CLOCK_EXYNOS_4_H + +/* core clocks */ +#define CLK_XXTI 1 +#define CLK_XUSBXTI 2 +#define CLK_FIN_PLL 3 +#define CLK_FOUT_APLL 4 +#define CLK_FOUT_MPLL 5 +#define CLK_FOUT_EPLL 6 +#define CLK_FOUT_VPLL 7 +#define CLK_SCLK_APLL 8 +#define CLK_SCLK_MPLL 9 +#define CLK_SCLK_EPLL 10 +#define CLK_SCLK_VPLL 11 +#define CLK_ARM_CLK 12 +#define CLK_ACLK200 13 +#define CLK_ACLK100 14 +#define CLK_ACLK160 15 +#define CLK_ACLK133 16 +#define CLK_MOUT_MPLL_USER_T 17 +#define CLK_MOUT_MPLL_USER_C 18 +#define CLK_MOUT_CORE 19 +#define CLK_MOUT_APLL 20 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_FIMC0 128 +#define CLK_SCLK_FIMC1 129 +#define CLK_SCLK_FIMC2 130 +#define CLK_SCLK_FIMC3 131 +#define CLK_SCLK_CAM0 132 +#define CLK_SCLK_CAM1 133 +#define CLK_SCLK_CSIS0 134 +#define CLK_SCLK_CSIS1 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_MIXER 137 +#define CLK_SCLK_DAC 138 +#define CLK_SCLK_PIXEL 139 +#define CLK_SCLK_FIMD0 140 +#define CLK_SCLK_MDNIE0 141 +#define CLK_SCLK_MDNIE_PWM0 142 +#define CLK_SCLK_MIPI0 143 +#define CLK_SCLK_AUDIO0 144 +#define CLK_SCLK_MMC0 145 +#define CLK_SCLK_MMC1 146 +#define CLK_SCLK_MMC2 147 +#define CLK_SCLK_MMC3 148 +#define CLK_SCLK_MMC4 149 +#define CLK_SCLK_SATA 150 +#define CLK_SCLK_UART0 151 +#define CLK_SCLK_UART1 152 +#define CLK_SCLK_UART2 153 +#define CLK_SCLK_UART3 154 +#define CLK_SCLK_UART4 155 +#define CLK_SCLK_AUDIO1 156 +#define CLK_SCLK_AUDIO2 157 +#define CLK_SCLK_SPDIF 158 +#define CLK_SCLK_SPI0 159 +#define CLK_SCLK_SPI1 160 +#define CLK_SCLK_SPI2 161 +#define CLK_SCLK_SLIMBUS 162 +#define CLK_SCLK_FIMD1 163 +#define CLK_SCLK_MIPI1 164 +#define CLK_SCLK_PCM1 165 +#define CLK_SCLK_PCM2 166 +#define CLK_SCLK_I2S1 167 +#define CLK_SCLK_I2S2 168 +#define CLK_SCLK_MIPIHSI 169 +#define CLK_SCLK_MFC 170 +#define CLK_SCLK_PCM0 171 +#define CLK_SCLK_G3D 172 +#define CLK_SCLK_PWM_ISP 173 +#define CLK_SCLK_SPI0_ISP 174 +#define CLK_SCLK_SPI1_ISP 175 +#define CLK_SCLK_UART_ISP 176 +#define CLK_SCLK_FIMG2D 177 + +/* gate clocks */ +#define CLK_FIMC0 256 +#define CLK_FIMC1 257 +#define CLK_FIMC2 258 +#define CLK_FIMC3 259 +#define CLK_CSIS0 260 +#define CLK_CSIS1 261 +#define CLK_JPEG 262 +#define CLK_SMMU_FIMC0 263 +#define CLK_SMMU_FIMC1 264 +#define CLK_SMMU_FIMC2 265 +#define CLK_SMMU_FIMC3 266 +#define CLK_SMMU_JPEG 267 +#define CLK_VP 268 +#define CLK_MIXER 269 +#define CLK_TVENC 270 +#define CLK_HDMI 271 +#define CLK_SMMU_TV 272 +#define CLK_MFC 273 +#define CLK_SMMU_MFCL 274 +#define CLK_SMMU_MFCR 275 +#define CLK_G3D 276 +#define CLK_G2D 277 +#define CLK_ROTATOR 278 +#define CLK_MDMA 279 +#define CLK_SMMU_G2D 280 +#define CLK_SMMU_ROTATOR 281 +#define CLK_SMMU_MDMA 282 +#define CLK_FIMD0 283 +#define CLK_MIE0 284 +#define CLK_MDNIE0 285 +#define CLK_DSIM0 286 +#define CLK_SMMU_FIMD0 287 +#define CLK_FIMD1 288 +#define CLK_MIE1 289 +#define CLK_DSIM1 290 +#define CLK_SMMU_FIMD1 291 +#define CLK_PDMA0 292 +#define CLK_PDMA1 293 +#define CLK_PCIE_PHY 294 +#define CLK_SATA_PHY 295 +#define CLK_TSI 296 +#define CLK_SDMMC0 297 +#define CLK_SDMMC1 298 +#define CLK_SDMMC2 299 +#define CLK_SDMMC3 300 +#define CLK_SDMMC4 301 +#define CLK_SATA 302 +#define CLK_SROMC 303 +#define CLK_USB_HOST 304 +#define CLK_USB_DEVICE 305 +#define CLK_PCIE 306 +#define CLK_ONENAND 307 +#define CLK_NFCON 308 +#define CLK_SMMU_PCIE 309 +#define CLK_GPS 310 +#define CLK_SMMU_GPS 311 +#define CLK_UART0 312 +#define CLK_UART1 313 +#define CLK_UART2 314 +#define CLK_UART3 315 +#define CLK_UART4 316 +#define CLK_I2C0 317 +#define CLK_I2C1 318 +#define CLK_I2C2 319 +#define CLK_I2C3 320 +#define CLK_I2C4 321 +#define CLK_I2C5 322 +#define CLK_I2C6 323 +#define CLK_I2C7 324 +#define CLK_I2C_HDMI 325 +#define CLK_TSADC 326 +#define CLK_SPI0 327 +#define CLK_SPI1 328 +#define CLK_SPI2 329 +#define CLK_I2S1 330 +#define CLK_I2S2 331 +#define CLK_PCM0 332 +#define CLK_I2S0 333 +#define CLK_PCM1 334 +#define CLK_PCM2 335 +#define CLK_PWM 336 +#define CLK_SLIMBUS 337 +#define CLK_SPDIF 338 +#define CLK_AC97 339 +#define CLK_MODEMIF 340 +#define CLK_CHIPID 341 +#define CLK_SYSREG 342 +#define CLK_HDMI_CEC 343 +#define CLK_MCT 344 +#define CLK_WDT 345 +#define CLK_RTC 346 +#define CLK_KEYIF 347 +#define CLK_AUDSS 348 +#define CLK_MIPI_HSI 349 +#define CLK_MDMA2 350 +#define CLK_PIXELASYNCM0 351 +#define CLK_PIXELASYNCM1 352 +#define CLK_FIMC_LITE0 353 +#define CLK_FIMC_LITE1 354 +#define CLK_PP
[PATCH 09/12] clk: exynos5420: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda
Signed-off-by: Kyungmin Park
---
drivers/clk/samsung/clk-exynos5420.c | 648 +--
1 file changed, 309 insertions(+), 339 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 48c4a93..ab223f0 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -10,6 +10,7 @@
* Common Clock Framework support for Exynos5420 SoC.
*/
+#include
#include
#include
#include
@@ -107,48 +108,6 @@ enum exynos5420_plls {
nr_plls /* number of PLLs */
};
-enum exynos5420_clks {
- none,
-
- /* core clocks */
- fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
- fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
-
- /* gate for special clocks (sclk) */
- sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
- sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1,
- sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
- sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
- sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
- sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
-
- /* gate clocks */
- aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
- i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1,
- i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300,
- chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7,
- tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu,
- pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs,
- aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301,
- aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1,
- smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr,
- aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1,
- smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1,
- smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg,
- aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
- gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
- aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
- smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer,
-
- /* mux clocks */
- mout_hdmi = 640,
-
- /* divider clocks */
- dout_pixel = 768,
-
- nr_clks,
-};
-
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
@@ -298,225 +257,226 @@ PNAME(maudio0_p)= { "fin_pll", "maudio_clk",
"sclk_dpll", "sclk_mpll",
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[]
__initdata = {
- FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+ FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
};
/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata
= {
- FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2400),
- FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 2400),
- FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 4800),
- FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 4800),
- FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 48000),
+ FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2400),
+ FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 2400),
+ FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 4800),
+ FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 4800),
+ FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 48000),
};
static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[]
__initdata = {
- FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
+ FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
};
static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
- MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
- MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
- MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
- MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
- MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
+ MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
+ MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
+ MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
+ MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
+ MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0,
[PATCH 10/12] ARM: exynos5440: create a DT header defining CLK IDs
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- include/dt-bindings/clock/exynos5440.h | 29 + 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5440.h diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h new file mode 100644 index 000..68a472d --- /dev/null +++ b/include/dt-bindings/clock/exynos5440.h @@ -0,0 +1,29 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H + +#define CLK_XTAL 1 +#define CLK_ARM_CLK 2 +#define CLK_SPI_BAUD 16 +#define CLK_PB0_250 17 +#define CLK_PR0_250 18 +#define CLK_PR1_250 19 +#define CLK_B_250 20 +#define CLK_B_125 21 +#define CLK_B_200 22 +#define CLK_SATA 23 +#define CLK_USB 24 +#define CLK_GMAC0 25 +#define CLK_CS250 26 +#define CLK_PB0_250_O 27 +#define CLK_PR0_250_O 28 +#define CLK_PR1_250_O 29 +#define CLK_B_250_O 30 +#define CLK_B_125_O 31 +#define CLK_B_200_O 32 +#define CLK_SATA_O 33 +#define CLK_USB_O 34 +#define CLK_GMAC0_O 35 +#define CLK_CS250_O 36 +#define CLK_NR_CLKS 37 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ -- 1.8.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 00/12] clk/exynos convert clock IDs to macros
Hi, This patch set adds headers with defines of exynos clocks. Then it converts dts files and drivers to use macros instead of magic numbers/enums to describe clock bindings. The patchset is based on the latest mturquette/clk-next branch. The patches are generated by script. I have verified random clocks by hand. I have also tested it on exynos4 based board. Btw I have spotted and 'error' in bindings/clock/exynos5250-clock.txt. Example is syntactically correct, but it contains obviously incorect clock bindings. Separate patch can be created to 'fix' it if needed. Regards Andrzej Andrzej Hajda (12): ARM: exynos4: create a DT header defining CLK IDs ARM: dts: exynos4: convert magic numbers to macros in clock bindings clk: exynos4: replace clock ID private enums with IDs from DT header ARM: exynos5250: create a DT header defining CLK IDs ARM: dts: exynos5250: convert magic numbers to macros in clock bindings clk: exynos5250: replace clock ID private enums with IDs from DT header ARM: exynos5420: create a DT header defining CLK IDs ARM: dts: exynos5420: convert magic numbers to macros in clock bindings clk: exynos5420: replace clock ID private enums with IDs from DT header ARM: exynos5440: create a DT header defining CLK IDs ARM: dts: exynos5440: convert magic numbers to macros in clock bindings clk: exynos5440: replace clock ID private enums with IDs from DT header .../devicetree/bindings/clock/exynos4-clock.txt| 259 +-- .../devicetree/bindings/clock/exynos5250-clock.txt | 160 +--- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 + .../devicetree/bindings/clock/exynos5440-clock.txt | 45 +- arch/arm/boot/dts/exynos4.dtsi | 55 +- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 91 +-- arch/arm/boot/dts/exynos5420.dtsi | 13 +- arch/arm/boot/dts/exynos5440.dtsi | 27 +- drivers/clk/samsung/clk-exynos4.c | 857 ++--- drivers/clk/samsung/clk-exynos5250.c | 501 ++-- drivers/clk/samsung/clk-exynos5420.c | 648 drivers/clk/samsung/clk-exynos5440.c | 81 +- include/dt-bindings/clock/exynos4.h| 231 ++ include/dt-bindings/clock/exynos5250.h | 144 include/dt-bindings/clock/exynos5420.h | 175 + include/dt-bindings/clock/exynos5440.h | 29 + 19 files changed, 1681 insertions(+), 1829 deletions(-) create mode 100644 include/dt-bindings/clock/exynos4.h create mode 100644 include/dt-bindings/clock/exynos5250.h create mode 100644 include/dt-bindings/clock/exynos5420.h create mode 100644 include/dt-bindings/clock/exynos5440.h -- 1.8.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/12] ARM: exynos5420: create a DT header defining CLK IDs
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- include/dt-bindings/clock/exynos5420.h | 175 + 1 file changed, 175 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5420.h diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h new file mode 100644 index 000..01e4409 --- /dev/null +++ b/include/dt-bindings/clock/exynos5420.h @@ -0,0 +1,175 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_CPLL 3 +#define CLK_FOUT_DPLL 4 +#define CLK_FOUT_EPLL 5 +#define CLK_FOUT_RPLL 6 +#define CLK_FOUT_IPLL 7 +#define CLK_FOUT_SPLL 8 +#define CLK_FOUT_VPLL 9 +#define CLK_FOUT_MPLL 10 +#define CLK_FOUT_BPLL 11 +#define CLK_FOUT_KPLL 12 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_UART0 128 +#define CLK_SCLK_UART1 129 +#define CLK_SCLK_UART2 130 +#define CLK_SCLK_UART3 131 +#define CLK_SCLK_MMC0 132 +#define CLK_SCLK_MMC1 133 +#define CLK_SCLK_MMC2 134 +#define CLK_SCLK_SPI0 135 +#define CLK_SCLK_SPI1 136 +#define CLK_SCLK_SPI2 137 +#define CLK_SCLK_I2S1 138 +#define CLK_SCLK_I2S2 139 +#define CLK_SCLK_PCM1 140 +#define CLK_SCLK_PCM2 141 +#define CLK_SCLK_SPDIF 142 +#define CLK_SCLK_HDMI 143 +#define CLK_SCLK_PIXEL 144 +#define CLK_SCLK_DP1 145 +#define CLK_SCLK_MIPI1 146 +#define CLK_SCLK_FIMD1 147 +#define CLK_SCLK_MAUDIO0 148 +#define CLK_SCLK_MAUPCM0 149 +#define CLK_SCLK_USBD300 150 +#define CLK_SCLK_USBD301 151 +#define CLK_SCLK_USBPHY300 152 +#define CLK_SCLK_USBPHY301 153 +#define CLK_SCLK_UNIPRO 154 +#define CLK_SCLK_PWM 155 +#define CLK_SCLK_GSCL_WA 156 +#define CLK_SCLK_GSCL_WB 157 +#define CLK_SCLK_HDMIPHY 158 + +/* gate clocks */ +#define CLK_ACLK66_PERIC 256 +#define CLK_UART0 257 +#define CLK_UART1 258 +#define CLK_UART2 259 +#define CLK_UART3 260 +#define CLK_I2C0 261 +#define CLK_I2C1 262 +#define CLK_I2C2 263 +#define CLK_I2C3 264 +#define CLK_I2C4 265 +#define CLK_I2C5 266 +#define CLK_I2C6 267 +#define CLK_I2C7 268 +#define CLK_I2C_HDMI 269 +#define CLK_TSADC 270 +#define CLK_SPI0 271 +#define CLK_SPI1 272 +#define CLK_SPI2 273 +#define CLK_KEYIF 274 +#define CLK_I2S1 275 +#define CLK_I2S2 276 +#define CLK_PCM1 277 +#define CLK_PCM2 278 +#define CLK_PWM 279 +#define CLK_SPDIF 280 +#define CLK_I2C8 281 +#define CLK_I2C9 282 +#define CLK_I2C10 283 +#define CLK_ACLK66_PSGEN 300 +#define CLK_CHIPID 301 +#define CLK_SYSREG 302 +#define CLK_TZPC0 303 +#define CLK_TZPC1 304 +#define CLK_TZPC2 305 +#define CLK_TZPC3 306 +#define CLK_TZPC4 307 +#define CLK_TZPC5 308 +#define CLK_TZPC6 309 +#define CLK_TZPC7 310 +#define CLK_TZPC8 311 +#define CLK_TZPC9 312 +#define CLK_HDMI_CEC 313 +#define CLK_SECKEY 314 +#define CLK_MCT 315 +#define CLK_WDT 316 +#define CLK_RTC 317 +#define CLK_TMU 318 +#define CLK_TMU_GPU 319 +#define CLK_PCLK66_GPIO 330 +#define CLK_ACLK200_FSYS2 350 +#define CLK_MMC0 351 +#define CLK_MMC1 352 +#define CLK_MMC2 353 +#define CLK_SROMC 354 +#define CLK_UFS 355 +#define CLK_ACLK200_FSYS 360 +#define CLK_TSI 361 +#define CLK_PDMA0 362 +#define CLK_PDMA1 363 +#define CLK_RTIC 364 +#define CLK_USBH20 365 +#define CLK_USBD300 366 +#define CLK_USBD301 367 +#define CLK_ACLK400_MSCL 380 +#define CLK_MSCL0 381 +#define CLK_MSCL1 382 +#define CLK_MSCL2 383 +#define CLK_SMMU_MSCL0 384 +#define CLK_SMMU_MSCL1 385 +#define CLK_SMMU_MSCL2 386 +#define CLK_ACLK333 400 +#define CLK_MFC 401 +#define CLK_SMMU_MFCL 402 +#define CLK_SMMU_MFCR 403 +#define CLK_ACLK200_DISP1 410 +#define CLK_DSIM1 411 +#define CLK_DP1 412 +#define CLK_HDMI 413 +#define CLK_ACLK300_DISP1 420 +#define CLK_FIMD1 421 +#define CLK_SMMU_FIMD1 422 +#define CLK_ACLK166 430 +#define CLK_MIXER 431 +#define CLK_ACLK266 440 +#define CLK_ROTATOR 441 +#define CLK_MDMA1 442 +#define CLK_SMMU_ROTATOR 443 +#define CLK_SMMU_MDMA1 444 +#define CLK_ACLK300_JPEG 450 +#define CLK_JPEG 451 +#define CLK_JPEG2 452 +#define CLK_SMMU_JPEG 453 +#define CLK_ACLK300_GSCL 460 +#define CLK_SMMU_GSCL0 461 +#define CLK_SMMU_GSCL1 462 +#define CLK_GSCL_WA 463 +#define CLK_GSCL_WB 464 +#define CLK_GSCL0 465 +#define CLK_GSCL1 466 +#define CLK_CLK_3AA 467 +#define CLK_ACLK266_G2D 470 +#define CLK_SSS 471 +#define CLK_SLIM_SSS 472 +#define CLK_MDMA0 473 +#define CLK_ACLK333_G2D 480 +#define CLK_G2D 481 +#define CLK_ACLK333_432_GSCL 490 +#define CLK_SMMU_3AA 491 +#define CLK_SMMU_FIMCL0 492 +#define CLK_SMMU_FIMCL1 493 +#define CLK_SMMU_FIMCL3 494 +#define CLK_FIMC_LITE3 495 +#define CLK_ACLK_G3D 500 +#define CLK_G3D 501 +#define CLK_SMMU_MIXER 502 + +/* mux clocks */ +#define CLK_MOUT_HDMI 640 + +/* divider clocks */ +#define CLK_DOUT_PIXEL 768 +#define CLK_NR_CLKS 769 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ -- 1.8.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the
[PATCH 02/12] ARM: dts: exynos4: convert magic numbers to macros in clock bindings
The patch replaces magic numbers with macros defined in DT header in exynos4 clock bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- .../devicetree/bindings/clock/exynos4-clock.txt| 259 + arch/arm/boot/dts/exynos4.dtsi | 55 ++--- arch/arm/boot/dts/exynos4210.dtsi | 6 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12.dtsi | 2 +- 5 files changed, 39 insertions(+), 285 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index c6bf8a6..e30c31e 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,259 +15,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. Some of the clocks are available only on a particular -Exynos4 SoC and this is specified where applicable. - - -[Core Clocks] - - Clock ID SoC (if specific) - --- - - xxti1 - xusbxti 2 - fin_pll 3 - fout_apll 4 - fout_mpll 5 - fout_epll 6 - fout_vpll 7 - sclk_apll 8 - sclk_mpll 9 - sclk_epll 10 - sclk_vpll 11 - arm_clk 12 - aclk200 13 - aclk100 14 - aclk160 15 - aclk133 16 - mout_mpll_user_t17 Exynos4x12 - mout_mpll_user_c18 Exynos4x12 - mout_core 19 - mout_apll 20 - - -[Clock Gate for Special Clocks] - - Clock ID SoC (if specific) - --- - - sclk_fimc0 128 - sclk_fimc1 129 - sclk_fimc2 130 - sclk_fimc3 131 - sclk_cam0 132 - sclk_cam1 133 - sclk_csis0 134 - sclk_csis1 135 - sclk_hdmi 136 - sclk_mixer 137 - sclk_dac138 - sclk_pixel 139 - sclk_fimd0 140 - sclk_mdnie0 141 Exynos4412 - sclk_mdnie_pwm0 12 142 Exynos4412 - sclk_mipi0 143 - sclk_audio0 144 - sclk_mmc0 145 - sclk_mmc1 146 - sclk_mmc2 147 - sclk_mmc3 148 - sclk_mmc4 149 - sclk_sata 150 Exynos4210 - sclk_uart0 151 - sclk_uart1 152 - sclk_uart2 153 - sclk_uart3 154 - sclk_uart4 155 - sclk_audio1 156 - sclk_audio2 157 - sclk_spdif 158 - sclk_spi0 159 - sclk_spi1 160 - sclk_spi2 161 - sclk_slimbus162 - sclk_fimd1 163 Exynos4210 - sclk_mipi1 164 Exynos4210 - sclk_pcm1 165 - sclk_pcm2 166 - sclk_i2s1 167 - sclk_i2s2 168 - sclk_mipihsi169 Exynos4412 - sclk_mfc170 - sclk_pcm0 171 - sclk_g3d172 - sclk_pwm_isp173 Exynos4x12 - sclk_spi0_isp 174 Exynos4x12 - sclk_spi1_isp 175 Exynos4x12 - sclk_uart_isp 176 Exynos4x12 - sclk_fimg2d 177 - - [Peripheral Clock Gates] - - Clock ID SoC (if specific) - --- - - fimc0 256 - fimc1 257 - fimc2 258 - fimc3 259 - csis0 260 - csis1 261 - jpeg262 - smmu_fimc0 263 - smmu_fimc1 264 - smmu_fimc2 265 - smmu_fimc3 266 - smmu_jpeg 267 - vp 268 - mixer 269 - tvenc 270 Exynos4210 - hdmi271 - smmu_tv 272 - mfc 273 - smmu_mfcl 274 - smmu_mfcr 275 - g3d 276 - g2d 277 - rotator 278 Exynos4210 - mdma279 Exynos4210 - smmu_g2d280 Exynos4210 - smmu_rotator281 Exynos4210 - smmu_mdma 282 Exynos4210 - fimd0 283 - mie0284 - mdnie0 285 Exynos4412 - dsim0 286 - smmu_fimd0 287 - fimd1 288 Exynos4210 - mie1289 Exynos4210 - dsim1 290 Exynos4210 - smmu_fimd1 291 Exynos4210 - pdma0 292 - pdma1 293 - pcie_phy294 - sata_phy295 Exynos4210 - tsi 296 - sdmmc0 297 - sdmmc1
[PATCH 04/12] ARM: exynos5250: create a DT header defining CLK IDs
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- include/dt-bindings/clock/exynos5250.h | 144 + 1 file changed, 144 insertions(+) create mode 100644 include/dt-bindings/clock/exynos5250.h diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h new file mode 100644 index 000..f23aa75 --- /dev/null +++ b/include/dt-bindings/clock/exynos5250.h @@ -0,0 +1,144 @@ +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H +#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H + +/* core clocks */ +#define CLK_FIN_PLL 1 +#define CLK_FOUT_APLL 2 +#define CLK_FOUT_MPLL 3 +#define CLK_FOUT_BPLL 4 +#define CLK_FOUT_GPLL 5 +#define CLK_FOUT_CPLL 6 +#define CLK_FOUT_EPLL 7 +#define CLK_FOUT_VPLL 8 + +/* gate for special clocks (sclk) */ +#define CLK_SCLK_CAM_BAYER 128 +#define CLK_SCLK_CAM0 129 +#define CLK_SCLK_CAM1 130 +#define CLK_SCLK_GSCL_WA 131 +#define CLK_SCLK_GSCL_WB 132 +#define CLK_SCLK_FIMD1 133 +#define CLK_SCLK_MIPI1 134 +#define CLK_SCLK_DP 135 +#define CLK_SCLK_HDMI 136 +#define CLK_SCLK_PIXEL 137 +#define CLK_SCLK_AUDIO0 138 +#define CLK_SCLK_MMC0 139 +#define CLK_SCLK_MMC1 140 +#define CLK_SCLK_MMC2 141 +#define CLK_SCLK_MMC3 142 +#define CLK_SCLK_SATA 143 +#define CLK_SCLK_USB3 144 +#define CLK_SCLK_JPEG 145 +#define CLK_SCLK_UART0 146 +#define CLK_SCLK_UART1 147 +#define CLK_SCLK_UART2 148 +#define CLK_SCLK_UART3 149 +#define CLK_SCLK_PWM 150 +#define CLK_SCLK_AUDIO1 151 +#define CLK_SCLK_AUDIO2 152 +#define CLK_SCLK_SPDIF 153 +#define CLK_SCLK_SPI0 154 +#define CLK_SCLK_SPI1 155 +#define CLK_SCLK_SPI2 156 +#define CLK_DIV_I2S1 157 +#define CLK_DIV_I2S2 158 +#define CLK_SCLK_HDMIPHY 159 + +/* gate clocks */ +#define CLK_GSCL0 256 +#define CLK_GSCL1 257 +#define CLK_GSCL2 258 +#define CLK_GSCL3 259 +#define CLK_GSCL_WA 260 +#define CLK_GSCL_WB 261 +#define CLK_SMMU_GSCL0 262 +#define CLK_SMMU_GSCL1 263 +#define CLK_SMMU_GSCL2 264 +#define CLK_SMMU_GSCL3 265 +#define CLK_MFC 266 +#define CLK_SMMU_MFCL 267 +#define CLK_SMMU_MFCR 268 +#define CLK_ROTATOR 269 +#define CLK_JPEG 270 +#define CLK_MDMA1 271 +#define CLK_SMMU_ROTATOR 272 +#define CLK_SMMU_JPEG 273 +#define CLK_SMMU_MDMA1 274 +#define CLK_PDMA0 275 +#define CLK_PDMA1 276 +#define CLK_SATA 277 +#define CLK_USBOTG 278 +#define CLK_MIPI_HSI 279 +#define CLK_SDMMC0 280 +#define CLK_SDMMC1 281 +#define CLK_SDMMC2 282 +#define CLK_SDMMC3 283 +#define CLK_SROMC 284 +#define CLK_USB2 285 +#define CLK_USB3 286 +#define CLK_SATA_PHYCTRL 287 +#define CLK_SATA_PHYI2C 288 +#define CLK_UART0 289 +#define CLK_UART1 290 +#define CLK_UART2 291 +#define CLK_UART3 292 +#define CLK_UART4 293 +#define CLK_I2C0 294 +#define CLK_I2C1 295 +#define CLK_I2C2 296 +#define CLK_I2C3 297 +#define CLK_I2C4 298 +#define CLK_I2C5 299 +#define CLK_I2C6 300 +#define CLK_I2C7 301 +#define CLK_I2C_HDMI 302 +#define CLK_ADC 303 +#define CLK_SPI0 304 +#define CLK_SPI1 305 +#define CLK_SPI2 306 +#define CLK_I2S1 307 +#define CLK_I2S2 308 +#define CLK_PCM1 309 +#define CLK_PCM2 310 +#define CLK_PWM 311 +#define CLK_SPDIF 312 +#define CLK_AC97 313 +#define CLK_HSI2C0 314 +#define CLK_HSI2C1 315 +#define CLK_HSI2C2 316 +#define CLK_HSI2C3 317 +#define CLK_CHIPID 318 +#define CLK_SYSREG 319 +#define CLK_PMU 320 +#define CLK_CMU_TOP 321 +#define CLK_CMU_CORE 322 +#define CLK_CMU_MEM 323 +#define CLK_TZPC0 324 +#define CLK_TZPC1 325 +#define CLK_TZPC2 326 +#define CLK_TZPC3 327 +#define CLK_TZPC4 328 +#define CLK_TZPC5 329 +#define CLK_TZPC6 330 +#define CLK_TZPC7 331 +#define CLK_TZPC8 332 +#define CLK_TZPC9 333 +#define CLK_HDMI_CEC 334 +#define CLK_MCT 335 +#define CLK_WDT 336 +#define CLK_RTC 337 +#define CLK_TMU 338 +#define CLK_FIMD1 339 +#define CLK_MIE1 340 +#define CLK_DSIM0 341 +#define CLK_DP 342 +#define CLK_MIXER 343 +#define CLK_HDMI 344 +#define CLK_G2D 345 + +/* mux clocks */ +#define CLK_MOUT_HDMI 1024 +#define CLK_NR_CLKS 1025 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ -- 1.8.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/12] ARM: dts: exynos5250: convert magic numbers to macros in clock bindings
The patch replaces magic numbers with macros defined in DT header in exynos5250 clock bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- .../devicetree/bindings/clock/exynos5250-clock.txt | 160 + arch/arm/boot/dts/exynos5250.dtsi | 91 ++-- 2 files changed, 52 insertions(+), 199 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 24765c1..8e21c7f 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,160 +13,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. - - - [Core Clocks] - - ClockID - - - fin_pll 1 - - [Clock Gate for Special Clocks] - - ClockID - - - sclk_cam_bayer 128 - sclk_cam0129 - sclk_cam1130 - sclk_gscl_wa 131 - sclk_gscl_wb 132 - sclk_fimd1 133 - sclk_mipi1 134 - sclk_dp 135 - sclk_hdmi136 - sclk_pixel 137 - sclk_audio0 138 - sclk_mmc0139 - sclk_mmc1140 - sclk_mmc2141 - sclk_mmc3142 - sclk_sata143 - sclk_usb3144 - sclk_jpeg145 - sclk_uart0 146 - sclk_uart1 147 - sclk_uart2 148 - sclk_uart3 149 - sclk_pwm 150 - sclk_audio1 151 - sclk_audio2 152 - sclk_spdif 153 - sclk_spi0154 - sclk_spi1155 - sclk_spi2156 - div_i2s1 157 - div_i2s2 158 - sclk_hdmiphy 159 - - - [Peripheral Clock Gates] - - ClockID - - - gscl0256 - gscl1257 - gscl2258 - gscl3259 - gscl_wa 260 - gscl_wb 261 - smmu_gscl0 262 - smmu_gscl1 263 - smmu_gscl2 264 - smmu_gscl3 265 - mfc 266 - smmu_mfcl267 - smmu_mfcr268 - rotator 269 - jpeg 270 - mdma1271 - smmu_rotator 272 - smmu_jpeg273 - smmu_mdma1 274 - pdma0275 - pdma1276 - sata 277 - usbotg 278 - mipi_hsi 279 - sdmmc0 280 - sdmmc1 281 - sdmmc2 282 - sdmmc3 283 - sromc284 - usb2 285 - usb3 286 - sata_phyctrl 287 - sata_phyi2c 288 - uart0289 - uart1290 - uart2291 - uart3292 - uart4293 - i2c0 294 - i2c1 295 - i2c2 296 - i2c3 297 - i2c4 298 - i2c5 299 - i2c6 300 - i2c7 301 - i2c_hdmi 302 - adc 303 - spi0 304 - spi1 305 - spi2 306 - i2s1 307 - i2s2 308 - pcm1 309 - pcm2 310 - pwm 311 - spdif312 - ac97 313 - hsi2c0 314 - hsi2c1 315 - hs12c2 316 - hs12c3 317 - chipid 318 - sysreg 319 - pmu 320 - cmu_top 321 - cmu_core 322 - cmu_mem 323 - tzpc0324 - tzpc1325 - tzpc2326 - tzpc3327 - tzpc4328 - tzpc5329 - tzpc6330 - tzpc7331 - tzpc8332 - tzpc9333 - hdmi_cec 334 - mct 335 - wdt 336 - rtc 337 - tmu 338 - fimd1339 - mie1 340 - dsim0341 - dp 342 - mixer343 - hdmi 344 - g2d 345 - - - [Clock Muxes] - - ClockID - - mout_hdmi
[PATCH 11/12] ARM: dts: exynos5440: convert magic numbers to macros in clock bindings
The patch replaces magic numbers with macros defined in DT header
in exynos5440 clock bindings.
Signed-off-by: Andrzej Hajda
Signed-off-by: Kyungmin Park
---
.../devicetree/bindings/clock/exynos5440-clock.txt | 45 +++---
arch/arm/boot/dts/exynos5440.dtsi | 27 ++---
2 files changed, 20 insertions(+), 52 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
index 4499e99..56a0269b 100644
--- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -12,45 +12,12 @@ Required Properties:
- #clock-cells: should be 1.
-The following is the list of clocks generated by the controller. Each clock is
-assigned an identifier and client nodes use this identifier to specify the
-clock which they consume.
-
-
- [Core Clocks]
-
- ClockID
-
-
- xtal 1
- arm_clk 2
-
- [Peripheral Clock Gates]
-
- ClockID
-
-
- spi_baud 16
- pb0_250 17
- pr0_250 18
- pr1_250 19
- b_25020
- b_12521
- b_20022
- sata 23
- usb 24
- gmac025
- cs25026
- pb0_250_o27
- pr0_250_o28
- pr1_250_o29
- b_250_o 30
- b_125_o 31
- b_200_o 32
- sata_o 33
- usb_o34
- gmac0_o 35
- cs250_o 36
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5440.h header and can be used in device
+tree sources.
Example: An example of a clock controller node is listed below.
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index ff7f5d8..bf22d98 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
+#include
#include "skeleton.dtsi"
/ {
@@ -102,7 +103,7 @@
compatible = "samsung,exynos4210-uart";
reg = <0xB 0x1000>;
interrupts = <0 2 0>;
- clocks = <&clock 21>, <&clock 21>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -110,7 +111,7 @@
compatible = "samsung,exynos4210-uart";
reg = <0xC 0x1000>;
interrupts = <0 3 0>;
- clocks = <&clock 21>, <&clock 21>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -122,7 +123,7 @@
#size-cells = <0>;
samsung,spi-src-clk = <0>;
num-cs = <1>;
- clocks = <&clock 21>, <&clock 16>;
+ clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
clock-names = "spi", "spi_busclk0";
};
@@ -158,7 +159,7 @@
interrupts = <0 5 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 21>;
+ clocks = <&clock CLK_B_125>;
clock-names = "i2c";
};
@@ -168,7 +169,7 @@
interrupts = <0 6 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 21>;
+ clocks = <&clock CLK_B_125>;
clock-names = "i2c";
};
@@ -176,7 +177,7 @@
compatible = "samsung,s3c2410-wdt";
reg = <0x11 0x1000>;
interrupts = <0 1 0>;
- clocks = <&clock 21>;
+ clocks = <&clock CLK_B_125>;
clock-names = "watchdog";
};
@@ -187,7 +188,7 @@
interrupts = <0 31 4>;
interrupt-names = "macirq";
phy-mode = "sgmii";
- clocks = <&clock 25>;
+ clocks = <&clock CLK_GMAC0>;
clock-names = "stmmaceth";
};
@@ -203,7 +204,7 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x13 0x1000>;
interrupts = <0 17 0>, <0 16 0>;
- clocks = <&clock 21>;
+ clocks = <&clock CLK_B_125>;
clock-names = "rtc";
};
@@ -211,7 +212,7 @@
compatible = "snps,exynos5440-ahci";
reg = <0x21 0x1>;
interrupts = <0 30 0>;
- clocks = <&clock 2
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae wrote:
>
>
>> -Original Message-
>> From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
>> ow...@vger.kernel.org] On Behalf Of Rahul Sharma
>> Sent: Thursday, September 05, 2013 3:04 PM
>> To: Inki Dae
>> Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
>> sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
>> Shirish S
>> Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
>> driver
>>
>> On 5 September 2013 10:52, Inki Dae wrote:
>> >> >> >> >> +static struct hdmiphy_config hdmiphy_4210_configs[] = {
>> >> >> >> >> + {
>> >> >> >> >> + .pixel_clock = 2700,
>> >> >> >> >> + .conf = {
>> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
> 0x30,
>> >> > 0x40,
>> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
> 0x54,
>> >> > 0x87,
>> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> 0x10,
>> >> > 0xE0,
>> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
> 0x00,
>> >> > 0x00,
>> >> >> >> >> + },
>> >> >> >> >> + },
>> >> >> >> >> + {
>> >> >> >> >> + .pixel_clock = 27027000,
>> >> >> >> >> + .conf = {
>> >> >> >> >> + 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
> 0x09,
>> >> > 0x64,
>> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
> 0x54,
>> >> > 0x87,
>> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> 0x10,
>> >> > 0xE0,
>> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
> 0x00,
>> >> > 0x00,
>> >> >> >> >> + },
>> >> >> >> >> + },
>> >> >> >> >> + {
>> >> >> >> >> + .pixel_clock = 74176000,
>> >> >> >> >> + .conf = {
>> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
> 0xef,
>> >> > 0x5B,
>> >> >> >> >> + 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
> 0x54,
>> >> > 0xb9,
>> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> 0x10,
>> >> > 0xE0,
>> >> >> >> >> + 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
> 0x00,
>> >> > 0x00,
>> >> >> >> >> + },
>> >> >> >> >> + },
>> >> >> >> >> + {
>> >> >> >> >> + .pixel_clock = 7425,
>> >> >> >> >> + .conf = {
>> >> >> >> >> + 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
> 0xf8,
>> >> > 0x40,
>> >> >> >> >> + 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
> 0x54,
>> >> > 0xba,
>> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
> 0x10,
>> >> > 0xe0,
>> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
> 0x00,
>> >> > 0x00,
>> >> >> >> >> + },
>> >> >> >> >> + },
>> >> >> >> >> + {
>> >> >> >> >> + .pixel_clock = 14850,
>> >> >> >> >> + .conf = {
>> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
> 0xf8,
>> >> > 0x40,
>> >> >> >> >> + 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
> 0x54,
>> >> > 0xba,
>> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
> 0x10,
>> >> > 0xE0,
>> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
> 0x00,
>> >> > 0x00,
>> >> >> >> >> + },
>> >> >> >> >> + },
>> >> >> >> >> +};
>> >> >> >> >> +
>> >> >> >> >
>> >> >> >> > Are you aware of the effort to move these to dt? Since these
>> are
>> >> >> >> > board-specific values, it seems incorrect to apply them
>> >> universally.
>> >> >> >> > Shirish has uploaded a patch to the chromium review site to
>> push
>> >> >> these
>> >> >> >> > into dt (https://chromium-review.googlesource.com/#/c/65581).
>> >> Maybe
>> >> >> >> > you can work that into your patch set?
>> >> >> >> >
>> >> >> >
>> >> >> > Are these really board-specific values?
>> >> >>
>> >> >> According to your hardware people:
>> >> >>
>> >> >> "If the signal pattern doesn't change for new board, the phy setting
>> >> >> is same as the current board. But if changed, you need to confirm
>> with
>> >> >> measurement of signals, because it may vary slightly by resistance
>> of
>> >> >> board pattern"
>> >> >>
>> >> >
>> >> > Right. it seems that the phy configuration should be adjusted
>> according
>> >> to
>> >> > PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided by
>> PCB
>> >> > even though most PCBs use 27MHz.
>> >> >
>> >> >> That indicates to me that we might need to tweak these on a per-
>> board
>> >> >> basis.
>> >> >>
>> >> >> In the 5420 datasheet, there are a few register descriptions
>> available
>> >> >> for the phy. 0x145D0004 is CLK_SEL which seems like it would be
>> >> >> board-specific, same with TX_* registers.
>> >> >>
>> >> >
>> >> > And we can select HDMI Tx PHY internal PLL input clock by se
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
> -Original Message-
> From: Sean Paul [mailto:seanp...@chromium.org]
> Sent: Thursday, September 05, 2013 10:20 PM
> To: Inki Dae
> Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
> sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
> Shirish S
> Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
> driver
>
> On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae wrote:
> >
> >
> >> -Original Message-
> >> From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-
> soc-
> >> ow...@vger.kernel.org] On Behalf Of Rahul Sharma
> >> Sent: Thursday, September 05, 2013 3:04 PM
> >> To: Inki Dae
> >> Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
> >> sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
> >> Shirish S
> >> Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
> hdmiphy
> >> driver
> >>
> >> On 5 September 2013 10:52, Inki Dae wrote:
> >> >> >> >> >> +static struct hdmiphy_config hdmiphy_4210_configs[] = {
> >> >> >> >> >> + {
> >> >> >> >> >> + .pixel_clock = 2700,
> >> >> >> >> >> + .conf = {
> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
> > 0x30,
> >> >> > 0x40,
> >> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
> > 0x54,
> >> >> > 0x87,
> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> > 0x10,
> >> >> > 0xE0,
> >> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
> > 0x00,
> >> >> > 0x00,
> >> >> >> >> >> + },
> >> >> >> >> >> + },
> >> >> >> >> >> + {
> >> >> >> >> >> + .pixel_clock = 27027000,
> >> >> >> >> >> + .conf = {
> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
> > 0x09,
> >> >> > 0x64,
> >> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
> > 0x54,
> >> >> > 0x87,
> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> > 0x10,
> >> >> > 0xE0,
> >> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
> > 0x00,
> >> >> > 0x00,
> >> >> >> >> >> + },
> >> >> >> >> >> + },
> >> >> >> >> >> + {
> >> >> >> >> >> + .pixel_clock = 74176000,
> >> >> >> >> >> + .conf = {
> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
> > 0xef,
> >> >> > 0x5B,
> >> >> >> >> >> + 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
> > 0x54,
> >> >> > 0xb9,
> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
> > 0x10,
> >> >> > 0xE0,
> >> >> >> >> >> + 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
> > 0x00,
> >> >> > 0x00,
> >> >> >> >> >> + },
> >> >> >> >> >> + },
> >> >> >> >> >> + {
> >> >> >> >> >> + .pixel_clock = 7425,
> >> >> >> >> >> + .conf = {
> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
> > 0xf8,
> >> >> > 0x40,
> >> >> >> >> >> + 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
> > 0x54,
> >> >> > 0xba,
> >> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
> > 0x10,
> >> >> > 0xe0,
> >> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
> > 0x00,
> >> >> > 0x00,
> >> >> >> >> >> + },
> >> >> >> >> >> + },
> >> >> >> >> >> + {
> >> >> >> >> >> + .pixel_clock = 14850,
> >> >> >> >> >> + .conf = {
> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
> > 0xf8,
> >> >> > 0x40,
> >> >> >> >> >> + 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
> > 0x54,
> >> >> > 0xba,
> >> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
> > 0x10,
> >> >> > 0xE0,
> >> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
> > 0x00,
> >> >> > 0x00,
> >> >> >> >> >> + },
> >> >> >> >> >> + },
> >> >> >> >> >> +};
> >> >> >> >> >> +
> >> >> >> >> >
> >> >> >> >> > Are you aware of the effort to move these to dt? Since these
> >> are
> >> >> >> >> > board-specific values, it seems incorrect to apply them
> >> >> universally.
> >> >> >> >> > Shirish has uploaded a patch to the chromium review site to
> >> push
> >> >> >> these
> >> >> >> >> > into dt
(https://chromium-review.googlesource.com/#/c/65581).
> >> >> Maybe
> >> >> >> >> > you can work that into your patch set?
> >> >> >> >> >
> >> >> >> >
> >> >> >> > Are these really board-specific values?
> >> >> >>
> >> >> >> According to your hardware people:
> >> >> >>
> >> >> >> "If the signal pattern doesn't change for new board, the phy
> setting
> >> >> >> is same as the current board. But if changed, you need to confirm
> >> with
> >> >> >> measurement of signals, because it may vary slightly by
> resistance
> >> of
> >> >> >> board p
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
Can you please quote only related part of e-mails when replying ? It discourages to read such discussions when you have to scroll through few pages of "garbage" before getting to the actual reply text. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Xen-devel] [PATCH v5 02/13] arm: introduce a global dma_ops pointer
On Mon, 2 Sep 2013, Julien Grall wrote:
> On 08/29/2013 07:32 PM, Stefano Stabellini wrote:
> > Initially set dma_ops to arm_dma_ops.
> >
> >
> > Signed-off-by: Stefano Stabellini
> > Acked-by: Konrad Rzeszutek Wilk
> > CC: will.dea...@arm.com
> > CC: li...@arm.linux.org.uk
> >
> >
> > Changes in v3:
> > - keep using arm_dma_ops in dmabounce.
> > ---
> > arch/arm/include/asm/dma-mapping.h |3 ++-
> > arch/arm/mm/dma-mapping.c |3 +++
> > 2 files changed, 5 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/dma-mapping.h
> > b/arch/arm/include/asm/dma-mapping.h
> > index 0982206..7d6e4f9 100644
> > --- a/arch/arm/include/asm/dma-mapping.h
> > +++ b/arch/arm/include/asm/dma-mapping.h
> > @@ -13,6 +13,7 @@
> > #include
> >
> > #define DMA_ERROR_CODE (~0)
> > +extern struct dma_map_ops *dma_ops;
>
> Hi,
>
> I tried to build your swiotlb patch series for the Arndale. I have a
> compilation
> error because dma_ops is already used in samsung sound driver
> (sound/soc/samsung/dma.c).
>
> This small fix allow me to built this serie for the Arndale.
> Do I need to send it separately?
This looks like a good fix, I'll append it to the series
> ===
> commit 73d4ceded87f52fa958b92d8d8d65be485e90857
> Author: Julien Grall
> Date: Mon Sep 2 15:36:35 2013 +0100
>
> ASoC: Samsung: Rename dma_ops by samsung_dma_ops
>
> The commit "arm: introduce a global dma_ops pointer" introduce
> compilation issue
> when CONFIG_SND_SOC_SAMSUNG is enabled.
>
> sound/soc/samsung/dma.c:345:27: error: conflicting types for 'dma_ops'
>
> /local/home/julien/works/arndale/linux/arch/arm/include/asm/dma-mapping.h:16:28:
> note: previous declaration of 'dma_ops' was here
>
> Signed-off-by: Julien Grall
>
> diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
> index ddea134..c341603 100644
> --- a/sound/soc/samsung/dma.c
> +++ b/sound/soc/samsung/dma.c
> @@ -342,7 +342,7 @@ static int dma_mmap(struct snd_pcm_substream *substream,
> runtime->dma_bytes);
> }
>
> -static struct snd_pcm_ops dma_ops = {
> +static struct snd_pcm_ops samsung_dma_ops = {
> .open = dma_open,
> .close = dma_close,
> .ioctl = snd_pcm_lib_ioctl,
> @@ -429,7 +429,7 @@ out:
> }
>
> static struct snd_soc_platform_driver samsung_asoc_platform = {
> - .ops= &dma_ops,
> + .ops= &samsung_dma_ops,
> .pcm_new= dma_new,
> .pcm_free = dma_free_dma_buffers,
> };
>
> --
> Julien Grall
>
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC Patch v2 0/3] add temporary parent migration support
On Wed, Sep 4, 2013 at 11:01 AM, Tomasz Figa wrote: > On Wednesday 04 of September 2013 10:43:28 Mike Turquette wrote: >> Quoting Tomasz Figa (2013-09-03 15:36:50) >> >> > Hi Chander, >> > >> > On Tuesday 03 of September 2013 17:04:28 Chander Kashyap wrote: >> > > Some platform has provision to change cpu parent clock during >> > > cpu frequency scaling. This patch series provides a mechanism to >> > > implement the same using CCF. >> > > >> > > Patch1 provides mechanism to migrate to new parent temporarily. >> > > >> > > Patch2 updates the user of clk_register_mux and DEFINE_CLK_MUX which >> > > are modified to add support for clk migration. >> > > >> > > Patch3 adds support to Exynos5250 to use the clock parent migration >> > > feature implemented in CCF. >> > >> > I don't really like this approach. A need to change mux setting >> > temporarily is heavily platform-specific and I don't think it should >> > be >> > handled by generic code. >> >> I agree with Tomasz. >> >> > First of all there are many factor that you would >> > >> > have to account for to make this solution generic, such as: >> > - board specific alternative parents, >> > - exact moment of parent change, >> > - some other platform specific conditions, like CPU voltage that must >> > be> >> > changed when mux is changed, because it changes CPU frequency, >> > >> > - and probably a lot of more factors that only people working with >> > all >> > >> > the platforms supported (and unsupported yet) by Linux. >> > >> > I can see at least two solutions for this problem that don't require >> > changing core code of common clock framework: >> > >> > 1) Implementing a special clock type using normal mux ops, but also >> > registering a notifier for its PRE_RATE_CHANGE and POST_RATE_CHANGE >> > events to perform parent switching. >> >> Creating a custom clock type is the way to go here. It is possible to >> wrap the mux clk_ops to re-use that code, or just write a custom clock >> type from scratch. >> >> I do not like using the clock rate-change notifiers for this purpose. >> The notifiers provide hooks to drivers that need to take care around >> clock transitions. Using the notifiers from within the clock framework >> indicates poor design. > > I was not sure how a .set_parent() from inside a .set_rate() would > interact with rate setting, so I mentioned notifiers here, but now as I > think of it, CCF is supposed to be re-entrant, so things should be fine. > >> > 2) Using normal mux clock, but registering such notifiers in clock >> > controller or cpufreq driver. >> >> This depends on what the data sheet or reference manual states. If using >> a temporary parent is a property of the clock programming sequence >> (e.g. to have a glitch-less transition) then that logic belongs in the >> clock provider driver (i.e. a custom clock type needs to be created >> with this logic). >> >> However if using a temporary parent is not required for programming the >> clock, but is instead a requirement of the clock consumer (e.g. a CPU, >> or some I/O controller) then perhaps putting this logic in that driver >> is the right way to go. In that case the logic could be explicit: >> >> clk_set_parent(clk, temp_parent); >> clk_set_rate(clk, target_rate); >> clk_set_parent(clk, target_parent); >> >> Or it could implicit with the use of rate-change notifiers. Again the >> rate-change notifiers exist for clock consumer drivers to use, so this >> is OK. >> >> I have a hunch that the right way to do this is for a custom clock type >> to be created which simply calls clk_set_parent from within the clock's >> .set_rate callback, but I'll wait on feedback from Chander on the needs >> of his platform. > > I believe Chander has exactly the same use case for this as we have for > Exynos 4210 and 4x12. > > On these SoCs, CPU frequency is being scaled by reconfiguring PLL, which > needs to be masked for locking time. To let the CPU operate normally, a > mux that allows switching CPU clock domain between two PLLs can be > switched to the other PLL (MPLL) until the main ARM PLL (APLL) starts > operating again. Right, this is the "glitchless" operation I mentioned earlier and it is not uncommon in PLLs. > > However this issue is not limited to clocks, because there must be also a > voltage transition involved if the utility PLL has frequency higher than > the one currently being reconfigured. Right, that is an altogether different issue. What I would like to see is the temporary parent managed by calls to clk_set_parent from within a custom .set_rate callback. As for the voltage scaling, it would be cool to see this working with the voltage notifier series I posted recently. Both parents of the PLLs can have their own operating point tables and each transition would fire off notifiers that scale voltage. Something like this: clk_set_rate(pll, rate) -> enter .set_rate -> clk_set_parent(pll, temp_parent) -> temp_parent PRE_RATE_CHANGE notifier is trigg
Re: [PATCH v3 2/2] arm: dt: Exynos5420: populate cpu node enteries to 8 cpus
On 09/05/2013 01:29 PM, Chander Kashyap wrote: Exynos5420 is octacore SoC from samsung. s/octacore/octa-core ? s/samsung/Samsung Hence populate all the cpu node enteries. s/cpu/CPU ? s/enteries/entries Signed-off-by: Chander Kashyap Subjects of the dts patches normally start with "ARM: dts:". I guess this all could be corrected while the patch is being applied to the platform maitainter's tree. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
Like s5k6a3, it is also another fimc-is firmware controlled
sensor. This minimal sensor driver doesn't do any I2C communications
as its done by ISP firmware. It can be updated if needed to a
regular sensor driver by adding the I2C communication.
Signed-off-by: Arun Kumar K
Reviewed-by: Sylwester Nawrocki
---
.../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
drivers/media/i2c/Kconfig |8 +
drivers/media/i2c/Makefile |1 +
drivers/media/i2c/s5k4e5.c | 361
4 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
create mode 100644 drivers/media/i2c/s5k4e5.c
diff --git a/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
new file mode 100644
index 000..5af462c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
@@ -0,0 +1,43 @@
+* Samsung S5K4E5 Raw Image Sensor
+
+S5K4E5 is a raw image sensor with maximum resolution of 2560x1920
+pixels. Data transfer is carried out via MIPI CSI-2 port and controls
+via I2C bus.
+
+Required Properties:
+- compatible : must be "samsung,s5k4e5"
+- reg : I2C device address
+- gpios: reset gpio pin
I guess this should be "reset-gpios". How about changing description to:
- reset-gpios : specifier of a GPIO connected to the RESET pin;
?
+- clocks : clock specifier for the clock-names property
Perhaps something along the lines of:
- clocks : "should contain the sensor's MCLK clock specifier, from
the common clock bindings"
?
+- clock-names : must contain "mclk" entry
Is name of the clock input pin really MCLK ?
+- svdda-supply : core voltage supply
+- svddio-supply: I/O voltage supply
+
+Optional Properties:
+- clock-frequency : operating frequency for the sensor
+default value will be taken if not provided.
How about clarifying it a bit, as Stephen suggested, e.g.:
- clock-frequency : the frequency at which the "mclk" clock should be
configured to operate, in Hz; if this property is not
specified default 24 MHz value will be used.
+The device node should be added to respective control bus controller
+(e.g. I2C0) nodes and linked to the csis port node, using the common
+video interfaces bindings, defined in video-interfaces.txt.
This seems misplaced, S5K4E5 image sensor has nothingto do with csis nodes.
How about something like this instead:
"The common video interfaces bindings (see video-interfaces.txt) should be
used to specify link to the image data receiver. The S5K6A3(YX) device
node should contain one 'port' child node with an 'endpoint' subnode.
Following properties are valid for the endpoint node:
..."
+Example:
+
+ i2c-isp@1313 {
+ s5k4e5@20 {
+ compatible = "samsung,s5k4e5";
+ reg =<0x20>;
+ gpios =<&gpx1 2 1>;
+ clock-frequency =<2400>;
+ clocks =<&clock 129>;
+ clock-names = "mclk";
+ svdda-supply =<...>;
+ svddio-supply =<...>;
+ port {
+ is_s5k4e5_ep: endpoint {
+ data-lanes =<1 2 3 4>;
+ remote-endpoint =<&csis0_ep>;
+ };
+ };
+ };
+ };
--
Thanks,
Sylwester
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Re: [PATCH v7 02/13] [media] exynos5-fimc-is: Add Exynos5 FIMC-IS device tree bindings documentation
On 08/21/2013 08:34 AM, Arun Kumar K wrote: The patch adds the DT binding documentation for Samsung Exynos5 SoC series imaging subsystem (FIMC-IS). Signed-off-by: Arun Kumar K Reviewed-by: Sylwester Nawrocki Can I have a DT binding maintainer Ack for this binding ? I'd like to queue this patch for 3.13 once the merge window has closed. --- .../devicetree/bindings/media/exynos5-fimc-is.txt | 46 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/exynos5-fimc-is.txt diff --git a/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt new file mode 100644 index 000..5611401 --- /dev/null +++ b/Documentation/devicetree/bindings/media/exynos5-fimc-is.txt @@ -0,0 +1,46 @@ +Samsung EXYNOS5 SoC series Imaging Subsystem (FIMC-IS) +-- + +The camera subsystem on Samsung Exynos5 SoC has some changes relative +to previous SoC versions. Exynos5 has almost similar MIPI-CSIS and +FIMC-LITE IPs but has a much improved version of FIMC-IS which can +handle sensor controls and camera post-processing operations. The +Exynos5 FIMC-IS has a dedicated ARM Cortex A5 processor, many +post-processing blocks (ISP, DRC, FD, ODC, DIS, 3DNR) and two +dedicated scalers (SCC and SCP). + +fimc-is node + + +Required properties: + +- compatible: must be "samsung,exynos5250-fimc-is" +- reg : physical base address and size of the memory mapped + registers +- interrupt-parent : parent interrupt controller +- interrupts: fimc-is interrupt to the parent interrupt controller +- clocks: list of clock specifiers, corresponding to entries in + clock-names property +- clock-names : must contain "isp", "mcu_isp", "isp_div0", "isp_div1", + "isp_divmpwm", "mcu_isp_div0", "mcu_isp_div1" entries, + matching entries in the clocks property +- samsung,pmu : phandle to the Power Management Unit (PMU) node + +i2c-isp (ISP I2C bus controller) nodes +-- + +Required properties: + +- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212, + Exynos4412 and Exynos5250 SoCs +- reg : physical base address and length of the registers set +- clocks : must contain gate clock specifier for this controller +- clock-names : must contain "i2c_isp" entry + +For the i2c-isp node, it is required to specify a pinctrl state named "default", +according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt. + +Device tree nodes of the image sensors controlled directly by the FIMC-IS +firmware must be child nodes of their corresponding ISP I2C bus controller node. +The data link of these image sensors must be specified using the common video +interfaces bindings, defined in video-interfaces.txt. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 01/13] [media] exynos5-is: Adding media device driver for exynos5
On 08/21/2013 08:34 AM, Arun Kumar K wrote:
From: Shaik Ameer Basha
This patch adds support for media device for EXYNOS5 SoCs.
The current media device supports the following ips to connect
through the media controller framework.
* MIPI-CSIS
Support interconnection(subdev interface) between devices
* FIMC-LITE
Support capture interface from device(Sensor, MIPI-CSIS) to memory
Support interconnection(subdev interface) between devices
* FIMC-IS
Camera post-processing IP having multiple sub-nodes.
G-Scaler will be added later to the current media device.
The media device creates two kinds of pipelines for connecting
the above mentioned IPs.
The pipeline0 is uses Sensor, MIPI-CSIS and FIMC-LITE which captures
image data and dumps to memory.
Pipeline1 uses FIMC-IS components for doing post-processing
operations on the captured image and give scaled YUV output.
Pipeline0
++ +---+ +---+ ++
| Sensor | --> | MIPI-CSIS | --> | FIMC-LITE | --> | Memory |
++ +---+ +---+ ++
Pipeline1
++ ++ +---+ +---+
| Memory | --> | ISP | --> |SCC| --> |SCP|
++ ++ +---+ +---+
Signed-off-by: Shaik Ameer Basha
Signed-off-by: Arun Kumar K
---
.../bindings/media/exynos5250-camera.txt | 126 ++
drivers/media/platform/exynos5-is/exynos5-mdev.c | 1210
drivers/media/platform/exynos5-is/exynos5-mdev.h | 126 ++
3 files changed, 1462 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/exynos5250-camera.txt
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.c
create mode 100644 drivers/media/platform/exynos5-is/exynos5-mdev.h
diff --git a/Documentation/devicetree/bindings/media/exynos5250-camera.txt
b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
new file mode 100644
index 000..09420ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5250-camera.txt
@@ -0,0 +1,126 @@
+Samsung EXYNOS5 SoC Camera Subsystem
+
+
+The Exynos5 SoC Camera subsystem comprises of multiple sub-devices
+represented by separate device tree nodes. Currently this includes: FIMC-LITE,
+MIPI CSIS and FIMC-IS.
+
+The sub-device nodes are referenced using phandles in the common 'camera' node
+which also includes common properties of the whole subsystem not really
+specific to any single sub-device, like common camera port pins or the common
+camera bus clocks.
+
+Common 'camera' node
+
+
+Required properties:
+
+- compatible : must be "samsung,exynos5250-fimc"
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property
+- clock-names : must contain "sclk_bayer" entry
+- samsung,csis : list of phandles to the mipi-csis device nodes
+- samsung,fimc-lite: list of phandles to the fimc-lite device nodes
+- samsung,fimc-is : phandle to the fimc-is device node
+
+The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
+to define a required pinctrl state named "default".
+
+'parallel-ports' node
+-
+
+This node should contain child 'port' nodes specifying active parallel video
+input ports. It includes camera A, camera B and RGB bay inputs.
+'reg' property in the port nodes specifies the input type:
+ 1 - parallel camport A
+ 2 - parallel camport B
+ 5 - RGB camera bay
+
+3, 4 are for MIPI CSI-2 bus and are already described in samsung-mipi-csis.txt
+
+Image sensor nodes
+--
+
+The sensor device nodes should be added to their control bus controller (e.g.
+I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
+using the common video interfaces bindings, defined in video-interfaces.txt.
+
+Example:
+
+ aliases {
+ fimc-lite0 =&fimc_lite_0
+ };
+
+ /* Parallel bus IF sensor */
+ i2c_0: i2c@1386 {
+ s5k6aa: sensor@3c {
+ compatible = "samsung,s5k6aafx";
+ reg =<0x3c>;
+ vddio-supply =<...>;
+
+ clock-frequency =<2400>;
+ clocks =<...>;
+ clock-names = "mclk";
+
+ port {
+ s5k6aa_ep: endpoint {
+ remote-endpoint =<&fimc0_ep>;
+ bus-width =<8>;
+ hsync-active =<0>;
+ vsync-active =<1>;
+ pclk-sample =<1>;
+ };
+ };
+ };
+ };
+
+ /* MIPI CSI-2 bus IF sensor */
+ s5c73m3: sensor@1a {
+
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 5 September 2013 19:20, Inki Dae wrote:
>
>
>> -Original Message-
>> From: Sean Paul [mailto:seanp...@chromium.org]
>> Sent: Thursday, September 05, 2013 10:20 PM
>> To: Inki Dae
>> Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
>> sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
>> Shirish S
>> Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
>> driver
>>
>> On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae wrote:
>> >
>> >
>> >> -Original Message-
>> >> From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-
>> soc-
>> >> ow...@vger.kernel.org] On Behalf Of Rahul Sharma
>> >> Sent: Thursday, September 05, 2013 3:04 PM
>> >> To: Inki Dae
>> >> Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
>> >> sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
>> >> Shirish S
>> >> Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
>> hdmiphy
>> >> driver
>> >>
>> >> On 5 September 2013 10:52, Inki Dae wrote:
>> >> >> >> >> >> +static struct hdmiphy_config hdmiphy_4210_configs[] = {
>> >> >> >> >> >> + {
>> >> >> >> >> >> + .pixel_clock = 2700,
>> >> >> >> >> >> + .conf = {
>> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
>> > 0x30,
>> >> >> > 0x40,
>> >> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
>> > 0x54,
>> >> >> > 0x87,
>> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
>> > 0x10,
>> >> >> > 0xE0,
>> >> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
>> > 0x00,
>> >> >> > 0x00,
>> >> >> >> >> >> + },
>> >> >> >> >> >> + },
>> >> >> >> >> >> + {
>> >> >> >> >> >> + .pixel_clock = 27027000,
>> >> >> >> >> >> + .conf = {
>> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
>> > 0x09,
>> >> >> > 0x64,
>> >> >> >> >> >> + 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
>> > 0x54,
>> >> >> > 0x87,
>> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
>> > 0x10,
>> >> >> > 0xE0,
>> >> >> >> >> >> + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
>> > 0x00,
>> >> >> > 0x00,
>> >> >> >> >> >> + },
>> >> >> >> >> >> + },
>> >> >> >> >> >> + {
>> >> >> >> >> >> + .pixel_clock = 74176000,
>> >> >> >> >> >> + .conf = {
>> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
>> > 0xef,
>> >> >> > 0x5B,
>> >> >> >> >> >> + 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
>> > 0x54,
>> >> >> > 0xb9,
>> >> >> >> >> >> + 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
>> > 0x10,
>> >> >> > 0xE0,
>> >> >> >> >> >> + 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
>> > 0x00,
>> >> >> > 0x00,
>> >> >> >> >> >> + },
>> >> >> >> >> >> + },
>> >> >> >> >> >> + {
>> >> >> >> >> >> + .pixel_clock = 7425,
>> >> >> >> >> >> + .conf = {
>> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
>> > 0xf8,
>> >> >> > 0x40,
>> >> >> >> >> >> + 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
>> > 0x54,
>> >> >> > 0xba,
>> >> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
>> > 0x10,
>> >> >> > 0xe0,
>> >> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
>> > 0x00,
>> >> >> > 0x00,
>> >> >> >> >> >> + },
>> >> >> >> >> >> + },
>> >> >> >> >> >> + {
>> >> >> >> >> >> + .pixel_clock = 14850,
>> >> >> >> >> >> + .conf = {
>> >> >> >> >> >> + 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
>> > 0xf8,
>> >> >> > 0x40,
>> >> >> >> >> >> + 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
>> > 0x54,
>> >> >> > 0xba,
>> >> >> >> >> >> + 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
>> > 0x10,
>> >> >> > 0xE0,
>> >> >> >> >> >> + 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
>> > 0x00,
>> >> >> > 0x00,
>> >> >> >> >> >> + },
>> >> >> >> >> >> + },
>> >> >> >> >> >> +};
>> >> >> >> >> >> +
>> >> >> >> >> >
>> >> >> >> >> > Are you aware of the effort to move these to dt? Since these
>> >> are
>> >> >> >> >> > board-specific values, it seems incorrect to apply them
>> >> >> universally.
>> >> >> >> >> > Shirish has uploaded a patch to the chromium review site to
>> >> push
>> >> >> >> these
>> >> >> >> >> > into dt
> (https://chromium-review.googlesource.com/#/c/65581).
>> >> >> Maybe
>> >> >> >> >> > you can work that into your patch set?
>> >> >> >> >> >
>> >> >> >> >
>> >> >> >> > Are these really board-specific values?
>> >> >> >>
>> >> >> >> According to your hardware people:
>> >> >> >>
>> >> >> >> "If the signal pattern doesn't change for new board, the phy
>> setting
>> >> >> >>
Re: [PATCH v7 13/13] V4L: Add driver for s5k4e5 image sensor
Hi Sylwester,
Will make the changes you suggested.
Will re-spin this entire series with some more minor fixes after more
rigorous testing.
Regards
Arun
On Fri, Sep 6, 2013 at 1:32 AM, Sylwester Nawrocki
wrote:
> On 08/21/2013 08:34 AM, Arun Kumar K wrote:
>>
>> This patch adds subdev driver for Samsung S5K4E5 raw image sensor.
>> Like s5k6a3, it is also another fimc-is firmware controlled
>> sensor. This minimal sensor driver doesn't do any I2C communications
>> as its done by ISP firmware. It can be updated if needed to a
>> regular sensor driver by adding the I2C communication.
>>
>> Signed-off-by: Arun Kumar K
>> Reviewed-by: Sylwester Nawrocki
>> ---
>> .../devicetree/bindings/media/i2c/s5k4e5.txt | 43 +++
>> drivers/media/i2c/Kconfig |8 +
>> drivers/media/i2c/Makefile |1 +
>> drivers/media/i2c/s5k4e5.c | 361
>>
>> 4 files changed, 413 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
>> create mode 100644 drivers/media/i2c/s5k4e5.c
>>
>> diff --git a/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
>> b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
>> new file mode 100644
>> index 000..5af462c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/i2c/s5k4e5.txt
>> @@ -0,0 +1,43 @@
>> +* Samsung S5K4E5 Raw Image Sensor
>> +
>> +S5K4E5 is a raw image sensor with maximum resolution of 2560x1920
>> +pixels. Data transfer is carried out via MIPI CSI-2 port and controls
>> +via I2C bus.
>> +
>> +Required Properties:
>> +- compatible : must be "samsung,s5k4e5"
>> +- reg : I2C device address
>> +- gpios: reset gpio pin
>
>
> I guess this should be "reset-gpios". How about changing description to:
>
> - reset-gpios : specifier of a GPIO connected to the RESET pin;
>
>
> ?
>>
>> +- clocks : clock specifier for the clock-names property
>
>
> Perhaps something along the lines of:
>
> - clocks : "should contain the sensor's MCLK clock specifier, from
> the common clock bindings"
>
> ?
>>
>> +- clock-names : must contain "mclk" entry
>
>
> Is name of the clock input pin really MCLK ?
>
>
>> +- svdda-supply : core voltage supply
>> +- svddio-supply: I/O voltage supply
>> +
>> +Optional Properties:
>> +- clock-frequency : operating frequency for the sensor
>> +default value will be taken if not provided.
>
>
> How about clarifying it a bit, as Stephen suggested, e.g.:
>
> - clock-frequency : the frequency at which the "mclk" clock should be
> configured to operate, in Hz; if this property is not
> specified default 24 MHz value will be used.
>
>
>> +The device node should be added to respective control bus controller
>> +(e.g. I2C0) nodes and linked to the csis port node, using the common
>> +video interfaces bindings, defined in video-interfaces.txt.
>
>
> This seems misplaced, S5K4E5 image sensor has nothingto do with csis nodes.
> How about something like this instead:
>
> "The common video interfaces bindings (see video-interfaces.txt) should be
> used to specify link to the image data receiver. The S5K6A3(YX) device
> node should contain one 'port' child node with an 'endpoint' subnode.
>
> Following properties are valid for the endpoint node:
> ..."
>
>
>> +Example:
>> +
>> + i2c-isp@1313 {
>> + s5k4e5@20 {
>> + compatible = "samsung,s5k4e5";
>> + reg =<0x20>;
>> + gpios =<&gpx1 2 1>;
>> + clock-frequency =<2400>;
>> + clocks =<&clock 129>;
>> + clock-names = "mclk";
>> + svdda-supply =<...>;
>> + svddio-supply =<...>;
>> + port {
>> + is_s5k4e5_ep: endpoint {
>> + data-lanes =<1 2 3 4>;
>> + remote-endpoint =<&csis0_ep>;
>> + };
>> + };
>> + };
>> + };
>
>
> --
> Thanks,
> Sylwester
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Re: [PATCH 2/3] thermal: samsung: change base_common to more meaningful base_second
On Wed, Sep 4, 2013 at 9:53 AM, Naveen Krishna Chatradhi
wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
>
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
>
> Signed-off-by: Naveen Krishna Chatradhi
The changes look good. For all the 3 patches in the series,
Acked-by: Amit Daniel Kachhap
Reviewed-by: Amit Daniel Kachhap
Thanks,
Amit Daniel
> ---
> Changes since v2:
> Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
> https://lkml.org/lkml/2013/8/1/38
>
> .../devicetree/bindings/thermal/exynos-thermal.txt |4 ++--
> drivers/thermal/samsung/exynos_tmu.c | 12 ++--
> drivers/thermal/samsung/exynos_tmu.h |4 ++--
> drivers/thermal/samsung/exynos_tmu_data.c |2 +-
> 4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
> - reg : Address range of the thermal registers. For soc's which has multiple
> instances of TMU and some registers are shared across all TMU's like
> interrupt related then 2 set of register has to supplied. First set
> - belongs to each instance of TMU and second set belongs to common TMU
> - registers.
> + belongs to each instance of TMU and second set belongs to second set
> + of common TMU registers.
> - interrupts : Should contain interrupt for thermal system
> - clocks : The main clock for TMU device
> - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c
> b/drivers/thermal/samsung/exynos_tmu.c
> index d201ed8..3a55caf 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
> * @id: identifier of the one instance of the TMU controller.
> * @pdata: pointer to the tmu platform/configuration data
> * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
> * @irq: irq number of the TMU controller.
> * @soc: id of the SOC type.
> * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
> int id;
> struct exynos_tmu_platform_data *pdata;
> void __iomem *base;
> - void __iomem *base_common;
> + void __iomem *base_second;
> int irq;
> enum soc_type soc;
> struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
> }
> /*Clear the PMIN in the common TMU register*/
> if (reg->tmu_pmin && !data->id)
> - writel(0, data->base_common + reg->tmu_pmin);
> + writel(0, data->base_second + reg->tmu_pmin);
> out:
> clk_disable(data->clk);
> mutex_unlock(&data->lock);
> @@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
>
> /* Find which sensor generated this interrupt */
> if (reg->tmu_irqstatus) {
> - val_type = readl(data->base_common + reg->tmu_irqstatus);
> + val_type = readl(data->base_second + reg->tmu_irqstatus);
> if (!((val_type >> data->id) & 0x1))
> goto out;
> }
> @@ -582,7 +582,7 @@ static int exynos_map_dt_data(struct platform_device
> *pdev)
> * Check if the TMU shares some registers and then try to map the
> * memory of common registers.
> */
> - if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> + if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
> return 0;
>
> if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -590,7 +590,7 @@ static int exynos_map_dt_data(struct platform_device
> *pdev)
> return -ENODEV;
> }
>
> - data->base_common = devm_ioremap(&pdev->dev, res.start,
> + data->base_second = devm_ioremap(&pdev->dev, res.start,
> resource_size(&res));
> if (!data->base) {
> dev_err(&pdev->dev, "Failed to ioremap memory\n");
> diff --git a/drivers/thermal/samsung/exynos_tmu.h
> b/drivers/thermal/samsung/exynos_tmu.h
> index 7c6c34a..ebd2ec1 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -59,7 +59,7 @@ enum soc_type {
> * state(active/idle) can be checked.
> * TMU_S
[PATCH V3] PCI: exynos: add support for MSI
This patch adds support for Message Signaled Interrupt in the
Exynos PCIe diver using Synopsys designware PCIe core IP.
Signed-off-by: Siva Reddy Kallam
Signed-off-by: Srikanth T Shivanand
Signed-off-by: Jingoo Han
Cc: Pratyush Anand
Cc: Mohit KUMAR
---
Changes since v2:
- fixed MAX_MSI_CTRLS because MAX_MSI_IRQS is 32 only
- used __get_free_pages() to allocate msi_data
- used one msi_data and msi_irq_in_use per one RC
- used irq_domain to represent the MSI controller
- removed msi-base irq number from device tree because this is not
a hardware property.
Changes since v1:
- removed unnecessary exynos_pcie_clear_irq_level()
- updated the bindings documentation
- used new msi_chip infrastructure
- removed ARCH_SUPPORTS_MSI
- replaced #ifdef guards with IS_ENABLED(CONFIG_PCI_MSI)
drivers/pci/host/pci-exynos.c | 44 +++
drivers/pci/host/pcie-designware.c | 240
drivers/pci/host/pcie-designware.h | 14 +++
3 files changed, 298 insertions(+)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 94e096b..f062aca 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -48,6 +48,7 @@ struct exynos_pcie {
#define PCIE_IRQ_SPECIAL 0x008
#define PCIE_IRQ_EN_PULSE 0x00c
#define PCIE_IRQ_EN_LEVEL 0x010
+#define IRQ_MSI_ENABLE (0x1 << 2)
#define PCIE_IRQ_EN_SPECIAL0x014
#define PCIE_PWR_RESET 0x018
#define PCIE_CORE_RESET0x01c
@@ -342,9 +343,36 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void
*arg)
return IRQ_HANDLED;
}
+static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
+{
+ struct pcie_port *pp = arg;
+
+ dw_handle_msi_irq(pp);
+
+ return IRQ_HANDLED;
+}
+
+static void exynos_pcie_msi_init(struct pcie_port *pp)
+{
+ u32 val;
+ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+
+ dw_pcie_msi_init(pp);
+
+ /* enable MSI interrupt */
+ val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
+ val |= IRQ_MSI_ENABLE;
+ exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
+ return;
+}
+
static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
{
exynos_pcie_enable_irq_pulse(pp);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ exynos_pcie_msi_init(pp);
+
return;
}
@@ -430,6 +458,22 @@ static int add_pcie_port(struct pcie_port *pp, struct
platform_device *pdev)
return ret;
}
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq(pdev, 0);
+ if (!pp->msi_irq) {
+ dev_err(&pdev->dev, "failed to get msi irq\n");
+ return -ENODEV;
+ }
+
+ ret = devm_request_irq(&pdev->dev, pp->msi_irq,
+ exynos_pcie_msi_irq_handler,
+ IRQF_SHARED, "exynos-pcie", pp);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request msi irq\n");
+ return ret;
+ }
+ }
+
pp->root_bus_nr = -1;
pp->ops = &exynos_pcie_host_ops;
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index c10e9ac..8963017 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -11,8 +11,11 @@
* published by the Free Software Foundation.
*/
+#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -142,6 +145,204 @@ int dw_pcie_wr_own_conf(struct pcie_port *pp, int where,
int size,
return ret;
}
+static struct irq_chip dw_msi_irq_chip = {
+ .name = "PCI-MSI",
+ .irq_enable = unmask_msi_irq,
+ .irq_disable = mask_msi_irq,
+ .irq_mask = mask_msi_irq,
+ .irq_unmask = unmask_msi_irq,
+};
+
+/* MSI int handler */
+void dw_handle_msi_irq(struct pcie_port *pp)
+{
+ unsigned long val;
+ int i, pos;
+
+ for (i = 0; i < MAX_MSI_CTRLS; i++) {
+ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
+ (u32 *)&val);
+ if (val) {
+ pos = 0;
+ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
+ generic_handle_irq(pp->msi_irq_start
+ + (i * 32) + pos);
+ pos++;
+ }
+ }
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
+ }
+}
+
+void dw_pcie_msi_init(struct pcie_port *pp)
+{
+ pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
+
+ /* program the msi_data */
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
+ virt_to_phys((void *)pp->msi_data));
