[PATCH] ARM: exynos_defconfig: increase CONFIG_NR_CPUS value to 8
Current CONFIG_NR_CPUS value (2) is too small for: - EXYNOS4412 (4 cores) - EXYNOS5440 (4 cores) - EXYNOS5410 (8 cores) - EXYNOS5420 (8 cores) Set CONFIG_NR_CPUS to 8 so it is correct for all currently supported SoCs. Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- arch/arm/configs/exynos_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index ad7dfbb..aec8a3e 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -13,7 +13,7 @@ CONFIG_S3C24XX_PWM=y CONFIG_ARCH_EXYNOS5=y CONFIG_MACH_EXYNOS4_DT=y CONFIG_SMP=y -CONFIG_NR_CPUS=2 +CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: exynos_defconfig: increase CONFIG_NR_CPUS value to 8
Hi Bart, On Thursday 21 of November 2013 13:06:06 Bartlomiej Zolnierkiewicz wrote: Current CONFIG_NR_CPUS value (2) is too small for: - EXYNOS4412 (4 cores) - EXYNOS5440 (4 cores) - EXYNOS5410 (8 cores) - EXYNOS5420 (8 cores) Set CONFIG_NR_CPUS to 8 so it is correct for all currently supported SoCs. Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com --- arch/arm/configs/exynos_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Definitely a change we want to have. Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Thu, Oct 31, 2013 at 1:15 PM, Vivek Gautam gautam.vi...@samsung.com wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE (0x1 6) +#define PHYUTMI_FORCESUSPEND (0x1 1) +#define PHYUTMI_FORCESLEEP (0x1 0) + +#define EXYNOS5_DRD_PHYPIPE(0x0c) + +#define EXYNOS5_DRD_PHYCLKRST (0x10) + +#define
Re: [PATCH v3 0/4] Exynos 5410 Dual cluster support
Hello, On ODROID-XU XOMCCI is connected to VDD. Best Regards, Mauro On Wed, Nov 20, 2013 at 10:54 PM, Tarek Dakhran t.dakh...@samsung.com wrote: Hi, On 20.11.2013 03:23, Tomasz Figa wrote: Hi, On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote: The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12. Has been tested on Exynos 5410 reference board (exynos_defconfig). I've applied the patches on top of today's linux-next and tried to boot my ODROID-XU using exynos5410-smdk5410.dts and exynos_defconfig, but all I can get is an imprecise external abort, when the kernel tries to jump to init. Full boot log below. Any ideas? Best regards, Tomasz 8 U-Boot 2012.07-g2bcb371 (Nov 19 2013 - 20:17:37) for Exynos5410 CPU: Exynos5410 Rev2.3 [Samsung SOC on SMP Platform Base on ARM CortexA15] APLL = 900MHz, KPLL = 600MHz [snip] Starting kernel ... Uncompressing Linux... done, booting the kernel. [0.00] Booting Linux on physical CPU 0x0 [0.00] Initializing cgroup subsys cpuset [0.00] Initializing cgroup subsys cpu [0.00] Initializing cgroup subsys cpuacct [0.00] Linux version 3.12.0-next-20131119-4-g27f3f5f-dirty (tom3q@flatron) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.6, pie-0.5.5) ) #11 SMP PREEMPT Wed Nov 20 00:08:02 CET 2013 [0.00] CPU: ARMv7 Processor [412fc0f3] revision 3 (ARMv7), cr=10c5387d [0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache [0.00] Machine model: Hardkernel ODROID-XU board based on EXYNOS5410 [0.00] bootconsole [earlycon0] enabled [0.00] debug: ignoring loglevel setting. [0.00] Memory policy: Data cache writealloc [0.00] CPU EXYNOS5410 (id 0xe5410023) [0.00] On node 0 totalpages: 262144 [snip] [5.04] isa bounce pool size: 16 pages [5.045000] mmcblk0: mmc1:e624 SU16G 14.8 GiB [5.05] mmcblk0: p1 [5.12] EXT3-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) [5.125000] EXT2-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) [5.145000] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) [5.15] VFS: Mounted root (ext4 filesystem) readonly on device 179:1. [5.165000] devtmpfs: mounted [5.17] Freeing unused kernel memory: 228K (c0513000 - c054c000) [5.195000] Unhandled fault: imprecise external abort (0x1406) at 0x [5.21] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0007 [5.21] [5.21] CPU: 2 PID: 1 Comm: init Not tainted 3.12.0-next-20131119-4-g27f3f5f-dirty #11 [5.21] [c0014068] (unwind_backtrace+0x0/0xf8) from [c0011438] (show_stack+0x10/0x14) [5.21] [c0011438] (show_stack+0x10/0x14) from [c03a486c] (dump_stack+0x7c/0xbc) [5.21] [c03a486c] (dump_stack+0x7c/0xbc) from [c03a1e78] (panic+0x8c/0x1e4) [5.21] [c03a1e78] (panic+0x8c/0x1e4) from [c001f504] (do_exit+0x850/0x920) [5.21] [c001f504] (do_exit+0x850/0x920) from [c001f63c] (do_group_exit+0x3c/0xb0) [5.21] [c001f63c] (do_group_exit+0x3c/0xb0) from [c0029e1c] (get_signal_to_deliver+0x1d4/0x538) [5.21] [c0029e1c] (get_signal_to_deliver+0x1d4/0x538) from [c0010974] (do_signal+0x100/0x40c) [5.21] [c0010974] (do_signal+0x100/0x40c) from [c0010fb4] (do_work_pending+0x68/0xa8) [5.21] [c0010fb4] (do_work_pending+0x68/0xa8) from [c000e620] (work_pending+0xc/0x20) [5.30] CPU3: stopping [5.30] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 3.12.0-next-20131119-4-g27f3f5f-dirty #11 Tomasz, there is CCI on/off switcher on smdk5410 board, also there is XOMCCI pin on SoC. Looks like switcher on board controls the XOMCCI SoC pin. When I turn switcher OFF, I getting the same problem you got. Please, check the cci state on Odroid-XU Board, maybe it is turned off. Best regards, Tarek Dakhran -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/3] phy: Add new Exynos USB PHY driver
On Tue, Nov 5, 2013 at 9:43 PM, Kamil Debski k.deb...@samsung.com wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/phy/samsung-usbphy.txt | 52
drivers/phy/Kconfig| 23 +-
drivers/phy/Makefile |4 +
drivers/phy/phy-exynos-usb2.c | 234 ++
drivers/phy/phy-exynos-usb2.h | 87 ++
drivers/phy/phy-exynos4210-usb2.c | 272
drivers/phy/phy-exynos4212-usb2.c | 324
7 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt
create mode 100644 drivers/phy/phy-exynos-usb2.c
create mode 100644 drivers/phy/phy-exynos-usb2.h
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4212-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
new file mode 100644
index 000..c8fbc70
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
@@ -0,0 +1,52 @@
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usbphy
+ - samsung,exynos4212-usbphy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+ - second and also required is the location of isolation registers
+ (isolation registers control the physical connection between the in
+ SoC modules and outside of the SoC, this also can be called enable
+ control in the documentation of the SoC)
+ - third is the location of the mode switch register, this only applies
+ to SoCs that have such a feature; mode switching enables to have
+ both host and device used the same SoC pins and is commonly used
+ when OTG is supported
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clocks is required by the phy module
+ - other clocks are associated by name with their respective phys and
+ are used to determine the value of the clock settings register
+
+The second cell in the PHY specifier identifies the PHY, its meaning is
+compatible dependent. For the currently supported SoCs (Exynos 4210 and
+Exynos 4212) it is as follows:
+ 0 - USB device,
+ 1 - USB host,
+ 2 - HSIC0,
+ 3 - HSIC1,
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+exynos_usbphy: exynos-usbphy@125B {
+ compatible = samsung,exynos4212-usbphy;
+ reg = 0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4;
+ clocks = clock 305, clock 2, clock 2, clock 2,
+ clock 2;
+ clock-names = phy, device, host, hsic0, hsic1;
+ status = okay;
+ #phy-cells = 1;
+};
+
+Then the PHY can be used in other nodes such as:
+
+ehci@1258 {
+ status = okay;
+ phys = exynos_usbphy 2;
+ phy-names = hsic0;
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..bdf0fab 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -14,7 +14,7 @@ config GENERIC_PHY
API by which phy drivers can create PHY using the phy framework and
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
-
+
config PHY_EXYNOS_MIPI_VIDEO
tristate S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver
help
@@ -51,4 +51,25 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_EXYNOS_USB2
+ tristate Samsung USB 2.0 PHY driver
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung
SoCs.
+ This driver provides common interface to interact, for Samsung
+ USB 2.0 PHY driver.
+
+config PHY_EXYNOS4210_USB2
+ bool Support for Exynos 4210
+ depends on PHY_EXYNOS_USB2
+ depends on CPU_EXYNOS4210
+ help
+ Enable USB PHY support for Exynos 4210
+
+config PHY_EXYNOS4212_USB2
+ bool Support for Exynos 4212
+ depends on PHY_EXYNOS_USB2
+ depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+ help
+ Enable USB PHY support for Exynos 4212
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..c87bc65 100644
---
[PATCH] clk: samsung: exynos4: Correct SRC_MFC register
The SRC_MFC register was incorrect. This patch corrects it. Signed-off-by: Seung-Woo Kim sw0312@samsung.com --- drivers/clk/samsung/clk-exynos4.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ad5ff50..1a7c1b9 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -39,7 +39,7 @@ #define SRC_TOP1 0xc214 #define SRC_CAM0xc220 #define SRC_TV 0xc224 -#define SRC_MFC0xcc28 +#define SRC_MFC0xc228 #define SRC_G3D0xc22c #define E4210_SRC_IMAGE0xc230 #define SRC_LCD0 0xc234 -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] i2c: s3c2410 : Add polling mode support
Any comments on this patch?
On Mon, Nov 11, 2013 at 4:50 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
From: Vasanth Ananthan vasanthanant...@gmail.com
This patch adds polling mode support for i2c-s3c2410 driver.The
SATA PHY controller's CMU and TRSV block's are of I2C register
map in exynos5250.These blocks can be configured using i2c.
But i2c controller instance on which these block's sits lacks an
interrupt line.Also the current i2c-s3c2410 driver is only interrupt
driven, thus a polling mode support is required in the driver for
supporting this controller. This patch adds this support to the driver.
Changes from V1:
1.Changed the is_ack() to have even period b/w polls and
used usleep_range() instead of udelay().
Signed-off-by: Vasanth Ananthan vasant...@samsung.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
drivers/i2c/busses/i2c-s3c2410.c | 66
+---
2 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index 296eb45..278de8e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
@@ -10,6 +10,8 @@ Required properties:
inside HDMIPHY block found on several samsung SoCs
(d) samsung, exynos5440-i2c, for s3c2440-like i2c used
on EXYNOS5440 which does not need GPIO configuration.
+ (e) samsung, exynos5-sata-phy-i2c, for s3c2440-like i2c used as
+ a host to SATA PHY controller on an internal bus.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-s3c2410.c
b/drivers/i2c/busses/i2c-s3c2410.c
index 3747b9b..08ed126 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -85,6 +85,7 @@
#define QUIRK_S3C2440 (1 0)
#define QUIRK_HDMIPHY (1 1)
#define QUIRK_NO_GPIO (1 2)
+#define QUIRK_POLL (1 3)
/* Max time to wait for bus to become idle after a xfer (in us) */
#define S3C2410_IDLE_TIMEOUT 5000
@@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
};
MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
+static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long
iicstat);
+
#ifdef CONFIG_OF
static const struct of_device_id s3c24xx_i2c_match[] = {
{ .compatible = samsung,s3c2410-i2c, .data = (void *)0 },
@@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
.data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
{ .compatible = samsung,exynos5440-i2c,
.data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
+ { .compatible = samsung,exynos5-sata-phy-i2c,
+ .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
@@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct
s3c24xx_i2c *i2c, int ret)
if (ret)
i2c-msg_idx = ret;
- wake_up(i2c-wait);
+ if (!(i2c-quirks QUIRK_POLL))
+ wake_up(i2c-wait);
}
static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
@@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct
s3c24xx_i2c *i2c)
writel(tmp | S3C2410_IICCON_IRQEN, i2c-regs + S3C2410_IICCON);
}
+static bool is_ack(struct s3c24xx_i2c *i2c)
+{
+ int tries;
+
+ for (tries = 50; tries; --tries) {
+ if (readl(i2c-regs + S3C2410_IICCON)
+S3C2410_IICCON_IRQPEND) {
+ if (!(readl(i2c-regs + S3C2410_IICSTAT)
+S3C2410_IICSTAT_LASTBIT))
+ return true;
+ }
+ usleep_range(1000, 2000);
+ }
+ dev_err(i2c-dev, ack was not recieved\n);
+ return false;
+}
/* s3c24xx_i2c_message_start
*
@@ -268,6 +290,16 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c
*i2c,
stat |= S3C2410_IICSTAT_START;
writel(stat, i2c-regs + S3C2410_IICSTAT);
+
+ if (i2c-quirks QUIRK_POLL) {
+ while ((i2c-msg_num != 0) is_ack(i2c)) {
+ i2c_s3c_irq_nextbyte(i2c, stat);
+ stat = readl(i2c-regs + S3C2410_IICSTAT);
+
+ if (stat S3C2410_IICSTAT_ARBITR)
+ dev_err(i2c-dev, deal with arbitration
loss\n);
+ }
+ }
}
static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
@@ -675,6 +707,15 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c
[PATCH 1/2] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
This patch adds new compatible to support HSI2C module on Exynos5260
HSI2C module on Exynos5260 needs to be reset during during initialization.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|6 +++-
drivers/i2c/busses/i2c-exynos5.c | 31 ++--
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 056732c..704ab92 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -5,7 +5,11 @@ at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
- - samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - samsung,exynos5-hsi2c, for i2c compatible with HSI2C available on
+ Exynos5250/5420 SoCs.
+ - samsung,exynos5260-hsi2c, for i2c compatible with HSI2C available
+ on Exynos5260 SoCs.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index aca3991..cbb49e2 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -184,14 +184,35 @@ struct exynos5_i2c {
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
+
+ /* Version of HS-I2C Hardware */
+ unsigned intversion;
+};
+
+enum hsi2c_version {
+ EXYNOS_5,
+ EXYNOS_5260
};
static const struct of_device_id exynos5_i2c_match[] = {
- { .compatible = samsung,exynos5-hsi2c },
+ {
+ .compatible = samsung,exynos5-hsi2c,
+ .data = (void *)EXYNOS_5 },
+ {
+ .compatible = samsung,exynos5260-hsi2c,
+ .data = (void *)EXYNOS_5260 },
{},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+static inline unsigned int exynos5_i2c_get_version(struct platform_device
*pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos5_i2c_match, pdev-dev.of_node);
+ return (unsigned int)match-data;
+}
+
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c-regs + HSI2C_INT_STATUS),
@@ -692,7 +713,13 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
if (ret)
goto err_clk;
- exynos5_i2c_init(i2c);
+ i2c-version = exynos5_i2c_get_version(pdev);
+
+ /* The HS-I2C core on Exynos5260 needs a reset to start with */
+ if (i2c-version == EXYNOS_5260)
+ exynos5_i2c_reset(i2c);
+ else
+ exynos5_i2c_init(i2c);
ret = i2c_add_adapter(i2c-adap);
if (ret 0) {
--
1.7.10.4
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[PATCH 2/2] i2c: exynos5: configure fifo_depth based on HSI2C module version
fifo_depth of the HSI2C is not constant
Exynos5420 and Exynos5250 supports fifo_depth of 64bytes
Exynos5260 supports fifo_depth of 16bytes
This patch configures the fifo_depth based on HSI2C modules version.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index cbb49e2..19277d8 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -77,12 +77,6 @@
#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) 4)
#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) 16)
-/* As per user manual FIFO max depth is 64bytes */
-#define HSI2C_FIFO_MAX 0x40
-/* default trigger levels for Tx and Rx FIFOs */
-#define HSI2C_DEF_TXFIFO_LVL (HSI2C_FIFO_MAX - 0x30)
-#define HSI2C_DEF_RXFIFO_LVL (HSI2C_FIFO_MAX - 0x10)
-
/* I2C_TRAILING_CTL Register bits */
#define HSI2C_TRAILING_COUNT (0xf)
@@ -187,6 +181,9 @@ struct exynos5_i2c {
/* Version of HS-I2C Hardware */
unsigned intversion;
+
+ /* FIFO depth */
+ unsigned intfifo_depth;
};
enum hsi2c_version {
@@ -437,7 +434,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
fifo_status = readl(i2c-regs + HSI2C_FIFO_STATUS);
fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
- len = HSI2C_FIFO_MAX - fifo_level;
+ len = i2c-fifo_depth - fifo_level;
if (len (i2c-msg-len - i2c-msg_ptr))
len = i2c-msg-len - i2c-msg_ptr;
@@ -505,6 +502,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
u32 i2c_auto_conf = 0;
u32 fifo_ctl;
unsigned long flags;
+ unsigned short trig_lvl;
i2c_ctl = readl(i2c-regs + HSI2C_CTL);
i2c_ctl = ~(HSI2C_TXCHON | HSI2C_RXCHON);
@@ -515,13 +513,19 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
i2c_auto_conf = HSI2C_READ_WRITE;
- fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(HSI2C_DEF_TXFIFO_LVL);
+ trig_lvl = (i2c-msg-len i2c-fifo_depth) ?
+ (i2c-fifo_depth * 3/4) : i2c-msg-len;
+ fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
+
int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
HSI2C_INT_TRAILING_EN);
} else {
i2c_ctl |= HSI2C_TXCHON;
- fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(HSI2C_DEF_RXFIFO_LVL);
+ trig_lvl = (i2c-msg-len i2c-fifo_depth) ?
+ (i2c-fifo_depth * 1/4) : i2c-msg-len;
+ fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
+
int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
}
@@ -716,10 +720,13 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
i2c-version = exynos5_i2c_get_version(pdev);
/* The HS-I2C core on Exynos5260 needs a reset to start with */
- if (i2c-version == EXYNOS_5260)
+ if (i2c-version == EXYNOS_5260) {
+ i2c-fifo_depth = 16;
exynos5_i2c_reset(i2c);
- else
+ } else {
+ i2c-fifo_depth = 64;
exynos5_i2c_init(i2c);
+ }
ret = i2c_add_adapter(i2c-adap);
if (ret 0) {
--
1.7.10.4
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Re: [PATCH 1/2] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
On Fri, Nov 22, 2013 at 11:42 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch adds new compatible to support HSI2C module on Exynos5260
HSI2C module on Exynos5260 needs to be reset during during initialization.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|6 +++-
drivers/i2c/busses/i2c-exynos5.c | 31
++--
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 056732c..704ab92 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -5,7 +5,11 @@ at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
- - samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - samsung,exynos5-hsi2c, for i2c compatible with HSI2C available on
+ Exynos5250/5420 SoCs.
+ - samsung,exynos5260-hsi2c, for i2c compatible with HSI2C available
+ on Exynos5260 SoCs.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-exynos5.c
b/drivers/i2c/busses/i2c-exynos5.c
index aca3991..cbb49e2 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -184,14 +184,35 @@ struct exynos5_i2c {
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
+
+ /* Version of HS-I2C Hardware */
+ unsigned intversion;
+};
+
+enum hsi2c_version {
+ EXYNOS_5,
+ EXYNOS_5260
};
static const struct of_device_id exynos5_i2c_match[] = {
- { .compatible = samsung,exynos5-hsi2c },
+ {
+ .compatible = samsung,exynos5-hsi2c,
+ .data = (void *)EXYNOS_5 },
+ {
+ .compatible = samsung,exynos5260-hsi2c,
+ .data = (void *)EXYNOS_5260 },
{},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+static inline unsigned int exynos5_i2c_get_version(struct platform_device
*pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos5_i2c_match, pdev-dev.of_node);
+ return (unsigned int)match-data;
+}
+
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c-regs + HSI2C_INT_STATUS),
@@ -692,7 +713,13 @@ static int exynos5_i2c_probe(struct platform_device
*pdev)
if (ret)
goto err_clk;
- exynos5_i2c_init(i2c);
+ i2c-version = exynos5_i2c_get_version(pdev);
+
+ /* The HS-I2C core on Exynos5260 needs a reset to start with */
+ if (i2c-version == EXYNOS_5260)
Is there is any change in the HSI2C IP for EXYNOS5260?
Can you let me know whats the change w.r.t IP and
why it needs reset to start,which was not needed in earlier SOC?
+ exynos5_i2c_reset(i2c);
+ else
+ exynos5_i2c_init(i2c);
ret = i2c_add_adapter(i2c-adap);
if (ret 0) {
--
1.7.10.4
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Re: [PATCH 1/2] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
Hello Yuvaraj,
On 22 November 2013 12:16, Yuvaraj Cd yuvaraj.l...@gmail.com wrote:
On Fri, Nov 22, 2013 at 11:42 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch adds new compatible to support HSI2C module on Exynos5260
HSI2C module on Exynos5260 needs to be reset during during initialization.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|6 +++-
drivers/i2c/busses/i2c-exynos5.c | 31
++--
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 056732c..704ab92 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -5,7 +5,11 @@ at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
- - samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - samsung,exynos5-hsi2c, for i2c compatible with HSI2C available
on
+ Exynos5250/5420 SoCs.
+ - samsung,exynos5260-hsi2c, for i2c compatible with HSI2C
available
+ on Exynos5260 SoCs.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-exynos5.c
b/drivers/i2c/busses/i2c-exynos5.c
index aca3991..cbb49e2 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -184,14 +184,35 @@ struct exynos5_i2c {
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
+
+ /* Version of HS-I2C Hardware */
+ unsigned intversion;
+};
+
+enum hsi2c_version {
+ EXYNOS_5,
+ EXYNOS_5260
};
static const struct of_device_id exynos5_i2c_match[] = {
- { .compatible = samsung,exynos5-hsi2c },
+ {
+ .compatible = samsung,exynos5-hsi2c,
+ .data = (void *)EXYNOS_5 },
+ {
+ .compatible = samsung,exynos5260-hsi2c,
+ .data = (void *)EXYNOS_5260 },
{},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+static inline unsigned int exynos5_i2c_get_version(struct platform_device
*pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos5_i2c_match, pdev-dev.of_node);
+ return (unsigned int)match-data;
+}
+
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c-regs + HSI2C_INT_STATUS),
@@ -692,7 +713,13 @@ static int exynos5_i2c_probe(struct platform_device
*pdev)
if (ret)
goto err_clk;
- exynos5_i2c_init(i2c);
+ i2c-version = exynos5_i2c_get_version(pdev);
+
+ /* The HS-I2C core on Exynos5260 needs a reset to start with */
+ if (i2c-version == EXYNOS_5260)
Is there is any change in the HSI2C IP for EXYNOS5260?
Can you let me know whats the change w.r.t IP and
why it needs reset to start,which was not needed in earlier SOC?
Problem:
While working on HSI2C on uboot for Exynos5260 i faced a problem.
To operate on bus 0 which was default bus
If i try i2c md/mw on channel 0 without selecting the bus using i2c dev 0
the transaction was failing. But, the subsequent transactions were passing.
Software Work around:
After looking at the code i found out, resetting the bus for the first
time made it work.
Hardware engg suggestion:
Meanwhile inputs from Hardware engineers are, HSI2C on Exynos5260 needs a reset
during init. I've not gone personally into the internals of HSI2C module.
From user manual for Exynos5260, FIFO depth supported is 16bytes
instead of 64bytes.
+ exynos5_i2c_reset(i2c);
+ else
+ exynos5_i2c_init(i2c);
ret = i2c_add_adapter(i2c-adap);
if (ret 0) {
--
1.7.10.4
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--
Shine bright,
(: Nav :)
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I want to add dts for a exynos4412 board but usb doesn't work
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
The board is FriendlyArm tiny4412 ver.1306.
I have made the mmc2(sd slot) work and place rootfs in it.
But I failed in usbhost part(not otg which has been broken by me),
which works properly in manufacturer's kernel.
I can't find the ehci controller and root hub at all.
In this board, the usb host is conntected to a external hub to change
voltage level.
in dmesg, log shows as below:
[1.075000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[1.075000] ehci-exynos: EHCI EXYNOS driver
[1.075000] unable to find transceiver of type USB2 PHY
[1.075000] exynos-ehci 1258.ehci: no platform data or
transceiver defined
[1.085000] platform 1258.ehci: Driver exynos-ehci requests
probe deferral
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.12 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
iQEcBAEBAgAGBQJSjwn3AAoJEPb4VsMIzTziaFIH/0wxwYrSp0HCSQtCN8v4g9Vj
2YxATdQ/SeTLN6F+h6ggooIlaWOUyH2H+yz73T4YYnh+swqPUGyBoXa6KZNep2na
O9xCNWSntELXHKJqrVFPBOBSWkhqf71q4DbApWHZYMvVCa1UhAYqg6AFy5M3gMWl
jbMd5SBDwKjIioJhgOgqGa1w2HUp8QNmCACtKl+YagTBNAdv3BJr7egKhWoRqOQR
INk2kb3UeptmKeTL08uUcgxMxEAn/W+r53FBjbvuU+TKMccj48kpWpZ513hfKKva
W9NmaLWDiuV73kz135o/955lCO7wdrs2cVtp37g6BCc0U+RdUI3tqwyswYFWwg4=
=suW2
-END PGP SIGNATURE-
/*
* Hardkernel's Exynos4412 based tiny4412 1306 board device tree source
*
* Copyright (c) 2013 Tomoya Gitsufuki ay...@mail.soulik.info
*
* Device tree source file for Friendyarm tiny4412 1306 board which is based on
* Samsung's Exynos4412 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include exynos4412.dtsi
/ {
model = Friendly Arm Tiny4412 1306 board based on Exynos4412;
compatible = friendlyarm,tiny4412-1306, samsung,exynos4412;
memory {
reg = 0x4000 0x4000;
};
chosen {
bootargs =root=/dev/mmcblk0p1 rootfstype=ext4 rw
console=ttySAC0,115200 init=/sbin/init;
};
leds {
compatible = gpio-leds;
led1 {
label = led1:heart;
gpios = gpm4 0 1;
default-state = on;
linux,default-trigger = heartbeat;
};
led2 {
label = led2:mmc0;
gpios = gpm4 1 1;
default-state = on;
linux,default-trigger = mmc0;
};
};
regulators {
compatible = simple-bus;
#address-cells = 1;
vemmc_reg: regulator-0 {
compatible = regulator-fixed;
regulator-name = VMEM_VDD_2.8V;
regulator-max-microvolt = 280;
regulator-min-microvolt = 280;
gpio = gpk0 2 0;
enable-active-high;
};
};
/*
mshc@1255 {
#address-cells = 1;
#size-cells = 0;
pinctrl-0 = sd4_clk sd4_cmd sd4_bus4 sd4_bus8;
pinctrl-names = default;
status = okay;
vmmc-supply = vemmc_reg;
clocks = clock 301, clock 149;
clocks-name = dwmci, sclk_dwmci;
clock-frequency = 4;
num-slots = 1;
supports-highspeed;
broken-cd;
fifo-depth = 0x80;
card-detect-delay = 200;
samsung,dw-mshc-sdr-timing = 2 3;
samsung,dw-mshc-ddr-timing = 1 2;
slot@0 {
reg = 0;
bus-width = 8;
};
};
*/
rtc@1007 {
status = okay;
};
sdhci@1253 {
bus-width = 4;
pinctrl-0 = sd2_clk sd2_cmd sd2_bus4 sd2_cd;
pinctrl-names = default;
status = okay;
};
sdhci@1254000 {
bus-width = 4;
pinctrl-0 = sd3_clk sd3_cmd sd3_bus4 sd3_cd;
pinctrl-names = default;
status = okay;
};
usbhost0@1258 {
#address-cells = 1;
#size-cells = 1;
compatible = samsung,exynos4210-usbphy;
reg = 0x1258 0x100;
ranges;
clocks = clock 2, clock 304;
clock-names = xusbxti, usbhost;
usbphy-sys {
/* USB device and host PHY_CONTROL registers */
reg = 0x10020708 0x8;
};
};
otg@125B {
#address-cells
