[PATCH] ARM: s3c24xx: get rid of custom
This isolates the custom S3C24xx GPIO definition table to as this is used in a few different places in the kernel, removing the need to depend on the implicit inclusion of from and thus getting rid of a few nasty cross-dependencies. We also delete the nifty CONFIG_S3C24XX_GPIO_EXTRA stuff. The biggest this can ever be for the S3C24XX is CONFIG_S3C24XX_GPIO_EXTRA = 128, and then for CPU_S3C2443 or CPU_S3C2416 32*12 GPIOs are added, so 32*12+128 = 512 is the absolute roof value on this platform. So we set the size of ARCH_NR_GPIO to this and the GPIOs array will fit any S3C24XX platform, as per pattern from other archs. Cc: Heiko Stuebner Cc: Tomasz Figa Cc: Sylwester Nawrocki Cc: Ben Dooks Cc: Kukjin Kim Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Linus Walleij --- If one of the maintainers give me an ACK for this I will take it through the GPIO tree. --- arch/arm/Kconfig | 3 +- arch/arm/mach-s3c24xx/Kconfig | 21 arch/arm/mach-s3c24xx/common-smdk.c| 2 +- arch/arm/mach-s3c24xx/h1940-bluetooth.c| 1 + arch/arm/mach-s3c24xx/include/mach/gpio.h | 114 - arch/arm/mach-s3c24xx/mach-amlm5900.c | 1 + arch/arm/mach-s3c24xx/mach-anubis.c| 1 + arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 + arch/arm/mach-s3c24xx/mach-bast.c | 1 + arch/arm/mach-s3c24xx/mach-gta02.c | 1 + arch/arm/mach-s3c24xx/mach-h1940.c | 1 + arch/arm/mach-s3c24xx/mach-jive.c | 1 + arch/arm/mach-s3c24xx/mach-mini2440.c | 1 + arch/arm/mach-s3c24xx/mach-n30.c | 1 + arch/arm/mach-s3c24xx/mach-nexcoder.c | 1 + arch/arm/mach-s3c24xx/mach-osiris.c| 1 + arch/arm/mach-s3c24xx/mach-qt2410.c| 1 + arch/arm/mach-s3c24xx/mach-rx1950.c| 1 + arch/arm/mach-s3c24xx/mach-rx3715.c| 1 + arch/arm/mach-s3c24xx/mach-smdk2413.c | 1 + arch/arm/mach-s3c24xx/mach-smdk2416.c | 1 + arch/arm/mach-s3c24xx/mach-vr1000.c| 1 + arch/arm/mach-s3c24xx/pm-s3c2410.c | 1 + arch/arm/mach-s3c24xx/pm.c | 1 + arch/arm/mach-s3c24xx/s3c2410.c| 1 + arch/arm/mach-s3c24xx/s3c2416.c| 1 + arch/arm/mach-s3c24xx/s3c2440.c| 1 + arch/arm/mach-s3c24xx/s3c2442.c| 1 + arch/arm/mach-s3c24xx/s3c2443.c| 1 + arch/arm/mach-s3c24xx/setup-i2c.c | 1 + arch/arm/mach-s3c24xx/setup-sdhci-gpio.c | 1 + arch/arm/mach-s3c24xx/setup-ts.c | 1 + arch/arm/mach-s3c24xx/simtec-usb.c | 1 + arch/arm/plat-samsung/pm-gpio.c| 1 + arch/arm/plat-samsung/setup-camif.c| 1 + drivers/gpio/gpio-samsung.c| 1 + drivers/mmc/host/s3cmci.c | 1 + include/linux/platform_data/gpio-samsung-s3c24xx.h | 106 +++ 38 files changed, 141 insertions(+), 138 deletions(-) delete mode 100644 arch/arm/mach-s3c24xx/include/mach/gpio.h create mode 100644 include/linux/platform_data/gpio-samsung-s3c24xx.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1f1a7eee953..6a26bcb3a63a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -710,7 +710,6 @@ config ARCH_S3C24XX select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select MULTI_IRQ_HANDLER - select NEED_MACH_GPIO_H select NEED_MACH_IO_H select SAMSUNG_ATAGS help @@ -1593,7 +1592,7 @@ config ARM_PSCI config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA - default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX + default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX default 392 if ARCH_U8500 default 352 if ARCH_VT8500 default 288 if ARCH_SUNXI diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 8f1d327e0cd1..d876431d64c0 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -180,27 +180,6 @@ config CPU_LLSERIAL_S3C2440 Selected if there is an S3C2440 (or register compatible) serial low-level implementation needed -# gpio configurations - -config S3C24XX_GPIO_EXTRA - int - default 128 if S3C24XX_GPIO_EXTRA128 - default 64 if S3C24XX_GPIO_EXTRA64 - default 16 if ARCH_H1940 - default 0 - -config S3C24XX_GPIO_EXTRA64 - bool - help - Add an extra 64 gpio numbers to the available GPIO pool. This is - available for boards that need extra gpios for external devices. - -config S3C24XX_GPIO_EXTRA128 -
[PATCH 0/3] Exynos5420 Cpufreq support
The patch series adds the cpufreq driver for exynos5420 with its dependencies. This initial version of the driver only modifies the A15 core frequencies. Arjun.K.V (1): cpufreq: exynos: Add exynos5420 cpufreq driver Arun Kumar K (2): ARM: EXYNOS: Add exynos5 CPU clock divider offsets clk: exynos5420: Add alias names for cpu clocks arch/arm/mach-exynos/include/mach/regs-clock.h | 24 ++ drivers/clk/samsung/clk-exynos5420.c |9 +- drivers/cpufreq/Kconfig.arm| 11 + drivers/cpufreq/Makefile |1 + drivers/cpufreq/exynos-cpufreq.c |2 + drivers/cpufreq/exynos-cpufreq.h |8 + drivers/cpufreq/exynos5420-cpufreq.c | 346 7 files changed, 397 insertions(+), 4 deletions(-) create mode 100644 drivers/cpufreq/exynos5420-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: EXYNOS: Add exynos5 CPU clock divider offsets
Adds the CPU clock divider shifts and masks for Exynos5 SoC. These defines will be used in cpufreq driver. Signed-off-by: Arjun.K.V Signed-off-by: Arun Kumar K --- arch/arm/mach-exynos/include/mach/regs-clock.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76..d0186d3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -347,6 +347,30 @@ #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) +/* CLK_DIV_CPU0 */ +#define EXYNOS5_CLKDIV_CPU0_CORE_SHIFT 0 +#define EXYNOS5_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CORE_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT 4 +#define EXYNOS5_CLKDIV_CPU0_CPUD_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_ACP_SHIFT 8 +#define EXYNOS5_CLKDIV_CPU0_ACP_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_ACP_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_ATB_SHIFT 16 +#define EXYNOS5_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_ATB_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT 20 +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_APLL_SHIFT 24 +#define EXYNOS5_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_APLL_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT28 +#define EXYNOS5_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT) + +/* CLK_DIV_CPU1 */ +#define EXYNOS5_CLKDIV_CPU1_COPY_SHIFT 0 +#define EXYNOS5_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS5_CLKDIV_CPU1_COPY_SHIFT) +#define EXYNOS5_CLKDIV_CPU1_HPM_SHIFT 4 +#define EXYNOS5_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS5_CLKDIV_CPU1_HPM_SHIFT) +#define EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT 16 +#define EXYNOS5_CLKMUX_STATCPU_MUXCORE_MASK(0x7 << EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT) + #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] cpufreq: exynos: Add exynos5420 cpufreq driver
From: "Arjun.K.V"
The patch adds cpufreq driver for exynos5420.
Signed-off-by: Arjun.K.V
Signed-off-by: Andrew Bresticker
Signed-off-by: Arun Kumar K
---
drivers/cpufreq/Kconfig.arm | 11 ++
drivers/cpufreq/Makefile |1 +
drivers/cpufreq/exynos-cpufreq.c |2 +
drivers/cpufreq/exynos-cpufreq.h |8 +
drivers/cpufreq/exynos5420-cpufreq.c | 346 ++
5 files changed, 368 insertions(+)
create mode 100644 drivers/cpufreq/exynos5420-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index ce52ed9..96769fe 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -51,6 +51,17 @@ config ARM_EXYNOS5250_CPUFREQ
If in doubt, say N.
+config ARM_EXYNOS5420_CPUFREQ
+ bool "SAMSUNG EXYNOS5420"
+ depends on SOC_EXYNOS5420
+ default y
+ select ARM_EXYNOS_CPUFREQ
+ help
+ This adds the CPUFreq driver for Samsung EXYNOS5420
+ SoC.
+
+ If in doubt, say N.
+
config ARM_EXYNOS5440_CPUFREQ
bool "SAMSUNG EXYNOS5440"
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 7494565..802c251 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
+obj-$(CONFIG_ARM_EXYNOS5420_CPUFREQ) += exynos5420-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index f3c2287..ac556eb 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -246,6 +246,8 @@ static int __init exynos_cpufreq_init(void)
ret = exynos4x12_cpufreq_init(exynos_info);
else if (soc_is_exynos5250())
ret = exynos5250_cpufreq_init(exynos_info);
+ else if (soc_is_exynos5420())
+ ret = exynos5420_cpufreq_init(exynos_info);
else
return 0;
diff --git a/drivers/cpufreq/exynos-cpufreq.h b/drivers/cpufreq/exynos-cpufreq.h
index 7f25cee..d2f3d1e 100644
--- a/drivers/cpufreq/exynos-cpufreq.h
+++ b/drivers/cpufreq/exynos-cpufreq.h
@@ -67,3 +67,11 @@ static inline int exynos5250_cpufreq_init(struct
exynos_dvfs_info *info)
return -EOPNOTSUPP;
}
#endif
+#ifdef CONFIG_ARM_EXYNOS5420_CPUFREQ
+extern int exynos5420_cpufreq_init(struct exynos_dvfs_info *);
+#else
+static inline int exynos5420_cpufreq_init(struct exynos_dvfs_info *info)
+{
+ return -EOPNOTSUPP;
+}
+#endif
diff --git a/drivers/cpufreq/exynos5420-cpufreq.c
b/drivers/cpufreq/exynos5420-cpufreq.c
new file mode 100644
index 000..728ce71
--- /dev/null
+++ b/drivers/cpufreq/exynos5420-cpufreq.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS5420 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "exynos-cpufreq.h"
+
+#define CPUFREQ_NUM_LEVELS (L18 + 1)
+#define EXYNOS5_CLKDIV_STATCPU0_MASK 0x
+#define EXYNOS5_CLKDIV_STATCPU1_MASK 0x111
+
+static struct clk *mout_cpu;
+static struct clk *mout_mspll_cpu;
+static struct clk *mout_apll;
+static struct clk *fout_apll;
+static struct clk *fout_spll;
+
+struct cpufreq_clkdiv {
+ unsigned intindex;
+ unsigned intclkdiv;
+ unsigned intclkdiv1;
+};
+
+static unsigned int exynos5420_volt_table[CPUFREQ_NUM_LEVELS];
+static struct cpufreq_frequency_table exynos5420_freq_table[] = {
+ {L0, 2000 * 1000},
+ {L1, 1900 * 1000},
+ {L2, 1800 * 1000},
+ {L3, 1700 * 1000},
+ {L4, 1600 * 1000},
+ {L5, 1500 * 1000},
+ {L6, 1400 * 1000},
+ {L7, 1300 * 1000},
+ {L8, 1200 * 1000},
+ {L9, 1100 * 1000},
+ {L10, 1000 * 1000},
+ {L11, 900 * 1000},
+ {L12, 800 * 1000},
+ {L13, 700 * 1000},
+ {L14, 600 * 1000},
+ {L15, 500 * 1000},
+ {L16, 400 * 1000},
+ {L17, 300 * 1000},
+ {L18, 200 * 1000},
+ {0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos5420_clkdiv_table[CPUFREQ_NUM_LEVELS];
+
+static unsigned int clkdiv_cpu0_5420[CPUFREQ_NUM_LEVELS][7] = {
+ /*
+* Clock divider values for {CPUD, ATB, PCLK_DBG, APLL, ARM2}
+*/
+ { 2, 7, 7, 3, 0 }, /*
[PATCH 2/3] clk: exynos5420: Add alias names for cpu clocks
Adds alias names for cpu clocks to be used in the cpufreq driver.
Signed-off-by: Arun Kumar K
---
drivers/clk/samsung/clk-exynos5420.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 48c4a93..c65c040 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -316,9 +316,10 @@ static struct samsung_fixed_factor_clock
exynos5420_fixed_factor_clks[] __initda
static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
- MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1),
- MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
+ MUX_A(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2,
+ "mout_mspll_cpu"),
+ MUX_A(none, "mout_apll", apll_p, SRC_CPU, 0, 1, "mout_apll"),
+ MUX_A(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
@@ -373,7 +374,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[]
__initdata = {
MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
- MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
+ MUX_A(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1, "mout_spll"),
MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
--
1.7.9.5
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[PATCH v4 6/9] phy: Add support for S5PV210 to the Exynos USB PHY driver
From: Mateusz Krawczuk
Add support for the Samsung's S5PV210 SoC to the Exynos USB PHY driver.
Signed-off-by: Mateusz Krawczuk
[k.deb...@samsung.com: cleanup and commit description]
[k.deb...@samsung.com: make changes accordingly to the mailing list
comments]
Signed-off-by: Kamil Debski
Signed-off-by: Kyungmin Park
---
.../devicetree/bindings/phy/samsung-usbphy.txt |1 +
drivers/phy/Kconfig|7 +
drivers/phy/Makefile |1 +
drivers/phy/phy-s5pv210-usb2.c | 206
drivers/phy/phy-samsung-usb2.c |6 +
drivers/phy/phy-samsung-usb2.h |1 +
6 files changed, 222 insertions(+)
create mode 100644 drivers/phy/phy-s5pv210-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
index cadbf70..77a8e9c 100644
--- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
@@ -3,6 +3,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
Required properties:
- compatible : should be one of the listed compatibles:
+ - "samsung,s5pv210-usb2-phy"
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4212-usb2-phy"
- reg : a list of registers used by phy driver
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index b29018f..2e433cd 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -58,6 +58,13 @@ config PHY_SAMSUNG_USB2
This driver provides common interface to interact, for Samsung
USB 2.0 PHY driver.
+config PHY_S5PV210_USB2
+ bool "Support for S5PV210"
+ depends on PHY_SAMSUNG_USB2
+ depends on ARCH_S5PV210
+ help
+ Enable USB PHY support for S5PV210
+
config PHY_EXYNOS4210_USB2
bool "Support for Exynos 4210"
depends on PHY_SAMSUNG_USB2
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9f4befd..fefc6c2 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) +=
phy-exynos-mipi-video.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o
+obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
obj-$(CONFIG_PHY_EXYNOS4212_USB2) += phy-exynos4212-usb2.o
diff --git a/drivers/phy/phy-s5pv210-usb2.c b/drivers/phy/phy-s5pv210-usb2.c
new file mode 100644
index 000..528a114
--- /dev/null
+++ b/drivers/phy/phy-s5pv210-usb2.c
@@ -0,0 +1,206 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Kamil Debski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define S5PV210_UPHYPWR0x0
+
+#define S5PV210_UPHYPWR_PHY0_SUSPEND (1 << 0)
+#define S5PV210_UPHYPWR_PHY0_PWR (1 << 3)
+#define S5PV210_UPHYPWR_PHY0_OTG_PWR (1 << 4)
+#define S5PV210_UPHYPWR_PHY0 ( \
+ S5PV210_UPHYPWR_PHY0_SUSPEND | \
+ S5PV210_UPHYPWR_PHY0_PWR | \
+ S5PV210_UPHYPWR_PHY0_OTG_PWR)
+
+#define S5PV210_UPHYPWR_PHY1_SUSPEND (1 << 6)
+#define S5PV210_UPHYPWR_PHY1_PWR (1 << 7)
+#define S5PV210_UPHYPWR_PHY1 ( \
+ S5PV210_UPHYPWR_PHY1_SUSPEND | \
+ S5PV210_UPHYPWR_PHY1_PWR)
+
+/* PHY clock control */
+#define S5PV210_UPHYCLK0x4
+
+#define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
+#define S5PV210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
+
+#define S5PV210_UPHYCLK_PHY0_ID_PULLUP (0x1 << 2)
+#define S5PV210_UPHYCLK_PHY0_COMMON_ON (0x1 << 4)
+#define S5PV210_UPHYCLK_PHY1_COMMON_ON (0x1 << 7)
+
+/* PHY reset control */
+#define S5PV210_UPHYRST0x8
+
+#define S5PV210_URSTCON_PHY0 (1 << 0)
+#define S5PV210_URSTCON_OTG_HLINK (1 << 1)
+#define S5PV210_URSTCON_OTG_PHYLINK(1 << 2)
+#define S5PV210_URSTCON_PHY1_ALL (1 << 3)
+#define S5PV210_URSTCON_HOST_LINK_ALL (1 << 4)
+
+/* Isolation, configured in the power management unit */
+#define S5PV210_USB_ISOL_DEVICE_OFFSET 0x704
+#define S5PV210_USB_ISOL_DEVICE(1 << 0)
+#define S5PV210_USB_ISOL_HOST_OFFSET 0x708
+#define S5PV210_USB_ISOL_HOST (1 << 1)
+
+
+enum s5pv210_phy_id {
+ S5PV210_DEVICE,
+ S5PV210
[PATCH 8/9] dts: Add usb2phy to Exynos 4
Add support of new USB 2.0 phy driver to Exynos 4 SoC device tree.
Signed-off-by: Kamil Debski
Signed-off-by: Kyungmin Park
---
.../devicetree/bindings/arm/samsung/pmu.txt|2 ++
arch/arm/boot/dts/exynos4.dtsi | 31
arch/arm/boot/dts/exynos4210.dtsi | 17 +++
arch/arm/boot/dts/exynos4x12.dtsi | 17 +++
4 files changed, 67 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 307e727..bfccab0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -3,6 +3,8 @@ SAMSUNG Exynos SoC series PMU Registers
Properties:
- name : should be 'syscon';
- compatible : should contain two values. First value must be one from
following list:
+ - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
+ - "samsung,exynos4212-pmu" - for Exynos4212 SoC,
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
second value must be always "syscon".
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a73eeb5..031d07a 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -253,6 +253,17 @@
status = "disabled";
};
+ usbotg@1248 {
+ compatible = "samsung,s3c6400-hsotg";
+ reg = <0x1248 0x2>;
+ interrupts = <0 71 0>;
+ clocks = <&clock 305>;
+ clock-names = "otg";
+ phys = <&usb2phy 0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
ehci@1258 {
compatible = "samsung,exynos4210-ehci";
reg = <0x1258 0x100>;
@@ -260,6 +271,26 @@
clocks = <&clock 304>;
clock-names = "usbhost";
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ phys = <&usb2phy 1>;
+ phy-names = "host";
+ reg = <0>;
+ status = "disabled";
+ };
+ port@1 {
+ phys = <&usb2phy 2>;
+ phy-names = "hsic0";
+ reg = <1>;
+ status = "disabled";
+ };
+ port@2 {
+ phys = <&usb2phy 3>;
+ phy-names = "hsic1";
+ reg = <2>;
+ status = "disabled";
+ };
};
ohci@1259 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 057d682..f9d06bb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -155,4 +155,21 @@
samsung,lcd-wb;
};
};
+
+ pmu_reg: syscon@1002 {
+ compatible = "samsung,exynos4210-pmu", "syscon";
+ reg = <0x1002 0x4000>;
+ };
+
+ usb2phy: phy@125B {
+ compatible = "samsung,exynos4210-usb2-phy";
+ reg = <0x125B 0x100>;
+ clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+ <&clock 2>;
+ clock-names = "phy", "device", "host", "hsic0", "hsic1";
+ status = "disabled";
+ #phy-cells = <1>;
+ samsung,sysreg-phandle = <&sys_reg>;
+ samsung,pmureg-phandle = <&pmu_reg>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe..712 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -176,4 +176,21 @@
};
};
};
+
+ pmu_reg: syscon@1002 {
+ compatible = "samsung,exynos4212-pmu", "syscon";
+ reg = <0x1002 0x4000>;
+ };
+
+ usb2phy: phy@125B {
+ compatible = "samsung,exynos4212-usb2-phy";
+ reg = <0x125B 0x100>;
+ clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+ <&clock 2>;
+ clock-names = "phy", "device", "host", "hsic0", "hsic1";
+ status = "disabled";
+ #phy-cells = <1>;
+ samsung,sysreg-phandle = <&sys_reg>;
+ samsung,pmureg-phandle = <&pmu_reg>;
+ };
};
--
1.7.9.5
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[PATCH v4 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski Signed-off-by: Kyungmin Park --- .../devicetree/bindings/phy/samsung-usbphy.txt |1 + drivers/phy/Kconfig|8 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5250-usb2.c | 363 drivers/phy/phy-samsung-usb2.c |6 + drivers/phy/phy-samsung-usb2.h |1 + 6 files changed, 380 insertions(+) create mode 100644 drivers/phy/phy-exynos5250-usb2.c diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt index 77a8e9c..94096fc 100644 --- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt @@ -6,6 +6,7 @@ Required properties: - "samsung,s5pv210-usb2-phy" - "samsung,exynos4210-usb2-phy" - "samsung,exynos4212-usb2-phy" + - "samsung,exynos5250-usb2-phy" - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers - samsung,sysreg-phandle - handle to syscon used to control the system registers diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 2e433cd..74e9064 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -78,4 +78,12 @@ config PHY_EXYNOS4212_USB2 depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) help Enable USB PHY support for Exynos 4212 + +config PHY_EXYNOS5250_USB2 + bool "Support for Exynos 5250" + depends on PHY_SAMSUNG_USB2 + depends on SOC_EXYNOS5250 + help + Enable USB PHY support for Exynos 5250 + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index fefc6c2..33c3ac1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_SAMSUNG_USB2)+= phy-samsung-usb2.o obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4212_USB2) += phy-exynos4212-usb2.o +obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c new file mode 100644 index 000..7aeebc8 --- /dev/null +++ b/drivers/phy/phy-exynos5250-usb2.c @@ -0,0 +1,363 @@ +/* + * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Kamil Debski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "phy-samsung-usb2.h" + +/* Exynos USB PHY registers */ +#define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0 +#define EXYNOS_5250_REFCLKSEL_XO 0x1 +#define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2 + +#define EXYNOS_5250_FSEL_9MHZ6 0x0 +#define EXYNOS_5250_FSEL_10MHZ 0x1 +#define EXYNOS_5250_FSEL_12MHZ 0x2 +#define EXYNOS_5250_FSEL_19MHZ20x3 +#define EXYNOS_5250_FSEL_20MHZ 0x4 +#define EXYNOS_5250_FSEL_24MHZ 0x5 +#define EXYNOS_5250_FSEL_50MHZ 0x7 + +/* Normal host */ +#define EXYNOS_5250_HOSTPHYCTRL0 0x0 + +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL (0x1 << 31) +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19 +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK\ + (0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT16 +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \ + (0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN(0x1 << 11) +#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE (0x1 << 10) +#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N (0x1 << 9) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK(0x3 << 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL(0x0 << 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 << 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST (0x2 << 7) +#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ (0x1 << 6) +#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP(0x1 << 5) +#define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND (0x1 << 4) +#define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE (0x1 << 3) +#define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST (0x1 << 2) +#define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST (0x1 << 1) +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST (0x1 << 0) + +/* HSIC0 & HSCI1 */ +#define EXYNOS_5250_HOSTPHYCTRL1
[PATCH 9/9] dts: Add usb2phy to Exynos 5250
Add support of new USB 2.0 phy driver to the Exynos 5250 SoC device tree.
Signed-off-by: Kamil Debski
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5250.dtsi | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 2f264ad..922e0ed 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -163,6 +163,11 @@
interrupts = <0 47 0>;
};
+ sys_syscon: syscon@1004 {
+ compatible = "samsung,exynos5250-sys", "syscon";
+ reg = <0x1005 0x5000>;
+ };
+
pmu_syscon: syscon@1004 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x1004 0x5000>;
@@ -505,6 +510,14 @@
clocks = <&clock 285>;
clock-names = "usbhost";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&usb2_phy 1>;
+ phy-names = "host";
+ status = "ok";
+ };
};
usb@1212 {
@@ -516,19 +529,15 @@
clock-names = "usbhost";
};
- usb2_phy: usbphy@1213 {
- compatible = "samsung,exynos5250-usb2phy";
+ usb2_phy: phy@1213 {
+ compatible = "samsung,exynos5250-usb2-phy";
reg = <0x1213 0x100>;
- clocks = <&clock 1>, <&clock 285>;
- clock-names = "ext_xtal", "usbhost";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbphy-sys {
- reg = <0x10040704 0x8>,
- <0x10050230 0x4>;
- };
+ clocks = <&clock 285>, <&clock 1>, <&clock 1>, <&clock 1>,
+ <&clock 1>;
+ clock-names = "phy", "device", "host", "hsic0", "hsic1";
+ #phy-cells = <1>;
+ samsung,sysreg-phandle = <&sys_syscon>;
+ samsung,pmureg-phandle = <&pmu_syscon>;
};
amba {
--
1.7.9.5
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RE: [PATCH v4 0/9] phy: Add new Exynos USB 2.0 PHY driver
Hi, > From: Kishon Vijay Abraham I [mailto:kis...@ti.com] > Sent: Thursday, December 05, 2013 4:07 PM > > Hi, > > On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote: > > Hi, > > > > This is the fourth version of the patchset adding the new Exynos USB > > 2.0 PHY driver. The driver uses the Generic PHY Framework. > > > > A month has passed since the last version. I have addressed numerous > > comments that appeared on the mailing list in this patch. I would > like > > to specially thank Kishon, Tomasz, Matt and Vivek for their comments. > > > > This patch contains two necessary patches to the phy core. > > It is very useful to be able to get phy using a device tree node. > > > > In addition this patch depends on: > > [PATCH V11 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and > > exynos5420 dtsi files [1]. > > > > Best wishes, > > Kamil Debski > > The last four patches are missing [1] I am sorry, git send-email failed on the 6th patch thus that and the Following patches were not sent. I guess it is the Murphy's law, sending patches just before leaving office had high chances of such a mishap. Best wishes, -- Kamil Debski Samsung R&D Institute Poland > [1] -> https://lkml.org/lkml/2013/12/5/166 > > Thanks > Kishon > > > > [1] - http://www.spinics.net/lists/linux-samsung-soc/msg24528.html > > > > > > Changes from v3: > > - using PMU and system registers indirectly via syscon > > - change labelling > > - change Kconfig name > > - fixed typos/stray whitespace > > - move of_phy_provider_register() to the end of probe > > - add a regular error return code to the rate_to_clk functions > > - cleanup code and remove unused code > > - change struct names to avoid collisions > > - add mechanism to support multiple phys by the ehci driver > > > > > > Changes from v2: > > - rebase all patches to the usb-next branch > > - fixes in the documentation file > > - remove wrong entries in the phy node (ranges, and #address- & > #size-cells) > > - add clocks and clock-names as required properites > > - rephrase a few sentences > > - fixes in the ehci-exynos.c file > > - move phy_name variable next to phy in exynos_ehci_hcd > > - remove otg from exynos_ehci_hcd as it was no longer used > > - move devm_phy_get after the Exynos5440 skip_phy check > > - fixes in the s3c-hsotg.c file > > - cosmetic fixes (remove empty line that was wrongfully added) > > - fixes in the main driver > > - remove cpu_type in favour for a boolean flag matched with the > compatible > > value > > - rename files, structures, variables and Kconfig entires - change > from simple > > "uphy" to "usb2_phy" > > - fix multiline comments style > > - simplify #ifdefs in of_device_id > > - fix Kconfig description > > - change dev_info to dev_dbg where reasonable > > - cosmetic changes (remove wrongful blank lines) > > - remove unnecessary reference counting > > > > > > Changes from v1: > > - the changes include minor fixes of the hardware initialization of > the PHY > > module > > - some other minor fixes were introduced > > > > -- > > Original cover letter: > > > > Hi, > > > > This patch adds a new drive for USB PHYs for Samsung SoCs. The driver > > is using the Generic PHY Framework created by Kishon Vijay Abrahan I. > > It can be found here https://lkml.org/lkml/2013/8/21/29. This patch > > adds support to Exynos4 family of SoCs. Support for Exynos3 and > > Exynos5 is planned to be added in the near future. > > > > I welcome your comments. > > > > -- > > > > [1] https://lkml.org/lkml/2013/8/21/29 > > > > > > Kamil Debski (8): > > phy: core: Change the way of_phy_get is called > > phy: core: Add devm_of_phy_get to phy-core > > phy: Add new Exynos USB PHY driver > > usb: ehci-s5p: Change to use phy provided by the generic phy > > framework > > usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic > > phy framework > > phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver > > dts: Add usb2phy to Exynos 4 > > dts: Add usb2phy to Exynos 5250 > > > > Mateusz Krawczuk (1): > > phy: Add support for S5PV210 to the Exynos USB PHY driver > > > > .../devicetree/bindings/arm/samsung/pmu.txt|2 + > > .../devicetree/bindings/phy/samsung-usbphy.txt | 56 +++ > > .../devicetree/bindings/usb/samsung-hsotg.txt |4 + > > Documentation/devicetree/bindings/usb/usb-ehci.txt | 35 ++ > > arch/arm/boot/dts/exynos4.dtsi | 31 ++ > > arch/arm/boot/dts/exynos4210.dtsi | 17 + > > arch/arm/boot/dts/exynos4x12.dtsi | 17 + > > arch/arm/boot/dts/exynos5250.dtsi | 33 +- > > drivers/phy/Kconfig| 35 ++ > > drivers/phy/Makefile |5 + > > drivers/phy/phy-core.c | 43 ++- > > drivers/phy/phy-exynos42
RE: [PATCH 1/9] phy: core: Change the way of_phy_get is called
Hi,
> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> Sent: Friday, December 06, 2013 6:31 AM
>
> Hi,
>
> On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> > Previously the of_phy_get function took a struct device * and was
> > declared static. It was impossible to call it from another driver and
> > thus it was impossible to get phy defined
>
> It was never intended to be called from other drivers. What's up with
> the wrapper of of_phy_get, phy_get()/devm_phy_get()? Why isn't that
> enough?
Implementing support for multiple phys in the ehci driver is a bit tricky.
Especially when we want to do it right. Please have a look at this part of
the dts file:
+ehci@1258 {
+compatible = "samsung,exynos4210-ehci";
+reg = <0x1258 0x2>;
+interrupts = <0 70 0>;
+clocks = <&clock 304>, <&clock 305>;
+clock-names = "usbhost", "otg";
+status = "disabled";
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+phys = <&usb2phy 1>;
+phy-names = "host";
+status = "disabled";
+};
+port@1 {
+reg = <1>;
+phys = <&usb2phy 2>;
+phy-names = "hsic0";
+status = "disabled";
+};
+port@2 {
+reg = <2>;
+phys = <&usb2phy 3>;
+phy-names = "hsic1";
+status = "disabled";
+};
+};
With the above we have a clear specification of ports and their respective
phys. But to do this properly the ehci driver has to iterate over port
nodes. It is much easier to use devm_of_phy_get by giving the node as its
argument.
[snip]
Best wishes,
--
Kamil Debski
Samsung R&D Institute Poland
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Re: [PATCH v4 3/9] phy: Add new Exynos USB PHY driver
Hi,
On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> Add a new driver for the Exynos USB PHY. The new driver uses the generic
> PHY framework. The driver includes support for the Exynos 4x10 and 4x12
> SoC families.
>
> Signed-off-by: Kamil Debski
> Signed-off-by: Kyungmin Park
> ---
> .../devicetree/bindings/phy/samsung-usbphy.txt | 54
> drivers/phy/Kconfig| 20 ++
> drivers/phy/Makefile |3 +
> drivers/phy/phy-exynos4210-usb2.c | 264 +
> drivers/phy/phy-exynos4212-usb2.c | 312
>
> drivers/phy/phy-samsung-usb2.c | 228 ++
> drivers/phy/phy-samsung-usb2.h | 72 +
> 7 files changed, 953 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> create mode 100644 drivers/phy/phy-exynos4210-usb2.c
> create mode 100644 drivers/phy/phy-exynos4212-usb2.c
> create mode 100644 drivers/phy/phy-samsung-usb2.c
> create mode 100644 drivers/phy/phy-samsung-usb2.h
>
> diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> new file mode 100644
> index 000..cadbf70
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
use the existing samsung-phy.txt.
> @@ -0,0 +1,54 @@
> +Samsung S5P/EXYNOS SoC series USB PHY
> +-
> +
> +Required properties:
> +- compatible : should be one of the listed compatibles:
> + - "samsung,exynos4210-usb2-phy"
> + - "samsung,exynos4212-usb2-phy"
> +- reg : a list of registers used by phy driver
> + - first and obligatory is the location of phy modules registers
> +- samsung,sysreg-phandle - handle to syscon used to control the system
> registers
> +- samsung,pmureg-phandle - handle to syscon used to control PMU registers
> +- #phy-cells : from the generic phy bindings, must be 1;
> +- clocks and clock-names:
> + - the "phy" clocks is required by the phy module
> + - next for each of the phys a clock has to be assidned, this clock
%s/assidned/assigned/
> + will be used to determine clocking frequency for the phys
> + (the labels are specified in the paragraph below)
> +
> +The first phandle argument in the PHY specifier identifies the PHY, its
> +meaning is compatible dependent. For the currently supported SoCs (Exynos
> 4210
> +and Exynos 4212) it is as follows:
> + 0 - USB device ("device"),
> + 1 - USB host ("host"),
> + 2 - HSIC0 ("hsic0"),
> + 3 - HSIC1 ("hsic1"),
> +
> +Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
> +register is supplied.
> +
> +Example:
> +
> +For Exynos 4412 (compatible with Exynos 4212):
> +
> +usbphy: phy@125B {
use lower case for address here...
> + compatible = "samsung,exynos4212-usb2-phy";
> + reg = <0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4>;
and here..
> + clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
> + <&clock 2>;
> + clock-names = "phy", "device", "host", "hsic0", "hsic1";
> + status = "okay";
> + #phy-cells = <1>;
> + samsung,sysreg-phandle = <&sys_reg>;
> + samsung,pmureg-phandle = <&pmu_reg>;
> +};
> +
> +Then the PHY can be used in other nodes such as:
> +
> +phy-consumer@1234 {
> + phys = <&usbphy 2>;
> + phy-names = "phy";
> +};
> +
> +Refer to DT bindings documentation of particular PHY consumer devices for
> more
> +information about required PHYs and the way of specification.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index a344f3d..b29018f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -51,4 +51,24 @@ config PHY_EXYNOS_DP_VIDEO
> help
> Support for Display Port PHY found on Samsung EXYNOS SoCs.
>
> +config PHY_SAMSUNG_USB2
> + tristate "Samsung USB 2.0 PHY driver"
> + help
> + Enable this to support Samsung USB phy helper driver for Samsung SoCs.
> + This driver provides common interface to interact, for Samsung
> + USB 2.0 PHY driver.
> +
> +config PHY_EXYNOS4210_USB2
> + bool "Support for Exynos 4210"
> + depends on PHY_SAMSUNG_USB2
> + depends on CPU_EXYNOS4210
select GENERIC_PHY here?
> + help
> + Enable USB PHY support for Exynos 4210
Add more explanation here and make checkpatch happy.
> +
> +config PHY_EXYNOS4212_USB2
> + bool "Support for Exynos 4212"
> + depends on PHY_SAMSUNG_USB2
> + depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
select GENERIC_PHY.
> + help
> + Enable USB PHY support for Exynos 4212
more explanation here too..
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index d0caae9..9f4befd 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -7,3 +7,6 @@ ob
Re: [PATCH v4 5/9] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework
Hi,
On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> Change the used phy driver to the new Exynos USB phy driver that uses the
> generic phy framework.
>
> Signed-off-by: Kamil Debski
> Signed-off-by: Kyungmin Park
> ---
> .../devicetree/bindings/usb/samsung-hsotg.txt |4
> drivers/usb/gadget/s3c-hsotg.c | 11 ++-
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> index b83d428..9340d06 100644
> --- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> +++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> @@ -24,6 +24,8 @@ Required properties:
> - first entry: must be "otg"
> - vusb_d-supply: phandle to voltage regulator of digital section,
> - vusb_a-supply: phandle to voltage regulator of analog section.
> +- phys: from general PHY binding: phandle to the PHY device
> +- phy-names: from general PHY binding: should be "usb2-phy"
are you sure it's usb2-phy. The example below seems to have a different value.
Thanks
Kishon
>
> Example
> -
> @@ -36,5 +38,7 @@ Example
> clock-names = "otg";
> vusb_d-supply = <&vusb_reg>;
> vusb_a-supply = <&vusbdac_reg>;
> + phys = <&usb2phy 0>;
> + phy-names = "device";
> };
>
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> index eccb147..db096fd 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -31,6 +31,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -162,7 +163,7 @@ struct s3c_hsotg_ep {
> struct s3c_hsotg {
> struct device*dev;
> struct usb_gadget_driver *driver;
> - struct usb_phy *phy;
> + struct phy *phy;
> struct s3c_hsotg_plat*plat;
>
> spinlock_t lock;
> @@ -2905,7 +2906,7 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg
> *hsotg)
> dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
>
> if (hsotg->phy)
> - usb_phy_init(hsotg->phy);
> + phy_power_on(hsotg->phy);
> else if (hsotg->plat->phy_init)
> hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
> }
> @@ -2922,7 +2923,7 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg
> *hsotg)
> struct platform_device *pdev = to_platform_device(hsotg->dev);
>
> if (hsotg->phy)
> - usb_phy_shutdown(hsotg->phy);
> + phy_power_off(hsotg->phy);
> else if (hsotg->plat->phy_exit)
> hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
> }
> @@ -3529,7 +3530,7 @@ static void s3c_hsotg_delete_debug(struct s3c_hsotg
> *hsotg)
> static int s3c_hsotg_probe(struct platform_device *pdev)
> {
> struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
> - struct usb_phy *phy;
> + struct phy *phy;
> struct device *dev = &pdev->dev;
> struct s3c_hsotg_ep *eps;
> struct s3c_hsotg *hsotg;
> @@ -3544,7 +3545,7 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
> return -ENOMEM;
> }
>
> - phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
> + phy = devm_phy_get(&pdev->dev, "usb2-phy");
> if (IS_ERR(phy)) {
> /* Fallback for pdata */
> plat = dev_get_platdata(&pdev->dev);
>
--
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Re: [PATCH v4 6/9] phy: Add support for S5PV210 to the Exynos USB PHY driver
Hi, On Friday 06 December 2013 04:01 PM, Kamil Debski wrote: > From: Mateusz Krawczuk > > Add support for the Samsung's S5PV210 SoC to the Exynos USB PHY driver. > > Signed-off-by: Mateusz Krawczuk > [k.deb...@samsung.com: cleanup and commit description] > [k.deb...@samsung.com: make changes accordingly to the mailing list > comments] > Signed-off-by: Kamil Debski > Signed-off-by: Kyungmin Park > --- > .../devicetree/bindings/phy/samsung-usbphy.txt |1 + > drivers/phy/Kconfig|7 + > drivers/phy/Makefile |1 + > drivers/phy/phy-s5pv210-usb2.c | 206 > > drivers/phy/phy-samsung-usb2.c |6 + > drivers/phy/phy-samsung-usb2.h |1 + > 6 files changed, 222 insertions(+) > create mode 100644 drivers/phy/phy-s5pv210-usb2.c > > diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > index cadbf70..77a8e9c 100644 > --- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > @@ -3,6 +3,7 @@ Samsung S5P/EXYNOS SoC series USB PHY > > Required properties: > - compatible : should be one of the listed compatibles: > + - "samsung,s5pv210-usb2-phy" > - "samsung,exynos4210-usb2-phy" > - "samsung,exynos4212-usb2-phy" > - reg : a list of registers used by phy driver > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index b29018f..2e433cd 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -58,6 +58,13 @@ config PHY_SAMSUNG_USB2 > This driver provides common interface to interact, for Samsung > USB 2.0 PHY driver. > > +config PHY_S5PV210_USB2 > + bool "Support for S5PV210" > + depends on PHY_SAMSUNG_USB2 > + depends on ARCH_S5PV210 > + help > + Enable USB PHY support for S5PV210 more description here.. > + > config PHY_EXYNOS4210_USB2 > bool "Support for Exynos 4210" > depends on PHY_SAMSUNG_USB2 > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 9f4befd..fefc6c2 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += > phy-exynos-mipi-video.o > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o > obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o > obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o > +obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o > obj-$(CONFIG_PHY_EXYNOS4210_USB2)+= phy-exynos4210-usb2.o > obj-$(CONFIG_PHY_EXYNOS4212_USB2)+= phy-exynos4212-usb2.o > diff --git a/drivers/phy/phy-s5pv210-usb2.c b/drivers/phy/phy-s5pv210-usb2.c > new file mode 100644 > index 000..528a114 > --- /dev/null > +++ b/drivers/phy/phy-s5pv210-usb2.c > @@ -0,0 +1,206 @@ > +/* > + * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support > + * > + * Copyright (C) 2013 Samsung Electronics Co., Ltd. > + * Authors: Kamil Debski > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include I think my comments for the previous patch with a similar driver (phy-exynos4210-usb2.c) is applicable here also. Thanks Kishon > +#include "phy-samsung-usb2.h" > + > +/* Exynos USB PHY registers */ > + > +/* PHY power control */ > +#define S5PV210_UPHYPWR 0x0 > + > +#define S5PV210_UPHYPWR_PHY0_SUSPEND (1 << 0) > +#define S5PV210_UPHYPWR_PHY0_PWR (1 << 3) > +#define S5PV210_UPHYPWR_PHY0_OTG_PWR (1 << 4) > +#define S5PV210_UPHYPWR_PHY0 ( \ > + S5PV210_UPHYPWR_PHY0_SUSPEND | \ > + S5PV210_UPHYPWR_PHY0_PWR | \ > + S5PV210_UPHYPWR_PHY0_OTG_PWR) > + > +#define S5PV210_UPHYPWR_PHY1_SUSPEND (1 << 6) > +#define S5PV210_UPHYPWR_PHY1_PWR (1 << 7) > +#define S5PV210_UPHYPWR_PHY1 ( \ > + S5PV210_UPHYPWR_PHY1_SUSPEND | \ > + S5PV210_UPHYPWR_PHY1_PWR) > + > +/* PHY clock control */ > +#define S5PV210_UPHYCLK 0x4 > + > +#define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0) > +#define S5PV210_UPHYCLK_PHYFSEL_48MHZ(0x0 << 0) > +#define S5PV210_UPHYCLK_PHYFSEL_24MHZ(0x3 << 0) > +#define S5PV210_UPHYCLK_PHYFSEL_12MHZ(0x2 << 0) > + > +#define S5PV210_UPHYCLK_PHY0_ID_PULLUP (0x1 << 2) > +#define S5PV210_UPHYCLK_PHY0_COMMON_ON (0x1 << 4) > +#define S5PV210_UPHYCLK_PHY1_COMMON_ON (0x1 << 7) > + > +/* PHY reset control */ > +#define S5PV210_UPHYRST 0x8 > + > +#define S5PV210_URSTCON_PHY0 (1 << 0) > +#define S5PV210_URSTCON_OTG_HLINK(1 << 1) > +#define S5PV210_URSTCON_OTG
Re: [PATCH v4 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
On Friday 06 December 2013 04:02 PM, Kamil Debski wrote: > Add support for Exynos 5250. This driver is to replace the old > USB 2.0 PHY driver. > > Signed-off-by: Kamil Debski > Signed-off-by: Kyungmin Park > --- > .../devicetree/bindings/phy/samsung-usbphy.txt |1 + > drivers/phy/Kconfig|8 + > drivers/phy/Makefile |1 + > drivers/phy/phy-exynos5250-usb2.c | 363 > > drivers/phy/phy-samsung-usb2.c |6 + > drivers/phy/phy-samsung-usb2.h |1 + > 6 files changed, 380 insertions(+) > create mode 100644 drivers/phy/phy-exynos5250-usb2.c > > diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > index 77a8e9c..94096fc 100644 > --- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt > @@ -6,6 +6,7 @@ Required properties: > - "samsung,s5pv210-usb2-phy" > - "samsung,exynos4210-usb2-phy" > - "samsung,exynos4212-usb2-phy" > + - "samsung,exynos5250-usb2-phy" > - reg : a list of registers used by phy driver > - first and obligatory is the location of phy modules registers > - samsung,sysreg-phandle - handle to syscon used to control the system > registers > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 2e433cd..74e9064 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -78,4 +78,12 @@ config PHY_EXYNOS4212_USB2 > depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) > help > Enable USB PHY support for Exynos 4212 > + > +config PHY_EXYNOS5250_USB2 > + bool "Support for Exynos 5250" > + depends on PHY_SAMSUNG_USB2 > + depends on SOC_EXYNOS5250 > + help > + Enable USB PHY support for Exynos 5250 My comments for the previous patch is applicable here too.. Thanks Kishon > + > endmenu > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index fefc6c2..33c3ac1 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_SAMSUNG_USB2) += > phy-samsung-usb2.o > obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o > obj-$(CONFIG_PHY_EXYNOS4210_USB2)+= phy-exynos4210-usb2.o > obj-$(CONFIG_PHY_EXYNOS4212_USB2)+= phy-exynos4212-usb2.o > +obj-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o > diff --git a/drivers/phy/phy-exynos5250-usb2.c > b/drivers/phy/phy-exynos5250-usb2.c > new file mode 100644 > index 000..7aeebc8 > --- /dev/null > +++ b/drivers/phy/phy-exynos5250-usb2.c > @@ -0,0 +1,363 @@ > +/* > + * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support > + * > + * Copyright (C) 2013 Samsung Electronics Co., Ltd. > + * Author: Kamil Debski > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "phy-samsung-usb2.h" > + > +/* Exynos USB PHY registers */ > +#define EXYNOS_5250_REFCLKSEL_CRYSTAL0x0 > +#define EXYNOS_5250_REFCLKSEL_XO 0x1 > +#define EXYNOS_5250_REFCLKSEL_CLKCORE0x2 > + > +#define EXYNOS_5250_FSEL_9MHZ6 0x0 > +#define EXYNOS_5250_FSEL_10MHZ 0x1 > +#define EXYNOS_5250_FSEL_12MHZ 0x2 > +#define EXYNOS_5250_FSEL_19MHZ2 0x3 > +#define EXYNOS_5250_FSEL_20MHZ 0x4 > +#define EXYNOS_5250_FSEL_24MHZ 0x5 > +#define EXYNOS_5250_FSEL_50MHZ 0x7 > + > +/* Normal host */ > +#define EXYNOS_5250_HOSTPHYCTRL0 0x0 > + > +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL (0x1 << 31) > +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19 > +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK \ > + (0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT) > +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT 16 > +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \ > + (0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT) > +#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN (0x1 << 11) > +#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE (0x1 << 10) > +#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N (0x1 << 9) > +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK (0x3 << 7) > +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL (0x0 << 7) > +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 << 7) > +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST(0x2 << 7) > +#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ (0x1 << 6) > +#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP (0x1 << 5) > +#defi
Re: [alsa-devel] [PATCH 1/2] ASoC: samsung: Provide helper for DMA init
On Fri, Dec 06, 2013 at 10:44:33AM +0530, Padma Venkat wrote: > This is done in your earlier patch " ASoC: samsung: Ensure DMA data is > initialised for secondary DAI ". Was it done on purpose or by mistake > in this patch? It's intentional - notice that the function has changed, this is why I kept asking you about mainline. Mainline doesn't have the wrapper function that abstracts the difference between s3c-dma and dmaengine, this is why I'm saying these two will need to be rebased on top of the mainline fix. > I think you also told to include a patch for reinitialization of the > dma_data in i2s_hw_params. If you are in the process of debugging some > bug as you mentioned earlier you can ignore this comment. Otherwise it > is just a reminder. Hrm, forgot to commit that bit. signature.asc Description: Digital signature
Re: [PATCH] ARM: s3c24xx: get rid of custom
On Fri, Dec 6, 2013 at 10:31 AM, Linus Walleij wrote: > This isolates the custom S3C24xx GPIO definition table to > Maybe I'm too trigger happy. I'll send a combined series with S3C24xx, S3C64xx and maybe also S5P variants all fixed so you can see the overall idea here. Hold on. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] ASoC: samsung: Provide helper for DMA init
From: Mark Brown
In preparation for using the dmaengine helpers in ASoC rather than the
dmaengine wrappers for the Samsung API wrap the configuration of dma_data.
The dmaengine code expects different data to that used by the legacy API.
Signed-off-by: Mark Brown
---
sound/soc/samsung/ac97.c | 51 +++-
sound/soc/samsung/dma.c | 8
sound/soc/samsung/dma.h | 3 +++
sound/soc/samsung/i2s.c | 7 +--
sound/soc/samsung/pcm.c | 18 +
5 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 350ba23a9893..4a88e36c82ec 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -221,24 +221,6 @@ static struct snd_ac97_bus_ops s3c_ac97_ops = {
.reset = s3c_ac97_cold_reset,
};
-static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- struct s3c_dma_params *dma_data;
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- dma_data = &s3c_ac97_pcm_out;
- else
- dma_data = &s3c_ac97_pcm_in;
-
- snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
-
- return 0;
-}
-
static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
@@ -279,21 +261,6 @@ static int s3c_ac97_trigger(struct snd_pcm_substream
*substream, int cmd,
return 0;
}
-static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- return -ENODEV;
- else
- snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
-
- return 0;
-}
-
static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
@@ -329,15 +296,27 @@ static int s3c_ac97_mic_trigger(struct snd_pcm_substream
*substream,
}
static const struct snd_soc_dai_ops s3c_ac97_dai_ops = {
- .hw_params = s3c_ac97_hw_params,
.trigger= s3c_ac97_trigger,
};
static const struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
- .hw_params = s3c_ac97_hw_mic_params,
.trigger= s3c_ac97_mic_trigger,
};
+static int s3c_ac97_dai_probe(struct snd_soc_dai *dai)
+{
+ samsung_asoc_init_dma_data(dai, &s3c_ac97_pcm_out, &s3c_ac97_pcm_in);
+
+ return 0;
+}
+
+static int s3c_ac97_mic_dai_probe(struct snd_soc_dai *dai)
+{
+ samsung_asoc_init_dma_data(dai, NULL, &s3c_ac97_mic_in);
+
+ return 0;
+}
+
static struct snd_soc_dai_driver s3c_ac97_dai[] = {
[S3C_AC97_DAI_PCM] = {
.name = "samsung-ac97",
@@ -354,6 +333,7 @@ static struct snd_soc_dai_driver s3c_ac97_dai[] = {
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+ .probe = s3c_ac97_dai_probe,
.ops = &s3c_ac97_dai_ops,
},
[S3C_AC97_DAI_MIC] = {
@@ -365,6 +345,7 @@ static struct snd_soc_dai_driver s3c_ac97_dai[] = {
.channels_max = 1,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
+ .probe = s3c_ac97_mic_dai_probe,
.ops = &s3c_ac97_mic_dai_ops,
},
};
diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c
index fe2748b494d4..ee23194f7ab8 100644
--- a/sound/soc/samsung/dma.c
+++ b/sound/soc/samsung/dma.c
@@ -441,6 +441,14 @@ static struct snd_soc_platform_driver
samsung_asoc_platform = {
.pcm_free = dma_free_dma_buffers,
};
+void samsung_asoc_init_dma_data(struct snd_soc_dai *dai,
+ struct s3c_dma_params *playback,
+ struct s3c_dma_params *capture)
+{
+ snd_soc_dai_init_dma_data(dai, playback, capture);
+}
+EXPORT_SYMBOL_GPL(samsung_asoc_init_dma_data);
+
int samsung_asoc_dma_platform_register(struct device *dev)
{
return snd_soc_register_platform(dev, &samsung_asoc_platform);
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index 0e86315a3eaf..fb09a1c5f75b 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -22,6 +22,9 @@ struct s3c_dma_params {
char *ch_name;
};
+void samsung_asoc_init_dma_data(struct snd_soc_dai
[PATCH 2/2] ASoC: samsung: Use ASoC dmaengine code where possible
From: Mark Brown
Since all Exynos platforms have been converted to dmaengine and many of
the older platforms are in the process of conversion they do not need to
use the legacy s3c-dma APIs for DMA but can instead use the standard ASoC
dmaengine helpers. This both allows them to benefit from improvements
implemented in the generic code and supports multiplatform.
This patch includes some fixes from Padma for Exynos SoCs.
Signed-off-by: Mark Brown
Tested By: Padmavathi Venna
---
sound/soc/samsung/Kconfig | 13 +--
sound/soc/samsung/Makefile| 6 ++--
sound/soc/samsung/dma.h | 3 ++
sound/soc/samsung/dmaengine.c | 84 +++
sound/soc/samsung/i2s.c | 2 ++
5 files changed, 104 insertions(+), 4 deletions(-)
create mode 100644 sound/soc/samsung/dmaengine.c
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index 37459dfd168d..27930fc432dc 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,13 +1,22 @@
config SND_SOC_SAMSUNG
tristate "ASoC support for Samsung"
depends on PLAT_SAMSUNG
- select S3C64XX_DMA if ARCH_S3C64XX
- select S3C24XX_DMA if ARCH_S3C24XX
+ select S3C2410_DMA if ARCH_S3C24XX
+ select S3C64XX_PL080 if ARCH_S3C64XX
+ select SND_S3C_DMA if !ARCH_S3C24XX
+ select SND_S3C_DMA_LEGACY if ARCH_S3C24XX
+ select SND_SOC_GENERIC_DMAENGINE_PCM if !ARCH_S3C24XX
help
Say Y or M if you want to add support for codecs attached to
the Samsung SoCs' Audio interfaces. You will also need to
select the audio interfaces to support below.
+config SND_S3C_DMA
+ tristate
+
+config SND_S3C_DMA_LEGACY
+ tristate
+
config SND_S3C24XX_I2S
tristate
select S3C2410_DMA
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 709f6059ad67..86715d8efee6 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -1,5 +1,6 @@
# S3c24XX Platform Support
-snd-soc-s3c24xx-objs := dma.o
+snd-soc-s3c-dma-objs := dmaengine.o
+snd-soc-s3c-dma-legacy-objs := dma.o
snd-soc-idma-objs := idma.o
snd-soc-s3c24xx-i2s-objs := s3c24xx-i2s.o
snd-soc-s3c2412-i2s-objs := s3c2412-i2s.o
@@ -9,7 +10,8 @@ snd-soc-samsung-spdif-objs := spdif.o
snd-soc-pcm-objs := pcm.o
snd-soc-i2s-objs := i2s.o
-obj-$(CONFIG_SND_SOC_SAMSUNG) += snd-soc-s3c24xx.o
+obj-$(CONFIG_SND_S3C_DMA) += snd-soc-s3c-dma.o
+obj-$(CONFIG_SND_S3C_DMA_LEGACY) += snd-soc-s3c-dma-legacy.o
obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o
obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o
obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o
diff --git a/sound/soc/samsung/dma.h b/sound/soc/samsung/dma.h
index fb09a1c5f75b..225e5378014e 100644
--- a/sound/soc/samsung/dma.h
+++ b/sound/soc/samsung/dma.h
@@ -12,6 +12,8 @@
#ifndef _S3C_AUDIO_H
#define _S3C_AUDIO_H
+#include
+
struct s3c_dma_params {
struct s3c2410_dma_client *client; /* stream identifier */
int channel;/* Channel ID */
@@ -20,6 +22,7 @@ struct s3c_dma_params {
unsigned ch;
struct samsung_dma_ops *ops;
char *ch_name;
+ struct snd_dmaengine_dai_dma_data dma_data;
};
void samsung_asoc_init_dma_data(struct snd_soc_dai *dai,
diff --git a/sound/soc/samsung/dmaengine.c b/sound/soc/samsung/dmaengine.c
new file mode 100644
index ..3be479d51b9b
--- /dev/null
+++ b/sound/soc/samsung/dmaengine.c
@@ -0,0 +1,84 @@
+/*
+ * dmaengine.c - Samsung dmaengine wrapper
+ *
+ * Author: Mark Brown
+ * Copyright 2013 Linaro
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dma.h"
+
+#ifdef CONFIG_ARCH_S3C64XX
+#define filter_fn pl08x_filter_id
+#else
+#define filter_fn NULL
+#endif
+
+static const struct snd_dmaengine_pcm_config samsung_dmaengine_pcm_config = {
+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
+ .compat_filter_fn = filter_fn,
+};
+
+void samsung_asoc_init_dma_data(struct snd_soc_dai *dai,
+ struct s3c_dma_params *playback,
+ struct s3c_dma_params *capture)
+{
+ struct snd_dmaengine_dai_dma_data *playback_data = NULL;
+ struct snd_dmaengine_dai_dma_data *capture_data = NULL;
+
+ if (playback) {
+ playback_data = &playback->dma_data;
+ playback_data->filter_data = (void *)playback->channel;
+ playbac
RE: [PATCH v4 4/9] usb: ehci-s5p: Change to use phy provided by the generic phy framework
Hi Alan,
Thank you for the review. Please find my replies inline.
> From: Alan Stern [mailto:st...@rowland.harvard.edu]
> Sent: Thursday, December 05, 2013 7:53 PM
>
> On Thu, 5 Dec 2013, Kamil Debski wrote:
>
> > Change the phy provider used from the old usb phy specific to a new
> > one using the generic phy framework.
> >
> > Signed-off-by: Kamil Debski
> > Signed-off-by: Kyungmin Park
>
> > --- a/drivers/usb/host/ehci-exynos.c
> > +++ b/drivers/usb/host/ehci-exynos.c
>
> > @@ -42,10 +42,10 @@
> > static const char hcd_name[] = "ehci-exynos"; static struct
> > hc_driver __read_mostly exynos_ehci_hc_driver;
> >
> > +#define PHY_NUMBER 3
> > struct exynos_ehci_hcd {
> > struct clk *clk;
> > - struct usb_phy *phy;
> > - struct usb_otg *otg;
>
> Are you sure you want to remove that line?
Yes, I am. The new generic phy interface does not have the otg field in it.
> > + struct phy *phy[PHY_NUMBER];
> > };
> >
> > #define to_exynos_ehci(hcd) (struct exynos_ehci_hcd
> > *)(hcd_to_ehci(hcd)->priv)
>
> > @@ -102,13 +132,24 @@ static int exynos_ehci_probe(struct
> platform_device *pdev)
> > "samsung,exynos5440-ehci"))
> > goto skip_phy;
> >
> > - phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
> > - if (IS_ERR(phy)) {
> > - usb_put_hcd(hcd);
> > - dev_warn(&pdev->dev, "no platform data or transceiver
> defined\n");
> > - return -EPROBE_DEFER;
> > - } else {
> > - exynos_ehci->phy = phy;
> > + for_each_available_child_of_node(pdev->dev.of_node, child) {
> > + err = of_property_read_u32(child, "reg", &phy_number);
> > + if (err) {
> > + dev_err(&pdev->dev, "Failed to parse device
tree\n");
> > + return err;
> > + }
> > + if (phy_number >= PHY_NUMBER) {
> > + dev_err(&pdev->dev, "Failed to parse device tree -
> number out of range\n");
> > + return -EINVAL;
>
> Do you need to call of_node_put(child) before each of these return
> statements?
You are right, thank you for spotting this.
>
> > + }
> > + phy = devm_of_phy_get(&pdev->dev, child, 0);
> > + of_node_put(child);
> > + if (IS_ERR(phy)) {
> > + dev_err(&pdev->dev, "Failed to get phy number %d",
> > + phy_number);
> > + return PTR_ERR(phy);
> > + }
> > + exynos_ehci->phy[phy_number] = phy;
> > exynos_ehci->otg = phy->otg;
>
> Did you intend to remove this line? Above, you removed the
> exynos_ehci->otg field. I can't see how this patch would ever compile
> without an error.
Yes, I had this in a separate fix patch which I forgot to squash. Sorry for
this.
> > }
> >
> > @@ -149,11 +190,11 @@ skip_phy:
> > goto fail_io;
> > }
> >
> > - if (exynos_ehci->otg)
> > - exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> > -
> > - if (exynos_ehci->phy)
> > - usb_phy_init(exynos_ehci->phy);
> > + err = exynos_phys_on(exynos_ehci->phy);
> > + if (err) {
> > + dev_err(&pdev->dev, "Failed to enabled phys\n");
> > + goto fail_phys_on;
>
> Why add a new statement label? Just goto fail_io.
To me it seemed better to add a new label. I will drop it and use
goto fail_io, as you suggested.
>
> > + }
> >
> > ehci = hcd_to_ehci(hcd);
> > ehci->caps = hcd->regs;
> > @@ -172,8 +213,8 @@ skip_phy:
> > return 0;
> >
> > fail_add_hcd:
> > - if (exynos_ehci->phy)
> > - usb_phy_shutdown(exynos_ehci->phy);
> > + exynos_phys_off(exynos_ehci->phy);
> > +fail_phys_on:
> > fail_io:
> > clk_disable_unprepare(exynos_ehci->clk);
> > fail_clk:
>
> Alan Stern
Best wishes,
--
Kamil Debski
Samsung R&D Institute Poland
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Re: [PATCH v4 5/9] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework
On Fri, Dec 06, 2013 at 04:41:51PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> > Change the used phy driver to the new Exynos USB phy driver that uses the
> > generic phy framework.
> >
> > Signed-off-by: Kamil Debski
> > Signed-off-by: Kyungmin Park
> > ---
> > .../devicetree/bindings/usb/samsung-hsotg.txt |4
> > drivers/usb/gadget/s3c-hsotg.c | 11 ++-
> > 2 files changed, 10 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> > b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> > index b83d428..9340d06 100644
> > --- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> > +++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
> > @@ -24,6 +24,8 @@ Required properties:
> > - first entry: must be "otg"
> > - vusb_d-supply: phandle to voltage regulator of digital section,
> > - vusb_a-supply: phandle to voltage regulator of analog section.
> > +- phys: from general PHY binding: phandle to the PHY device
> > +- phy-names: from general PHY binding: should be "usb2-phy"
>
> are you sure it's usb2-phy. The example below seems to have a different value.
I requested this be changed to usb2-phy, looks like he just missed the
update to the example.
>
> >
> > Example
> > -
> > @@ -36,5 +38,7 @@ Example
> > clock-names = "otg";
> > vusb_d-supply = <&vusb_reg>;
> > vusb_a-supply = <&vusbdac_reg>;
> > + phys = <&usb2phy 0>;
> > + phy-names = "device";
> > };
> >
> > diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> > index eccb147..db096fd 100644
> > --- a/drivers/usb/gadget/s3c-hsotg.c
> > +++ b/drivers/usb/gadget/s3c-hsotg.c
> > @@ -31,6 +31,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include
> > #include
> > @@ -162,7 +163,7 @@ struct s3c_hsotg_ep {
> > struct s3c_hsotg {
> > struct device*dev;
> > struct usb_gadget_driver *driver;
> > - struct usb_phy *phy;
> > + struct phy *phy;
> > struct s3c_hsotg_plat*plat;
> >
> > spinlock_t lock;
> > @@ -2905,7 +2906,7 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg
> > *hsotg)
> > dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
> >
> > if (hsotg->phy)
> > - usb_phy_init(hsotg->phy);
> > + phy_power_on(hsotg->phy);
> > else if (hsotg->plat->phy_init)
> > hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
> > }
> > @@ -2922,7 +2923,7 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg
> > *hsotg)
> > struct platform_device *pdev = to_platform_device(hsotg->dev);
> >
> > if (hsotg->phy)
> > - usb_phy_shutdown(hsotg->phy);
> > + phy_power_off(hsotg->phy);
> > else if (hsotg->plat->phy_exit)
> > hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
> > }
> > @@ -3529,7 +3530,7 @@ static void s3c_hsotg_delete_debug(struct s3c_hsotg
> > *hsotg)
> > static int s3c_hsotg_probe(struct platform_device *pdev)
> > {
> > struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
> > - struct usb_phy *phy;
> > + struct phy *phy;
> > struct device *dev = &pdev->dev;
> > struct s3c_hsotg_ep *eps;
> > struct s3c_hsotg *hsotg;
> > @@ -3544,7 +3545,7 @@ static int s3c_hsotg_probe(struct platform_device
> > *pdev)
> > return -ENOMEM;
> > }
> >
> > - phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
> > + phy = devm_phy_get(&pdev->dev, "usb2-phy");
> > if (IS_ERR(phy)) {
> > /* Fallback for pdata */
> > plat = dev_get_platdata(&pdev->dev);
> >
>
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[PATCH 6/7] clk/samsung: add support for pll2650xx
Add support for pll2650xx in samsung pll file. This pll variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma
---
drivers/clk/samsung/clk-pll.c | 101 +
drivers/clk/samsung/clk-pll.h |2 +-
2 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 237a889..60c5679 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops
= {
.recalc_rate = samsung_pll2550xx_recalc_rate,
};
+/*
+ * PLL2650XX Clock Type
+ */
+
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL2650XX_LOCK_FACTOR (3000)
+
+#define PLL2650XX_MDIV_SHIFT (9)
+#define PLL2650XX_PDIV_SHIFT (3)
+#define PLL2650XX_SDIV_SHIFT (0)
+#define PLL2650XX_KDIV_SHIFT (0)
+#define PLL2650XX_MDIV_MASK(0x1ff)
+#define PLL2650XX_PDIV_MASK(0x3f)
+#define PLL2650XX_SDIV_MASK(0x7)
+#define PLL2650XX_KDIV_MASK(0x)
+#define PLL2650XX_PLL_ENABLE_SHIFT (23)
+#define PLL2650XX_PLL_LOCKTIME_SHIFT (21)
+#define PLL2650XX_PLL_FOUTMASK_SHIFT (31)
+
+static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
+ s16 kdiv;
+ u64 fvco = parent_rate;
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+ mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
+ pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
+ sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
+ kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
+
+ fvco *= (mdiv << 16) + kdiv;
+ do_div(fvco, (pdiv << sdiv));
+ fvco >>= 16;
+
+ return (unsigned long)fvco;
+}
+
+static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con2;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = __raw_readl(pll->con_reg);
+ pll_con2 = __raw_readl(pll->con_reg + 8);
+
+/* Change PLL PMS values */
+ pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
+ PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
+ pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
+ pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
+ pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
+ pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
+
+ pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
+ pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
+ << PLL2650XX_KDIV_SHIFT;
+
+ /* Set PLL lock time. */
+ __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
+
+ __raw_writel(pll_con0, pll->con_reg);
+ __raw_writel(pll_con2, pll->con_reg + 8);
+
+ do {
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2650xx_clk_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+ .set_rate = samsung_pll2650xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2650xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -894,6 +989,12 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
else
init.ops = &samsung_pll2550xx_clk_ops;
break;
+ case pll_2650xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2650xx_clk_min_ops;
+ else
+ init.ops = &samsung_pll2650xx_clk_ops;
+ break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
diff --git a/drivers/clk/samsung/clk-pll.
[PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC
From: Arun Kumar K
The patch adds the dts files for exynos5260 and for xyref
evt0 board.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 +++
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 85
arch/arm/boot/dts/exynos5260.dtsi | 315
4 files changed, 987 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 741bf73..8d26135 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5260-xyref5260-evt0.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000..67aaee7
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,586 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1160 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
[PATCH 4/7] clk/samsung: add support for multuple clock providers
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation SoC platforms are not able to use these
helpers for registering mulitple clock providers and are
forced to bypass this layer.
This layer is modified acordingly to enable the support.
Clockfile for exynos4, exynos5250, exynos5420, exynos5440
and S3c64xx are also modified as per changed helper functions.
Signed-off-by: Rahul Sharma
---
drivers/clk/samsung/clk-exynos4.c| 47 ---
drivers/clk/samsung/clk-exynos5250.c | 26
drivers/clk/samsung/clk-exynos5420.c | 24 +---
drivers/clk/samsung/clk-exynos5440.c | 18 +++---
drivers/clk/samsung/clk-pll.c| 14 +++--
drivers/clk/samsung/clk-s3c64xx.c| 44 --
drivers/clk/samsung/clk.c| 110 +++---
drivers/clk/samsung/clk.h| 46 ++
8 files changed, 195 insertions(+), 134 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ca2a940..e634ba9 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1093,7 +1093,7 @@ static unsigned long exynos4_get_xom(void)
return xom;
}
-static void __init exynos4_clk_register_finpll(void)
+static void __init exynos4_clk_register_finpll(struct samsung_clk_provider
*ctx)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
@@ -1116,7 +1116,7 @@ static void __init exynos4_clk_register_finpll(void)
fclk.parent_name = NULL;
fclk.flags = CLK_IS_ROOT;
fclk.fixed_rate = finpll_f;
- samsung_clk_register_fixed_rate(&fclk, 1);
+ samsung_clk_register_fixed_rate(ctx, &fclk, 1);
}
@@ -1226,22 +1226,25 @@ static struct samsung_pll_clock
exynos4x12_plls[nr_plls] __initdata = {
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
{
+ struct samsung_clk_provider *ctx;
exynos4_soc = soc;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
- samsung_clk_init(np, reg_base, nr_clks);
+ ctx = samsung_clk_init(np, reg_base, nr_clks);
+ if (!ctx)
+ panic("%s: unable to allocate context.\n", __func__);
- samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+ samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
- exynos4_clk_register_finpll();
+ exynos4_clk_register_finpll(ctx);
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_mux(exynos4210_mux_early,
+ samsung_clk_register_mux(ctx, exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
if (_get_rate("fin_pll") == 2400) {
@@ -1255,7 +1258,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4210_plls[vpll].rate_table =
exynos4210_vpll_rates;
- samsung_clk_register_pll(exynos4210_plls,
+ samsung_clk_register_pll(ctx, exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
} else {
if (_get_rate("fin_pll") == 2400) {
@@ -1267,42 +1270,42 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4x12_vpll_rates;
}
- samsung_clk_register_pll(exynos4x12_plls,
+ samsung_clk_register_pll(ctx, exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
}
- samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
ARRAY_SIZE(exynos4_fixed_rate_clks));
- samsung_clk_register_mux(exynos4_mux_clks,
+ samsung_clk_register_mux(ctx, exynos4_mux_clks,
ARRAY_SIZE(exynos4_mux_clks));
- samsung_clk_register_div(exynos4_div_clks,
+ samsung_clk_register_div(ctx, exynos4_div_clks,
ARRAY_SIZE(exynos4_div_clks));
- samsung_clk_register_gate(exynos4_gate_clks,
+ samsung_clk_register_gate(ctx, exynos4_gate_clks,
ARRAY_SIZE(exynos4_gate_clks));
if (exynos4_soc == EXYNOS4210) {
- samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+ samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
ARRAY_SIZE(exynos4210_fixed_rate_clks));
- samsung_clk_register_mux(exynos4210_mux_clks,
+ samsung_clk_register_mux(ctx, exynos42
[PATCH 0/7] exynos: add basic support for exynos5260 SoC
add basic support for exynos5260 SoC. This series is based on linux-next, Kukjin's for-next and Mike's clk-for-linus-3.13 branches. This patch is dependent on the following series from Tomasz Figa : http://www.spinics.net/lists/arm-kernel/msg280223.html Arun Kumar K (1): ARM: dts: add dts files for exynos5260 SoC Pankaj Dubey (2): ARM: EXYNOS: initial board support for exynos5260 SoC clk/samsung: add support for pll2550xx Rahul Sharma (3): clk/samsung: add support for multuple clock providers clk/samsung: add support for pll2650xx clk/exynos5260: add clock file for exynos5260 Young-Gun Jang (1): pinctrl: exynos: add exynos5260 SoC specific data .../devicetree/bindings/clock/exynos5260-clock.txt | 228 ++ .../bindings/pinctrl/samsung-pinctrl.txt |1 + arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 586 + arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts| 85 + arch/arm/boot/dts/exynos5260.dtsi | 315 +++ arch/arm/mach-exynos/Kconfig |9 + arch/arm/mach-exynos/common.c | 19 +- arch/arm/mach-exynos/cpuidle.c |2 +- arch/arm/mach-exynos/include/mach/map.h|1 + arch/arm/mach-exynos/include/mach/regs-pmu.h |4 + arch/arm/mach-exynos/mach-exynos5-dt.c |1 + arch/arm/plat-samsung/include/plat/cpu.h |8 + arch/arm/plat-samsung/include/plat/map-s5p.h |1 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos4.c | 47 +- drivers/clk/samsung/clk-exynos5250.c | 26 +- drivers/clk/samsung/clk-exynos5260.c | 2661 drivers/clk/samsung/clk-exynos5260.h | 496 drivers/clk/samsung/clk-exynos5420.c | 24 +- drivers/clk/samsung/clk-exynos5440.c | 18 +- drivers/clk/samsung/clk-pll.c | 222 +- drivers/clk/samsung/clk-pll.h |3 +- drivers/clk/samsung/clk-s3c64xx.c | 44 +- drivers/clk/samsung/clk.c | 110 +- drivers/clk/samsung/clk.h | 46 +- drivers/pinctrl/pinctrl-exynos.c | 82 + drivers/pinctrl/pinctrl-samsung.c |2 + drivers/pinctrl/pinctrl-samsung.h |1 + include/dt-bindings/clk/exynos5260-clk.h | 169 ++ 30 files changed, 5076 insertions(+), 137 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clk/exynos5260-clk.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/7] clk/samsung: add support for pll2550xx
From: Pankaj Dubey
exynos5260 use pll2520xx and it has different bitfields
for P,M,S values as compared to pll2550xx. Support for
pll2520xx is added here.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
---
drivers/clk/samsung/clk-pll.c | 107 +
drivers/clk/samsung/clk-pll.h |1 +
2 files changed, 108 insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index e8e8953..237a889 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const
char *name,
return clk;
}
+/*
+ * PLL2550xx Clock Type
+ */
+
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL2550XX_LOCK_FACTOR (270)
+
+#define PLL2550XX_MDIV_MASK(0x3FF)
+#define PLL2550XX_PDIV_MASK(0x3F)
+#define PLL2550XX_SDIV_MASK(0x7)
+#define PLL2550XX_LOCK_STAT_MASK (0x1)
+#define PLL2550XX_MDIV_SHIFT (9)
+#define PLL2550XX_PDIV_SHIFT (3)
+#define PLL2550XX_SDIV_SHIFT (0)
+#define PLL2550XX_LOCK_STAT_SHIFT (21)
+
+static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 mdiv, pdiv, sdiv, pll_con;
+ u64 fvco = parent_rate;
+
+ pll_con = __raw_readl(pll->con_reg);
+ mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK;
+ pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK;
+ sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
+{
+ if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) &
+ PLL2550XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) &
+ PLL2550XX_PDIV_MASK)))
+ return 1;
+ else
+ return 0;
+}
+
+static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ tmp = __raw_readl(pll->con_reg);
+
+ if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT);
+ tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT;
+ __raw_writel(tmp, pll->con_reg);
+ } else {
+ /* Set PLL lock time. */
+ __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
+
+ /* Change PLL PMS values */
+ tmp &= ~((PLL2550XX_MDIV_MASK << PLL2550XX_MDIV_SHIFT) |
+ (PLL2550XX_PDIV_MASK << PLL2550XX_PDIV_SHIFT) |
+ (PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT));
+ tmp |= (rate->mdiv << PLL2550XX_MDIV_SHIFT) |
+ (rate->pdiv << PLL2550XX_PDIV_SHIFT) |
+ (rate->sdiv << PLL2550XX_SDIV_SHIFT);
+ __raw_writel(tmp, pll->con_reg);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = __raw_readl(pll->con_reg);
+ } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
+ << PLL2550XX_LOCK_STAT_SHIFT)));
+ }
+
+ return 0;
+}
+
+static const struct clk_ops samsung_pll2550xx_clk_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll2550xx_set_rate,
+};
+
+static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
+ .recalc_rate = samsung_pll2550xx_recalc_rate,
+};
+
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
struct samsung_pll_clock *pll_clk,
void __iomem *base)
@@ -787,6 +888,12 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
else
init.ops = &samsung_pll46xx_clk_ops;
break;
+ case pll_2550xx:
+ if (!pll->rate_table)
+ init.ops = &samsung_pll2550xx_clk_min_ops;
+
[PATCH 1/7] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Pankaj Dubey
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by: Pankaj Dubey
Signed-off-by: Arun Kumar K
---
arch/arm/mach-exynos/Kconfig |9 +
arch/arm/mach-exynos/common.c| 19 ++-
arch/arm/mach-exynos/cpuidle.c |2 +-
arch/arm/mach-exynos/include/mach/map.h |1 +
arch/arm/mach-exynos/include/mach/regs-pmu.h |4
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
arch/arm/plat-samsung/include/plat/cpu.h |8
arch/arm/plat-samsung/include/plat/map-s5p.h |1 +
8 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..dcae2ec 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,15 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5260
+ bool "SAMSUNG EXYNOS5260"
+ default y
+ depends on ARCH_EXYNOS5
+ select AUTO_ZRELADDR
+ select SAMSUNG_DMADEV
+ help
+ Enable EXYNOS5260 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..5eb77d1 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5260[] = "EXYNOS5260";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5260_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5260,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -263,6 +270,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
@@ -371,7 +387,8 @@ static void __init exynos4_map_io(void)
static void __init exynos5_map_io(void)
{
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-
+ if (soc_is_exynos5260())
+ iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ddbfe87..405c11a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -120,7 +120,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device
*dev,
cpu_suspend(0, idle_finisher);
#ifdef CONFIG_SMP
- if (!soc_is_exynos5250())
+ if (!soc_is_exynos5250() || soc_is_exynos5260())
scu_enable(S5P_VA_SCU);
#endif
cpu_pm_exit();
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..bd6fa02 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5260_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h
b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 2cdb63e..09ae29a 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -234,6 +234,10 @@
#define EXYNOS5_SYS_WDTRESET (1 << 20)
+#define EXYNOS5260_A7_WDTRST (1 << 24)
+#define EXYNOS5260_A15_WDTRST (1 << 23)
+#define EXYNOS5260_SYS_WDTRESET(EXYNOS5260_A7_WDTRST ||
EXYNOS5260_A15_WDTRST)
+
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG
S5P_PMUREG(0x1000)
#define
[PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data
From: Young-Gun Jang
Add Samsung Exynos5260 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5260.
Signed-off-by: Pankaj Dubey
Signed-off-by: Rahul Sharma
Signed-off-by: Arun Kumar K
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 82
drivers/pinctrl/pinctrl-samsung.c |2 +
drivers/pinctrl/pinctrl-samsung.h |1 +
4 files changed, 86 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677d..2b32783 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+ - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 155b1b3..9a93df6 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -1042,6 +1042,88 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
},
};
+/* pin banks of exynos5260 pin-controller 0 */
+static struct samsung_pin_bank exynos5260_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0A0, "gpb2", 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpb4", 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
+ EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
+ EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1A0, "gpe1", 0x34),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1C0, "gpf0", 0x38),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1E0, "gpf1", 0x3c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5260 pin-controller 1 */
+static struct samsung_pin_bank exynos5260_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
+};
+
+/* pin banks of exynos5260 pin-controller 2 */
+static struct samsung_pin_bank exynos5260_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5420 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5260_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = "exynos5260-gpio-ctrl0",
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5260_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
+ .geint_con = EXYNOS_GPIO_ECON_OFFSET,
+ .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
+ .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .label = "exynos5260-gpio-ctrl1",
+ }, {
+
RE: [PATCH v4 3/9] phy: Add new Exynos USB PHY driver
Hi Kishon,
Thank you for the review.
> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> Sent: Friday, December 06, 2013 11:59 AM
>
> Hi,
>
> On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> > Add a new driver for the Exynos USB PHY. The new driver uses the
> > generic PHY framework. The driver includes support for the Exynos
> 4x10
> > and 4x12 SoC families.
> >
> > Signed-off-by: Kamil Debski
> > Signed-off-by: Kyungmin Park
> > ---
> > .../devicetree/bindings/phy/samsung-usbphy.txt | 54
> > drivers/phy/Kconfig| 20 ++
> > drivers/phy/Makefile |3 +
> > drivers/phy/phy-exynos4210-usb2.c | 264
> +
> > drivers/phy/phy-exynos4212-usb2.c | 312
>
> > drivers/phy/phy-samsung-usb2.c | 228
> ++
> > drivers/phy/phy-samsung-usb2.h | 72 +
> > 7 files changed, 953 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > create mode 100644 drivers/phy/phy-exynos4210-usb2.c create mode
> > 100644 drivers/phy/phy-exynos4212-usb2.c create mode 100644
> > drivers/phy/phy-samsung-usb2.c create mode 100644
> > drivers/phy/phy-samsung-usb2.h
> >
> > diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > new file mode 100644
> > index 000..cadbf70
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
>
> use the existing samsung-phy.txt.
Ok.
> > @@ -0,0 +1,54 @@
> > +Samsung S5P/EXYNOS SoC series USB PHY
> > +-
> > +
> > +Required properties:
> > +- compatible : should be one of the listed compatibles:
> > + - "samsung,exynos4210-usb2-phy"
> > + - "samsung,exynos4212-usb2-phy"
> > +- reg : a list of registers used by phy driver
> > + - first and obligatory is the location of phy modules registers
> > +- samsung,sysreg-phandle - handle to syscon used to control the
> > +system registers
> > +- samsung,pmureg-phandle - handle to syscon used to control PMU
> > +registers
> > +- #phy-cells : from the generic phy bindings, must be 1;
> > +- clocks and clock-names:
> > + - the "phy" clocks is required by the phy module
> > + - next for each of the phys a clock has to be assidned, this
> clock
>
> %s/assidned/assigned/
Thank you for spotting this.
> > + will be used to determine clocking frequency for the phys
> > + (the labels are specified in the paragraph below)
> > +
> > +The first phandle argument in the PHY specifier identifies the PHY,
> > +its meaning is compatible dependent. For the currently supported
> SoCs
> > +(Exynos 4210 and Exynos 4212) it is as follows:
> > + 0 - USB device ("device"),
> > + 1 - USB host ("host"),
> > + 2 - HSIC0 ("hsic0"),
> > + 3 - HSIC1 ("hsic1"),
> > +
> > +Exynos 4210 and Exynos 4212 use mode switching and require that mode
> > +switch register is supplied.
> > +
> > +Example:
> > +
> > +For Exynos 4412 (compatible with Exynos 4212):
> > +
> > +usbphy: phy@125B {
>
> use lower case for address here...
Ok.
> > + compatible = "samsung,exynos4212-usb2-phy";
> > + reg = <0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4>;
> and here..
> > + clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
> > + <&clock 2>;
> > + clock-names = "phy", "device", "host", "hsic0", "hsic1";
> > + status = "okay";
> > + #phy-cells = <1>;
> > + samsung,sysreg-phandle = <&sys_reg>;
> > + samsung,pmureg-phandle = <&pmu_reg>; };
> > +
> > +Then the PHY can be used in other nodes such as:
> > +
> > +phy-consumer@1234 {
> > + phys = <&usbphy 2>;
> > + phy-names = "phy";
> > +};
> > +
> > +Refer to DT bindings documentation of particular PHY consumer
> devices
> > +for more information about required PHYs and the way of
> specification.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index
> > a344f3d..b29018f 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -51,4 +51,24 @@ config PHY_EXYNOS_DP_VIDEO
> > help
> > Support for Display Port PHY found on Samsung EXYNOS SoCs.
> >
> > +config PHY_SAMSUNG_USB2
> > + tristate "Samsung USB 2.0 PHY driver"
> > + help
> > + Enable this to support Samsung USB phy helper driver for
> Samsung SoCs.
> > + This driver provides common interface to interact, for Samsung
> > + USB 2.0 PHY driver.
> > +
> > +config PHY_EXYNOS4210_USB2
> > + bool "Support for Exynos 4210"
> > + depends on PHY_SAMSUNG_USB2
> > + depends on CPU_EXYNOS4210
>
> select GENERIC_PHY here?
I think that depends on PHY_SAMSUNG_USB2 is better in this place.
However, I agree that I should add select GENERIC_PHY to PHY_SAMSUNG_USB2.
The reason why I am saying this is that I like how it looks in
men
RE: [PATCH v4 5/9] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework
Hi, > From: Matt Porter [mailto:matt.por...@linaro.org] > Sent: Friday, December 06, 2013 4:01 PM > > On Fri, Dec 06, 2013 at 04:41:51PM +0530, Kishon Vijay Abraham I wrote: > > Hi, > > > > On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote: > > > Change the used phy driver to the new Exynos USB phy driver that > > > uses the generic phy framework. > > > > > > Signed-off-by: Kamil Debski > > > Signed-off-by: Kyungmin Park > > > --- > > > .../devicetree/bindings/usb/samsung-hsotg.txt |4 > > > drivers/usb/gadget/s3c-hsotg.c | 11 ++-- > --- > > > 2 files changed, 10 insertions(+), 5 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/usb/samsung- > hsotg.txt > > > b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt > > > index b83d428..9340d06 100644 > > > --- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt > > > +++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt > > > @@ -24,6 +24,8 @@ Required properties: > > > - first entry: must be "otg" > > > - vusb_d-supply: phandle to voltage regulator of digital section, > > > - vusb_a-supply: phandle to voltage regulator of analog section. > > > +- phys: from general PHY binding: phandle to the PHY device > > > +- phy-names: from general PHY binding: should be "usb2-phy" > > > > are you sure it's usb2-phy. The example below seems to have a > different value. > > I requested this be changed to usb2-phy, looks like he just missed the > update to the example. This is true. I missed the change in the example part of the file. > > > > > > > > > Example > > > - > > > @@ -36,5 +38,7 @@ Example > > > clock-names = "otg"; > > > vusb_d-supply = <&vusb_reg>; > > > vusb_a-supply = <&vusbdac_reg>; > > > + phys = <&usb2phy 0>; > > > + phy-names = "device"; > > > }; Best wishes, -- Kamil Debski Samsung R&D Institute Poland -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
Leela Krishna,
On Thu, Dec 5, 2013 at 9:47 PM, Leela Krishna Amudala
wrote:
> This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to
> handle PMU register accesses in a centralized way using syscon driver
>
> Signed-off-by: Leela Krishna Amudala
> Reviewed-by: Tomasz Figa
> Reviewed-by: Doug Anderson
> Tested-by: Doug Anderson
> ---
> Documentation/devicetree/bindings/arm/samsung/pmu.txt | 15 +++
> arch/arm/boot/dts/exynos5250.dtsi |5 +
> arch/arm/boot/dts/exynos5420.dtsi |5 +
> 3 files changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> new file mode 100644
> index 000..f1f1552
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> @@ -0,0 +1,15 @@
> +SAMSUNG Exynos SoC series PMU Registers
> +
> +Properties:
> + - compatible : should contain two values. First value must be one from
> following list:
> + - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
> + - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
> + second value must be always "syscon".
> +
> + - reg : offset and length of the register set.
> +
> +Example :
> +pmu_system_controller: system-controller@1004 {
> + compatible = "samsung,exynos5250-pmu", "syscon";
> + reg = <0x1004 0x5000>;
> +};
This looks right to me based on previous discussion. Hopefully Olof
and/or Tomasz can indicate that they're happy with it now.
-Doug
--
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Re: [PATCH V12 2/3] watchdog: s3c2410_wdt: use syscon regmap interface to configure pmu register
Leela Krishna, On Thu, Dec 5, 2013 at 9:47 PM, Leela Krishna Amudala wrote: > Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap > interface > to configure AUTOMATIC_WDT_RESET_DISABLE and MASK_WDT_RESET_REQUEST registers > of PMU > to mask/unmask enable/disable of watchdog in probe and s2r scenarios. > > Signed-off-by: Leela Krishna Amudala > Signed-off-by: Doug Anderson > --- > .../devicetree/bindings/watchdog/samsung-wdt.txt | 21 ++- > drivers/watchdog/Kconfig |1 + > drivers/watchdog/s3c2410_wdt.c | 154 > ++-- > 3 files changed, 166 insertions(+), 10 deletions(-) Thank you for incorporating the fixups. Reviewed-by: Doug Anderson Tested-by: Doug Anderson -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 3/9] phy: Add new Exynos USB PHY driver
Hi,
> From: Kamil Debski [mailto:k.deb...@samsung.com]
> Sent: Friday, December 06, 2013 5:28 PM
>
> Hi Kishon,
>
> Thank you for the review.
>
> > From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> > Sent: Friday, December 06, 2013 11:59 AM
> >
> > Hi,
> >
> > On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
> > > Add a new driver for the Exynos USB PHY. The new driver uses the
> > > generic PHY framework. The driver includes support for the Exynos
> > 4x10
> > > and 4x12 SoC families.
> > >
> > > Signed-off-by: Kamil Debski
> > > Signed-off-by: Kyungmin Park
> > > ---
> > > .../devicetree/bindings/phy/samsung-usbphy.txt | 54
> > > drivers/phy/Kconfig| 20 ++
> > > drivers/phy/Makefile |3 +
> > > drivers/phy/phy-exynos4210-usb2.c | 264
> > +
> > > drivers/phy/phy-exynos4212-usb2.c | 312
> >
> > > drivers/phy/phy-samsung-usb2.c | 228
> > ++
> > > drivers/phy/phy-samsung-usb2.h | 72 +
> > > 7 files changed, 953 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > > create mode 100644 drivers/phy/phy-exynos4210-usb2.c create mode
> > > 100644 drivers/phy/phy-exynos4212-usb2.c create mode 100644
> > > drivers/phy/phy-samsung-usb2.c create mode 100644
> > > drivers/phy/phy-samsung-usb2.h
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > > b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> > > new file mode 100644
> > > index 000..cadbf70
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
> >
> > use the existing samsung-phy.txt.
>
> Ok.
>
> > > @@ -0,0 +1,54 @@
> > > +Samsung S5P/EXYNOS SoC series USB PHY
> > > +-
> > > +
> > > +Required properties:
> > > +- compatible : should be one of the listed compatibles:
> > > + - "samsung,exynos4210-usb2-phy"
> > > + - "samsung,exynos4212-usb2-phy"
> > > +- reg : a list of registers used by phy driver
> > > + - first and obligatory is the location of phy modules registers
> > > +- samsung,sysreg-phandle - handle to syscon used to control the
> > > +system registers
> > > +- samsung,pmureg-phandle - handle to syscon used to control PMU
> > > +registers
> > > +- #phy-cells : from the generic phy bindings, must be 1;
> > > +- clocks and clock-names:
> > > + - the "phy" clocks is required by the phy module
> > > + - next for each of the phys a clock has to be assidned, this
> > clock
> >
> > %s/assidned/assigned/
>
> Thank you for spotting this.
>
> > > + will be used to determine clocking frequency for the phys
> > > + (the labels are specified in the paragraph below)
> > > +
> > > +The first phandle argument in the PHY specifier identifies the PHY,
> > > +its meaning is compatible dependent. For the currently supported
> > SoCs
> > > +(Exynos 4210 and Exynos 4212) it is as follows:
> > > + 0 - USB device ("device"),
> > > + 1 - USB host ("host"),
> > > + 2 - HSIC0 ("hsic0"),
> > > + 3 - HSIC1 ("hsic1"),
> > > +
> > > +Exynos 4210 and Exynos 4212 use mode switching and require that
> > > +mode switch register is supplied.
> > > +
> > > +Example:
> > > +
> > > +For Exynos 4412 (compatible with Exynos 4212):
> > > +
> > > +usbphy: phy@125B {
> >
> > use lower case for address here...
>
> Ok.
>
> > > + compatible = "samsung,exynos4212-usb2-phy";
> > > + reg = <0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4>;
> > and here..
> > > + clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
> > > + <&clock 2>;
> > > + clock-names = "phy", "device", "host", "hsic0", "hsic1";
> > > + status = "okay";
> > > + #phy-cells = <1>;
> > > + samsung,sysreg-phandle = <&sys_reg>;
> > > + samsung,pmureg-phandle = <&pmu_reg>; };
> > > +
> > > +Then the PHY can be used in other nodes such as:
> > > +
> > > +phy-consumer@1234 {
> > > + phys = <&usbphy 2>;
> > > + phy-names = "phy";
> > > +};
> > > +
> > > +Refer to DT bindings documentation of particular PHY consumer
> > devices
> > > +for more information about required PHYs and the way of
> > specification.
> > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index
> > > a344f3d..b29018f 100644
> > > --- a/drivers/phy/Kconfig
> > > +++ b/drivers/phy/Kconfig
> > > @@ -51,4 +51,24 @@ config PHY_EXYNOS_DP_VIDEO
> > > help
> > > Support for Display Port PHY found on Samsung EXYNOS SoCs.
> > >
> > > +config PHY_SAMSUNG_USB2
> > > + tristate "Samsung USB 2.0 PHY driver"
> > > + help
> > > + Enable this to support Samsung USB phy helper driver for
> > Samsung SoCs.
> > > + This driver provides common interface to interact, for Samsung
> > > + USB 2.0 PHY driver.
> > > +
> > > +config PHY_EXYNOS4210_USB2
> > > + bool "Support for
Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
Hi,
Just a few minor comments...
On 12/06/2013 06:47 AM, Leela Krishna Amudala wrote:
This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to
s/pmusysreg/PMU sysreg ? Similarly I would capitalize it in the subject
line as well.
handle PMU register accesses in a centralized way using syscon driver
Signed-off-by: Leela Krishna Amudala
Reviewed-by: Tomasz Figa
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 15 +++
arch/arm/boot/dts/exynos5250.dtsi |5 +
arch/arm/boot/dts/exynos5420.dtsi |5 +
3 files changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
new file mode 100644
index 000..f1f1552
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
I might be easy to confuse this with ARM Performance Monitoring Unit.
So perhaps we should rename this file to, e.g. power-management-unit.txt ?
@@ -0,0 +1,15 @@
+SAMSUNG Exynos SoC series PMU Registers
s/PMU/Power Management Unit ?
+
+Properties:
+ - compatible : should contain two values. First value must be one from
following list:
+ - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
+ - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
s/./; ?
+ second value must be always "syscon".
It might be more safe to specify it as the last value, so something along
the lines of:
The last value should be "syscon".
+
+ - reg : offset and length of the register set.
+
+Example :
+pmu_system_controller: system-controller@1004 {
Might be more sensible to use 'power_management_unit' for the label.
+ compatible = "samsung,exynos5250-pmu", "syscon";
+ reg =<0x1004 0x5000>;
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index b98ffc3..62f9e36 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -163,6 +163,11 @@
interrupts =<0 47 0>;
};
+ pmu_system_controller: system-controller@1004 {
s/pmu_system_controller/power_management_unit ? So it describes the
subsystem
better in terms used in the SoCs User Manual ?
+ compatible = "samsung,exynos5250-pmu", "syscon";
+ reg =<0x1004 0x5000>;
+ };
+
watchdog {
clocks =<&clock 336>;
clock-names = "watchdog";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index b1fa334..cd47db0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -402,4 +402,9 @@
clock-names = "gscl";
samsung,power-domain =<&gsc_pd>;
};
+
+ pmu_system_controller: system-controller@1004 {
s/pmu_system_controller/power_management_unit ?
+ compatible = "samsung,exynos5420-pmu", "syscon";
+ reg =<0x1004 0x5000>;
+ };
};
Otherwise looks good.
Thanks,
Sylwester
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Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
On Fri, Dec 06, 2013 at 11:17:46AM +0530, Leela Krishna Amudala wrote: > This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to > handle PMU register accesses in a centralized way using syscon driver > > Signed-off-by: Leela Krishna Amudala > Reviewed-by: Tomasz Figa > Reviewed-by: Doug Anderson > Tested-by: Doug Anderson Acked-by: Guenter Roeck -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 2/3] watchdog: s3c2410_wdt: use syscon regmap interface to configure pmu register
On Fri, Dec 06, 2013 at 11:17:47AM +0530, Leela Krishna Amudala wrote: > Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap > interface > to configure AUTOMATIC_WDT_RESET_DISABLE and MASK_WDT_RESET_REQUEST registers > of PMU > to mask/unmask enable/disable of watchdog in probe and s2r scenarios. > > Signed-off-by: Leela Krishna Amudala > Signed-off-by: Doug Anderson Reviewed-by: Guenter Roeck -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 3/3] ARM: dts: update watchdog device nodes for Exynos5250 and Exynos5420
On Fri, Dec 06, 2013 at 11:17:48AM +0530, Leela Krishna Amudala wrote: > In Exynos5 series SoCs, PMU has registers to enable/disable mask/unmask > watchdog timer which is not the case with s3c series SoCs so, there is a > need to have different compatible names for watchdog to handle these pmu > registers access. > > Hence this patch removes watchdog node from Exynos5.dtsi common file and > make it separate by updating existing node in Exynos5250 and adding new node > to Exynos5420. This patch also makes the watchdog node enabled by default > > Signed-off-by: Leela Krishna Amudala > Reviewed-by: Tomasz Figa > Reviewed-by: Doug Anderson > Tested-by: Doug Anderson Acked-by: Guenter Roeck -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/2] watchdog: s3c2410_wdt: Report when the watchdog reset the system
On Thu, Dec 05, 2013 at 10:15:29AM -0800, Doug Anderson wrote:
> A good watchdog driver is supposed to report when it was responsible
> for resetting the system. Implement this for the s3c2410, at least on
> exynos5250 and exynos5420 where we already have a pointer to the PMU
> registers to read the information.
>
> Note that exynos4 SoCs also provide the reset status, but providing
> that is left as an exercise for future changes and is not plumbed up
> in this patch series. Also note the exynos4 SoCs don't appear to need
> any PMU config, which is why this patch separates the concepts of
> having PMU Registers vs. needing PMU Config.
>
> Signed-off-by: Doug Anderson
> ---
> Changes in v2:
> - Explained QUIRK organization in patch descritpion.
> - Reduced indentation as per Olof and Tomasz suggestion.
> - Now atop proposed v12 of Leela Krishna's patches.
Hi Doug,
The patch doesn't apply on top of v12, unfortunately.
> - NEEDS => HAS, EXYNOS5 prefix
>
> drivers/watchdog/s3c2410_wdt.c | 42
> +++---
> 1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 6a00299..45a9503 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -62,9 +62,15 @@
> #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
> #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
>
> +#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
> #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
> #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET0x040c
> #define QUIRK_HAS_PMU_CONFIG (1 << 0)
> +#define QUIRK_HAS_RST_STAT (1 << 1)
> +
> +/* These quirks require that we have a PMU register map */
> +#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
> + QUIRK_HAS_RST_STAT)
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> static int tmr_margin;
> @@ -98,6 +104,9 @@ MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for
> debug (default 0)");
> * timer reset functionality.
> * @mask_bit: Bit number for the watchdog timer in the disable register and
> the
> * mask reset register.
> + * @rst_stat_reg: Offset in pmureg for the register that has the reset
> status.
> + * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
> + * reset.
> * @quirks: A bitfield of quirks.
> */
>
> @@ -105,6 +114,8 @@ struct s3c2410_wdt_variant {
> int disable_reg;
> int mask_reset_reg;
> int mask_bit;
> + int rst_stat_reg;
> + int rst_stat_bit;
> u32 quirks;
> };
>
> @@ -131,14 +142,20 @@ static const struct s3c2410_wdt_variant
> drv_data_exynos5250 = {
> .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
> .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
> .mask_bit = 20,
> - .quirks = QUIRK_HAS_PMU_CONFIG
> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 20,
> + .quirks = QUIRK_HAS_PMU_CONFIG |
> + QUIRK_HAS_RST_STAT,
Any reason not to use QUIRKS_HAVE_PMUREG ?
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
> .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
> .mask_bit = 0,
> - .quirks = QUIRK_HAS_PMU_CONFIG
> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 9,
> + .quirks = QUIRK_HAS_PMU_CONFIG |
> + QUIRK_HAS_RST_STAT,
Same here. Even if you don't use QUIRKS_HAVE_PMUREG, the continuation line is
not needed.
Thanks,
Guenter
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Re: [PATCH v2 2/2] watchdog: s3c2410_wdt: Report when the watchdog reset the system
Guenter,
On Fri, Dec 6, 2013 at 11:54 AM, Guenter Roeck wrote:
> On Thu, Dec 05, 2013 at 10:15:29AM -0800, Doug Anderson wrote:
>> A good watchdog driver is supposed to report when it was responsible
>> for resetting the system. Implement this for the s3c2410, at least on
>> exynos5250 and exynos5420 where we already have a pointer to the PMU
>> registers to read the information.
>>
>> Note that exynos4 SoCs also provide the reset status, but providing
>> that is left as an exercise for future changes and is not plumbed up
>> in this patch series. Also note the exynos4 SoCs don't appear to need
>> any PMU config, which is why this patch separates the concepts of
>> having PMU Registers vs. needing PMU Config.
>>
>> Signed-off-by: Doug Anderson
>> ---
>> Changes in v2:
>> - Explained QUIRK organization in patch descritpion.
>> - Reduced indentation as per Olof and Tomasz suggestion.
>> - Now atop proposed v12 of Leela Krishna's patches.
>
> Hi Doug,
>
> The patch doesn't apply on top of v12, unfortunately.
OK, I'll re-send shortly.
>> - NEEDS => HAS, EXYNOS5 prefix
>>
>> drivers/watchdog/s3c2410_wdt.c | 42
>> +++---
>> 1 file changed, 39 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
>> index 6a00299..45a9503 100644
>> --- a/drivers/watchdog/s3c2410_wdt.c
>> +++ b/drivers/watchdog/s3c2410_wdt.c
>> @@ -62,9 +62,15 @@
>> #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
>> #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
>>
>> +#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
>> #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
>> #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET0x040c
>> #define QUIRK_HAS_PMU_CONFIG (1 << 0)
>> +#define QUIRK_HAS_RST_STAT (1 << 1)
>> +
>> +/* These quirks require that we have a PMU register map */
>> +#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
>> + QUIRK_HAS_RST_STAT)
>>
>> static bool nowayout = WATCHDOG_NOWAYOUT;
>> static int tmr_margin;
>> @@ -98,6 +104,9 @@ MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for
>> debug (default 0)");
>> * timer reset functionality.
>> * @mask_bit: Bit number for the watchdog timer in the disable register and
>> the
>> * mask reset register.
>> + * @rst_stat_reg: Offset in pmureg for the register that has the reset
>> status.
>> + * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
>> + * reset.
>> * @quirks: A bitfield of quirks.
>> */
>>
>> @@ -105,6 +114,8 @@ struct s3c2410_wdt_variant {
>> int disable_reg;
>> int mask_reset_reg;
>> int mask_bit;
>> + int rst_stat_reg;
>> + int rst_stat_bit;
>> u32 quirks;
>> };
>>
>> @@ -131,14 +142,20 @@ static const struct s3c2410_wdt_variant
>> drv_data_exynos5250 = {
>> .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
>> .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
>> .mask_bit = 20,
>> - .quirks = QUIRK_HAS_PMU_CONFIG
>> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
>> + .rst_stat_bit = 20,
>> + .quirks = QUIRK_HAS_PMU_CONFIG |
>> + QUIRK_HAS_RST_STAT,
>
> Any reason not to use QUIRKS_HAVE_PMUREG ?
My intent was that the QUIRKS_HAVE_PMUREG is a list of quirks that
require a PMU register and is used for testing, not for setting. When
someone adds another quirk that requires the PMU Registers I don't
want that to automatically apply to old hardware.
>> };
>>
>> static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
>> .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
>> .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
>> .mask_bit = 0,
>> - .quirks = QUIRK_HAS_PMU_CONFIG
>> + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
>> + .rst_stat_bit = 9,
>> + .quirks = QUIRK_HAS_PMU_CONFIG |
>> + QUIRK_HAS_RST_STAT,
>
> Same here. Even if you don't use QUIRKS_HAVE_PMUREG, the continuation line is
> not needed.
I will spin.
Thanks!
-Doug
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[PATCH v3] watchdog: s3c2410_wdt: Report when the watchdog reset the system
A good watchdog driver is supposed to report when it was responsible
for resetting the system. Implement this for the s3c2410, at least on
exynos5250 and exynos5420 where we already have a pointer to the PMU
registers to read the information.
Note that exynos4 SoCs also provide the reset status, but providing
that is left as an exercise for future changes and is not plumbed up
in this patch series. Also note the exynos4 SoCs don't appear to need
any PMU config, which is why this patch separates the concepts of
having PMU Registers vs. needing PMU Config.
Signed-off-by: Doug Anderson
---
Changes in v3:
- Atop the real v12 of Leela Krishna's patches.
- Combine QURIKs to one line.
Changes in v2:
- Explained QUIRK organization in patch descritpion.
- Reduced indentation as per Olof and Tomasz suggestion.
- Now atop proposed v12 of Leela Krishna's patches.
- NEEDS => HAS, EXYNOS5 prefix
drivers/watchdog/s3c2410_wdt.c | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index e1b1a75..ff1b5cc 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -62,9 +62,15 @@
#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
+#define EXYNOS5_RST_STAT_REG_OFFSET0x0404
#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
#define QUIRK_HAS_PMU_CONFIG (1 << 0)
+#define QUIRK_HAS_RST_STAT (1 << 1)
+
+/* These quirks require that we have a PMU register map */
+#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
+QUIRK_HAS_RST_STAT)
static bool nowayout = WATCHDOG_NOWAYOUT;
static int tmr_margin;
@@ -98,6 +104,9 @@ MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug
(default 0)");
* timer reset functionality.
* @mask_bit: Bit number for the watchdog timer in the disable register and the
* mask reset register.
+ * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
+ * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
+ * reset.
* @quirks: A bitfield of quirks.
*/
@@ -105,6 +114,8 @@ struct s3c2410_wdt_variant {
int disable_reg;
int mask_reset_reg;
int mask_bit;
+ int rst_stat_reg;
+ int rst_stat_bit;
u32 quirks;
};
@@ -131,14 +142,18 @@ static const struct s3c2410_wdt_variant
drv_data_exynos5250 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 20,
- .quirks = QUIRK_HAS_PMU_CONFIG
+ .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 20,
+ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
};
static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 0,
- .quirks = QUIRK_HAS_PMU_CONFIG
+ .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 9,
+ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
};
static const struct of_device_id s3c2410_wdt_match[] = {
@@ -427,6 +442,23 @@ static inline void s3c2410wdt_cpufreq_deregister(struct
s3c2410_wdt *wdt)
}
#endif
+static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
+{
+ unsigned int rst_stat;
+ int ret;
+
+ if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
+ return 0;
+
+ ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
+ if (ret)
+ dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
+ else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
+ return WDIOF_CARDRESET;
+
+ return 0;
+}
+
/* s3c2410_get_wdt_driver_data */
static inline struct s3c2410_wdt_variant *
get_wdt_drv_data(struct platform_device *pdev)
@@ -464,7 +496,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
wdt->wdt_device = s3c2410_wdd;
wdt->drv_data = get_wdt_drv_data(pdev);
- if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG) {
+ if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
"samsung,syscon-phandle");
if (IS_ERR(wdt->pmureg)) {
@@ -535,6 +567,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
watchdog_set_nowayout(&wdt->wdt_device, nowayout);
+ wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
+
ret = watchdog_register_device(&wdt->wdt_device);
if (ret) {
dev_err(dev, "cannot register watchdog (%d)\n", ret);
--
1.8.5
Re: [PATCH v3] watchdog: s3c2410_wdt: Report when the watchdog reset the system
On Fri, Dec 06, 2013 at 01:08:07PM -0800, Doug Anderson wrote: > A good watchdog driver is supposed to report when it was responsible > for resetting the system. Implement this for the s3c2410, at least on > exynos5250 and exynos5420 where we already have a pointer to the PMU > registers to read the information. > > Note that exynos4 SoCs also provide the reset status, but providing > that is left as an exercise for future changes and is not plumbed up > in this patch series. Also note the exynos4 SoCs don't appear to need > any PMU config, which is why this patch separates the concepts of > having PMU Registers vs. needing PMU Config. > > Signed-off-by: Doug Anderson Reviewed-by: Guenter Roeck -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
Guenter, On Fri, Dec 6, 2013 at 11:47 AM, Guenter Roeck wrote: > On Fri, Dec 06, 2013 at 11:17:46AM +0530, Leela Krishna Amudala wrote: >> This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to >> handle PMU register accesses in a centralized way using syscon driver >> >> Signed-off-by: Leela Krishna Amudala >> Reviewed-by: Tomasz Figa >> Reviewed-by: Doug Anderson >> Tested-by: Doug Anderson > > Acked-by: Guenter Roeck I'm curious of your opinion of Sylwester's requests, since your Ack came in after his requests. Would you like to see a respin of this, or do you think it's gone through enough spinning and are thinking it would go in as-is? -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
On Fri, Dec 06, 2013 at 03:01:23PM -0800, Doug Anderson wrote: > Guenter, > > On Fri, Dec 6, 2013 at 11:47 AM, Guenter Roeck wrote: > > On Fri, Dec 06, 2013 at 11:17:46AM +0530, Leela Krishna Amudala wrote: > >> This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to > >> handle PMU register accesses in a centralized way using syscon driver > >> > >> Signed-off-by: Leela Krishna Amudala > >> Reviewed-by: Tomasz Figa > >> Reviewed-by: Doug Anderson > >> Tested-by: Doug Anderson > > > > Acked-by: Guenter Roeck > > I'm curious of your opinion of Sylwester's requests, since your Ack > came in after his requests. Would you like to see a respin of this, > or do you think it's gone through enough spinning and are thinking it > would go in as-is? > My Ack means "I am ok with this patch without further changes". My reaction to the new comments was along the line of "sigh". Whoever comments now had more than 10 chances to comment earlier, which should have been way enough, and thus deserves to be ignored. Sorry if that statement happens to offend any listener, but I am not really known for my patience. Guenter -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V12 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files
Hi Sylwester,
On Friday 06 of December 2013 18:22:32 Sylwester Nawrocki wrote:
> Hi,
>
> Just a few minor comments...
I wouldn't really nitpick on such things, but if we end up needing another
respin, here's what I think.
>
> On 12/06/2013 06:47 AM, Leela Krishna Amudala wrote:
> > This patch adds pmusysreg node to exynos5250 and exynos5420 dtsi files to
>
> s/pmusysreg/PMU sysreg ? Similarly I would capitalize it in the subject
> line as well.
Well, since this is supposed to be a human readable description, I would
go even further and write "...device tree node of Power Management Unit
to...".
>
> > handle PMU register accesses in a centralized way using syscon driver
> >
> > Signed-off-by: Leela Krishna Amudala
> > Reviewed-by: Tomasz Figa
> > Reviewed-by: Doug Anderson
> > Tested-by: Doug Anderson
> > ---
> > Documentation/devicetree/bindings/arm/samsung/pmu.txt | 15
> > +++
> > arch/arm/boot/dts/exynos5250.dtsi |5 +
> > arch/arm/boot/dts/exynos5420.dtsi |5 +
> > 3 files changed, 25 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> > b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> > new file mode 100644
> > index 000..f1f1552
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
>
> I might be easy to confuse this with ARM Performance Monitoring Unit.
> So perhaps we should rename this file to, e.g. power-management-unit.txt ?
Considering location of this file, which is arm/samsung, I think this
name is pretty much clear. ARM PMU is a generic thing, so it couldn't
be placed here.
>
> > @@ -0,0 +1,15 @@
> > +SAMSUNG Exynos SoC series PMU Registers
>
> s/PMU/Power Management Unit ?
s/PMU Registers/Power Management Unit/
>
> > +
> > +Properties:
> > + - compatible : should contain two values. First value must be one from
> > following list:
> > + - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
> > + - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
>
> s/./; ?
>
> > + second value must be always "syscon".
>
> It might be more safe to specify it as the last value, so something along
> the lines of:
>
> The last value should be "syscon".
>
> > +
> > + - reg : offset and length of the register set.
> > +
> > +Example :
> > +pmu_system_controller: system-controller@1004 {
>
> Might be more sensible to use 'power_management_unit' for the label.
That's quite a lot of text for a label. pmu_syscon as in previous version
of this patch would look more sensible to me.
>
> > + compatible = "samsung,exynos5250-pmu", "syscon";
> > + reg =<0x1004 0x5000>;
> > +};
> > diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> > b/arch/arm/boot/dts/exynos5250.dtsi
> > index b98ffc3..62f9e36 100644
> > --- a/arch/arm/boot/dts/exynos5250.dtsi
> > +++ b/arch/arm/boot/dts/exynos5250.dtsi
> > @@ -163,6 +163,11 @@
> > interrupts =<0 47 0>;
> > };
> >
> > + pmu_system_controller: system-controller@1004 {
>
> s/pmu_system_controller/power_management_unit ? So it describes the
> subsystem
> better in terms used in the SoCs User Manual ?
See above.
>
> > + compatible = "samsung,exynos5250-pmu", "syscon";
> > + reg =<0x1004 0x5000>;
> > + };
> > +
> > watchdog {
> > clocks =<&clock 336>;
> > clock-names = "watchdog";
> > diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> > b/arch/arm/boot/dts/exynos5420.dtsi
> > index b1fa334..cd47db0 100644
> > --- a/arch/arm/boot/dts/exynos5420.dtsi
> > +++ b/arch/arm/boot/dts/exynos5420.dtsi
> > @@ -402,4 +402,9 @@
> > clock-names = "gscl";
> > samsung,power-domain =<&gsc_pd>;
> > };
> > +
> > + pmu_system_controller: system-controller@1004 {
>
> s/pmu_system_controller/power_management_unit ?
See above.
Best regards,
Tomasz
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