Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Tim Harvey]

On Mon, Mar 3, 2014 at 4:01 PM, Jason Gunthorpe
 wrote:
> On Mon, Mar 03, 2014 at 03:40:43PM -0800, Tim Harvey wrote:
>
>> of_irq_parse_and_map_pci().  The GIC function that translates the
>> interrupt per domain is given irq_data: 0x123 0x04 0x00
>
> This has been shifted by 1 byte..
>
>> IRQ 123, which should get 32 added to it for irq155).  Instead, the
>> implementation of gic_irq_domain_xlate()
>> (http://lxr.missinglinkelectronics.com/linux/drivers/irqchip/irq-gic.c#L832)
>> adds 32 to the 0x04 returning 20:
>> [1.841781] of_irq_parse_raw:  /soc/pcie@0x0100:0001
>> [1.841813] of_irq_parse_raw: ipar=/soc/pcie@0x0100, size=1
>> [1.841838]  -> addrsize=3
>> [1.841870]  -> match=1 (imaplen=28)
>   ^
>
> That looks odd, it should be the number of dwords in the
> interrupt-map, you have 4 lines of 8 dwords each, so it should be
> 32.

(+cc Grant Likely)

imaplen does indeed get initialized to 32 (size of interrupt-map /
sizeof(u32)) but its printed above after its been decremented in the
loop which is misleading
(http://lxr.missinglinkelectronics.com/linux/drivers/of/irq.c#L201)

The issue appears to me to be a bug in of_irq_parse_raw() which has
been around since Graht's original commit:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/of/irq.c?id=7dc2e1134a22dc242175d5321c0c9e97d16eb87b

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 9bcf2cf..8829197 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -237,11 +237,11 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle
/* Check for malformed properties */
if (WARN_ON(newaddrsize + newintsize > MAX_PHANDLE_ARGS)
goto fail;
-   if (imaplen < (newaddrsize + newintsize))
+   if (imaplen < newintsize)
goto fail;

-   imap += newaddrsize + newintsize;
-   imaplen -= newaddrsize + newintsize;
+   imap += newintsize;
+   imaplen -= newintsize;

pr_debug(" -> imaplen=%d\n", imaplen);
}

The issue is that the interrupt-map table point (imap) needs to be
incremented over the parent unit interrupt specifier which is
newintsize cells, not newaddrsize + newintsize cells.  The invalid
calculation would cause the pointer to get mis-aligned and thus only
the first interrupt entry would ever get properly checked for a match.

It looks like of_irq_parse_raw() is only called from
of_irq_parse_pci() which prior to Lucas' patch was only called from
pci_read_irq_line() called from pcibios_setup_device() used in
arch/arm/powerpc, so perhaps this function isn't widely used
explaining why the bug was never caught.

I'll post a patch shortly with the above fix.



>> [1.841972] irq_create_of_mapping: calling xlate for 123/4/0 3
>
> And it is the wrong data.. 123/4/0 is

right - this is shifted because of the issue above.

With the above patch Lucas' original patch now operates correctly to
resolve the 4 legacy PCI interrupts required when using a P2P bridge
on the IMX6.

Tim
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Re: [PATCH v3 5/5] clk/exynos5260: add clock file for exynos5260

[Rahul Sharma]

Thanks Tomasz,

I have almost reworked this file as per your comments. Please find my
inline comments.

On 23 February 2014 07:49, Tomasz Figa  wrote:
> Hi Rahul,
>
> On 18.02.2014 12:56, Rahul Sharma wrote:
>
> [snip]
>
>
>> diff --git a/drivers/clk/samsung/clk-exynos5260.c
>> b/drivers/clk/samsung/clk-exynos5260.c
>> new file mode 100644
>> index 000..bcb633e
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos5260.c
>> @@ -0,0 +1,2235 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>
>
> Most likely it should be 2013-2014 now.
Done.
>
>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Exynos5260 SoC.
>> +*/
>
>
> [snip]
>
>
>> +#ifdef CONFIG_PM_SLEEP
>> +
>> +/*
>> + * list of controller registers to be saved and restored during a
>> + * suspend/resume cycle.
>> +*/
>
>
> nit: Unaligned star. + The same for a lot of comments in this file.
>
Done.
>
>> +
>> +static unsigned long exynos5260_aud_clk_regs[] __initdata = {
>
>
> nit: There is no need to prefix every static variable in this file with
> exynos5260_. Shorter (but still completely readable) names will let the code
> using them have shorter lines.
>
Removed.
>
>> + *Registers for CMU_AUD
>> +*/
>> +   MUX_SEL_AUD,
>> +   DIV_AUD0,
>> +   DIV_AUD1,
>
>
> [snip]
>
>
>> +static void exynos5260_clk_sleep_init(void __iomem *reg_base,
>> +   unsigned long *rdump,
>> +   unsigned long nr_rdump)
>> +{
>> +   struct exynos5260_clock_reg_cache *reg_cache;
>> +
>> +   reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
>> +   GFP_KERNEL);
>> +   if (!reg_cache)
>> +   panic("could not allocate register cache.\n");
>> +
>> +   reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
>> +
>> +   if (!reg_cache->rdump)
>> +   panic("could not allocate register dump storage.\n");
>> +
>> +   reg_cache->rd_num = nr_rdump;
>> +   reg_cache->reg_base = reg_base;
>> +   list_add_tail(®_cache->node, &clock_reg_cache_list);
>> +
>> +   if (!syscore_ops_registered) {
>
>
> To eliminate the need for having a separate variable, you can simply move
> this if clause before list_add_tail() and check for list_empty().
>
Done. Removed this var.
>
>> +   register_syscore_ops(&exynos5260_clk_syscore_ops);
>> +   syscore_ops_registered = true;
>> +   }
>> +
>> +   exynos5260_clk_suspend();
>
>
> What is the reason to call this here and save register values of all
> registered CMus every time a new CMU is instantiated?
>
It is not required. Cleaned.

>
>> +}
>> +
>> +#else
>> +static void exynos5260_clk_sleep_init(void) {}
>> +#endif
>> +
>> +/*
>> + * List of parent clocks for muses in CMU_AUD
>> +*/
>> +PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
>> +PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user",
>> "ioclk_audcdclk0_user"};
>> +PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user",
>> "ioclk_audcdclk0_user"};
>> +
>> +/*
>> + * List of parent clocks for muses in CMU_DISP
>> +*/
>> +PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
>> +   "phyclk_dptx_phy_ch3_txd_clk"};
>> +PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
>> +   "phyclk_dptx_phy_ch2_txd_clk"};
>> +PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
>> +   "phyclk_dptx_phy_ch1_txd_clk"};
>> +PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
>> +   "phyclk_dptx_phy_ch0_txd_clk"};
>
>
> Whoa, these clock names are incredibly long. Are they real names from SoC
> User's Manual?
>
Yea, these are same in manual. I kept the name similar, otherwise not easy to
search them in UM.

>
>> +
>> +PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
>> +PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
>
>
> [snip]
>
>
>> +/* fixed rate clocks generated outside the soc */
>
>
> Huh? If they are generated outside the SoC, they shouldn't be registered by
> this driver, but rather by respective fixed rate clock nodes in DT.

I tried but system doesn't boot if fin_plll is registered from DT as
"fixed-clock".
of_fixed_clk_setup hits after the registration of other CMUs. System asserts
in many places due to div by zero error. It is exactly same for Exynos5420.
So I took 5420 as example and defined fin_pll as osc clock of compatible type
"samsung,exynos5260-oscclk". Rest of the ext clocks are registered as
"fixed-clock". What you say on this ?

>
>
>> +struct samsung_fixed_rate_clock exynos5260_fixed_rate_ext_clks[]
>> __initdata = {
>> +   FRATE(FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 2400),
>> +   FRATE(ID_NONE, "xrtcxti", NULL, CLK_IS_ROOT

Re: [REGRESSION] Arndale Octa panics when booting 3.14-rc1

[Mike Turquette]

On Mon, Mar 3, 2014 at 11:04 AM, Tomasz Figa  wrote:
> Hi,
>
>
> On 03.03.2014 19:57, Javi Merino wrote:
>>
>> Hi,
>>
>> Commit fcb0ee6a3d (clk: Implement clk_unregister) added calls to
>> kref_get() and kref_put() to __clk_get() and __clk_put() without
>> checking if clk is not NULL:
>>
>>> @@ -1987,6 +2097,7 @@ int __clk_get(struct clk *clk)
>>>  if (clk && !try_module_get(clk->owner))
>>>  return 0;
>>>
>>> +   kref_get(&clk->ref);
>>>  return 1;
>>>   }
>>>
>>> @@ -1995,6 +2106,10 @@ void __clk_put(struct clk *clk)
>>>  if (WARN_ON_ONCE(IS_ERR(clk)))
>>>  return;
>>>
>>> +   clk_prepare_lock();
>>> +   kref_put(&clk->ref, __clk_release);
>>> +   clk_prepare_unlock();
>>> +
>>>  if (clk)
>>>  module_put(clk->owner);
>>>   }
>>
>>
>> Before this commit, these functions allowed clk to be NULL.  In
>> particular, the "if (clk)" in __clk_put() is now useless, as clk has
>> been dereferenced by the time you reach it.
>>
>> This causes Arndale Octa to panic on boot:
>>
>> 8<---
>>  [7.43] Creating amba device /amba/pdma@121B
>>  [7.435000]create child: /amba/mdma@1080
>>  [7.44] Creating amba device /amba/mdma@1080
>>  [7.445000] Unable to handle kernel NULL pointer dereference at
>> virtual address 0050
>>  [7.45] pgd = c0004000
>>  [7.45] [0050] *pgd=
>>  [7.455000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
>>  [7.455000] Modules linked in:
>>  [7.455000] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 3.14.0-rc3-3-gb6026fe-dirty #23
>>  [7.455000] task: ee0a8000 ti: ee0a6000 task.ti: ee0a6000
>>  [7.455000] PC is at __clk_get+0x24/0x84
>>  [7.455000] LR is at of_clk_get+0x5c/0x74
>>  [7.455000] pc : []lr : []psr:
>> 6113
>>  [7.455000] sp : ee0a7d78  ip : ee0a7d88  fp : 0001
>>  [7.455000] r10: f001c000  r9 : ee193a10  r8 : 
>>  [7.455000] r7 :   r6 : ee7dedb4  r5 : c045e930  r4 :
>> 
>>  [7.455000] r3 : 0050  r2 : 01d9  r1 : c0575df8  r0 :
>> 
>>  [7.455000] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
>> Segment kernel
>>  [7.455000] Control: 10c5387d  Table: 2000406a  DAC: 0015
>>  [7.455000] Process swapper/0 (pid: 1, stack limit = 0xee0a6240)
>>  [7.455000] Stack: (0xee0a7d78 to 0xee0a8000)
>>  [7.455000] 7d60:
>>  c02e34b8
>>  [7.455000] 7d80: ee0a7d88 c02df2e4 ee7dd984 0001 01d9
>> ee7dedb4  c02df300
>>  [7.455000] 7da0: ee1779c0 c045e930 ee7dedb4  ee1779c0
>> c02e350c  ee1779c0
>>  [7.455000] 7dc0: c045e930 1000  c02e35a4 
>> ee194000 ee194128 c01ee6fc
>>  [7.455000] 7de0: ee194000 ee194128 1000 c01ee7ec 
>> ee7dedb4 ee194000 0009
>>  [7.455000] 7e00: ee19416c  0001 c02e0f94 c053f0f2
>>  ee193a10 c03b6880
>>  [7.455000] 7e20:  ee7dedb4 ee193a10  
>> 0001  c0385924
>>  [7.455000] 7e40: c047832c ee7dea18  ee7dedb4 ee193a10
>>   0001
>>  [7.455000] 7e60:  c02e103c 0001 c04c9500 0079
>> c03b6880  
>>  [7.455000] 7e80: 6113 c05352d8   c03b6880
>> 0001  ee7dea18
>>  [7.455000] 7ea0: ee7d6e28   c03b6880 
>> 0001  c02e116c
>>  [7.455000] 7ec0: 0001  c04cc264 ee0a6000 c04ec240
>>  c04c9500 c04fec18
>>  [7.455000] 7ee0: 0079 c04cc280  c00088e8 
>> c038cb70 006d 
>>  [7.455000] 7f00: 0001 c0101a2c ee15ce00 ee15d080 6100
>> c050fb40 6113 c050fb40
>>  [7.455000] 7f20: c04ec230 c050fb3c c050fb3c c04a79f0 c04a79f0
>> ef7fc9ff ef7fc9fb c0034f40
>>  [7.455000] 7f40: c043e434 c04a7260 0003 0003 
>> c04ec260 0003 c04ec240
>>  [7.455000] 7f60: c053b2c0 c04c9500 c04fec18 0079 
>> c04c9c50 0003 0003
>>  [7.455000] 7f80: c04c9500 c003e450  c0384474 
>>   
>>  [7.455000] 7fa0:  c038447c  c000e4b8 
>>   
>>  [7.455000] 7fc0:     
>>   
>>  [7.455000] 7fe0:     0013
>>   
>>  [7.455000] [] (__clk_get) from []
>> (of_clk_get+0x5c/0x74)
>>  [7.455000] [] (of_clk_get) from []
>> (of_clk_get_by_name+0x3c/0xb0)
>>  [7.455000] [] (of_clk_get_by_name) from []
>> (clk_get+0x24/0x44)
>>  [7.455000] [] (clk_get) from []
>> (amba_get_enable_pclk+0x10/0x60)
>>  [7.455000] [] (amba_get_enable

Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Jason Gunthorpe]

On Mon, Mar 03, 2014 at 03:40:43PM -0800, Tim Harvey wrote:

> of_irq_parse_and_map_pci().  The GIC function that translates the
> interrupt per domain is given irq_data: 0x123 0x04 0x00 

This has been shifted by 1 byte..

> IRQ 123, which should get 32 added to it for irq155).  Instead, the
> implementation of gic_irq_domain_xlate()
> (http://lxr.missinglinkelectronics.com/linux/drivers/irqchip/irq-gic.c#L832)
> adds 32 to the 0x04 returning 20:
> [1.841781] of_irq_parse_raw:  /soc/pcie@0x0100:0001
> [1.841813] of_irq_parse_raw: ipar=/soc/pcie@0x0100, size=1
> [1.841838]  -> addrsize=3
> [1.841870]  -> match=1 (imaplen=28)
  ^

That looks odd, it should be the number of dwords in the
interrupt-map, you have 4 lines of 8 dwords each, so it should be
32. 

You have 7*4, which really suggests to me that your interrupt-map
is corrupted somehow, are you sure you are using this:

>   interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>   <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
>   <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
>   <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

If an element was missing it would explain why everything is broken,
in fact if GIC_SPI was missing it would match the debug perfectly.

> [1.841903]  -> newintsize=3, newaddrsize=1
> [1.841916]  -> imaplen=23
> [1.841928]  -> new parent: /interrupt-controller@00a01000
> [1.841946]  -> got it !

K..

> [1.841972] irq_create_of_mapping: calling xlate for 123/4/0 3

And it is the wrong data.. 123/4/0 is 


> For the slots above that swizzle to pin2,3,4 of_irq_parse_raw()
> returns -EINVAL because for some reason it can't match an interrupt
> mapping for the pcie host controller:
> [1.842996] of_irq_parse_raw:  /soc/pcie@0x0100/pcie@0,0:0002
> [1.843046] of_irq_parse_raw: ipar=/soc/pcie@0x0100, size=1
> [1.843070]  -> addrsize=3
> [1.843100]  -> match=0 (imaplen=28)
> ^ indicates no match in interrupt map.

Well, since we know the map is corrupted somehow, it isn't surprising
that the 2nd entry won't match anything. It is probably matching
against '0 0 2 &intc'
 
Jason
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Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Tim Harvey]

On Mon, Mar 3, 2014 at 9:49 AM, Tim Harvey  wrote:
> On Mon, Mar 3, 2014 at 12:11 AM, Jingoo Han  wrote:
>> On Sunday, March 02, 2014 3:31 AM, Jason Gunthorpe wrote:
>>> On Fri, Feb 28, 2014 at 04:53:33PM -0800, Tim Harvey wrote:
>>>

> The configuration I'm testing is:
> root@OpenWrt:/# lspci -n
> 00:00.0 0604: 16c3:abcd (rev 01)
> 01:00.0 0604: 10b5:8609 (rev ba)
> 01:00.1 0880: 10b5:8609 (rev ba)
> 02:01.0 0604: 10b5:8609 (rev ba)
> 02:04.0 0604: 10b5:8609 (rev ba)
> 02:05.0 0604: 10b5:8609 (rev ba)
> 02:06.0 0604: 10b5:8609 (rev ba)
> 02:07.0 0604: 10b5:8609 (rev ba)
> 02:08.0 0604: 10b5:8609 (rev ba)
> 02:09.0 0604: 10b5:8609 (rev ba)
> 07:00.0 0280: 168c:002b (rev 01)
> 08:00.0 0200: 11ab:4380
> root@OpenWrt:/# lspci -tnv
> -[:00]---00.0-[01-09]--+-00.0-[02-09]--+-01.0-[03]--
>|   +-04.0-[04]--
>|   +-05.0-[05]--
>|   +-06.0-[06]--
>|   +-07.0-[07]00.0  168c:002b
>|   +-08.0-[08]00.0  11ab:4380
>|   \-09.0-[09]--
>\-00.1  10b5:8609
>
>
> The dev_info showing what of_irq_parse_and_map_pci() above produces:
> [1.818485] pci :00:00.0: dw_pcie_map_irq: 16c3:abcd slot0 pin1 irq20
> [1.818703] pci :01:00.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
> [1.818939] pci :01:00.1: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
> [1.819179] pci :02:01.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
> [1.819395] pci :02:04.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
> [1.819631] pci :02:05.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
> [1.819859] pci :02:06.0: dw_pcie_map_irq: 10b5:8609 slot0 pin3 irq0
> [1.820087] pci :02:07.0: dw_pcie_map_irq: 10b5:8609 slot0 pin4 irq0
> [1.820404] pci :02:08.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
> [1.820650] pci :02:09.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
> [1.820881] pci :07:00.0: dw_pcie_map_irq: 168c:002b slot0 pin4 irq0
> [1.821100] pci :08:00.0: dw_pcie_map_irq: 11ab:4380 slot0 pin1 irq20
>
> I'm not clear why irq 20 is getting returned for all the slots with
> (slot%4)=0 and func=0.  If I start debugging of_irq_parse_pci() I see
> that it walks up the tree until it gets to the pcie host controller
> then calls of_irq_parse_raw() which is returning irq20 or -EINVAL.

For the slots above that are swizzling to pin1 this appears to be an
issue with irq_create_of_mapping() called form
of_irq_parse_and_map_pci().  The GIC function that translates the
interrupt per domain is given irq_data: 0x123 0x04 0x00 (meaning GIC
IRQ 123, which should get 32 added to it for irq155).  Instead, the
implementation of gic_irq_domain_xlate()
(http://lxr.missinglinkelectronics.com/linux/drivers/irqchip/irq-gic.c#L832)
adds 32 to the 0x04 returning 20:
[1.841781] of_irq_parse_raw:  /soc/pcie@0x0100:0001
[1.841813] of_irq_parse_raw: ipar=/soc/pcie@0x0100, size=1
[1.841838]  -> addrsize=3
[1.841870]  -> match=1 (imaplen=28)
[1.841903]  -> newintsize=3, newaddrsize=1
[1.841916]  -> imaplen=23
[1.841928]  -> new parent: /interrupt-controller@00a01000
[1.841946]  -> got it !
[1.841972] irq_create_of_mapping: calling xlate for 123/4/0 3
[1.841984] irq_create_of_mapping got irq from xlate: 20
^ added debugging shows 3 u32's passed to xlate and returned value of 20
[1.841998] irq: irq_create_mapping(0xbec10400, 0x14)
[1.842009] irq: -> using domain @bec10400
[1.842021] irq: -> existing mapping on virq 20
[1.842032] irq_create_of_mapping created virq=20
[1.842042] irq_create_of_mapping returning virq=20
[1.842059] pci :00:00.0: dw_pcie_map_irq: 16c3:abcd slot0 pin1 irq20

Perhaps this is a byte-ordering issue?  I'm wondering if the args
created in of_irq_parse_pci are getting put in the wrong place for
what irq_create_of_mapping() expects.

For the slots above that swizzle to pin2,3,4 of_irq_parse_raw()
returns -EINVAL because for some reason it can't match an interrupt
mapping for the pcie host controller:
[1.842996] of_irq_parse_raw:  /soc/pcie@0x0100/pcie@0,0:0002
[1.843046] of_irq_parse_raw: ipar=/soc/pcie@0x0100, size=1
[1.843070]  -> addrsize=3
[1.843100]  -> match=0 (imaplen=28)
^ indicates no match in interrupt map.

I think this is because size=1 above, when we should see an
interrupt-map of size 4.  I'm guessing that the function is confused
between the single interrupt in the DT for the host controller, vs the
interrupt-map for the PCI interrupts.

At this point, with no match, of_irq_parse_raw() will travel up to the
parent of the interrupt which is wrong.

Note the pcie host controller DT is:

pcie: pcie@0x0100 {
  compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
  reg = <0x01ff

Re: [REGRESSION] Arndale Octa panics when booting 3.14-rc1

[Sylwester Nawrocki]

Hi,

On 03/03/2014 08:04 PM, Tomasz Figa wrote:

On 03.03.2014 19:57, Javi Merino wrote:

Hi,

Commit fcb0ee6a3d (clk: Implement clk_unregister) added calls to
kref_get() and kref_put() to __clk_get() and __clk_put() without
checking if clk is not NULL:


@@ -1987,6 +2097,7 @@ int __clk_get(struct clk *clk)
 if (clk && !try_module_get(clk->owner))
 return 0;

+   kref_get(&clk->ref);
 return 1;
  }

@@ -1995,6 +2106,10 @@ void __clk_put(struct clk *clk)
 if (WARN_ON_ONCE(IS_ERR(clk)))
 return;

+   clk_prepare_lock();
+   kref_put(&clk->ref, __clk_release);
+   clk_prepare_unlock();
+
 if (clk)
 module_put(clk->owner);
  }


Before this commit, these functions allowed clk to be NULL.  In
particular, the "if (clk)" in __clk_put() is now useless, as clk has
been dereferenced by the time you reach it.

This causes Arndale Octa to panic on boot:

8<---
 [7.43] Creating amba device /amba/pdma@121B
 [7.435000]create child: /amba/mdma@1080
 [7.44] Creating amba device /amba/mdma@1080
 [7.445000] Unable to handle kernel NULL pointer dereference at virtual 
address 0050

 [7.45] pgd = c0004000
 [7.45] [0050] *pgd=
 [7.455000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
 [7.455000] Modules linked in:
 [7.455000] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 
3.14.0-rc3-3-gb6026fe-dirty #23

 [7.455000] task: ee0a8000 ti: ee0a6000 task.ti: ee0a6000
 [7.455000] PC is at __clk_get+0x24/0x84
 [7.455000] LR is at of_clk_get+0x5c/0x74

[...]


 [7.455000] [] (__clk_get) from [] 
(of_clk_get+0x5c/0x74)

 [7.455000] [] (of_clk_get) from [] 
(of_clk_get_by_name+0x3c/0xb0)

 [7.455000] [] (of_clk_get_by_name) from [] 
(clk_get+0x24/0x44)

 [7.455000] [] (clk_get) from [] 
(amba_get_enable_pclk+0x10/0x60)

 [7.455000] [] (amba_get_enable_pclk) from [] 
(amba_device_add+0xa0/0x1e0)

 [7.455000] [] (amba_device_add) from [] 
(of_platform_bus_create+0x190/0x308)

 [7.455000] [] (of_platform_bus_create) from [] 
(of_platform_bus_create+0x238

 [7.455000] [] (of_platform_bus_create) from [] 
(of_platform_populate+0x60/0x

 [7.455000] [] (of_platform_populate) from [] 
(customize_machine+0x1c/0x40)

 [7.455000] [] (customize_machine) from [] 
(do_one_initcall+0xe4/0x140)

 [7.455000] [] (do_one_initcall) from [] 
(kernel_init_freeable+0xfc/0x1c8)

 [7.455000] [] (kernel_init_freeable) from [] 
(kernel_init+0x8/0xe4)

 [7.455000] [] (kernel_init) from [] 
(ret_from_fork+0x14/0x3c)

 [7.455000] Code: e350 08bd8010 e2843050 f57ff05b (e1932f9f)
 [7.46] ---[ end trace fe5cfa405506a77d ]---
 [7.46] Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x000b

8<---

I've tried putting "if (clk)" around the calls to kref_get() and
kref_put(), but that makes the Octa fail to boot like 3.13 did: when
tries to mount root.

What works for me so far is to remove the offending nodes from the DT:

8<---
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi

index 8db792b..c4ab992 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -303,27 +303,6 @@
 #dma-requests = <32>;
 };

-   mdma0: mdma@1080 {
-   compatible = "arm,pl330", "arm,primecell";
-   reg = <0x1080 0x1000>;
-   interrupts = <0 33 0>;
-   clocks = <&clock 473>;
-   clock-names = "apb_pclk";
-   #dma-cells = <1>;
-   #dma-channels = <8>;
-   #dma-requests = <1>;
-   };
-
-   mdma1: mdma@11C1 {
-   compatible = "arm,pl330", "arm,primecell";
-   reg = <0x11C1 0x1000>;
-   interrupts = <0 124 0>;
-   clocks = <&clock 442>;
-   clock-names = "apb_pclk";
-   #dma-cells = <1>;
-   #dma-channels = <8>;
-   #dma-requests = <1>;
-   };
 };

 spi_0: spi@12d2 {
8<---

With this the Arndale Octa boots.  This issue is present from 3.14-rc1
to 3.14-rc5.  Any idea how this should be properly fixed in mainline?


This should be fixed with [1], which was supposed to be merged for
3.14-rc5. Mike?

[1] 
https://git.linaro.org/people/mike.turquette/linux.git/commit/00efcb1c8e1c3c5e5d3ce6f0682d66402911a84f


You may also want to consider this patch:
https://patchwork.kernel.org/patch/3597711

It looks like there is no clock registered for the mdm0 PL330 device
in exynos5420 clocks driver (drivers/clk/samsung/clk-exyn

Re: [REGRESSION] Arndale Octa panics when booting 3.14-rc1

[Tomasz Figa]

Hi,

On 03.03.2014 19:57, Javi Merino wrote:

Hi,

Commit fcb0ee6a3d (clk: Implement clk_unregister) added calls to
kref_get() and kref_put() to __clk_get() and __clk_put() without
checking if clk is not NULL:


@@ -1987,6 +2097,7 @@ int __clk_get(struct clk *clk)
 if (clk && !try_module_get(clk->owner))
 return 0;

+   kref_get(&clk->ref);
 return 1;
  }

@@ -1995,6 +2106,10 @@ void __clk_put(struct clk *clk)
 if (WARN_ON_ONCE(IS_ERR(clk)))
 return;

+   clk_prepare_lock();
+   kref_put(&clk->ref, __clk_release);
+   clk_prepare_unlock();
+
 if (clk)
 module_put(clk->owner);
  }


Before this commit, these functions allowed clk to be NULL.  In
particular, the "if (clk)" in __clk_put() is now useless, as clk has
been dereferenced by the time you reach it.

This causes Arndale Octa to panic on boot:

8<---
 [7.43] Creating amba device /amba/pdma@121B
 [7.435000]create child: /amba/mdma@1080
 [7.44] Creating amba device /amba/mdma@1080
 [7.445000] Unable to handle kernel NULL pointer dereference at virtual 
address 0050
 [7.45] pgd = c0004000
 [7.45] [0050] *pgd=
 [7.455000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
 [7.455000] Modules linked in:
 [7.455000] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 
3.14.0-rc3-3-gb6026fe-dirty #23
 [7.455000] task: ee0a8000 ti: ee0a6000 task.ti: ee0a6000
 [7.455000] PC is at __clk_get+0x24/0x84
 [7.455000] LR is at of_clk_get+0x5c/0x74
 [7.455000] pc : []lr : []psr: 6113
 [7.455000] sp : ee0a7d78  ip : ee0a7d88  fp : 0001
 [7.455000] r10: f001c000  r9 : ee193a10  r8 : 
 [7.455000] r7 :   r6 : ee7dedb4  r5 : c045e930  r4 : 
 [7.455000] r3 : 0050  r2 : 01d9  r1 : c0575df8  r0 : 
 [7.455000] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  
Segment kernel
 [7.455000] Control: 10c5387d  Table: 2000406a  DAC: 0015
 [7.455000] Process swapper/0 (pid: 1, stack limit = 0xee0a6240)
 [7.455000] Stack: (0xee0a7d78 to 0xee0a8000)
 [7.455000] 7d60:   
 c02e34b8
 [7.455000] 7d80: ee0a7d88 c02df2e4 ee7dd984 0001 01d9 ee7dedb4 
 c02df300
 [7.455000] 7da0: ee1779c0 c045e930 ee7dedb4  ee1779c0 c02e350c 
 ee1779c0
 [7.455000] 7dc0: c045e930 1000  c02e35a4  ee194000 
ee194128 c01ee6fc
 [7.455000] 7de0: ee194000 ee194128 1000 c01ee7ec  ee7dedb4 
ee194000 0009
 [7.455000] 7e00: ee19416c  0001 c02e0f94 c053f0f2  
ee193a10 c03b6880
 [7.455000] 7e20:  ee7dedb4 ee193a10   0001 
 c0385924
 [7.455000] 7e40: c047832c ee7dea18  ee7dedb4 ee193a10  
 0001
 [7.455000] 7e60:  c02e103c 0001 c04c9500 0079 c03b6880 
 
 [7.455000] 7e80: 6113 c05352d8   c03b6880 0001 
 ee7dea18
 [7.455000] 7ea0: ee7d6e28   c03b6880  0001 
 c02e116c
 [7.455000] 7ec0: 0001  c04cc264 ee0a6000 c04ec240  
c04c9500 c04fec18
 [7.455000] 7ee0: 0079 c04cc280  c00088e8  c038cb70 
006d 
 [7.455000] 7f00: 0001 c0101a2c ee15ce00 ee15d080 6100 c050fb40 
6113 c050fb40
 [7.455000] 7f20: c04ec230 c050fb3c c050fb3c c04a79f0 c04a79f0 ef7fc9ff 
ef7fc9fb c0034f40
 [7.455000] 7f40: c043e434 c04a7260 0003 0003  c04ec260 
0003 c04ec240
 [7.455000] 7f60: c053b2c0 c04c9500 c04fec18 0079  c04c9c50 
0003 0003
 [7.455000] 7f80: c04c9500 c003e450  c0384474   
 
 [7.455000] 7fa0:  c038447c  c000e4b8   
 
 [7.455000] 7fc0:       
 
 [7.455000] 7fe0:     0013  
 
 [7.455000] [] (__clk_get) from [] 
(of_clk_get+0x5c/0x74)
 [7.455000] [] (of_clk_get) from [] 
(of_clk_get_by_name+0x3c/0xb0)
 [7.455000] [] (of_clk_get_by_name) from [] 
(clk_get+0x24/0x44)
 [7.455000] [] (clk_get) from [] 
(amba_get_enable_pclk+0x10/0x60)
 [7.455000] [] (amba_get_enable_pclk) from [] 
(amba_device_add+0xa0/0x1e0)
 [7.455000] [] (amba_device_add) from [] 
(of_platform_bus_create+0x190/0x308)
 [7.455000] [] (of_platform_bus_create) from [] 
(of_platform_bus_create+0x238
 [7.455000] [] (of_platform_bus_create) from [] 
(of_platform_populate+0x60/0x
 [7.45500

[REGRESSION] Arndale Octa panics when booting 3.14-rc1

[Javi Merino]

Hi,

Commit fcb0ee6a3d (clk: Implement clk_unregister) added calls to
kref_get() and kref_put() to __clk_get() and __clk_put() without
checking if clk is not NULL:

> @@ -1987,6 +2097,7 @@ int __clk_get(struct clk *clk)
> if (clk && !try_module_get(clk->owner))
> return 0;
> 
> +   kref_get(&clk->ref);
> return 1;
>  }
> 
> @@ -1995,6 +2106,10 @@ void __clk_put(struct clk *clk)
> if (WARN_ON_ONCE(IS_ERR(clk)))
> return;
> 
> +   clk_prepare_lock();
> +   kref_put(&clk->ref, __clk_release);
> +   clk_prepare_unlock();
> +
> if (clk)
> module_put(clk->owner);
>  }

Before this commit, these functions allowed clk to be NULL.  In
particular, the "if (clk)" in __clk_put() is now useless, as clk has
been dereferenced by the time you reach it.

This causes Arndale Octa to panic on boot:

8<---
[7.43] Creating amba device /amba/pdma@121B
[7.435000]create child: /amba/mdma@1080
[7.44] Creating amba device /amba/mdma@1080
[7.445000] Unable to handle kernel NULL pointer dereference at virtual 
address 0050
[7.45] pgd = c0004000
[7.45] [0050] *pgd=
[7.455000] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
[7.455000] Modules linked in:
[7.455000] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 
3.14.0-rc3-3-gb6026fe-dirty #23
[7.455000] task: ee0a8000 ti: ee0a6000 task.ti: ee0a6000
[7.455000] PC is at __clk_get+0x24/0x84
[7.455000] LR is at of_clk_get+0x5c/0x74
[7.455000] pc : []lr : []psr: 6113
[7.455000] sp : ee0a7d78  ip : ee0a7d88  fp : 0001
[7.455000] r10: f001c000  r9 : ee193a10  r8 : 
[7.455000] r7 :   r6 : ee7dedb4  r5 : c045e930  r4 : 
[7.455000] r3 : 0050  r2 : 01d9  r1 : c0575df8  r0 : 
[7.455000] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment 
kernel
[7.455000] Control: 10c5387d  Table: 2000406a  DAC: 0015
[7.455000] Process swapper/0 (pid: 1, stack limit = 0xee0a6240)
[7.455000] Stack: (0xee0a7d78 to 0xee0a8000)
[7.455000] 7d60:   
 c02e34b8
[7.455000] 7d80: ee0a7d88 c02df2e4 ee7dd984 0001 01d9 ee7dedb4 
 c02df300
[7.455000] 7da0: ee1779c0 c045e930 ee7dedb4  ee1779c0 c02e350c 
 ee1779c0
[7.455000] 7dc0: c045e930 1000  c02e35a4  ee194000 
ee194128 c01ee6fc
[7.455000] 7de0: ee194000 ee194128 1000 c01ee7ec  ee7dedb4 
ee194000 0009
[7.455000] 7e00: ee19416c  0001 c02e0f94 c053f0f2  
ee193a10 c03b6880
[7.455000] 7e20:  ee7dedb4 ee193a10   0001 
 c0385924
[7.455000] 7e40: c047832c ee7dea18  ee7dedb4 ee193a10  
 0001
[7.455000] 7e60:  c02e103c 0001 c04c9500 0079 c03b6880 
 
[7.455000] 7e80: 6113 c05352d8   c03b6880 0001 
 ee7dea18
[7.455000] 7ea0: ee7d6e28   c03b6880  0001 
 c02e116c
[7.455000] 7ec0: 0001  c04cc264 ee0a6000 c04ec240  
c04c9500 c04fec18
[7.455000] 7ee0: 0079 c04cc280  c00088e8  c038cb70 
006d 
[7.455000] 7f00: 0001 c0101a2c ee15ce00 ee15d080 6100 c050fb40 
6113 c050fb40
[7.455000] 7f20: c04ec230 c050fb3c c050fb3c c04a79f0 c04a79f0 ef7fc9ff 
ef7fc9fb c0034f40
[7.455000] 7f40: c043e434 c04a7260 0003 0003  c04ec260 
0003 c04ec240
[7.455000] 7f60: c053b2c0 c04c9500 c04fec18 0079  c04c9c50 
0003 0003
[7.455000] 7f80: c04c9500 c003e450  c0384474   
 
[7.455000] 7fa0:  c038447c  c000e4b8   
 
[7.455000] 7fc0:       
 
[7.455000] 7fe0:     0013  
 
[7.455000] [] (__clk_get) from [] 
(of_clk_get+0x5c/0x74)
[7.455000] [] (of_clk_get) from [] 
(of_clk_get_by_name+0x3c/0xb0)
[7.455000] [] (of_clk_get_by_name) from [] 
(clk_get+0x24/0x44)
[7.455000] [] (clk_get) from [] 
(amba_get_enable_pclk+0x10/0x60)
[7.455000] [] (amba_get_enable_pclk) from [] 
(amba_device_add+0xa0/0x1e0)
[7.455000] [] (amba_device_add) from [] 
(of_platform_bus_create+0x190/0x308)
[7.455000] [] (of_platform_bus_create) from [] 
(of_platform_bus_create+0x238
[7.455000] [] (of_platform_bus_create) from [] 
(of_platform_populate+0x60/0x
[7.455000] [] (of_platform_populate) from [] 
(customize_machine+0x1c/0x40)
   

Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Jason Gunthorpe]

On Mon, Mar 03, 2014 at 09:49:52AM -0800, Tim Harvey wrote:

> I'm not clear why irq 20 is getting returned for all the slots with
> (slot%4)=0 and func=0.  If I start debugging of_irq_parse_pci() I see
> that it walks up the tree until it gets to the pcie host controller
> then calls of_irq_parse_raw() which is returning irq20 or -EINVAL.

Can you share your DT as well?

Jason
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Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Tim Harvey]

On Mon, Mar 3, 2014 at 12:11 AM, Jingoo Han  wrote:
> On Sunday, March 02, 2014 3:31 AM, Jason Gunthorpe wrote:
>> On Fri, Feb 28, 2014 at 04:53:33PM -0800, Tim Harvey wrote:
>>
>> > In testing this on IMX6 I'm finding that 'of_irq_parse_and_map_pci()'
>> > always returns -EINVAL because it can't find a dt node for the host
>> > bridge:
>> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/of/of_pci_irq.c#n60.
>>
>> There may be some kind of issue in the pcie-designware.c:
>>
>> static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>> {
>> struct pci_bus *bus;
>> struct pcie_port *pp = sys_to_pcie(sys);
>>
>> if (pp) {
>> pp->root_bus_nr = sys->busnr;
>> bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
>>  ^^^
>>  Shouldn't be null for DT cases.
>>
>> Perhaps since the driver doesn't pass in a parent pointer, no parent
>> device is associated with the struct pci_bus that gets created, so
>> pci_bus_to_OF_node will always fail and the DT PCI mechanisms become
>> broken.
>
> Jason,
> Thank you for your advice. :-)

Jason,

Yes thank you - this does eliminate the -EINVAL from
of_irq_parse_pci() but something still is wrong (see below)

>
> Tim,
> I tested the following as Jason guided.

Jingoo,

Did you test this on in a configuration where devices are behind a
PCIe switch?  I'm still not getting the right IRQ's for that
configuration.

I'm working with the following patch:
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designwa
index 3e0c2af..a563a8d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -493,7 +493,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
dw_pci.nr_controllers = 1;
dw_pci.private_data = (void **)&pp;

-   pci_common_init(&dw_pci);
+   pci_common_init_dev(pp->dev, &dw_pci);
pci_assign_unassigned_resources();
 #ifdef CONFIG_PCI_DOMAINS
dw_pci.domain++;
@@ -726,7 +726,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_s

if (pp) {
pp->root_bus_nr = sys->busnr;
-   bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
+   bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
sys, &sys->resources);
} else {
bus = NULL;
@@ -742,6 +742,8 @@ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slo
int irq;

irq = of_irq_parse_and_map_pci(dev, slot, pin);
+   dev_info(&dev->dev, "%s: %04x:%04x slot%d pin%d irq%d\n",
+   __func__, dev->vendor, dev->device, slot, pin, irq);
if (!irq)
irq = pp->irq;


The configuration I'm testing is:
root@OpenWrt:/# lspci -n
00:00.0 0604: 16c3:abcd (rev 01)
01:00.0 0604: 10b5:8609 (rev ba)
01:00.1 0880: 10b5:8609 (rev ba)
02:01.0 0604: 10b5:8609 (rev ba)
02:04.0 0604: 10b5:8609 (rev ba)
02:05.0 0604: 10b5:8609 (rev ba)
02:06.0 0604: 10b5:8609 (rev ba)
02:07.0 0604: 10b5:8609 (rev ba)
02:08.0 0604: 10b5:8609 (rev ba)
02:09.0 0604: 10b5:8609 (rev ba)
07:00.0 0280: 168c:002b (rev 01)
08:00.0 0200: 11ab:4380
root@OpenWrt:/# lspci -tnv
-[:00]---00.0-[01-09]--+-00.0-[02-09]--+-01.0-[03]--
   |   +-04.0-[04]--
   |   +-05.0-[05]--
   |   +-06.0-[06]--
   |   +-07.0-[07]00.0  168c:002b
   |   +-08.0-[08]00.0  11ab:4380
   |   \-09.0-[09]--
   \-00.1  10b5:8609


The dev_info showing what of_irq_parse_and_map_pci() above produces:
[1.818485] pci :00:00.0: dw_pcie_map_irq: 16c3:abcd slot0 pin1 irq20
[1.818703] pci :01:00.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
[1.818939] pci :01:00.1: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
[1.819179] pci :02:01.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
[1.819395] pci :02:04.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
[1.819631] pci :02:05.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
[1.819859] pci :02:06.0: dw_pcie_map_irq: 10b5:8609 slot0 pin3 irq0
[1.820087] pci :02:07.0: dw_pcie_map_irq: 10b5:8609 slot0 pin4 irq0
[1.820404] pci :02:08.0: dw_pcie_map_irq: 10b5:8609 slot0 pin1 irq20
[1.820650] pci :02:09.0: dw_pcie_map_irq: 10b5:8609 slot0 pin2 irq0
[1.820881] pci :07:00.0: dw_pcie_map_irq: 168c:002b slot0 pin4 irq0
[1.821100] pci :08:00.0: dw_pcie_map_irq: 11ab:4380 slot0 pin1 irq20

I'm not clear why irq 20 is getting returned for all the slots with
(slot%4)=0 and func=0.  If I start debugging of_irq_parse_pci() I see
that it walks up the tree until it gets to the pcie host controller
then call

Re: [PATCH 3/3] regulator: s2mps11: Copy supported regulators from initconst

[Krzysztof Kozlowski]

> 
> Hi,
> 
> On Mon, 2014-03-03 at 10:09 +0800, Mark Brown wrote:
> > On Fri, Feb 28, 2014 at 11:01:50AM +0100, Krzysztof Kozlowski wrote:
> > > Add __initconst to 'regulator_desc' array with supported regulators.
> > > During probe choose how many and which regulators will be supported
> > > according to device ID. Then copy the 'regulator_desc' array to
> > > allocated memory so the regulator core can use it.
> > 
> > Applied, thanks.
> 
> Thanks! Unfortunately I wonder now whether it was a good idea to mark
> the regulator_desc array as __initconst. I've seen the warning from
> kbuild test robot:
> 
> >> WARNING: vmlinux.o(.text+0xf0faab): Section mismatch in reference
> from the function s2mps11_pmic_probe() to the
> variable .init.rodata:s2mps11_regulators
>The function s2mps11_pmic_probe() references
>the variable __initconst s2mps11_regulators.
>This is often because s2mps11_pmic_probe lacks a __initconst
>annotation or the annotation of s2mps11_regulators is wrong.
> 
> 
> I have two ideas for fixing this:
> 1. The s2mps11_pmic_probe() could be marked with __init and 
> platform_driver_probe() should be used. Unfortunately this does not work
> because the driver is registered and probed a little later after
> s2mps11_pmic_init() when I2C bus driver is probed. During that time the
> drv->probe() is actually NULL.
> 
> 2. The s2mps11_pmic_probe() won't be marked as __init and could copy the
> regulator_desc (__initconst) array to local static variable. This way if
> it would be called twice the mentioned array __initconst won't be
> dereferenced. Unfortunately this won't remove the warning.
> 
> Any ideas for solving this?

I sent a patch removing the __initconst. From my point of view these two
patches can be squashed, so effectively only choosing number of
supported regulators is introduced (as it was in my original patch from
11th of February).


Best regards,
Krzysztof

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[PATCH v2 01/11] base: power: Add generic OF-based power domain look-up

[Tomasz Figa]

This patch introduces generic code to perform power domain look-up using
device tree and automatically bind devices to their power domains.
Generic device tree binding is introduced to specify power domains of
devices in their device tree nodes.

Backwards compatibility with legacy Samsung-specific power domain
bindings is provided, but for now the new code is not compiled when
CONFIG_ARCH_EXYNOS is selected to avoid collision with legacy code. This
will change as soon as Exynos power domain code gets converted to use
the generic framework in further patch.

Signed-off-by: Tomasz Figa 
---
 .../devicetree/bindings/power/power_domain.txt |  51 
 drivers/base/power/domain.c| 298 +
 include/linux/pm_domain.h  |  46 
 kernel/power/Kconfig   |   4 +
 4 files changed, 399 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/power_domain.txt

diff --git a/Documentation/devicetree/bindings/power/power_domain.txt 
b/Documentation/devicetree/bindings/power/power_domain.txt
new file mode 100644
index 000..93be5d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/power_domain.txt
@@ -0,0 +1,51 @@
+* Generic power domains
+
+System on chip designs are often divided into multiple power domains that
+can be used for power gating of selected IP blocks for power saving by
+reduced leakage current.
+
+This device tree binding can be used to bind power domain consumer devices
+with their power domains provided by power domain providers. A power domain
+provider can be represented by any node in the device tree and can provide
+one or more power domains. A consumer node can refer to the provider by
+a phandle and a set of phandle arguments (so called power domain specifier)
+of length specified by #power-domain-cells property in the power domain
+provider node.
+
+==Power domain providers==
+
+Required properties:
+ - #power-domain-cells : Number of cells in a power domain specifier;
+   Typically 0 for nodes representing a single power domain and 1 for nodes
+   providing multiple power domains (e.g. power controllers), but can be
+   any value as specified by device tree binding documentation of particular
+   provider.
+
+Example:
+
+   power: power-controller@1234 {
+   compatible = "foo,power-controller";
+   reg = <0x1234 0x1000>;
+   #power-domain-cells = <1>;
+   };
+
+The node above defines a power controller that is a power domain provider
+and expects one cell as its phandle argument.
+
+==Power domain consumers==
+
+Required properties:
+ - power-domain : A phandle and power domain specifier as defined by bindings
+  of power controller specified by phandle.
+
+Example:
+
+   leaky-device@1235 {
+   compatible = "foo,i-leak-current";
+   reg = <0x1235 0x1000>;
+   power-domain = <&power 0>;
+   };
+
+The node above defines a typical power domain consumer device, which is located
+inside power domain with index 0 of power controller represented by node with
+label "power".
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index dc127e5..006b455 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -3,12 +3,16 @@
  *
  * Copyright (C) 2011 Rafael J. Wysocki , Renesas Electronics 
Corp.
  *
+ * Support for Device Tree based power domain providers:
+ * Copyright (C) 2014 Tomasz Figa 
+ *
  * This file is released under the GPLv2.
  */
 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2177,3 +2181,297 @@ void pm_genpd_init(struct generic_pm_domain *genpd,
list_add(&genpd->gpd_list_node, &gpd_list);
mutex_unlock(&gpd_list_lock);
 }
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+/*
+ * DEVICE TREE BASED POWER DOMAIN PROVIDERS
+ *
+ * The code below implements generic device tree based power domain providers
+ * that bind device tree nodes with generic power domains registered in the
+ * system.
+ *
+ * Any driver that registers generic power domains and need to support binding
+ * of devices to these domains is supposed to register a power domain provider,
+ * which maps a power domain specifier retrieved from device tree to a power
+ * domain.
+ *
+ * Two simple mapping functions have been provided for convenience:
+ *  - of_genpd_xlate_simple() for 1:1 device tree node to domain mapping,
+ *  - of_genpd_xlate_onecell() for mapping of multiple domains per node
+ *by index.
+ */
+
+/**
+ * struct of_genpd_provider - Power domain provider registration structure
+ * @link: Entry in global list of domain providers
+ * @node: Pointer to device tree node of domain provider
+ * @xlate: Provider-specific xlate callback mapping a set of specifier cells
+ * into a power domain.
+ * @data: context pointer to be passed into @xlate callback
+ */
+struct of_genpd_provider {
+   

[PATCH v2 00/11] Generic Device Tree based power domain look-up

[Tomasz Figa]

Up till now there was no single generic method to bind devices to their
power domains using Device Tree. Each platform has been doing this using
its own way, example of which are Exynos power domain bindings [1] and
look-up code [2].

This series is intended to change this and provide generic DT bindings for
power domain specification and generic code performing look-up of power
domains and binding them to devices.

First two patches are the most important part of this series, as they
introduce $subject. Patch 3 converts mach-exynos to use the new generic
method. Further patches are adding one more user of the new code,
mach-s3c64xx, with first 3 patches (4-6) required to clean-up its power
domain driver a bit and last 3 patches (9-11) adding display support for
Mini6410 board, including a node for display controller (FIMD) which is
a power domain consumer.

The design of DT bindings and provider code is heavily inspired by
implementation of clock providers in Common Clock Framework, while
the code binding devices to power domains by my Exynos power domain
implementation (now removed by this series ;)).

Successfully tested on S3C6410-based Mini6410 board.

[1] Documentation/devicetree/bindings/arm/exynos/power_domain.txt
[2] arch/arm/mach-exynos/pm_domains.c

Changes since v1 (RFC):
[https://lkml.org/lkml/2014/1/11/141]
 - rebased onto current Rafael's linux-pm bleeding-edge branch,
 - reordered the patches a bit (to have the generic ones first),
 - dropped renaming of S3C64xx power domains (as suggested by Mark Brown),
 - added support for deferred probing (as suggested by Stephen Boyd),
 - fixed several minor issues pointed by Stephen Boyd,
 - replaced notifiers with direct hooks in driver core to make power domain
   support independent from specific bus type and allow error handling.

Tomasz Figa (11):
  base: power: Add generic OF-based power domain look-up
  drivercore: Bind/unbind power domain on probe/remove
  ARM: exynos: Move to generic power domain bindings
  ARM: s3c64xx: pm: Use name field of generic_pm_domain
  ARM: s3c64xx: pm: Add always_on field to s3c64xx_pm_domain struct
  ARM: s3c64xx: pm: Add pwr_stat bit for domain G
  ARM: s3c64xx: pm: Add device tree based power domain instantiation
  ARM: s3c64xx: dt: Enable SoC-level power management
  ARM: dts: s3c64xx: Add nodes for power domains
  ARM: dts: s3c64xx: Add node for display controller
  ARM: dts: s3c6410-mini6410: Add support for LCD screen

 .../bindings/arm/exynos/power_domain.txt   |  12 +-
 .../devicetree/bindings/power/power_domain.txt |  51 
 arch/arm/boot/dts/s3c6400.dtsi |   1 +
 arch/arm/boot/dts/s3c6410-mini6410.dts |  33 +++
 arch/arm/boot/dts/s3c6410.dtsi |   1 +
 arch/arm/boot/dts/s3c64xx.dtsi |  13 +
 arch/arm/mach-exynos/pm_domains.c  |  80 +-
 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c|   8 +
 arch/arm/mach-s3c64xx/pm.c | 106 ++--
 drivers/base/dd.c  |   9 +-
 drivers/base/power/domain.c| 298 +
 include/dt-bindings/arm/s3c64xx-power-domains.h|  26 ++
 include/linux/pm_domain.h  |  46 
 kernel/power/Kconfig   |   4 +
 14 files changed, 576 insertions(+), 112 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/power/power_domain.txt
 create mode 100644 include/dt-bindings/arm/s3c64xx-power-domains.h

-- 
1.9.0

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[PATCH v2 02/11] drivercore: Bind/unbind power domain on probe/remove

[Tomasz Figa]

On a number of platforms, devices are part of controllable power
domains, which need to be enabled before such devices can be accessed
and may be powered down when the device is idle to save some power.
This means that on systems that support power domain control using
generic power domains subsystem, it is necessary to add device to its
power domain before binding a driver to it and remove it from its power
domain after its driver is unbound to make sure that an unused device
does not affect power domain state.

Since this is not limited to particular busses and specific
archs/platforms, it is more convenient to do the above directly in
driver core, just as done with pinctrl default configuration. This patch
adds necessary code to really_probe() and __device_release_driver() to
achieve this and maintain consistent stack-like ordering of operations
happening when binding and unbinding a driver.

Signed-off-by: Tomasz Figa 
---
 drivers/base/dd.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 0605176..78e5b36 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -273,6 +274,11 @@ static int really_probe(struct device *dev, struct 
device_driver *drv)
 
dev->driver = drv;
 
+   /* If using genpd, bind power domain now before probing */
+   ret = genpd_bind_domain(dev);
+   if (ret)
+   goto probe_failed;
+
/* If using pinctrl, bind pins now before probing */
ret = pinctrl_bind_pins(dev);
if (ret)
@@ -303,6 +309,7 @@ static int really_probe(struct device *dev, struct 
device_driver *drv)
 probe_failed:
devres_release_all(dev);
driver_sysfs_remove(dev);
+   genpd_unbind_domain(dev);
dev->driver = NULL;
dev_set_drvdata(dev, NULL);
 
@@ -513,7 +520,7 @@ static void __device_release_driver(struct device *dev)
blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
 BUS_NOTIFY_UNBOUND_DRIVER,
 dev);
-
+   genpd_unbind_domain(dev);
}
 }
 
-- 
1.9.0

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[PATCH v2 04/11] ARM: s3c64xx: pm: Use name field of generic_pm_domain

[Tomasz Figa]

This patch removes name field from private s3c64xx_pm_domain struct and
moves domain name to dedicated field of generic_pm_domain struct.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-s3c64xx/pm.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b5a6698..df4b7b2 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -36,7 +36,6 @@
 #include "regs-syscon-power.h"
 
 struct s3c64xx_pm_domain {
-   char *const name;
u32 ena;
u32 pwr_stat;
struct generic_pm_domain pd;
@@ -77,7 +76,7 @@ static int s3c64xx_pd_on(struct generic_pm_domain *domain)
} while (retry--);
 
if (!retry) {
-   pr_err("Failed to start domain %s\n", pd->name);
+   pr_err("Failed to start domain %s\n", pd->pd.name);
return -EBUSY;
}
}
@@ -86,78 +85,78 @@ static int s3c64xx_pd_on(struct generic_pm_domain *domain)
 }
 
 static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
-   .name = "IROM",
.ena = S3C64XX_NORMALCFG_IROM_ON,
.pd = {
+   .name = "IROM",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
-   .name = "ETM",
.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
.pd = {
+   .name = "ETM",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_s = {
-   .name = "S",
.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_S,
.pd = {
+   .name = "S",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_f = {
-   .name = "F",
.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_F,
.pd = {
+   .name = "F",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_p = {
-   .name = "P",
.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_P,
.pd = {
+   .name = "P",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_i = {
-   .name = "I",
.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_I,
.pd = {
+   .name = "I",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_g = {
-   .name = "G",
.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
.pd = {
+   .name = "G",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
 };
 
 static struct s3c64xx_pm_domain s3c64xx_pm_v = {
-   .name = "V",
.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_V,
.pd = {
+   .name = "V",
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
-- 
1.9.0

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[PATCH v2 06/11] ARM: s3c64xx: pm: Add pwr_stat bit for domain G

[Tomasz Figa]

There is a status bit for domain G present in BLK_PWR_STAT register, but
it is currently not specified in the driver.

This patch adds the status bit of domain G to structure describing it.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-s3c64xx/pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index c930245..b422eed 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -147,6 +147,7 @@ static struct s3c64xx_pm_domain s3c64xx_pm_i = {
 
 static struct s3c64xx_pm_domain s3c64xx_pm_g = {
.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
+   .pwr_stat = S3C64XX_BLKPWRSTAT_G,
.pd = {
.name = "G",
.power_off = s3c64xx_pd_off,
-- 
1.9.0

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[PATCH v2 05/11] ARM: s3c64xx: pm: Add always_on field to s3c64xx_pm_domain struct

[Tomasz Figa]

This patch adds always_on field to s3c64xx_pm_domain struct to allow
handling registration of all domains in the same way, without the need
to have separate arrays for normal and always on domains.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-s3c64xx/pm.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index df4b7b2..c930245 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -36,6 +36,7 @@
 #include "regs-syscon-power.h"
 
 struct s3c64xx_pm_domain {
+   bool always_on;
u32 ena;
u32 pwr_stat;
struct generic_pm_domain pd;
@@ -85,6 +86,7 @@ static int s3c64xx_pd_on(struct generic_pm_domain *domain)
 }
 
 static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
+   .always_on = true,
.ena = S3C64XX_NORMALCFG_IROM_ON,
.pd = {
.name = "IROM",
@@ -162,11 +164,8 @@ static struct s3c64xx_pm_domain s3c64xx_pm_v = {
},
 };
 
-static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
-   &s3c64xx_pm_irom,
-};
-
 static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
+   &s3c64xx_pm_irom,
&s3c64xx_pm_etm,
&s3c64xx_pm_g,
&s3c64xx_pm_v,
@@ -312,12 +311,16 @@ int __init s3c64xx_pm_init(void)
 
s3c_pm_init();
 
-   for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
-   pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
- &pm_domain_always_on_gov, false);
 
-   for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
-   pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
+   for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) {
+   struct s3c64xx_pm_domain *pd = s3c64xx_pm_domains[i];
+   struct dev_power_governor *gov = NULL;
+
+   if (pd->always_on)
+   gov = &pm_domain_always_on_gov;
+
+   pm_genpd_init(&pd->pd, gov, false);
+   }
 
 #ifdef CONFIG_S3C_DEV_FB
if (dev_get_platdata(&s3c_device_fb.dev))
-- 
1.9.0

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[PATCH v2 03/11] ARM: exynos: Move to generic power domain bindings

[Tomasz Figa]

This patch moves Exynos power domain code to use the new generic power
domain look-up framework introduced by previous patch, allowing the new
code to be compiled with CONFIG_ARCH_EXYNOS selected as well.

Signed-off-by: Tomasz Figa 
---
 .../bindings/arm/exynos/power_domain.txt   | 12 ++--
 arch/arm/mach-exynos/pm_domains.c  | 80 +-
 kernel/power/Kconfig   |  2 +-
 3 files changed, 7 insertions(+), 87 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..60f26a8 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -8,6 +8,8 @@ Required Properties:
 * samsung,exynos4210-pd - for exynos4210 type power domain.
 - reg: physical base address of the controller and length of memory mapped
 region.
+- #power-domain-cells: number of cells in power domain specifier;
+must be 0.
 
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
@@ -17,12 +19,8 @@ Example:
lcd0: power-domain-lcd0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x10>;
+   #power-domain-cells = <0>;
};
 
-Example of the node using power domain:
-
-   node {
-   /* ... */
-   samsung,power-domain = <&lcd0>;
-   /* ... */
-   };
+See Documentation/devicetree/bindings/power/power_domain.txt for description
+of consumer-side bindings.
diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 8fd2488..48ee6c9 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -75,78 +75,6 @@ static int exynos_pd_power_off(struct generic_pm_domain 
*domain)
return exynos_pd_power(domain, false);
 }
 
-static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
-struct device *dev)
-{
-   int ret;
-
-   dev_dbg(dev, "adding to power domain %s\n", pd->pd.name);
-
-   while (1) {
-   ret = pm_genpd_add_device(&pd->pd, dev);
-   if (ret != -EAGAIN)
-   break;
-   cond_resched();
-   }
-
-   pm_genpd_dev_need_restore(dev, true);
-}
-
-static void exynos_remove_device_from_domain(struct device *dev)
-{
-   struct generic_pm_domain *genpd = dev_to_genpd(dev);
-   int ret;
-
-   dev_dbg(dev, "removing from power domain %s\n", genpd->name);
-
-   while (1) {
-   ret = pm_genpd_remove_device(genpd, dev);
-   if (ret != -EAGAIN)
-   break;
-   cond_resched();
-   }
-}
-
-static void exynos_read_domain_from_dt(struct device *dev)
-{
-   struct platform_device *pd_pdev;
-   struct exynos_pm_domain *pd;
-   struct device_node *node;
-
-   node = of_parse_phandle(dev->of_node, "samsung,power-domain", 0);
-   if (!node)
-   return;
-   pd_pdev = of_find_device_by_node(node);
-   if (!pd_pdev)
-   return;
-   pd = platform_get_drvdata(pd_pdev);
-   exynos_add_device_to_domain(pd, dev);
-}
-
-static int exynos_pm_notifier_call(struct notifier_block *nb,
-   unsigned long event, void *data)
-{
-   struct device *dev = data;
-
-   switch (event) {
-   case BUS_NOTIFY_BIND_DRIVER:
-   if (dev->of_node)
-   exynos_read_domain_from_dt(dev);
-
-   break;
-
-   case BUS_NOTIFY_UNBOUND_DRIVER:
-   exynos_remove_device_from_domain(dev);
-
-   break;
-   }
-   return NOTIFY_DONE;
-}
-
-static struct notifier_block platform_nb = {
-   .notifier_call = exynos_pm_notifier_call,
-};
-
 static __init int exynos4_pm_init_power_domain(void)
 {
struct platform_device *pdev;
@@ -156,8 +84,6 @@ static __init int exynos4_pm_init_power_domain(void)
struct exynos_pm_domain *pd;
int on;
 
-   pdev = of_find_device_by_node(np);
-
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
if (!pd) {
pr_err("%s: failed to allocate memory for domain\n",
@@ -170,17 +96,13 @@ static __init int exynos4_pm_init_power_domain(void)
pd->base = of_iomap(np, 0);
pd->pd.power_off = exynos_pd_power_off;
pd->pd.power_on = exynos_pd_power_on;
-   pd->pd.of_node = np;
-
-   platform_set_drvdata(pdev, pd);
 
on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
 
pm_genpd_init(&pd->pd, NULL, !on);
+   of_genpd_add_provider(np, of_genpd_xlate_simple, &pd->pd);
}
 
-   bus_register_

[PATCH v2 07/11] ARM: s3c64xx: pm: Add device tree based power domain instantiation

[Tomasz Figa]

This patch adds support for registering power domains of S3C64xx SoCs
and binding devices to them using device tree.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-s3c64xx/pm.c  | 71 +
 include/dt-bindings/arm/s3c64xx-power-domains.h | 26 +
 2 files changed, 88 insertions(+), 9 deletions(-)
 create mode 100644 include/dt-bindings/arm/s3c64xx-power-domains.h

diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b422eed..cebbd44 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -17,8 +17,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
+#include 
+
 #include 
 #include 
 
@@ -165,17 +168,63 @@ static struct s3c64xx_pm_domain s3c64xx_pm_v = {
},
 };
 
-static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
-   &s3c64xx_pm_irom,
-   &s3c64xx_pm_etm,
-   &s3c64xx_pm_g,
-   &s3c64xx_pm_v,
-   &s3c64xx_pm_i,
-   &s3c64xx_pm_p,
-   &s3c64xx_pm_s,
-   &s3c64xx_pm_f,
+static struct s3c64xx_pm_domain *s3c64xx_pm_domains[NR_DOMAINS] = {
+   [DOMAIN_V] = &s3c64xx_pm_v,
+   [DOMAIN_G] = &s3c64xx_pm_g,
+   [DOMAIN_I] = &s3c64xx_pm_i,
+   [DOMAIN_P] = &s3c64xx_pm_p,
+   [DOMAIN_F] = &s3c64xx_pm_f,
+   [DOMAIN_S] = &s3c64xx_pm_s,
+   [DOMAIN_ETM] = &s3c64xx_pm_etm,
+   [DOMAIN_IROM] = &s3c64xx_pm_irom,
+};
+
+#ifdef CONFIG_OF
+static struct of_device_id s3c64xx_pd_matches[] = {
+   { .compatible = "samsung,s3c6400-clock", },
+   { .compatible = "samsung,s3c6410-clock", },
+   { },
 };
 
+static struct genpd_onecell_data pd_data;
+
+static int s3c64xx_pm_parse_domains(void)
+{
+   struct device_node *np;
+   int i;
+
+   np = of_find_matching_node(NULL, s3c64xx_pd_matches);
+   if (!np)
+   return -ENODEV;
+
+   pd_data.domains = kcalloc(ARRAY_SIZE(s3c64xx_pm_domains),
+ sizeof(*pd_data.domains), GFP_KERNEL);
+   if (!pd_data.domains)
+   return -ENOMEM;
+
+   for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); ++i) {
+   struct s3c64xx_pm_domain *pd = s3c64xx_pm_domains[i];
+   struct dev_power_governor *gov = NULL;
+   int on;
+
+   on = __raw_readl(S3C64XX_NORMAL_CFG) & pd->ena;
+
+   if (pd->always_on)
+   gov = &pm_domain_always_on_gov;
+
+   pm_genpd_init(&pd->pd, gov, !on);
+   pd_data.domains[i] = &pd->pd;
+
+   pr_debug("%s: registered domain %s\n", __func__, pd->pd.name);
+   }
+
+   pd_data.domain_num = ARRAY_SIZE(s3c64xx_pm_domains);
+   of_genpd_add_provider(np, of_genpd_xlate_onecell, &pd_data);
+
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 void s3c_pm_debug_smdkled(u32 set, u32 clear)
 {
@@ -312,6 +361,10 @@ int __init s3c64xx_pm_init(void)
 
s3c_pm_init();
 
+#ifdef CONFIG_OF
+   if (of_have_populated_dt())
+   return s3c64xx_pm_parse_domains();
+#endif
 
for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++) {
struct s3c64xx_pm_domain *pd = s3c64xx_pm_domains[i];
diff --git a/include/dt-bindings/arm/s3c64xx-power-domains.h 
b/include/dt-bindings/arm/s3c64xx-power-domains.h
new file mode 100644
index 000..ce39bef
--- /dev/null
+++ b/include/dt-bindings/arm/s3c64xx-power-domains.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2014 Tomasz Figa 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S3C64xx power domains.
+*/
+
+#ifndef _DT_BINDINGS_ARM_S3C64XX_POWER_DOMAINS_H
+#define _DT_BINDINGS_ARM_S3C64XX_POWER_DOMAINS_H
+
+#define DOMAIN_V   0
+#define DOMAIN_G   1
+#define DOMAIN_I   2
+#define DOMAIN_P   3
+#define DOMAIN_F   4
+#define DOMAIN_S   5
+#define DOMAIN_ETM 6
+#define DOMAIN_IROM7
+
+/* Total number of clocks. */
+#define NR_DOMAINS (DOMAIN_IROM + 1)
+
+#endif /* _DT_BINDINGS_ARM_S3C64XX_POWER_DOMAINS_H */
-- 
1.9.0

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[PATCH v2 10/11] ARM: dts: s3c64xx: Add node for display controller

[Tomasz Figa]

This patch adds device tree node for the display controller present on
S3C64xx SoCs.

Signed-off-by: Tomasz Figa 
---
 arch/arm/boot/dts/s3c64xx.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index 4e3be4d..6fe1042 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -18,6 +18,7 @@
 
 #include "skeleton.dtsi"
 #include 
+#include 
 
 / {
aliases {
@@ -56,6 +57,18 @@
#interrupt-cells = <1>;
};
 
+   fimd: display@7710 {
+   compatible = "samsung,s3c6400-fimd";
+   reg = <0x7710 0x1000>;
+   interrupt-parent = <&vic0>;
+   interrupts = <29>, <30>, <31>;
+   interrupt-names = "fifo", "vsync", "lcd_sys";
+   clocks = <&clocks HCLK_LCD>, <&clocks SCLK_LCD>;
+   clock-names = "fimd", "sclk_fimd";
+   power-domain = <&clocks DOMAIN_F>;
+   status = "disabled";
+   };
+
sdhci0: sdhci@7c20 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c20 0x100>;
-- 
1.9.0

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[PATCH v2 08/11] ARM: s3c64xx: dt: Enable SoC-level power management

[Tomasz Figa]

This patch adds call to s3c64xx_pm_init() from init_machine() callback
of mach-s3c64xx-dt to enable SoC-level power management features, such
as power domain management and sleep support.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c 
b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
index 2fddf38..45a4ddc 100644
--- a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
+++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
@@ -15,6 +15,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include 
@@ -49,9 +50,15 @@ static void __init s3c64xx_dt_map_io(void)
 static void __init s3c64xx_dt_init_machine(void)
 {
samsung_wdt_reset_of_init();
+   s3c64xx_pm_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
+static void __init s3c64xx_dt_init_late(void)
+{
+   s3c64xx_pm_late_initcall();
+}
+
 static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
 {
if (mode != REBOOT_SOFT)
@@ -72,5 +79,6 @@ DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened 
Device Tree)")
.dt_compat  = s3c64xx_dt_compat,
.map_io = s3c64xx_dt_map_io,
.init_machine   = s3c64xx_dt_init_machine,
+   .init_late  = s3c64xx_dt_init_late,
.restart= s3c64xx_dt_restart,
 MACHINE_END
-- 
1.9.0

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[PATCH v2 09/11] ARM: dts: s3c64xx: Add nodes for power domains

[Tomasz Figa]

This patch adds device tree nodes for power domains available on S3C64xx
SoCs.

Signed-off-by: Tomasz Figa 
---
 arch/arm/boot/dts/s3c6400.dtsi | 1 +
 arch/arm/boot/dts/s3c6410.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi
index a7d1c8e..c1abdaf 100644
--- a/arch/arm/boot/dts/s3c6400.dtsi
+++ b/arch/arm/boot/dts/s3c6400.dtsi
@@ -37,5 +37,6 @@
compatible = "samsung,s3c6400-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
+   #power-domain-cells = <1>;
};
 };
diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi
index eb4226b..7e48c86 100644
--- a/arch/arm/boot/dts/s3c6410.dtsi
+++ b/arch/arm/boot/dts/s3c6410.dtsi
@@ -41,6 +41,7 @@
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
+   #power-domain-cells = <1>;
};
 
i2c1: i2c@7f00f000 {
-- 
1.9.0

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[PATCH v2 11/11] ARM: dts: s3c6410-mini6410: Add support for LCD screen

[Tomasz Figa]

This patch adds necessary device tree nodes and properties to enable LCD
screen on mini6410 board.

Signed-off-by: Tomasz Figa 
---
 arch/arm/boot/dts/s3c6410-mini6410.dts | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts 
b/arch/arm/boot/dts/s3c6410-mini6410.dts
index 57e00f9..97f6353 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -167,6 +167,33 @@
};
 };
 
+&fimd {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&lcd_data24>, <&lcd_power>;
+
+   display-timings {
+   native-mode = <&timing0>;
+
+   timing0: timing@0 {
+   /* 480x272@60Hz */
+   clock-frequency = <1000>;
+   hactive = <480>;
+   vactive = <272>;
+   hfront-porch = <4>;
+   hback-porch = <45>;
+   hsync-len = <40>;
+   vback-porch = <3>;
+   vfront-porch = <2>;
+   vsync-len = <6>;
+   vsync-active = <1>;
+   hsync-active = <1>;
+   de-active = <1>;
+   pixelclk-active = <0>;
+   };
+   };
+};
+
 &sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
@@ -213,6 +240,12 @@
"gpn-4", "gpn-5", "gpl-11", "gpl-12";
samsung,pin-pud = ;
};
+
+   lcd_power: lcd-power {
+   samsung,pins = "gpe-0";
+   samsung,pin-function = <0>;
+   samsung,pin-pud = ;
+   };
 };
 
 &i2c0 {
-- 
1.9.0

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Re: [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management

[Tomasz Figa]

On 03.03.2014 16:24, Chris Ball wrote:

Hi,

On Mon, Mar 03 2014, Tomasz Figa wrote:

It's been almost two months since I posted this series, it's been
already ACKed and it would be nice to have it applied for upcoming
release.


Sorry about this, Tomasz -- now pushed to mmc-next for 3.15, thanks.


Thanks. \o/

Best regards,
Tomasz
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Re: [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management

[Chris Ball]

Hi,

On Mon, Mar 03 2014, Tomasz Figa wrote:
> It's been almost two months since I posted this series, it's been
> already ACKed and it would be nice to have it applied for upcoming
> release.

Sorry about this, Tomasz -- now pushed to mmc-next for 3.15, thanks.

- Chris.
-- 
Chris Ball  
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Re: [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management

[Tomasz Figa]

On 20.02.2014 20:26, Tomasz Figa wrote:

Hi Chris,

On 07.02.2014 10:58, Tomasz Figa wrote:

Hi Chris,

On 11.01.2014 22:39, Tomasz Figa wrote:

On platforms prior to Exynos the SDHCI block used internal clock
divider controlled by SELFREQ field of CLKCON register to divide base
clock selected from several external clocks fed to the block by
SELBASECLK bitfield of CONTROL2 register. Depending on wanted clock
frequency, different external clock may be the best choice and so
the driver needs to switch the SELBASECLK mux on the fly.

However the selection logic has been broken for quite some time leaving
the controller using always clock 0, which is not always the right
source and leading to suboptimal performance of the SDHCI block on
affected platforms.

This series intends to fix the problems mentioned above and also
clean-up
clock management code slightly.

Tested on S3C6410-based Mini6410 board, with following performance
figures:

* Before this series (133 MHz HCLK always selected, leading to at most
   33 MHz card clock):

root@tiny6410:~# hdparm -t /dev/mmcblk0

/dev/mmcblk0:
  Timing buffered disk reads:  42 MB in  3.10 seconds =  13.54 MB/sec
root@tiny6410:~# hdparm -t /dev/mmcblk0

/dev/mmcblk0:
  Timing buffered disk reads:  44 MB in  3.11 seconds =  14.14 MB/sec
root@tiny6410:~#

* After this series (48 MHz EPLL clock selected, leading to 48 MHz card
   clock):

root@tiny6410:~# hdparm -t /dev/mmcblk0

/dev/mmcblk0:
  Timing buffered disk reads:  56 MB in  3.04 seconds =  18.41 MB/sec
root@tiny6410:~# hdparm -t /dev/mmcblk0

/dev/mmcblk0:
  Timing buffered disk reads:  60 MB in  3.06 seconds =  19.63 MB/sec
root@tiny6410:~#

Tomasz Figa (6):
   mmc: sdhci-s3c: Use shifts to divide by powers of two
   mmc: sdhci-s3c: Cache bus clock rates
   mmc: sdhci-s3c: Use correct condition to check for clock presence
   mmc: sdhci-s3c: Simplify min/max clock calculation
   mmc: sdhci-s3c: Fix handling of bus clock switching
   mmc: sdhci-s3c: Do not allow frequencies higher than requested

  drivers/mmc/host/sdhci-s3c.c | 170
---
  1 file changed, 77 insertions(+), 93 deletions(-)



What do you think about this series?


Could you take this series for 3.15?


Ping.

It's been almost two months since I posted this series, it's been 
already ACKed and it would be nice to have it applied for upcoming release.


Best regards,
Tomasz
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RE: [PATCH v6 5/8] phy: Add new Exynos USB PHY driver

[Kamil Debski]

Hi Kishon,

> From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
> Sent: Monday, March 03, 2014 3:28 PM
> 
> Hi,
> 
> On Wednesday 29 January 2014 10:59 PM, Kamil Debski wrote:
> > Add a new driver for the Exynos USB PHY. The new driver uses the
> > generic PHY framework. The driver includes support for the Exynos
> 4x10
> > and 4x12 SoC families.
> 
> Can the PHY part of this series be merged independently of the
> controller part?

I see no problems with merging the PHY part independently. However,
I would like to post an updated version of these patches. I am working
on them now and should send them tomorrow.

Best wishes,
-- 
Kamil Debski
Samsung R&D Institute Poland

> >
> > Signed-off-by: Kamil Debski 
> > ---
> >   .../devicetree/bindings/phy/samsung-phy.txt|   55 
> >   Documentation/phy/samsung-usb2.txt |  135 
> >   drivers/phy/Kconfig|   29 ++
> >   drivers/phy/Makefile   |3 +
> >   drivers/phy/phy-exynos4210-usb2.c  |  257
> 
> >   drivers/phy/phy-exynos4x12-usb2.c  |  323
> 
> >   drivers/phy/phy-samsung-usb2.c |  227
> ++
> >   drivers/phy/phy-samsung-usb2.h |   67 
> >   8 files changed, 1096 insertions(+)
> >   create mode 100644 Documentation/phy/samsung-usb2.txt
> >   create mode 100644 drivers/phy/phy-exynos4210-usb2.c
> >   create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
> >   create mode 100644 drivers/phy/phy-samsung-usb2.c
> >   create mode 100644 drivers/phy/phy-samsung-usb2.h
> >
> > diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> > b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> > index c0fccaa..6668c41 100644
> > --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> > +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> > @@ -20,3 +20,58 @@ Required properties:
> >   - compatible : should be "samsung,exynos5250-dp-video-phy";
> >   - reg : offset and length of the Display Port PHY register set;
> >   - #phy-cells : from the generic PHY bindings, must be 0;
> > +
> > +Samsung S5P/EXYNOS SoC series USB PHY
> > +-
> > +
> > +Required properties:
> > +- compatible : should be one of the listed compatibles:
> > +   - "samsung,exynos4210-usb2-phy"
> > +   - "samsung,exynos4x12-usb2-phy"
> > +- reg : a list of registers used by phy driver
> > +   - first and obligatory is the location of phy modules registers
> > +- samsung,sysreg-phandle - handle to syscon used to control the
> > +system registers
> > +- samsung,pmureg-phandle - handle to syscon used to control PMU
> > +registers
> > +- #phy-cells : from the generic phy bindings, must be 1;
> > +- clocks and clock-names:
> > +   - the "phy" clocks is required by the phy module
> > +   - next for each of the phys a clock has to be assigned, this
> clock
> > + will be used to determine clocking frequency for the phys
> > + (the labels are specified in the paragraph below)
> > +
> > +The first phandle argument in the PHY specifier identifies the PHY,
> > +its meaning is compatible dependent. For the currently supported
> SoCs
> > +(Exynos 4210 and Exynos 4212) it is as follows:
> > +  0 - USB device ("device"),
> > +  1 - USB host ("host"),
> > +  2 - HSIC0 ("hsic0"),
> > +  3 - HSIC1 ("hsic1"),
> > +
> > +Exynos 4210 and Exynos 4212 use mode switching and require that mode
> > +switch register is supplied.
> > +
> > +Example:
> > +
> > +For Exynos 4412 (compatible with Exynos 4212):
> > +
> > +usbphy: phy@125b {
> > +   compatible = "samsung,exynos4212-usb2-phy";
> > +   reg = <0x125b 0x100 0x10020704 0x0c 0x1001021c 0x4>;
> > +   clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
> > +   <&clock 2>;
> > +   clock-names = "phy", "device", "host", "hsic0", "hsic1";
> > +   status = "okay";
> > +   #phy-cells = <1>;
> > +   samsung,sysreg-phandle = <&sys_reg>;
> > +   samsung,pmureg-phandle = <&pmu_reg>; };
> > +
> > +Then the PHY can be used in other nodes such as:
> > +
> > +phy-consumer@1234 {
> > +   phys = <&usbphy 2>;
> > +   phy-names = "phy";
> > +};
> > +
> > +Refer to DT bindings documentation of particular PHY consumer
> devices
> > +for more information about required PHYs and the way of
> specification.
> > diff --git a/Documentation/phy/samsung-usb2.txt
> > b/Documentation/phy/samsung-usb2.txt
> > new file mode 100644
> > index 000..9f5826e
> > --- /dev/null
> > +++ b/Documentation/phy/samsung-usb2.txt
> > @@ -0,0 +1,135 @@
> > +.---
> -
> > +--+
> > +|  Samsung USB 2.0 PHY adaptation layer
> |
> > ++---
> --+'
> > +
> > +| 1. Description
> > ++
> > +
> >

Re: [PATCH v6 8/8] usb: ehci-exynos: Change to use phy provided by the generic phy framework

[Tomasz Figa]

On 05.02.2014 18:30, Olof Johansson wrote:

On Wed, Feb 5, 2014 at 7:57 AM, Kamil Debski  wrote:

Hi Olof,

Thank you for your review.


From: Olof Johansson [mailto:o...@lixom.net]
Sent: Wednesday, January 29, 2014 9:55 PM

Hi,

On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski 
wrote:

Change the phy provider used from the old one using the USB phy
framework to a new one using the Generic phy framework.

Signed-off-by: Kamil Debski 
---
  .../devicetree/bindings/usb/exynos-usb.txt |   13 +++
  drivers/usb/host/ehci-exynos.c |   97

+---

  2 files changed, 76 insertions(+), 34 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index d967ba1..25e199a 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -12,6 +12,10 @@ Required properties:
   - interrupts: interrupt number to the cpu.
   - clocks: from common clock binding: handle to usb clock.
   - clock-names: from common clock binding: Shall be "usbhost".
+  - port: if in the SoC there are EHCI phys, they should be listed

here.

+One phy per port. Each port should have its reg entry with a
+consecutive number. Also it should contain phys and phy-names

entries

+specifying the phy used by the port.

  Optional properties:
   - samsung,vbus-gpio:  if present, specifies the GPIO that @@ -27,6
+31,15 @@ Example:

 clocks = <&clock 285>;
 clock-names = "usbhost";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   port@0 {
+   reg = <0>;
+   phys = <&usb2phy 1>;
+   phy-names = "host";
+   status = "disabled";
+   };
 };

  OHCI


[...]


@@ -102,14 +132,26 @@ static int exynos_ehci_probe(struct

platform_device *pdev)

 "samsung,exynos5440-ehci"))
 goto skip_phy;

-   phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
-   if (IS_ERR(phy)) {
-   usb_put_hcd(hcd);
-   dev_warn(&pdev->dev, "no platform data or transceiver

defined\n");

-   return -EPROBE_DEFER;
-   } else {
-   exynos_ehci->phy = phy;
-   exynos_ehci->otg = phy->otg;
+   for_each_available_child_of_node(pdev->dev.of_node, child) {
+   err = of_property_read_u32(child, "reg",

&phy_number);

+   if (err) {
+   dev_err(&pdev->dev, "Failed to parse device

tree\n");

+   of_node_put(child);
+   return err;
+   }
+   if (phy_number >= PHY_NUMBER) {
+   dev_err(&pdev->dev, "Failed to parse device

tree - number out of range\n");

+   of_node_put(child);
+   return -EINVAL;
+   }
+   phy = devm_of_phy_get(&pdev->dev, child, 0);
+   of_node_put(child);
+   if (IS_ERR(phy)) {
+   dev_err(&pdev->dev, "Failed to get phy number

%d",

+

phy_number);

+   return PTR_ERR(phy);
+   }
+   exynos_ehci->phy[phy_number] = phy;


this looks like it is now breaking older device trees, where ports
might not be described. Since device tree interfaces need to be
backwards compatible, you still need to handle the old case of not
having ports described.

There are two ways of doing this:

1. Fall back to the old behavior if there are no ports 2. Use a new
compatible value for the new model with port subnodes, and if the old
compatible value is used, then fall back to the old behavior.

I'm guessing (1) might be easiest since you can check for the presence
of #address-cells to tell if this is just an old style node, or if it's
a new-style node without any ports below it.


The ultimate goal is to remove the old phy driver. Unfortunately
this has to be synced with the new USB3 phy driver by Vivek Gautam. I think
he
is also close to completion. What about this case? In the end the old driver
will be removed and no longer be supported. Having backward compatibility in
mind, it is possible to have the old and the new phy driver together in one
kernel release. But do we want to have two drivers doing the same thing at
the same time?


It is mostly irrelevant if there is a new driver or not -- the old
device tree has to keep working. In this case it would mean that the
new driver needs to work with older device trees as well, or people
will see functionality regressing.

The device tree is a description of the hardware, not an extension of
the driver.


The problem with this case is that when the original driver was added 
there was no way to bind PHY providers and consumers together.


Basically there was no generic PHY subsystem. Instead the hacky USB PHY 
subs

Re: [PATCH v6 5/8] phy: Add new Exynos USB PHY driver

[Kishon Vijay Abraham I]

Hi,

On Wednesday 29 January 2014 10:59 PM, Kamil Debski wrote:

Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.


Can the PHY part of this series be merged independently of the 
controller part?


Thanks
Kishon


Signed-off-by: Kamil Debski 
---
  .../devicetree/bindings/phy/samsung-phy.txt|   55 
  Documentation/phy/samsung-usb2.txt |  135 
  drivers/phy/Kconfig|   29 ++
  drivers/phy/Makefile   |3 +
  drivers/phy/phy-exynos4210-usb2.c  |  257 
  drivers/phy/phy-exynos4x12-usb2.c  |  323 
  drivers/phy/phy-samsung-usb2.c |  227 ++
  drivers/phy/phy-samsung-usb2.h |   67 
  8 files changed, 1096 insertions(+)
  create mode 100644 Documentation/phy/samsung-usb2.txt
  create mode 100644 drivers/phy/phy-exynos4210-usb2.c
  create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
  create mode 100644 drivers/phy/phy-samsung-usb2.c
  create mode 100644 drivers/phy/phy-samsung-usb2.h

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt 
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..6668c41 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,58 @@ Required properties:
  - compatible : should be "samsung,exynos5250-dp-video-phy";
  - reg : offset and length of the Display Port PHY register set;
  - #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+   - "samsung,exynos4210-usb2-phy"
+   - "samsung,exynos4x12-usb2-phy"
+- reg : a list of registers used by phy driver
+   - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system 
registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+   - the "phy" clocks is required by the phy module
+   - next for each of the phys a clock has to be assigned, this clock
+ will be used to determine clocking frequency for the phys
+ (the labels are specified in the paragraph below)
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+  0 - USB device ("device"),
+  1 - USB host ("host"),
+  2 - HSIC0 ("hsic0"),
+  3 - HSIC1 ("hsic1"),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125b {
+   compatible = "samsung,exynos4212-usb2-phy";
+   reg = <0x125b 0x100 0x10020704 0x0c 0x1001021c 0x4>;
+   clocks = <&clock 305>, <&clock 2>, <&clock 2>, <&clock 2>,
+   <&clock 2>;
+   clock-names = "phy", "device", "host", "hsic0", "hsic1";
+   status = "okay";
+   #phy-cells = <1>;
+   samsung,sysreg-phandle = <&sys_reg>;
+   samsung,pmureg-phandle = <&pmu_reg>;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@1234 {
+   phys = <&usbphy 2>;
+   phy-names = "phy";
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
diff --git a/Documentation/phy/samsung-usb2.txt 
b/Documentation/phy/samsung-usb2.txt
new file mode 100644
index 000..9f5826e
--- /dev/null
+++ b/Documentation/phy/samsung-usb2.txt
@@ -0,0 +1,135 @@
+.--+
+|  Samsung USB 2.0 PHY adaptation layer   |
++-+'
+
+| 1. Description
++
+
+The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
+among many SoCs. In spite of the similarities it proved difficult to
+create a one driver that would fit all these PHY controllers. Often
+the differences were minor and were found in particular bits of the
+registers of the PHY. In some rare cases the order of register writes or
+the PHY powering up process had to be altered. This adaptation layer is
+a compromise between having separate drivers and having a single driver
+with added support for many special cases.
+
+| 2. Files description
++--
+
+- phy-samsung-usb2.c
+   This is the main file of the adaptation layer. This file

Re: [PATCH 3/3] regulator: s2mps11: Copy supported regulators from initconst

[Krzysztof Kozlowski]

Hi,

On Mon, 2014-03-03 at 10:09 +0800, Mark Brown wrote:
> On Fri, Feb 28, 2014 at 11:01:50AM +0100, Krzysztof Kozlowski wrote:
> > Add __initconst to 'regulator_desc' array with supported regulators.
> > During probe choose how many and which regulators will be supported
> > according to device ID. Then copy the 'regulator_desc' array to
> > allocated memory so the regulator core can use it.
> 
> Applied, thanks.

Thanks! Unfortunately I wonder now whether it was a good idea to mark
the regulator_desc array as __initconst. I've seen the warning from
kbuild test robot:

>> WARNING: vmlinux.o(.text+0xf0faab): Section mismatch in reference
from the function s2mps11_pmic_probe() to the
variable .init.rodata:s2mps11_regulators
   The function s2mps11_pmic_probe() references
   the variable __initconst s2mps11_regulators.
   This is often because s2mps11_pmic_probe lacks a __initconst
   annotation or the annotation of s2mps11_regulators is wrong.


I have two ideas for fixing this:
1. The s2mps11_pmic_probe() could be marked with __init and 
platform_driver_probe() should be used. Unfortunately this does not work
because the driver is registered and probed a little later after
s2mps11_pmic_init() when I2C bus driver is probed. During that time the
drv->probe() is actually NULL.

2. The s2mps11_pmic_probe() won't be marked as __init and could copy the
regulator_desc (__initconst) array to local static variable. This way if
it would be called twice the mentioned array __initconst won't be
dereferenced. Unfortunately this won't remove the warning.

Any ideas for solving this?

Best regards,
Krzysztof





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[GIT PULL 6/6] Samsung clk-s3c24xx updates for v3.15

[Kukjin Kim]

The following changes since commit e11d919e4aa2009077e3e4f829ff991d37adca61:

  ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code (2014-02-14 
08:16:01 +0900)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/s3c24xx-clk

for you to fetch changes up to 315c62c750e82cb20845cbef585141cbf98aa1a0:

  ARM: S3C24XX: convert s3c2412 to common clock framework (2014-03-03 09:18:49 
+0900)


Samsung S3C24XX to use the common clock framework
- S3C2412, S3C2413, S3C2416 and S3C2443 to use CCF

Heiko Stuebner (12):
  clk: samsung: add pll_6552 variant for s3c2416
  clk: samsung: add plls used by the s3c2443
  dt-bindings: add binding for clock-controller of s3c2443 and following
  clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
  ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
  ARM: dts: add clock data for s3c2416
  ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
  ARM: S3C24XX: only store clock registers when old clock code is active
  clk: samsung: add plls used by the early s3c24xx cpus
  dt-bindings: add documentation for s3c2412 clock controller
  clk: samsung: add clock controller driver for s3c2412
  ARM: S3C24XX: convert s3c2412 to common clock framework

Note:
- This branch is based on v3.15-next/s2r-pm-samsung
- clock related stuff got ack from Mike and Tomasz


Heiko Stuebner (12):
  clk: samsung: add pll_6552 variant for s3c2416
  clk: samsung: add plls used by the s3c2443
  dt-bindings: add binding for clock-controller of s3c2443 and following
  clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450
  ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs
  ARM: dts: add clock data for s3c2416
  ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework
  ARM: S3C24XX: only store clock registers when old clock code is active
  clk: samsung: add plls used by the early s3c24xx cpus
  dt-bindings: add documentation for s3c2412 clock controller
  clk: samsung: add clock controller driver for s3c2412
  ARM: S3C24XX: convert s3c2412 to common clock framework

 .../bindings/clock/samsung,s3c2412-clock.txt   |   50 ++
 .../bindings/clock/samsung,s3c2443-clock.txt   |   56 ++
 arch/arm/boot/dts/s3c2416-smdk2416.dts |   13 +
 arch/arm/boot/dts/s3c2416.dtsi |   42 ++
 arch/arm/mach-s3c24xx/Kconfig  |   24 +-
 arch/arm/mach-s3c24xx/Makefile |7 +-
 arch/arm/mach-s3c24xx/clock-s3c2412.c  |  761 
 arch/arm/mach-s3c24xx/clock-s3c2416.c  |  171 -
 arch/arm/mach-s3c24xx/clock-s3c2443.c  |  212 --
 arch/arm/mach-s3c24xx/common-s3c2443.c |  675 -
 arch/arm/mach-s3c24xx/common.c |   27 +-
 arch/arm/mach-s3c24xx/common.h |   10 +
 arch/arm/mach-s3c24xx/mach-jive.c  |9 +-
 arch/arm/mach-s3c24xx/mach-s3c2416-dt.c|   39 +-
 arch/arm/mach-s3c24xx/mach-smdk2413.c  |9 +-
 arch/arm/mach-s3c24xx/mach-smdk2416.c  |9 +-
 arch/arm/mach-s3c24xx/mach-smdk2443.c  |9 +-
 arch/arm/mach-s3c24xx/mach-vstms.c |9 +-
 arch/arm/mach-s3c24xx/pm.c |   13 +-
 arch/arm/mach-s3c24xx/s3c2412.c|   43 --
 drivers/clk/samsung/Makefile   |2 +
 drivers/clk/samsung/clk-pll.c  |  266 ++-
 drivers/clk/samsung/clk-pll.h  |6 +
 drivers/clk/samsung/clk-s3c2412.c  |  269 +++
 drivers/clk/samsung/clk-s3c2443.c  |  462 
 include/dt-bindings/clock/s3c2412.h|   73 ++
 include/dt-bindings/clock/s3c2443.h|   92 +++
 27 files changed, 1428 insertions(+), 1930 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt
 create mode 100644 
Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2412.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c
 delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c
 delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c
 create mode 100644 drivers/clk/samsung/clk-s3c2412.c
 create mode 100644 drivers/clk/samsung/clk-s3c2443.c
 create mode 100644 include/dt-bindings/clock/s3c2412.h
 create mode 100644 include/dt-bindings/clock/s3c2443.h

[GIT PULL 5/6] Samsung PM updates for v3.15

[Kukjin Kim]

The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:

  Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-pm-1

for you to fetch changes up to e11d919e4aa2009077e3e4f829ff991d37adca61:

  ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code (2014-02-14 
08:16:01 +0900)


Samsung S2R PM updates for v3.15

From Tomasz Figa:
This series reworks suspend/resume handling of Samsung clock drivers
to cover more SoC specific aspects that are beyond simple register
save and restore. The goal is to have all the suspend/resume code
that touches the clock controller in single place, which is the clock
driver.


Tomasz Figa (9):
  clk: exynos4: Remove remnants of non-DT support
  clk: samsung: Provide common helpers for register save/restore
  clk: samsung: exynos4: Move suspend/resume handling to SoC driver
  clk: samsung: exynos5250: Move suspend/resume handling to SoC driver
  clk: samsung: exynos5420: Move suspend/resume handling to SoC driver
  clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver
  clk: samsung: Drop old suspend/resume code
  clk: samsung: exynos4: Add remaining suspend/resume handling
  ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code

 arch/arm/mach-exynos/pm.c|  148 +
 drivers/clk/samsung/clk-exynos4.c|  172 ++
 drivers/clk/samsung/clk-exynos5250.c |   49 +-
 drivers/clk/samsung/clk-exynos5420.c |   49 +-
 drivers/clk/samsung/clk-exynos5440.c |2 +-
 drivers/clk/samsung/clk-s3c64xx.c|   79 +---
 drivers/clk/samsung/clk.c|   71 +-
 drivers/clk/samsung/clk.h|   14 ++-
 8 files changed, 348 insertions(+), 236 deletions(-)

[GIT PULL 4/6] Samsung clk-exynos updates for v3.15

[Kukjin Kim]

The following changes since commit d726ca2d3316743841063a98fb113ff22a236e63:

  ARM: dts: Add vmmc-supply to MMC on arndale-octa board (2014-02-24 08:56:46 
+0900)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/exynos-clk

for you to fetch changes up to 86feafebbec2b510daf36ffbdbe10228ed890b00:

  ARM: dts: use macros in clock bindings for exynos5440 (2014-02-26 09:53:31 
+0900)


Samsung exynos clock related DT updates for v3.15

- use macros instead of hard coded numbers for clock bindings

NOTE: this is based on v3.15-next/dt-samsung


Andrzej Hajda (4):
  ARM: dts: use macros in clock bindings for exynos4
  ARM: dts: use macros in clock bindings for exynos5250
  ARM: dts: use macros in clock bindings for exynos5420
  ARM: dts: use macros in clock bindings for exynos5440

 .../devicetree/bindings/clock/exynos4-clock.txt|  259 +---
 .../devicetree/bindings/clock/exynos5250-clock.txt |  163 +---
 .../devicetree/bindings/clock/exynos5420-clock.txt |  184 +-
 .../devicetree/bindings/clock/exynos5440-clock.txt |   45 +---
 arch/arm/boot/dts/exynos4.dtsi |   73 +++---
 arch/arm/boot/dts/exynos4210.dtsi  |9 +-
 arch/arm/boot/dts/exynos4x12.dtsi  |   34 ++-
 arch/arm/boot/dts/exynos5250.dtsi  |  105 
 arch/arm/boot/dts/exynos5420.dtsi  |   95 +++
 arch/arm/boot/dts/exynos5440.dtsi  |   33 +--
 10 files changed, 207 insertions(+), 793 deletions(-)

[GIT PULL 3/6] Samsung DT updates for v3.15

[Kukjin Kim]

The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:

  Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-dt

for you to fetch changes up to d726ca2d3316743841063a98fb113ff22a236e63:

  ARM: dts: Add vmmc-supply to MMC on arndale-octa board (2014-02-24 08:56:46 
+0900)


Samsung DT updates for v3.15

For exynos4412
- update vdd_arm voltage range for odroidx board

For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250

For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
  for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
  support for arndale-octa board


Leela Krishna Amudala (2):
  ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420
  ARM: dts: update watchdog device nodes for exynos5250 and exynos5420

Sachin Kamat (9):
  ARM: dts: Add regulator entries to smdk5420
  ARM: dts: Re-organize RTC status for exynos5420
  ARM: dts: Re-organize RTC status for exynos5250
  ARM: dts: Add ADMA node to exynos5420
  ARM: dts: Add I2S nodes to exynos5420
  ARM: dts: Add fixed voltage regulators to smdk5420
  ARM: dts: Add PMIC support to arndale-octa board
  ARM: dts: Add wake up key to arndale-octa board
  ARM: dts: Add vmmc-supply to MMC on arndale-octa board

Thomas Abraham (2):
  ARM: dts: update vdd_arm voltage range for exynos4412 based boards
  ARM: dts: add max77686 pmic node for smdk5250

 .../devicetree/bindings/arm/samsung/pmu.txt|   15 +
 arch/arm/boot/dts/exynos4412-odroidx.dts   |2 +-
 arch/arm/boot/dts/exynos4412-origen.dts|4 +-
 arch/arm/boot/dts/exynos5.dtsi |7 -
 arch/arm/boot/dts/exynos5250-arndale.dts   |4 +
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |  146 ++
 arch/arm/boot/dts/exynos5250-snow.dts  |4 +
 arch/arm/boot/dts/exynos5250.dtsi  |   13 +-
 arch/arm/boot/dts/exynos5420-arndale-octa.dts  |  298 
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |  253 +
 arch/arm/boot/dts/exynos5420.dtsi  |   70 -
 11 files changed, 803 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
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[GIT PULL 1/6] Samsung cleanup for v3.15

[Kukjin Kim]

The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:

  Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-cleanup

for you to fetch changes up to d9671ca923445aa870ecc34df3db01dd602d87fc:

  ARM: EXYNOS: Remove uncompress.h (2014-02-24 09:39:18 +0900)


Samsung cleanup for v3.15
- Use generic uncompress.h for exynos and
  remove exynos accordingly
  (other uncompress.h files will be removed)
- move into s3c24xx 
- remove unused header files
- cleanup exynos related non-DT stuffs
- use inclusion instead of
  
- remove unneeded Kconfig entries:
  S3C24XX_GPIO_EXTRA64 and S3C24XX_GPIO_EXTRA128
- remove unneeded function s3c24xx_init_cpu()
- remove obsolete s3c24xx 


Heiko Stuebner (2):
  ARM: SAMSUNG: remove obsolete tick.h
  ARM: SAMSUNG: remove unneeded s3c24xx_init_cpu()

Paul Bolle (1):
  ARM: S3C24XX: get rid of unneeded selects

Sachin Kamat (4):
  ARM: SAMSUNG: Remove platform dependency from samsung.S
  ARM: S3C24XX: Move rtc-core.h from plat to mach
  ARM: debug: Use generic uncompress.h for exynos
  ARM: EXYNOS: Remove uncompress.h

Tushar Behera (4):
  ARM: SAMSUNG: Replace inclusion of plat/regs-serial.h header file
  ARM: SAMSUNG: Delete unused plat/regs-serial.h header file
  ARM: SAMSUNG: Remove Exynos specific code from devs, s5p-pm-irq and 
pm-gpio.c
  ARM: EXYNOS: Remove unused header file from pm_domains.c

arch/arm/Kconfig.debug |5 +-
arch/arm/include/debug/samsung.S   |2 +-
arch/arm/mach-exynos/common.c  |2 +-
arch/arm/mach-exynos/include/mach/uncompress.h |   48 
arch/arm/mach-exynos/pm_domains.c  |2 -
arch/arm/mach-s3c24xx/Kconfig  |2 -
arch/arm/mach-s3c24xx/clock-s3c2410.c  |3 +-
arch/arm/mach-s3c24xx/clock-s3c2412.c  |3 +-
arch/arm/mach-s3c24xx/clock-s3c2440.c  |2 +-
arch/arm/mach-s3c24xx/common.c |3 +-
arch/arm/mach-s3c24xx/dma-s3c2410.c|2 +-
arch/arm/mach-s3c24xx/dma-s3c2412.c|2 +-
arch/arm/mach-s3c24xx/dma-s3c2440.c|2 +-
arch/arm/mach-s3c24xx/dma-s3c2443.c|2 +-
arch/arm/mach-s3c24xx/include/mach/debug-macro.S   |2 +-
.../plat => mach-s3c24xx/include/mach}/rtc-core.h  |   13 +++---
arch/arm/mach-s3c24xx/include/mach/tick.h  |   15 --
arch/arm/mach-s3c24xx/mach-amlm5900.c  |2 +-
arch/arm/mach-s3c24xx/mach-anubis.c|2 +-
arch/arm/mach-s3c24xx/mach-at2440evb.c |2 +-
arch/arm/mach-s3c24xx/mach-bast.c  |2 +-
arch/arm/mach-s3c24xx/mach-gta02.c |2 +-
arch/arm/mach-s3c24xx/mach-h1940.c |2 +-
arch/arm/mach-s3c24xx/mach-jive.c  |2 +-
arch/arm/mach-s3c24xx/mach-mini2440.c  |2 +-
arch/arm/mach-s3c24xx/mach-n30.c   |2 +-
arch/arm/mach-s3c24xx/mach-nexcoder.c  |2 +-
arch/arm/mach-s3c24xx/mach-osiris.c|2 +-
arch/arm/mach-s3c24xx/mach-otom.c  |2 +-
arch/arm/mach-s3c24xx/mach-qt2410.c|2 +-
arch/arm/mach-s3c24xx/mach-rx1950.c|2 +-
arch/arm/mach-s3c24xx/mach-rx3715.c|2 +-
arch/arm/mach-s3c24xx/mach-s3c2416-dt.c|2 +-
arch/arm/mach-s3c24xx/mach-smdk2410.c  |2 +-
arch/arm/mach-s3c24xx/mach-smdk2413.c  |2 +-
arch/arm/mach-s3c24xx/mach-smdk2416.c  |2 +-
arch/arm/mach-s3c24xx/mach-smdk2440.c  |2 +-
arch/arm/mach-s3c24xx/mach-smdk2443.c  |2 +-
arch/arm/mach-s3c24xx/mach-tct_hammer.c|2 +-
arch/arm/mach-s3c24xx/mach-vr1000.c|2 +-
arch/arm/mach-s3c24xx/mach-vstms.c |2 +-
arch/arm/mach-s3c24xx/pm.c |2 +-
arch/arm/mach-s3c24xx/s3c2410.c|2 +-
arch/arm/mach-s3c24xx/s3c2412.c|2 +-
arch/arm/mach-s3c24xx/s3c2416.c|2 +-
arch/arm/mach-s3c24xx/s3c2443.c|2 +-
arch/arm/mach-s3c24xx/s3c244x.c|2 +-
arch/arm/mach-s3c24xx/sleep-s3c2410.S  |2 +-
arch/arm/mach-s3c24xx/sleep.S  |2 +-
arch/arm/mach-s3c64xx/common.c |2 +-
arch/arm/mach-s3c64xx/include/mach/debug-macro.S   |2 +-
arch/arm/mach-s3c64xx/include/mach/tick.h  |   31 -
arch/arm/mach-s3c64xx/irq-pm.c |2 +-
arch/arm/mach-s3c64xx/mach-anw6410.c   |2 +-
arch/a

[GIT PULL 2/6] Samsung drivers for v3.15

[Kukjin Kim]

The following changes since commit 38dbfb59d1175ef458d006556061adeaa8751b72:

  Linus 3.14-rc1 (2014-02-02 16:42:13 -0800)

are available in the git repository at:

  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-drivers

for you to fetch changes up to a83784859ccde07ebdc3a7acfbb2f74cb6c75a80:

  irqchip: exynos-combiner: call handle_bad_irq directly (2014-02-14 07:27:40 
+0900)


Samsung drivers update for v3.15
- remove inclusion from exynos_mct.c
- remove inclusion from exynos-combiner.c
  and use calling handle_bad_irq() instead of do_bad_IRQ()


Pankaj Dubey (2):
  clocksource: exynos_mct: remove unwanted header file inclusion
  irqchip: exynos-combiner: call handle_bad_irq directly

drivers/clocksource/exynos_mct.c  |2 --
drivers/irqchip/exynos-combiner.c |3 +--
2 files changed, 1 insertion(+), 4 deletions(-) 

Re: [PATCH 4/7] ARM: dts: exynos5440: fix PCIe interrupt mapping

[Lucas Stach]

Am Montag, den 03.03.2014, 16:53 +0900 schrieb Jingoo Han:
> On Monday, March 03, 2014 4:41 PM, Jingoo Han wrote:
> > On Saturday, March 01, 2014 2:29 AM, Lucas Stach wrote:
> > >
> > > So it actually works.
> > >
> > > Signed-off-by: Lucas Stach 
> > > ---
> > >  arch/arm/boot/dts/exynos5440.dtsi | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm/boot/dts/exynos5440.dtsi 
> > > b/arch/arm/boot/dts/exynos5440.dtsi
> > > index 02a0a1226cef..65d425d9ec27 100644
> > > --- a/arch/arm/boot/dts/exynos5440.dtsi
> > > +++ b/arch/arm/boot/dts/exynos5440.dtsi
> > > @@ -274,7 +274,7 @@
> > > 0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
> > > non-prefetchable memory */
> > >   #interrupt-cells = <1>;
> > >   interrupt-map-mask = <0 0 0 0>;
> > > - interrupt-map = <0x0 0 &gic 53>;
> > > + interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > 
> > It makes build errors as below:
> > 
> > DTC arch/arm/boot/dts/exynos5440-ssdk5440.dtb
> > Error: arch/arm/boot/dts/exynos5440.dtsi:289.33-34 syntax error
> > FATAL ERROR: Unable to parse input tree
> > make[1]: *** [arch/arm/boot/dts/exynos5440-ssdk5440.dtb] Error 1
> > make: *** [exynos5440-ssdk5440.dtb] Error 2
> > 
> > Would you fix it?
> 
> I fixed build errors after including 'arm-gic.h' as below:
> 
> --- a/arch/arm/boot/dts/exynos5440.dtsi
> +++ b/arch/arm/boot/dts/exynos5440.dtsi
> @@ -9,6 +9,8 @@
>   * published by the Free Software Foundation.
>  */
> 
> +#include 
> +
>  #include "skeleton.dtsi"
> 
> Would you confirm this?

That's the right fix, I'll include this (together with the other
feedback I received) in v2 of the series.

Regards,
Lucas

-- 
Pengutronix e.K.   | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

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Re: [PATCH 0/7] PCI irq mapping fixes and cleanups

[Jingoo Han]

On Sunday, March 02, 2014 3:31 AM, Jason Gunthorpe wrote:
> On Fri, Feb 28, 2014 at 04:53:33PM -0800, Tim Harvey wrote:
> 
> > In testing this on IMX6 I'm finding that 'of_irq_parse_and_map_pci()'
> > always returns -EINVAL because it can't find a dt node for the host
> > bridge:
> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/of/of_pci_irq.c#n60.
> 
> There may be some kind of issue in the pcie-designware.c:
> 
> static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> {
> struct pci_bus *bus;
> struct pcie_port *pp = sys_to_pcie(sys);
> 
> if (pp) {
> pp->root_bus_nr = sys->busnr;
> bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
>  ^^^
>  Shouldn't be null for DT cases.
> 
> Perhaps since the driver doesn't pass in a parent pointer, no parent
> device is associated with the struct pci_bus that gets created, so
> pci_bus_to_OF_node will always fail and the DT PCI mechanisms become
> broken.

Jason,
Thank you for your advice. :-)

Tim,
I tested the following as Jason guided.
You can test i.MX PCIe with this.

./drivers/pci/host/pcie-designware.c
@@ -726,7 +727,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct 
pci_sys_data *sys)

if (pp) {
pp->root_bus_nr = sys->busnr;
-   bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
+   bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
sys, &sys->resources);
} else {
bus = NULL;

However, I think that we may need to replace 'pci_common_init()'
with 'pci_common_init_dev()'.

Best regards,
Jingoo Han

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