[PATCH] mmc: dw_mmc: Make sure we don't get stuck when we get an error
From: Doug Anderson
If we happened to get a data error at just the wrong time the dw_mmc
driver could get into a state where it would never complete its
request. That would leave the caller just hanging there.
We fix this two ways and both of the two fixes on their own appear to
fix the problems we've seen:
1. Fix a race in the tasklet where the interrupt setting the data
error happens _just after_ we check for it, then we get a
EVENT_XFER_COMPLETE. We fix this by repeating a bit of code.
2. Fix it so that if we detect that we've got an error in the "data
busy" state and we're not going to do anything else we end the
request and unblock anyone waiting.
Signed-off-by: Doug Anderson
Signed-off-by: Yuvaraj Kumar C D
---
drivers/mmc/host/dw_mmc.c | 47 +
1 file changed, 47 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1d77431..4c589f1 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1300,6 +1300,14 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* fall through */
case STATE_SENDING_DATA:
+ /*
+* We could get a data error and never a transfer
+* complete so we'd better check for it here.
+*
+* Note that we don't really care if we also got a
+* transfer complete; stopping the DMA and sending an
+* abort won't hurt.
+*/
if (test_and_clear_bit(EVENT_DATA_ERROR,
&host->pending_events)) {
dw_mci_stop_dma(host);
@@ -1313,7 +1321,29 @@ static void dw_mci_tasklet_func(unsigned long priv)
break;
set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
+
+ /*
+* Handle an EVENT_DATA_ERROR that might have shown up
+* before the transfer completed. This might not have
+* been caught by the check above because the interrupt
+* could have gone off between the previous check and
+* the check for transfer complete.
+*
+* Technically this ought not be needed assuming we
+* get a DATA_COMPLETE eventually (we'll notice the
+* error and end the request), but it shouldn't hurt.
+*
+* This has the advantage of sending the stop command.
+*/
+ if (test_and_clear_bit(EVENT_DATA_ERROR,
+ &host->pending_events)) {
+ dw_mci_stop_dma(host);
+ send_stop_abort(host, data);
+ state = STATE_DATA_ERROR;
+ break;
+ }
prev_state = state = STATE_DATA_BUSY;
+
/* fall through */
case STATE_DATA_BUSY:
@@ -1336,6 +1366,23 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* stop command for open-ended transfer*/
if (data->stop)
send_stop_abort(host, data);
+ } else {
+ /*
+* If we don't have a command complete now we'll
+* never get one since we just reset everything;
+* better end the request.
+*
+* If we do have a command complete we'll fall
+* through to the SENDING_STOP command and
+* everything will be peachy keen.
+*
+* TODO: I guess we shouldn't send a stop?
+*/
+ if (!test_bit(EVENT_CMD_COMPLETE,
+ &host->pending_events)) {
+ dw_mci_request_end(host, mrq);
+ goto unlock;
+ }
}
/*
--
1.7.10.4
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[PATCH V2 3/3] ARM: dts: Add node for GPIO keys on SMDK5420
From: Abhilash Kesavan
Add support for the suspend/resume button (SW7) on SMDK5420 using
gpio-keys driver.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Vikas Sajjan
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6910485..5ae0dd4 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -158,6 +158,17 @@
};
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup {
+ label = "SW7";
+ gpios = <&gpx0 0 1>;
+ linux,code = <143>; /* KEY_WAKEUP */
+ gpio-key,wakeup;
+ };
+ };
+
hsi2c_4: i2c@12CA {
status = "okay";
--
1.7.9.5
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[PATCH V2 1/3] ARM: EXYNOS5: Add PMU settings for exynos5420
Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham
Signed-off-by: Abhilash Kesavan
Signed-off-by: Vikas Sajjan
---
arch/arm/mach-exynos/common.h | 10 ++
arch/arm/mach-exynos/pmu.c | 307 +++
arch/arm/mach-exynos/regs-pmu.h | 228 +
3 files changed, 545 insertions(+)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..347afc2 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,6 +15,16 @@
#include
#include
+#define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \
+| EXYNOS5420_ARM_USE_STANDBY_WFI1 \
+| EXYNOS5420_ARM_USE_STANDBY_WFI2 \
+| EXYNOS5420_ARM_USE_STANDBY_WFI3 \
+| EXYNOS5420_KFC_USE_STANDBY_WFI0 \
+| EXYNOS5420_KFC_USE_STANDBY_WFI1 \
+| EXYNOS5420_KFC_USE_STANDBY_WFI2 \
+| EXYNOS5420_KFC_USE_STANDBY_WFI3)
+
+
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
struct map_desc;
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce1..f69a6ed 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,9 +12,14 @@
#include
#include
#include
+#include
+#include
+#include
#include
+#include
+
#include "common.h"
#include "regs-pmu.h"
@@ -318,6 +323,212 @@ static const struct exynos_pmu_conf
exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
+static const struct exynos_pmu_conf exynos5420_pmu_config[] = {
+ /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+ { EXYNOS5_ARM_CORE0_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_ARM_CORE1_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,{ 0x1, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_L2_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { EXYNOS5_CMU_RESET_SYS_PWR_REG,{ 0x1, 0x1,
0x0} },
+ { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { E
[PATCH V2 0/3] Add PMU and S2R support for exynos5420
rebased on kgene tree for-next branch https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next changes since v1: - Addressed comments from Tomasz figa. - restructured/consolidated as per Tomasz figa's PM consolidations for exynos Abhilash Kesavan (1): ARM: dts: Add node for GPIO keys on SMDK5420 Vikas Sajjan (2): ARM: EXYNOS5: Add PMU settings for exynos5420 ARM: EXYNOS5: Support Suspend-to-RAM on EXYNOS5420 arch/arm/boot/dts/exynos5420-smdk5420.dts| 11 + arch/arm/mach-exynos/common.h| 10 + arch/arm/mach-exynos/pm.c| 148 +++-- arch/arm/mach-exynos/pmu.c | 307 ++ arch/arm/mach-exynos/regs-pmu.h | 230 +++ arch/arm/plat-samsung/include/plat/map-s5p.h |2 + drivers/clk/samsung/clk-exynos5420.c | 32 +++ 7 files changed, 722 insertions(+), 18 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 2/3] ARM: EXYNOS5: Support Suspend-to-RAM on EXYNOS5420
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by: Abhilash Kesavan
Signed-off-by: Vikas Sajjan
---
arch/arm/mach-exynos/pm.c| 148 ++
arch/arm/mach-exynos/regs-pmu.h |4 +-
arch/arm/plat-samsung/include/plat/map-s5p.h |2 +
drivers/clk/samsung/clk-exynos5420.c | 32 ++
4 files changed, 167 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ce..aa3c2c8 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -59,6 +59,16 @@ static struct sleep_save exynos_core_save[] = {
SAVE_ITEM(S5P_SROM_BC3),
};
+static struct sleep_save exynos5420_cpustate_save[] = {
+ SAVE_ITEM(EXYNOS5420_VA_CPU_STATE),
+};
+
+static struct sleep_save exynos5420_reg_save[] = {
+ SAVE_ITEM(EXYNOS5_SYS_DISP1_BLK_CFG),
+ SAVE_ITEM(S5P_PMU_SPARE3),
+};
+
+
/*
* GIC wake-up support
*/
@@ -81,7 +91,7 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
{
const struct exynos_wkup_irq *wkup_irq;
- if (soc_is_exynos5250())
+ if (soc_is_exynos5250() || soc_is_exynos5420())
wkup_irq = exynos5250_wkup_irq;
else
wkup_irq = exynos4_wkup_irq;
@@ -109,7 +119,15 @@ static int exynos_cpu_suspend(unsigned long arg)
outer_flush_all();
#endif
- if (soc_is_exynos5250())
+ /*
+* Clear IRAM register for cpu state so that primary CPU does
+* not enter low power start in U-Boot.
+* This is specific to exynos5420 SoC only.
+*/
+ if (soc_is_exynos5420())
+ __raw_writel(0x0, EXYNOS5420_VA_CPU_STATE);
+
+ if (soc_is_exynos5250() || soc_is_exynos5420())
flush_cache_all();
/* issue the standby signal into the pm unit. */
@@ -135,6 +153,20 @@ static void exynos_pm_prepare(void)
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+ } else if (soc_is_exynos5420()) {
+
+ s3c_pm_do_save(exynos5420_reg_save,
+ ARRAY_SIZE(exynos5420_reg_save));
+
+ /*
+* The cpu state needs to be saved and restored so that the
+* secondary CPUs will enter low power start. Though the U-Boot
+* is setting the cpu state with low power flag, the kernel
+* needs to restore it back in case, the primary cpu fails to
+* suspend for any reason
+*/
+ s3c_pm_do_save(exynos5420_cpustate_save,
+ ARRAY_SIZE(exynos5420_cpustate_save));
}
/* Set value of power down register for sleep mode */
@@ -145,11 +177,34 @@ static void exynos_pm_prepare(void)
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+
+ if (soc_is_exynos5420()) {
+
+ tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
+ tmp &= ~EXYNOS5_USE_RETENTION;
+ __raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+
+ tmp = __raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+ tmp |= EXYNOS5420_UFS;
+ __raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+
+ tmp = __raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+ tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
+ __raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
+ tmp = __raw_readl(EXYNOS5420_FSYS2_OPTION);
+ tmp |= EXYNOS5420_EMULATION;
+ __raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+ tmp = __raw_readl(EXYNOS5420_PSGEN_OPTION);
+ tmp |= EXYNOS5420_EMULATION;
+ __raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+ }
+
}
static int exynos_pm_suspend(void)
{
unsigned long tmp;
+ unsigned long cluster_id;
/* Setting Central Sequence Register for power down mode */
@@ -159,10 +214,20 @@ static int exynos_pm_suspend(void)
/* Setting SEQ_OPTION register */
- tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ if (soc_is_exynos5420()) {
+ cluster_id = (read_cpuid(CPUID_MPIDR) >> 8) & 0xf;
+ if (!cluster_id)
+ __raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
+S5P_CENTRAL_SEQ_OPTION);
+ else
+ __raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
+S5P_CENTRAL_SEQ_OPTION);
+ } else {
+ tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ }
- if (!soc_is_exynos5250()) {
+ if (!(soc_is_exynos5250() || soc_is_exynos5420(
Re: [PATCH V14 0/7] add new Samsung SXGBE driver
From: Byungho An Date: Tue, 25 Mar 2014 12:10:47 -0700 > This is 14th posting for SAMSUNG SXGBE driver. Series applied to net-next, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos-drm HDMI PHY configuration values
On Tue, Mar 25, 2014 at 2:52 PM, Daniel Drake wrote: > Hi Sean, > > In your commit "drm/exynos: hdmi: support extra resolutions using > drm_display_mode timings" you added several more HDMI PHY configs to > exynos-drm. Thanks for that. > > Can you explain where these magic numbers came from? > Hi Daniel, They come from Samsung. Unfortunately, I don't have any insight into how they are generated. Sean > I'm interested in adding 85.5MHz for 1366x768 support. > > Thanks, > Daniel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] mmc: dw_mmc: change to use recommended reset procedure
From: Sonny Rao
This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys Mobile storage host databook
7.2.13.
Without this patch, we could able to see eMMC was not detected after
multiple reboots due to driver hangs while eMMC tuning for HS200.
Signed-off-by: Sonny Rao
Signed-off-by: Yuvaraj Kumar C D
---
drivers/mmc/host/dw_mmc.c | 48 -
drivers/mmc/host/dw_mmc.h |1 +
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 32dd81d..1d77431 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2220,7 +2220,53 @@ static inline bool dw_mci_fifo_reset(struct dw_mci *host)
host->sg = NULL;
}
- return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
+ /*
+* The recommended method for resetting is to always reset the
+* controller and the fifo, but differs slightly depending on the mode.
+* Note that this doesn't handle the "generic DMA" (not IDMAC) case.
+*/
+ if (dw_mci_ctrl_reset(host, SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET)) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(500);
+ u32 status, rint;
+
+ /* if using dma we wait for dma_req to clear */
+ if (host->using_dma) {
+ do {
+ status = mci_readl(host, STATUS);
+ if (!(status & SDMMC_STATUS_DMA_REQ))
+ break;
+ cpu_relax();
+ } while (time_before(jiffies, timeout));
+
+ if (status & SDMMC_STATUS_DMA_REQ)
+ dev_err(host->dev,
+ "%s: Timeout waiting for dma_req to "
+ "clear during reset", __func__);
+
+ /* when using DMA next we reset the fifo again */
+ dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
+ }
+ /*
+* In all cases we clear the RAWINTS register to clear any
+* interrupts.
+*/
+ rint = mci_readl(host, RINTSTS);
+ rint = rint & (~mci_readl(host, MINTSTS));
+ if (rint)
+ mci_writel(host, RINTSTS, rint);
+
+ } else
+ dev_err(host->dev, "%s: Reset bits didn't clear", __func__);
+
+ #ifdef CONFIG_MMC_DW_IDMAC
+ /* It is also recommended that we reset and reprogram idmac */
+ dw_mci_idmac_reset(host);
+ #endif
+
+ /* After a CTRL reset we need to have CIU set clock registers */
+ mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
+
+ return true;
}
static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 738fa24..037e47a 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -129,6 +129,7 @@
#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
/* Status register defines */
#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
+#define SDMMC_STATUS_DMA_REQ BIT(31)
/* FIFOTH register defines */
#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
((r) & 0xFFF) << 16 | \
--
1.7.10.4
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[PATCH v2 7/7] ARM: dts: add HS400 support for Exynos5420
HS400 timing value set is added for SMDK5420.
And GPIO line for RCLK should be pull-down state.
Signed-off-by: Seungwon Jeon
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |6 ++
arch/arm/boot/dts/exynos5420-pinctrl.dtsi |7 +++
arch/arm/boot/dts/exynos5420-smdk5420.dts |5 -
3 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index ca1914f..39c3014 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -29,6 +29,9 @@ Required Properties:
data rate mode operation. Refer notes below for the order of the cells and
the
valid values.
+* samsung,dw-mshc-hs200-timing: Similar with dw-mshc-sdr-timing.
+* samsung,dw-mshc-hs400-timing: Similar with dw-mshc-ddr-timing.
+
Notes for the sdr-timing and ddr-timing values:
The order of the cells should be
@@ -45,6 +48,9 @@ Required Properties:
- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
phase shift clocks should be 0.
+* read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
+ (Latency value for delay line in Read path)
+
Required properties for a slot:
* gpios: specifies a list of gpios used for command, clock and data bus. The
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e62c8eb..51233ee 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -194,6 +194,13 @@
samsung,pin-drv = <3>;
};
+ sd0_rclk: sd0-rclk {
+ samsung,pins = "gpc0-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <1>;
+ samsung,pin-drv = <3>;
+ };
+
sd1_clk: sd1-clk {
samsung,pins = "gpc1-0";
samsung,pin-function = <2>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 3ad4ef3..4796d44 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -38,8 +38,11 @@
card-detect-delay = <200>;
samsung,dw-mshc-sdr-timing = <0 4 3>;
samsung,dw-mshc-ddr-timing = <0 2 3>;
+ samsung,dw-mshc-hs200-timing = <0 2 3>;
+ samsung,dw-mshc-hs400-timing = <0 2 1>;
+ read-strobe-delay = <90>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>;
slot@0 {
reg = <0>;
--
1.7.4.1
--
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[PATCH v2 6/7] ARM: dts: drop dw-mshc-ciu-div property from Exynos
As dw-mshc-ciu-div is strongly close to timing property,
it is merged with each timing property.
Signed-off-by: Seungwon Jeon
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt | 12 +---
arch/arm/boot/dts/exynos4412-odroidx.dts |5 ++---
arch/arm/boot/dts/exynos4412-origen.dts|5 ++---
arch/arm/boot/dts/exynos4412-trats2.dts|5 ++---
arch/arm/boot/dts/exynos5250-arndale.dts | 10 --
arch/arm/boot/dts/exynos5250-cros-common.dtsi | 15 ++-
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 --
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 10 --
arch/arm/boot/dts/exynos5420-smdk5420.dts | 10 --
9 files changed, 33 insertions(+), 49 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 532b1d4..ca1914f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -19,10 +19,6 @@ Required Properties:
- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
specific extensions.
-* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
- unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
- ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
-
* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift
value
in transmit mode and CIU clock phase shift value in receive mode for single
data rate mode operation. Refer notes below for the order of the cells and
the
@@ -38,6 +34,9 @@ Required Properties:
The order of the cells should be
- First Cell: CIU clock phase shift value for tx mode.
- Second Cell: CIU clock phase shift value for rx mode.
+ - Thrid Cell: Specifies the divider value for the card interface
+ unit (ciu) clock. This property is applicable only for Exynos5
SoC's and
+ ignored for Exynos4 SoC's. The valid range of divider value is 0 to
7.
Valid values for SDR and DDR CIU clock timing for Exynos5250:
- valid value for tx phase shift and rx phase shift is 0 to 7.
@@ -73,9 +72,8 @@ Example:
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
+ samsung,dw-mshc-sdr-timing = <2 3 3>;
+ samsung,dw-mshc-ddr-timing = <1 2 3>;
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 9804fcb..99f32db 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -48,9 +48,8 @@
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
+ samsung,dw-mshc-sdr-timing = <2 3 0>;
+ samsung,dw-mshc-ddr-timing = <1 2 0>;
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index 6bc0539..7c0b535 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -131,9 +131,8 @@
supports-highspeed;
broken-cd;
card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
+ samsung,dw-mshc-sdr-timing = <2 3 0>;
+ samsung,dw-mshc-ddr-timing = <1 2 0>;
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 4f851cc..556e414 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -451,9 +451,8 @@
card-detect-delay = <200>;
vmmc-supply = <&vemmc_reg>;
clock-frequency = <4>;
- samsung,dw-mshc-ciu-div = <0>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
+ samsung,dw-mshc-sdr-timing = <2 3 0>;
+ samsung,dw-mshc-ddr-timing = <1 2 0>;
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index b42e658..dc53b51 100644
---
[PATCH v2 5/7] mmc: dw_mmc: exynos: support eMMC's HS400 mode
Implements HS400 support for exynos host driver.
And this patch includes some updates as new mode is added.
Signed-off-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-exynos.c | 140 +++---
drivers/mmc/host/dw_mmc-exynos.h | 14
drivers/mmc/host/dw_mmc.c|3 +-
3 files changed, 130 insertions(+), 27 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 39f9114..78f3b07 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -40,7 +40,12 @@ struct dw_mci_exynos_priv_data {
u32 sdr_timing;
u32 ddr_timing;
u32 hs200_timing;
+ u32 hs400_timing;
+ u32 tuned_sample;
u32 cur_speed;
+ u32 dqs_delay;
+ u32 saved_dqs_en;
+ u32 saved_strobe_ctrl;
};
static struct dw_mci_exynos_compatible {
@@ -90,6 +95,16 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
}
+ if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
+ priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
+ priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
+ priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
+ mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
+ if (!priv->dqs_delay)
+ priv->dqs_delay =
+ DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
+ }
+
priv->ciu_div = dw_mci_exynos_get_ciu_div(host);
return 0;
@@ -104,6 +119,14 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
return 0;
}
+static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
+{
+ u32 clksel;
+ clksel = mci_readl(host, CLKSEL);
+ clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
+ mci_writel(host, CLKSEL, clksel);
+}
+
#ifdef CONFIG_PM_SLEEP
static int dw_mci_exynos_suspend(struct device *dev)
{
@@ -161,23 +184,39 @@ static void dw_mci_exynos_prepare_command(struct dw_mci
*host, u32 *cmdr)
*cmdr |= SDMMC_CMD_USE_HOLD_REG;
}
-static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
{
struct dw_mci_exynos_priv_data *priv = host->priv;
- unsigned int wanted = ios->clock;
- unsigned long actual;
+ u32 dqs, strobe;
- if (ios->timing == MMC_TIMING_MMC_HS200) {
- mci_writel(host, CLKSEL, priv->hs200_timing);
- } else if (ios->timing == MMC_TIMING_MMC_DDR52) {
- mci_writel(host, CLKSEL, priv->ddr_timing);
- /* Should be double rate for DDR mode */
- if (ios->bus_width == MMC_BUS_WIDTH_8)
- wanted <<= 1;
+ /*
+* Not suppported to configure register
+* related to HS400
+*/
+ if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
+ return;
+
+ dqs = priv->saved_dqs_en;
+ strobe = priv->saved_strobe_ctrl;
+
+ if (timing == MMC_TIMING_MMC_HS400) {
+ dqs |= DATA_STROBE_EN;
+ strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
} else {
- mci_writel(host, CLKSEL, priv->sdr_timing);
+ dqs &= ~DATA_STROBE_EN;
}
+ mci_writel(host, HS400_DQS_EN, dqs);
+ mci_writel(host, HS400_DLINE_CTRL, strobe);
+}
+
+static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int
wanted)
+{
+ struct dw_mci_exynos_priv_data *priv = host->priv;
+ unsigned long actual;
+ u8 div;
+ int ret;
+
/*
* Don't care if wanted clock is zero or
* ciu clock is unavailable
@@ -189,18 +228,57 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
if (wanted < EXYNOS_CCLKIN_MIN)
wanted = EXYNOS_CCLKIN_MIN;
- if (wanted != priv->cur_speed) {
- u8 div = dw_mci_exynos_get_ciu_div(host);
- int ret = clk_set_rate(host->ciu_clk, wanted * div);
- if (ret)
- dev_warn(host->dev,
- "failed to set clk-rate %u error: %d\n",
-wanted * div, ret);
- actual = clk_get_rate(host->ciu_clk);
- host->bus_hz = actual / div;
- priv->cur_speed = wanted;
- host->current_speed = 0;
+ if (wanted == priv->cur_speed)
+ return;
+
+ div = dw_mci_exynos_get_ciu_div(host);
+ ret = clk_set_rate(host->ciu_clk, wanted * div);
+
[PATCH v2 4/7] mmc: dw_mmc: exynos: incorporate ciu_div into timing property
ciu_div may not be common value for all speed mode.
So, it needs to be attached to CLKSEL timing.
Signed-off-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-exynos.c | 75 ++
drivers/mmc/host/dw_mmc-exynos.h |1 +
2 files changed, 53 insertions(+), 23 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index bab97e9..39f9114 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -39,6 +39,7 @@ struct dw_mci_exynos_priv_data {
u8 ciu_div;
u32 sdr_timing;
u32 ddr_timing;
+ u32 hs200_timing;
u32 cur_speed;
};
@@ -64,6 +65,18 @@ static struct dw_mci_exynos_compatible {
},
};
+static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
+{
+ struct dw_mci_exynos_priv_data *priv = host->priv;
+
+ if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
+ return EXYNOS4412_FIXED_CIU_CLK_DIV;
+ else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
+ return EXYNOS4210_FIXED_CIU_CLK_DIV;
+ else
+ return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
+}
+
static int dw_mci_exynos_priv_init(struct dw_mci *host)
{
struct dw_mci_exynos_priv_data *priv = host->priv;
@@ -77,6 +90,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
}
+ priv->ciu_div = dw_mci_exynos_get_ciu_div(host);
+
return 0;
}
@@ -84,7 +99,7 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
struct dw_mci_exynos_priv_data *priv = host->priv;
- host->bus_hz /= (priv->ciu_div + 1);
+ host->bus_hz /= priv->ciu_div;
return 0;
}
@@ -151,9 +166,10 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
struct dw_mci_exynos_priv_data *priv = host->priv;
unsigned int wanted = ios->clock;
unsigned long actual;
- u8 div = priv->ciu_div + 1;
- if (ios->timing == MMC_TIMING_MMC_DDR52) {
+ if (ios->timing == MMC_TIMING_MMC_HS200) {
+ mci_writel(host, CLKSEL, priv->hs200_timing);
+ } else if (ios->timing == MMC_TIMING_MMC_DDR52) {
mci_writel(host, CLKSEL, priv->ddr_timing);
/* Should be double rate for DDR mode */
if (ios->bus_width == MMC_BUS_WIDTH_8)
@@ -174,6 +190,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
wanted = EXYNOS_CCLKIN_MIN;
if (wanted != priv->cur_speed) {
+ u8 div = dw_mci_exynos_get_ciu_div(host);
int ret = clk_set_rate(host->ciu_clk, wanted * div);
if (ret)
dev_warn(host->dev,
@@ -186,14 +203,34 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
}
}
+static int dw_mci_exynos_dt_populate_timing(struct dw_mci *host,
+ unsigned int ctrl_type,
+ const char *propname,
+ u32 *out_values)
+{
+ struct device_node *np = host->dev->of_node;
+ u32 timing[3];
+ int ret;
+
+ ret = of_property_read_u32_array(np, propname, timing, 3);
+ if (ret)
+ return ret;
+
+ if (ctrl_type == DW_MCI_TYPE_EXYNOS4412 ||
+ ctrl_type == DW_MCI_TYPE_EXYNOS4210)
+ timing[2] = 0;
+
+ *out_values = SDMMC_CLKSEL_TIMING(timing[0], timing[1], timing[2]);
+
+ return 0;
+}
+
+
static int dw_mci_exynos_parse_dt(struct dw_mci *host)
{
struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host->dev->of_node;
- u32 timing[2];
- u32 div = 0;
- int idx;
- int ret;
+ int idx, ret;
priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
@@ -206,29 +243,21 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
priv->ctrl_type = exynos_compat[idx].ctrl_type;
}
- if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
- priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
- else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
- priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
- else {
- of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
- priv->ciu_div = div;
- }
-
- ret = of_property_read_u32_array(np,
- "samsung,dw-mshc-sdr-timing", timing, 2);
+ ret = dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type,
+ "samsung,dw-mshc-sdr-timing", &priv->sdr_timing);
if (ret)
return ret;
-
[PATCH v2 3/7] mmc: dw_mmc: exynos: move definitions to header file
Move some parts related to definition to header file.
Signed-off-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-exynos.c | 46 ---
drivers/mmc/host/dw_mmc-exynos.h | 55 ++
2 files changed, 61 insertions(+), 40 deletions(-)
create mode 100644 drivers/mmc/host/dw_mmc-exynos.h
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index a2d06c5..bab97e9 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -21,42 +21,8 @@
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
+#include "dw_mmc-exynos.h"
-#define NUM_PINS(x)(x + 2)
-
-#define SDMMC_CLKSEL 0x09C
-#define SDMMC_CLKSEL_CCLK_SAMPLE(x)(((x) & 7) << 0)
-#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
-#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
-#define SDMMC_CLKSEL_GET_DRV_WD3(x)(((x) >> 16) & 0x7)
-#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
- SDMMC_CLKSEL_CCLK_DRIVE(y) |\
- SDMMC_CLKSEL_CCLK_DIVIDER(z))
-#define SDMMC_CLKSEL_WAKEUP_INTBIT(11)
-
-#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
-#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
-
-/* Block number in eMMC */
-#define DWMCI_BLOCK_NUM0x
-
-#define SDMMC_EMMCP_BASE 0x1000
-#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
-#define SDMMC_MPSBEGIN0(SDMMC_EMMCP_BASE + 0x0200)
-#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
-#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
-
-/* SMU control bits */
-#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
-#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
-#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
-#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
-#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
-#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
-#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
-#define DWMCI_MPSCTRL_VALIDBIT(0)
-
-#define EXYNOS_CCLKIN_MIN 5000/* unit: HZ */
/* Variations in Exynos specific dw-mshc controller */
enum dw_mci_exynos_type {
@@ -104,11 +70,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
mci_writel(host, MPSBEGIN0, 0);
- mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
- mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
- DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
- DWMCI_MPSCTRL_VALID |
- DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+ mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
+ mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
+ SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
+ SDMMC_MPSCTRL_VALID |
+ SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
}
return 0;
diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h
new file mode 100644
index 000..2554e2f
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-exynos.h
@@ -0,0 +1,55 @@
+/*
+ * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _DW_MMC_EXYNOS_H_
+#define _DW_MMC_EXYNOS_H_
+
+/* Extended Register's Offset */
+#define SDMMC_CLKSEL 0x09C
+
+/* CLKSEL register defines */
+#define SDMMC_CLKSEL_CCLK_SAMPLE(x)(((x) & 7) << 0)
+#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
+#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
+#define SDMMC_CLKSEL_GET_DRV_WD3(x)(((x) >> 16) & 0x7)
+#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
+SDMMC_CLKSEL_CCLK_DRIVE(y) | \
+SDMMC_CLKSEL_CCLK_DIVIDER(z))
+#define SDMMC_CLKSEL_WAKEUP_INTBIT(11)
+
+/* Protector Register */
+#define SDMMC_EMMCP_BASE 0x1000
+#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control defines */
+#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
+#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
+#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT
[PATCH v2 1/7] mmc: dw_mmc: fix the max_blk_count in IDMAC
Even though 1MB is reserved for descriptor table in IDMAC, the dw_mmc host driver is allowed to receive only maximum 128KB block length in one request. This is caused by setting improper max_blk_count. It needs to be e adjusted so that descriptor table is used fully. It is found that the performance is improved with the increased the max_blk_count. Signed-off-by: Seungwon Jeon --- drivers/mmc/host/dw_mmc.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 3a6721e..aeb38f9 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2101,9 +2101,9 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) #ifdef CONFIG_MMC_DW_IDMAC mmc->max_segs = host->ring_size; mmc->max_blk_size = 65536; - mmc->max_blk_count = host->ring_size; mmc->max_seg_size = 0x1000; - mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; + mmc->max_req_size = mmc->max_seg_size * host->ring_size; + mmc->max_blk_count = mmc->max_req_size / 512; #else mmc->max_segs = 64; mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ -- 1.7.4.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/7] mmc: dw_mmc: update host driver including HS400 support
This patch-set includes several driver's updates. Specially, HS400 mode is enabled for eMMC5.0 spec. And it goes with "[PATCH v4 5/5] mmc: add support for HS400 mode of eMMC5.0" Changes in v2: (2/7) Reuse bus_hz for clock rate. (3/7) Fix typo. Seungwon Jeon (7): mmc: dw_mmc: fix the max_blk_count in IDMAC mmc: dw_mmc: exynos: don't use if clock isn't available mmc: dw_mmc: exynos: move definitions to header file mmc: dw_mmc: exynos: incorporate ciu_div into timing property mmc: dw_mmc: exynos: support eMMC's HS400 mode ARM: dts: drop dw-mshc-ciu-div property from Exynos ARM: dts: add HS400 support for Exynos5420 .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 18 +- arch/arm/boot/dts/exynos4412-odroidx.dts |5 +- arch/arm/boot/dts/exynos4412-origen.dts|5 +- arch/arm/boot/dts/exynos4412-trats2.dts|5 +- arch/arm/boot/dts/exynos5250-arndale.dts | 10 +- arch/arm/boot/dts/exynos5250-cros-common.dtsi | 15 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 +- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 10 +- arch/arm/boot/dts/exynos5420-pinctrl.dtsi |7 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 15 +- drivers/mmc/host/dw_mmc-exynos.c | 262 +--- drivers/mmc/host/dw_mmc-exynos.h | 70 ++ drivers/mmc/host/dw_mmc.c |7 +- 13 files changed, 298 insertions(+), 141 deletions(-) create mode 100644 drivers/mmc/host/dw_mmc-exynos.h Thanks, sw-j -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/7] mmc: dw_mmc: exynos: don't use if clock isn't available
Add checking whether the clock is valid.
Signed-off-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-exynos.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index a67e784..a2d06c5 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -117,9 +117,9 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
static int dw_mci_exynos_setup_clock(struct dw_mci *host)
{
struct dw_mci_exynos_priv_data *priv = host->priv;
- unsigned long rate = clk_get_rate(host->ciu_clk);
- host->bus_hz = rate / (priv->ciu_div + 1);
+ host->bus_hz /= (priv->ciu_div + 1);
+
return 0;
}
@@ -196,8 +196,11 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
mci_writel(host, CLKSEL, priv->sdr_timing);
}
- /* Don't care if wanted clock is zero */
- if (!wanted)
+ /*
+* Don't care if wanted clock is zero or
+* ciu clock is unavailable
+*/
+ if (!wanted || IS_ERR(host->ciu_clk))
return;
/* Guaranteed minimum frequency for cclkin */
--
1.7.4.1
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[PATCH v2] ARM: dts: exynos4210-trats: add max8997 IRQ
This patch adds IRQ line specification for the MAX8997 chip and necessary
pinctrl group to configure pull-up and driver strength of the pin.
It's needed for proper handling of IRQs coming from MAX8997 multifunction
device (IRQs are used by PMIC, MUIC and RTC).
Signed-off-by: Robert Baldyga
Reviewed-by: Tomasz Figa
---
Changelog:
v2:
- Corrected commit message.
v1: https://lkml.org/lkml/2014/3/14/124
arch/arm/boot/dts/exynos4210-trats.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 662b482..5629eef 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -156,6 +156,14 @@
};
};
+ pinctrl@1100 {
+ max8997_irq: max8997-irq {
+ samsung,pins = "gpx0-7";
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
i2c@1389 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-slave-addr = <0x10>;
@@ -187,6 +195,11 @@
max8997_pmic@66 {
compatible = "maxim,max8997-pmic";
+ pinctrl-0 = <&max8997_irq>;
+ pinctrl-names = "default";
+
+ interrupt-parent = <&gpx0>;
+ interrupts = <7 0>;
reg = <0x66>;
max8997,pmic-buck1-uses-gpio-dvs;
--
1.7.9.5
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[PATCH v3 2/3] drm/panel: add ld9040 driver
The patch adds LD9040 parallel RGB panel driver with SPI control interface.
The driver uses drm_panel framework.
Signed-off-by: Andrzej Hajda
---
v2: removed useless include
v3: added SPI dependency to Kconfig
---
drivers/gpu/drm/panel/Kconfig| 7 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-ld9040.c | 376 +++
3 files changed, 384 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-ld9040.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 3e0f13d..f0fcb62 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -16,4 +16,11 @@ config DRM_PANEL_SIMPLE
that it can be automatically turned off when the panel goes into a
low power state.
+config DRM_PANEL_LD9040
+ tristate "LD9040 RGB/SPI panel"
+ depends on DRM && DRM_PANEL
+ depends on OF
+ select SPI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index af9dfa2..4f7dfce 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-ld9040.c
b/drivers/gpu/drm/panel/panel-ld9040.c
new file mode 100644
index 000..1f1f837
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-ld9040.c
@@ -0,0 +1,376 @@
+/*
+ * ld9040 AMOLED LCD drm_panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ * Derived from drivers/video/backlight/ld9040.c
+ *
+ * Andrzej Hajda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/* Manufacturer Command Set */
+#define MCS_MANPWR 0xb0
+#define MCS_ELVSS_ON 0xb1
+#define MCS_USER_SETTING 0xf0
+#define MCS_DISPCTL0xf2
+#define MCS_GTCON 0xf7
+#define MCS_PANEL_CONDITION0xf8
+#define MCS_GAMMA_SET1 0xf9
+#define MCS_GAMMA_CTRL 0xfb
+
+/* array of gamma tables for gamma value 2.2 */
+static u8 const ld9040_gammas[25][22] = {
+ { 0xf9, 0x00, 0x13, 0xb2, 0xba, 0xd2, 0x00, 0x30, 0x00, 0xaf, 0xc0,
+ 0xb8, 0xcd, 0x00, 0x3d, 0x00, 0xa8, 0xb8, 0xb7, 0xcd, 0x00, 0x44 },
+ { 0xf9, 0x00, 0x13, 0xb9, 0xb9, 0xd0, 0x00, 0x3c, 0x00, 0xaf, 0xbf,
+ 0xb6, 0xcb, 0x00, 0x4b, 0x00, 0xa8, 0xb9, 0xb5, 0xcc, 0x00, 0x52 },
+ { 0xf9, 0x00, 0x13, 0xba, 0xb9, 0xcd, 0x00, 0x41, 0x00, 0xb0, 0xbe,
+ 0xb5, 0xc9, 0x00, 0x51, 0x00, 0xa9, 0xb9, 0xb5, 0xca, 0x00, 0x57 },
+ { 0xf9, 0x00, 0x13, 0xb9, 0xb8, 0xcd, 0x00, 0x46, 0x00, 0xb1, 0xbc,
+ 0xb5, 0xc8, 0x00, 0x56, 0x00, 0xaa, 0xb8, 0xb4, 0xc9, 0x00, 0x5d },
+ { 0xf9, 0x00, 0x13, 0xba, 0xb8, 0xcb, 0x00, 0x4b, 0x00, 0xb3, 0xbc,
+ 0xb4, 0xc7, 0x00, 0x5c, 0x00, 0xac, 0xb8, 0xb4, 0xc8, 0x00, 0x62 },
+ { 0xf9, 0x00, 0x13, 0xbb, 0xb7, 0xca, 0x00, 0x4f, 0x00, 0xb4, 0xbb,
+ 0xb3, 0xc7, 0x00, 0x60, 0x00, 0xad, 0xb8, 0xb4, 0xc7, 0x00, 0x67 },
+ { 0xf9, 0x00, 0x47, 0xba, 0xb6, 0xca, 0x00, 0x53, 0x00, 0xb5, 0xbb,
+ 0xb3, 0xc6, 0x00, 0x65, 0x00, 0xae, 0xb8, 0xb3, 0xc7, 0x00, 0x6c },
+ { 0xf9, 0x00, 0x71, 0xbb, 0xb5, 0xc8, 0x00, 0x57, 0x00, 0xb5, 0xbb,
+ 0xb0, 0xc5, 0x00, 0x6a, 0x00, 0xae, 0xb9, 0xb1, 0xc6, 0x00, 0x70 },
+ { 0xf9, 0x00, 0x7b, 0xbb, 0xb4, 0xc8, 0x00, 0x5b, 0x00, 0xb5, 0xba,
+ 0xb1, 0xc4, 0x00, 0x6e, 0x00, 0xae, 0xb9, 0xb0, 0xc5, 0x00, 0x75 },
+ { 0xf9, 0x00, 0x82, 0xba, 0xb4, 0xc7, 0x00, 0x5f, 0x00, 0xb5, 0xba,
+ 0xb0, 0xc3, 0x00, 0x72, 0x00, 0xae, 0xb8, 0xb0, 0xc3, 0x00, 0x7a },
+ { 0xf9, 0x00, 0x89, 0xba, 0xb3, 0xc8, 0x00, 0x62, 0x00, 0xb6, 0xba,
+ 0xaf, 0xc3, 0x00, 0x76, 0x00, 0xaf, 0xb7, 0xae, 0xc4, 0x00, 0x7e },
+ { 0xf9, 0x00, 0x8b, 0xb9, 0xb3, 0xc7, 0x00, 0x65, 0x00, 0xb7, 0xb8,
+ 0xaf, 0xc3, 0x00, 0x7a, 0x00, 0x80, 0xb6, 0xae, 0xc4, 0x00, 0x81 },
+ { 0xf9, 0x00, 0x93, 0xba, 0xb3, 0xc5, 0x00, 0x69, 0x00, 0xb8, 0xb9,
+ 0xae, 0xc1, 0x00, 0x7f, 0x00, 0xb0, 0xb6, 0xae, 0xc3, 0x00, 0x85 },
+ { 0xf9, 0x00, 0x97, 0xba, 0xb2, 0xc5, 0x00, 0x6c, 0x00, 0xb8, 0xb8,
+ 0xae, 0xc1, 0x00, 0x82, 0x00, 0xb0, 0xb6, 0xae, 0xc2, 0x00, 0x89 },
+ { 0xf9, 0x00, 0x9a, 0xba, 0xb1, 0xc4, 0x00, 0x6f, 0x00, 0xb8, 0xb8,
+ 0xad, 0xc0, 0x00, 0x86, 0x00, 0xb0, 0xb7, 0xad, 0xc0, 0x00, 0x8d },
+ { 0xf9, 0x00, 0x9c, 0xb9, 0xb0, 0xc4, 0x00, 0x72, 0x00, 0xb8, 0xb8,
+ 0xac, 0xbf, 0x00, 0x8a, 0x00, 0xb0, 0xb6, 0xac, 0xc0, 0x00, 0x91 },
+ { 0xf9, 0x00, 0x9e, 0xba, 0xb0, 0xc2, 0x00, 0x75, 0x00, 0xb9, 0xb8,
+ 0xab, 0xbe, 0x00, 0x8e, 0x00, 0xb0, 0xb6, 0xac, 0xbf, 0x00, 0x
[PATCH 2/3] ARM: dts: add cm36651 light/proximity sensor node
Exynos4412-trats2 board have light/proximity sensor.
This patch add cm36651 light/ proximity sensor node for exynos4412.
cm36651 is required properties as below.
- Use i2c-gpio for cm36651 sensor.
- Use fixed regulator for the IR LED.
It is a part of the cm36651 for proximity detection.
- cm36651 is i2c device driver so need to use i2c-gpio driver.
Signed-off-by: Beomho Seo
Signed-off-by: MyungJoo Ham
---
arch/arm/boot/dts/exynos4412-trats2.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 42418e2..c9f3c6e 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -21,6 +21,7 @@
aliases {
i2c8 = &i2c_ak8975;
+ i2c9 = &i2c_cm36651;
};
memory {
@@ -71,6 +72,14 @@
enable-active-high;
};
+ ps_als_reg: voltage-regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_A_3.0V";
+ regulator-min-microvolt = <300>;
+ regulator-max-microvolt = <300>;
+ gpio = <&gpj0 5 0>;
+ enable-active-high;
+ };
/* More to come */
};
@@ -500,6 +509,23 @@
};
};
+ i2c_cm36651: i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ gpios = <&gpf0 0 0>, <&gpf0 1 0>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ cm36651@18 {
+ compatible = "cm36651";
+ reg = <0x18>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <2 0>;
+ vled-supply = <&ps_als_reg>;
+ };
+ };
+
spi_1: spi@1393 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
--
1.7.9.5
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[PATCH 0/3] ARM: dts: add device data for exynos4412-trats2
This patchset add some device node for exynos4412-trats2. It is based on v3.15-next/dt-samsung-2 branch. exynos4412-trats2.dts - Fix incorrect compatible. Compatible of AK8975 are "ak8975" or "asahi-kasei,ak8975". - Add cm36651 light/proximity sensor device node. - Change gpio-key device node. fix incorrect gpio property, and then add "ok-key" node. Beomho Seo (3): ARM: dts: fix incorrect compatible for exynos4412 ARM: dts: add cm36651 light/proximity sensor node ARM: dts: fixed gpio key node for exynos4412 arch/arm/boot/dts/exynos4412-trats2.dts | 50 ++- 1 file changed, 43 insertions(+), 7 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] ARM: dts: fixed gpio key node for exynos4412
This patch fixed gpio key device node.
First, fix incorrect gpio property.
And then, add ok-key node where locate bottom center.
I have tested on exynos4412-trats2 board.
Signed-off-by: Beomho Seo
Signed-off-by: MyungJoo Ham
---
arch/arm/boot/dts/exynos4412-trats2.dts | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index c9f3c6e..cc96bee 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -87,18 +87,18 @@
compatible = "gpio-keys";
key-down {
- interrupt-parent = <&gpj1>;
- interrupts = <2 0>;
- gpios = <&gpj1 2 1>;
+ interrupt-parent = <&gpx3>;
+ interrupts = <3 0>;
+ gpios = <&gpx3 3 1>;
linux,code = <114>;
label = "volume down";
debounce-interval = <10>;
};
key-up {
- interrupt-parent = <&gpj1>;
- interrupts = <1 0>;
- gpios = <&gpj1 1 1>;
+ interrupt-parent = <&gpx2>;
+ interrupts = <2 0>;
+ gpios = <&gpx2 2 1>;
linux,code = <115>;
label = "volume up";
debounce-interval = <10>;
@@ -113,6 +113,16 @@
debounce-interval = <10>;
gpio-key,wakeup;
};
+
+ key-ok {
+ interrupt-parent = <&gpx0>;
+ interrupts = <1 0>;
+ gpios = <&gpx0 1 1>;
+ linux,code = <139>;
+ label = "ok";
+ debounce-inteval = <10>;
+ gpio-key,wakeup;
+ };
};
adc: adc@126C {
--
1.7.9.5
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[PATCH 1/3] ARM: dts: fix incorrect compatible for exynos4412
This patch fixed incorrect compatible for ak8975 magnetic sensor.
ak8975 magnetic sensor use compatible "ak8975" or "asahi-kasei,ak8975".
Signed-off-by: Beomho Seo
Signed-off-by: MyungJoo Ham
---
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 3228506..42418e2 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -494,7 +494,7 @@
status = "okay";
ak8975@0c {
- compatible = "ak,ak8975";
+ compatible = "ak8975";
reg = <0x0c>;
gpios = <&gpj0 7 0>;
};
--
1.7.9.5
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