Re: [PATCH 1/2] usb: ehci-exynos: Return immediately from suspend if ehci_suspend fails

[Jingoo Han]

On Wednesday, April 09, 2014 1:01 PM, Vivek Gautam wrote:
> 
> Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race'
> adds a check for possible race between suspend and wakeup interrupt,
> and thereby it returns -EBUSY as error code if there's a wakeup
> interrupt.
> So the platform host controller should not proceed further with
> its suspend callback, rather should return immediately to avoid
> powering down the essential things, like phy.
> 
> Signed-off-by: Vivek Gautam 
> Cc: Alan Stern 
> Cc: Jingoo Han 

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
> 
> Based on 'usb-next' branch of Greg's usb tree.
> 
>  drivers/usb/host/ehci-exynos.c |4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
> index d1d8c47..a4550eb 100644
> --- a/drivers/usb/host/ehci-exynos.c
> +++ b/drivers/usb/host/ehci-exynos.c
> @@ -212,6 +212,8 @@ static int exynos_ehci_suspend(struct device *dev)
>   int rc;
> 
>   rc = ehci_suspend(hcd, do_wakeup);
> + if (rc)
> + return rc;
> 
>   if (exynos_ehci->otg)
>   exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
> @@ -221,7 +223,7 @@ static int exynos_ehci_suspend(struct device *dev)
> 
>   clk_disable_unprepare(exynos_ehci->clk);
> 
> - return rc;
> + return 0;
>  }
> 
>  static int exynos_ehci_resume(struct device *dev)
> --
> 1.7.10.4

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[PATCH 2/2] usb: ehci-platform: Return immediately from suspend if ehci_suspend fails

[Vivek Gautam]

Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race'
adds a check for possible race between suspend and wakeup interrupt,
and thereby it returns -EBUSY as error code if there's a wakeup
interrupt.
So the platform host controller should not proceed further with
its suspend callback, rather should return immediately to avoid
powering down the essential things, like phy.

Signed-off-by: Vivek Gautam 
Cc: Alan Stern 
Cc: Hauke Mehrtens 
Cc: Hans de Goede 
---

Based on 'usb-next' branch of Greg's usb tree.

 drivers/usb/host/ehci-platform.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index b3a0e11..60d3d1a 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -303,11 +303,13 @@ static int ehci_platform_suspend(struct device *dev)
int ret;
 
ret = ehci_suspend(hcd, do_wakeup);
+   if (ret)
+   return ret;
 
if (pdata->power_suspend)
pdata->power_suspend(pdev);
 
-   return ret;
+   return 0;
 }
 
 static int ehci_platform_resume(struct device *dev)
-- 
1.7.10.4

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[PATCH 1/2] usb: ehci-exynos: Return immediately from suspend if ehci_suspend fails

[Vivek Gautam]

Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race'
adds a check for possible race between suspend and wakeup interrupt,
and thereby it returns -EBUSY as error code if there's a wakeup
interrupt.
So the platform host controller should not proceed further with
its suspend callback, rather should return immediately to avoid
powering down the essential things, like phy.

Signed-off-by: Vivek Gautam 
Cc: Alan Stern 
Cc: Jingoo Han 
---

Based on 'usb-next' branch of Greg's usb tree.

 drivers/usb/host/ehci-exynos.c |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index d1d8c47..a4550eb 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -212,6 +212,8 @@ static int exynos_ehci_suspend(struct device *dev)
int rc;
 
rc = ehci_suspend(hcd, do_wakeup);
+   if (rc)
+   return rc;
 
if (exynos_ehci->otg)
exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
@@ -221,7 +223,7 @@ static int exynos_ehci_suspend(struct device *dev)
 
clk_disable_unprepare(exynos_ehci->clk);
 
-   return rc;
+   return 0;
 }
 
 static int exynos_ehci_resume(struct device *dev)
-- 
1.7.10.4

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Re: [PATCH RESEND] usb: ohci-exynos: Remove locks for 'ohci' in suspend callback

[Jingoo Han]

On Tuesday, April 08, 2014 11:41 PM, Vivek Gautam wrote:
> 
> Patch : 14982e3 USB: OHCI: Properly handle ohci-exynos suspend
> has already removed 'ohci_hcd' settings from exynos glue layer
> as a part of streamlining the ohci controller's suspend.
> So we don't need the locks for 'ohci_hcd' anymore.

Right, this spin_lock/unlock is unnecessary, because it is
already used in ohci_suspend().

Acked-by: Jingoo Han 

Best regards,
Jingoo Han

> 
> Signed-off-by: Vivek Gautam 
> Cc: Manjunath Goudar 
> Cc: Alan Stern 
> ---
>  drivers/usb/host/ohci-exynos.c |6 --
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
> index 68588d8..9cf80cb 100644
> --- a/drivers/usb/host/ohci-exynos.c
> +++ b/drivers/usb/host/ohci-exynos.c
> @@ -190,17 +190,13 @@ static int exynos_ohci_suspend(struct device *dev)
>  {
>   struct usb_hcd *hcd = dev_get_drvdata(dev);
>   struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
> - struct ohci_hcd *ohci = hcd_to_ohci(hcd);
>   struct platform_device *pdev = to_platform_device(dev);
>   bool do_wakeup = device_may_wakeup(dev);
> - unsigned long flags;
>   int rc = ohci_suspend(hcd, do_wakeup);
> 
>   if (rc)
>   return rc;
> 
> - spin_lock_irqsave(&ohci->lock, flags);
> -
>   if (exynos_ohci->otg)
>   exynos_ohci->otg->set_host(exynos_ohci->otg, &hcd->self);
> 
> @@ -208,8 +204,6 @@ static int exynos_ohci_suspend(struct device *dev)
> 
>   clk_disable_unprepare(exynos_ohci->clk);
> 
> - spin_unlock_irqrestore(&ohci->lock, flags);
> -
>   return 0;
>  }
> 
> --
> 1.7.10.4

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Re: [PATCH V3 15/17] ARM: exynos: cpuidle: Disable cpuidle for 5440

[Nicolas Pitre]

On Tue, 8 Apr 2014, Daniel Lezcano wrote:

> On 04/08/2014 02:51 PM, Amit Kucheria wrote:
> > On Tue, Apr 8, 2014 at 5:49 PM, Daniel Lezcano
> > mailto:daniel.lezc...@linaro.org>> wrote:
> >
> > There is no point to register the cpuidle driver for the 5440 as it
> > has only
> > one WFI state which is the default idle function when the cpuidle
> > driver is
> > disabled.
> >
> > By disabling cpuidle we prevent to enter to the governor computation for
> > nothing, thus saving a lot of processing time.
> >
> > The only drawback is the statistic via sysfs on this state which is
> > lost but
> > it is meaningless and it could be retrieved from the ftrace easily.
> >
> >
> > So for the future, you'll only merge platform drivers that enable
> > something more than WFI?
> 
> Well, I already picked up a driver with only WFI because I knew the next idle
> states were in preparation. But adding a cpuidle driver just for WFI is no
> sense and if, for a reason I missed, it is really needed, I guess a generic
> WFI cpuidle driver for all platforms would be make much more sense.

Better relegate WFI-only configurations to arch_cpu_idle().


Nicolas
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Re: AFTR does not work on arndale 5250

[Daniel Lezcano]

On 04/08/2014 06:13 PM, Tomasz Figa wrote:

Hi Daniel, Vikas, Chander,

On 08.04.2014 16:27, Daniel Lezcano wrote:

On 04/08/2014 03:32 PM, Vikas Sajjan wrote:

  Hi Daniel,

  I checked AFTR on v3.14 (
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/log/?id=refs/tags/v3.14)


  on exynos5250 based chromebook (exynos5250-snow.dtb)

I am able to hotplug CPU1  (echo 0 >
/sys/devices/system/cpu/cpu1/online).
I can see, it enters exynos4_enter_core0_aftr() when I hotplug CPU1.


Hi,

thanks a lot for your help.

I reproduced it on my arndale board with linux-samsung/for-next and on
v3.14.

Used the exynos_defconfig, enabled cpuidle and used
exynos5250-arndale.dtb.



You should compare your bootloader versions as this is one of the
aspects that can break AFTR support as it relies on kind of ABI between
bootloader and kernel.


U-Boot 2013.01.-rc1 (Jul 10 2013 - 15:16:09) for ARNDALE5250
gcc-4.7 (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3
GNU ld (GNU Binutils for Ubuntu) 2.23.2



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[PATCH] arm: exynos: generalize power register address calculation

[Chander Kashyap]

Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap 
---
 arch/arm/mach-exynos/hotplug.c  |   10 +++---
 arch/arm/mach-exynos/platsmp.c  |   13 -
 arch/arm/mach-exynos/regs-pmu.h |9 +++--
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..460aec0 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -92,11 +92,15 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int cpunr;
+
+   cpunr = phys_cpu & 0xF00 ? (4 + phys_cpu & 0xFF) : phys_cpu & 0xFF;
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (cpu)
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr));
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 8ea02f6..e694bdf 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -92,6 +92,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
+   unsigned int cpunr;
 
/*
 * Set synchronisation state between this boot processor
@@ -109,14 +110,16 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+   cpunr = phys_cpu & 0xF00 ? (4 + phys_cpu & 0xFF) : phys_cpu & 0xFF;
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
+   & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(cpunr));
 
timeout = 10;
 
-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   /* wait max 10 ms until secondary cpu is on */
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -125,7 +128,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
}
 
if (timeout == 0) {
-   printk(KERN_ERR "cpu1 power enable failed");
+   pr_err("cpu%x power enable failed", cpu);
spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 7c029ce..16e17e4 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -104,8 +104,13 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * _cpunr)
+#define S5P_ARM_CORE_STATUS(_cpunr)\
+   (S5P_ARM_CORE0_STATUS + 0x80 * _cpunr)
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
-- 
1.7.9.5

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Re: AFTR does not work on arndale 5250

[Tomasz Figa]

Hi Daniel, Vikas, Chander,

On 08.04.2014 16:27, Daniel Lezcano wrote:

On 04/08/2014 03:32 PM, Vikas Sajjan wrote:

  Hi Daniel,

  I checked AFTR on v3.14 (
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/log/?id=refs/tags/v3.14)

  on exynos5250 based chromebook (exynos5250-snow.dtb)

I am able to hotplug CPU1  (echo 0 >
/sys/devices/system/cpu/cpu1/online).
I can see, it enters exynos4_enter_core0_aftr() when I hotplug CPU1.


Hi,

thanks a lot for your help.

I reproduced it on my arndale board with linux-samsung/for-next and on
v3.14.

Used the exynos_defconfig, enabled cpuidle and used exynos5250-arndale.dtb.



You should compare your bootloader versions as this is one of the 
aspects that can break AFTR support as it relies on kind of ABI between 
bootloader and kernel.


Bets regards,
Tomasz
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Re: [PATCH 05/10] ARM: EXYNOS: Move "regs-pmu" header inclusion in common.h

[Tomasz Figa]

Hi Pankaj,

On 02.04.2014 09:50, Pankaj Dubey wrote:

There are many machine files under "mach-exynos" including "regs-pmu.h"
as well as "common.h", so better we move this header inclusion in common.h.

Signed-off-by: Pankaj Dubey 
---
  arch/arm/mach-exynos/common.h  |1 +
  arch/arm/mach-exynos/cpuidle.c |1 -
  arch/arm/mach-exynos/exynos.c  |1 -
  arch/arm/mach-exynos/hotplug.c |1 -
  arch/arm/mach-exynos/platsmp.c |1 -
  arch/arm/mach-exynos/pm.c  |1 -
  arch/arm/mach-exynos/pmu.c |1 -
  7 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 277a83e..ff28334 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -14,6 +14,7 @@

  #include 
  #include 
+#include "regs-pmu.h"

  void exynos_init_io(void);
  void exynos_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index b530231..b9dd8c3 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -29,7 +29,6 @@
  #include 

  #include "common.h"
-#include "regs-pmu.h"

  #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 57bd1cd..a5e1349 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -30,7 +30,6 @@

  #include "common.h"
  #include "mfc.h"
-#include "regs-pmu.h"
  #include "regs-sys.h"

  #define L2_AUX_VAL 0x7C470001
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..33db6ee 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -22,7 +22,6 @@
  #include 

  #include "common.h"
-#include "regs-pmu.h"

  static inline void cpu_enter_lowpower_a9(void)
  {
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index d8d1555..3ebb03f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -29,7 +29,6 @@
  #include 

  #include "common.h"
-#include "regs-pmu.h"

  extern void exynos4_secondary_startup(void);

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 723c988..875151f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -34,7 +34,6 @@
  #include 

  #include "common.h"
-#include "regs-pmu.h"
  #include "regs-sys.h"

  /**
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce1..fb44352 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -16,7 +16,6 @@
  #include 

  #include "common.h"
-#include "regs-pmu.h"

  static const struct exynos_pmu_conf *exynos_pmu_config;




I don't think this is a good idea. It adds hidden indirect dependencies 
between source files and thus reduces maintainability and readability. 
In addition it causes the file to be included even by files that don't 
need it.


Best regards,
Tomasz
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Re: [PATCH 01/10] ARM: EXYNOS: Cleanup "mach-exynos/common.h" file

[Tomasz Figa]

Hi Pankaj,

On 02.04.2014 09:50, Pankaj Dubey wrote:

Remove unused declarations from "mach-exynos/common.h"

Signed-off-by: Pankaj Dubey 
---
  arch/arm/mach-exynos/common.h |3 ---
  1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..277a83e 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,9 +15,6 @@
  #include 
  #include 

-void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
-
-struct map_desc;
  void exynos_init_io(void);
  void exynos_restart(enum reboot_mode mode, const char *cmd);
  void exynos_cpuidle_init(void);



You could also drop a bit more. From the context above I can see that at 
least exynos_restart() and exynos_init_io() are never used outside of 
files they are defined in, so they too could be dropped from this 
header. Looking at rest of the header, there seems to be a lot of 
similar definitions. If cleaning up the header anyway, could you take 
care of them as well?


Best regards,
Tomasz
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Re: [PATCH 4/4] Revert "drm/exynos: add mout_hdmi clock in hdmi driver to change parent"

[Tomasz Figa]

Hi Tomasz,

On 04.04.2014 16:53, Tomasz Stanislawski wrote:

This reverts commit 59956d35a8618235ea715280b49447bb36f2c975.



Probably a reason why this commit is being reverted would be a good idea.


Signed-off-by: Tomasz Stanislawski 
---
  drivers/gpu/drm/exynos/exynos_hdmi.c |   14 --
  1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 9a6d652..8ebb4bf 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -75,7 +75,6 @@ struct hdmi_resources {
struct clk  *sclk_pixel;
struct clk  *sclk_hdmiphy;
struct clk  *hdmiphy;
-   struct clk  *mout_hdmi;
struct regulator_bulk_data  *regul_bulk;
int regul_count;
  };
@@ -1282,7 +1281,7 @@ static void hdmi_v13_mode_apply(struct hdmi_context 
*hdata)
}

clk_disable_unprepare(hdata->res.sclk_hdmi);
-   clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
+   clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
clk_prepare_enable(hdata->res.sclk_hdmi);

/* enable HDMI and timing generator */
@@ -1449,7 +1448,7 @@ static void hdmi_v14_mode_apply(struct hdmi_context 
*hdata)
}

clk_disable_unprepare(hdata->res.sclk_hdmi);
-   clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
+   clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
clk_prepare_enable(hdata->res.sclk_hdmi);

/* enable HDMI and timing generator */
@@ -1475,7 +1474,7 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
u32 reg;

clk_disable_unprepare(hdata->res.sclk_hdmi);
-   clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
+   clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
clk_prepare_enable(hdata->res.sclk_hdmi);

/* operation mode */
@@ -1982,13 +1981,8 @@ static int hdmi_resources_init(struct hdmi_context 
*hdata)
DRM_ERROR("failed to get clock 'hdmiphy'\n");
goto fail;
}
-   res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
-   if (IS_ERR(res->mout_hdmi)) {
-   DRM_ERROR("failed to get clock 'mout_hdmi'\n");
-   goto fail;
-   }

-   clk_set_parent(res->mout_hdmi, res->sclk_pixel);
+   clk_set_parent(res->sclk_hdmi, res->sclk_pixel);

res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
sizeof(res->regul_bulk[0]), GFP_KERNEL);



Otherwise looks fine and will apply after all its dependencies are 
agreed upon.


Best regards,
Tomasz
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Re: [PATCH 3/4] clk: exynos4: enable clk_set_parent() propagation for sclk_hdmi and sclk_mixer clocks

[Tomasz Figa]

On 04.04.2014 16:53, Tomasz Stanislawski wrote:

This patch enables clk_set_parent() propagation for clocks used
by s5p-tv and exynos-drm drivers.

Signed-off-by: Tomasz Stanislawski 
---
  drivers/clk/samsung/clk-exynos4.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c 
b/drivers/clk/samsung/clk-exynos4.c
index 528f8eb..87b8264 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -680,7 +680,8 @@ static struct samsung_gate_clock exynos4_gate_clks[] 
__initdata = {
 * the device name and clock alias names specified below for some
 * of the clocks can be removed.
 */
-   GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+   GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0,
+   CLK_SET_PARENT_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
0),
GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
@@ -880,7 +881,8 @@ static struct samsung_gate_clock exynos4210_gate_clks[] 
__initdata = {
E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
-   GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+   GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4,
+   CLK_SET_PARENT_PARENT, 0),
GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
0, 0),



Looks fine, but since it depends on patch 1/4, which needs to be 
discussed a bit, I'll hold on with applying it for now.


Best regards,
Tomasz
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Re: [PATCH 2/4] clk: exynos4: export sclk_hdmiphy clock

[Tomasz Figa]

Hi Tomasz,

On 04.04.2014 16:53, Tomasz Stanislawski wrote:

Export sclk_hdmiphy clock to be usable from DT.

Signed-off-by: Tomasz Stanislawski 
---
  drivers/clk/samsung/clk-exynos4.c   |2 +-
  include/dt-bindings/clock/exynos4.h |1 +
  2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c 
b/drivers/clk/samsung/clk-exynos4.c
index b4f9672..528f8eb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock 
exynos4_fixed_rate_ext_clks[] __initdata
  /* fixed rate clocks generated inside the soc */
  static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = 
{
FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 2400),
-   FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2700),
+   FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 2700),
FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 4800),
  };

diff --git a/include/dt-bindings/clock/exynos4.h 
b/include/dt-bindings/clock/exynos4.h
index 75aff33..0e245eb 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -33,6 +33,7 @@
  #define CLK_MOUT_MPLL_USER_C  18 /* Exynos4x12 only */
  #define CLK_MOUT_CORE 19
  #define CLK_MOUT_APLL 20
+#define CLK_SCLK_HDMIPHY   22

  /* gate for special clocks (sclk) */
  #define CLK_SCLK_FIMC0128



I believe this clock should be properly abstracted as an output of HDMI 
PHY, but I don't see any way to do this with existing infrastructure, so 
probably for now such workaround is fine.


Will apply, if nobody opposes.

Best regards,
Tomasz
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Re: [PATCH 1/4] clk: propagate parent change up one level

[Tomasz Figa]

Hi,

On 04.04.2014 16:53, Tomasz Stanislawski wrote:

This patch adds support for propagation of setup of clock's parent one level
up.

This feature is helpful when a driver changes topology of its clocks using
clk_set_parent().  The problem occurs when on one platform/SoC driver's clock
is located at MUX output but on the other platform/SoC there is a gated proxy
clock between the MUX and driver's clock.  In such a case, driver's code has to
be modified to use one clock for enabling and the other clock for setup of a
parent.

The code updates are avoided by propagating setup of a parent up one level.

Additionally, this patch adds CLK_SET_PARENT_PARENT (sorry for naming) flag to
inform clk-core that clk_set_parent() should be propagated.

Signed-off-by: Tomasz Stanislawski 
---
  drivers/clk/clk.c|6 ++
  include/linux/clk-provider.h |1 +
  2 files changed, 7 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index dff0373..53bbfda 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1737,6 +1737,12 @@ int clk_set_parent(struct clk *clk, struct clk *parent)

/* try finding the new parent index */
if (parent) {
+   if ((clk->flags & CLK_SET_PARENT_PARENT)
+   && clk->num_parents == 1) {
+   ret = clk_set_parent(clk->parent, parent);
+   goto out;
+   }
+
p_index = clk_fetch_parent_index(clk, parent);
p_rate = parent->rate;
if (p_index < 0) {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5119174..daa0b03 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -30,6 +30,7 @@
  #define CLK_GET_RATE_NOCACHE  BIT(6) /* do not use the cached clk rate */
  #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy 
*/
+#define CLK_SET_PARENT_PARENT  BIT(9) /* propagate parent change up one level 
*/

  struct clk_hw;
  struct dentry;



This would be very useful, at least on Exynos platforms, with 
mux-div-gate clock paths. PARENT_PARENT sounds a bit funny, though.


Reviewed-by: Tomasz Figa 

Best regards,
Tomasz
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[PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver

[Vivek Gautam]

Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Thereby, removing old phy-samsung-usb3 driver and related code
used untill now which was based on usb/phy framework.

Signed-off-by: Vivek Gautam 
---
 .../devicetree/bindings/phy/samsung-phy.txt|   42 ++
 drivers/phy/Kconfig|   11 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-exynos5-usbdrd.c   |  668 
 4 files changed, 722 insertions(+)
 create mode 100644 drivers/phy/phy-exynos5-usbdrd.c

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt 
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 28f9edb..6d99ba9 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -74,3 +74,45 @@ phy-consumer@1234 {
 
 Refer to DT bindings documentation of particular PHY consumer devices for more
 information about required PHYs and the way of specification.
+
+Samsung Exynos5 SoC series USB DRD PHY controller
+--
+
+Required properties:
+- compatible : Should be set to one of the following supported values:
+   - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
+   - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+- reg : Register offset and length of USB DRD PHY register set;
+- clocks: Clock IDs array as required by the controller
+- clock-names: names of clocks correseponding to IDs in the clock property;
+  Required clocks:
+   - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
+  used for register access.
+   - ref: PHY's reference clock (usually crystal clock), associated by
+  phy name, used to determine bit values for clock settings
+  register.
+   Additional clock required for Exynos5420:
+   - usb30_sclk_100m: Additional special clock used for PHY operation
+  depicted as 'sclk_usbphy30' in CMU of Exynos5420.
+- samsung,syscon-phandle: phandle for syscon interface, which is used to
+ control pmu registers for power isolation.
+- samsung,pmu-offset: phy power control register offset to 
pmu-system-controller
+ base.
+- #phy-cells : from the generic PHY bindings, must be 1;
+
+For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
+compatible PHYs, the second cell in the PHY specifier identifies the
+PHY id, which is interpreted as follows:
+  0 - UTMI+ type phy,
+  1 - PIPE3 type phy,
+
+Example:
+   usb3_phy: usbphy@1210 {
+   compatible = "samsung,exynos5250-usbdrd-phy";
+   reg = <0x1210 0x100>;
+   clocks = <&clock 286>, <&clock 1>;
+   clock-names = "phy", "usb3phy_refclk";
+   samsung,syscon-phandle = <&pmu_syscon>;
+   samsung,pmu-offset = <0x704>;
+   #phy-cells = <1>;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8d3c49c..d955a05 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -166,4 +166,15 @@ config PHY_XGENE
help
  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config PHY_EXYNOS5_USBDRD
+   tristate "Exynos5 SoC series USB DRD PHY driver"
+   depends on ARCH_EXYNOS5 && OF
+   depends on HAS_IOMEM
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Enable USB DRD PHY support for Exynos 5 SoC series.
+ This driver provides PHY interface for USB 3.0 DRD controller
+ present on Exynos5 SoC series.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2faf78e..31baa0c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4X12_USB2)  += phy-exynos4x12-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
new file mode 100644
index 000..ff54a7c
--- /dev/null
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -0,0 +1,668 @@
+/*
+ * Samsung EXYNOS5 SoC series USB DRD PHY driver
+ *
+ * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Vivek Gautam 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#

[PATCH V4 3/5] dt: exynos5420: Enable support for DWC3 controller

[Vivek Gautam]

Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.

Signed-off-by: Vivek Gautam 
---
 arch/arm/boot/dts/exynos5420.dtsi |   34 ++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index a6efb52..20c2d0b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -653,6 +653,23 @@
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
 
+   usb@1200 {
+   compatible = "samsung,exynos5250-dwusb3";
+   clocks = <&clock 366>;
+   clock-names = "usbdrd30";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   dwc3 {
+   compatible = "synopsys,dwc3";
+   reg = <0x1200 0x1>;
+   interrupts = <0 72 0>;
+   phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+   phy-names = "usb2-phy", "usb3-phy";
+   };
+   };
+
usbdrd_phy0: phy@1210 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x1210 0x100>;
@@ -663,6 +680,23 @@
#phy-cells = <1>;
};
 
+   usb@1240 {
+   compatible = "samsung,exynos5250-dwusb3";
+   clocks = <&clock 367>;
+   clock-names = "usbdrd30";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   dwc3 {
+   compatible = "synopsys,dwc3";
+   reg = <0x1240 0x1>;
+   interrupts = <0 73 0>;
+   phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+   phy-names = "usb2-phy", "usb3-phy";
+   };
+   };
+
usbdrd_phy1: phy@1250 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x1250 0x100>;
-- 
1.7.10.4

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[PATCH v4 2/5] dt: exynos5420: Enable support for USB 3.0 PHY controller

[Vivek Gautam]

Add device tree nodes for USB 3.0 PHY present alongwith
USB 3.0 controller Exynos 5420 SoC. This phy driver is
based on generic phy framework.

Signed-off-by: Vivek Gautam 
---
 arch/arm/boot/dts/exynos5420.dtsi |   20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 8db792b..a6efb52 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -652,4 +652,24 @@
clocks = <&clock 319>, <&clock 318>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
};
+
+   usbdrd_phy0: phy@1210 {
+   compatible = "samsung,exynos5420-usbdrd-phy";
+   reg = <0x1210 0x100>;
+   clocks = <&clock 366>, <&clock 1>, <&clock 152>;
+   clock-names = "phy", "ref", "usb30_sclk_100m";
+   samsung,syscon-phandle = <&pmu_system_controller>;
+   samsung,pmu-offset = <0x704>;
+   #phy-cells = <1>;
+   };
+
+   usbdrd_phy1: phy@1250 {
+   compatible = "samsung,exynos5420-usbdrd-phy";
+   reg = <0x1250 0x100>;
+   clocks = <&clock 367>, <&clock 1>, <&clock 153>;
+   clock-names = "phy", "ref", "usb30_sclk_100m";
+   samsung,syscon-phandle = <&pmu_system_controller>;
+   samsung,pmu-offset = <0x708>;
+   #phy-cells = <1>;
+   };
 };
-- 
1.7.10.4

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[PATCH RESEND] usb: ohci-exynos: Remove locks for 'ohci' in suspend callback

[Vivek Gautam]

Patch : 14982e3 USB: OHCI: Properly handle ohci-exynos suspend
has already removed 'ohci_hcd' settings from exynos glue layer
as a part of streamlining the ohci controller's suspend.
So we don't need the locks for 'ohci_hcd' anymore.

Signed-off-by: Vivek Gautam 
Cc: Manjunath Goudar 
Cc: Alan Stern 
---
 drivers/usb/host/ohci-exynos.c |6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 68588d8..9cf80cb 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -190,17 +190,13 @@ static int exynos_ohci_suspend(struct device *dev)
 {
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
-   struct ohci_hcd *ohci = hcd_to_ohci(hcd);
struct platform_device *pdev = to_platform_device(dev);
bool do_wakeup = device_may_wakeup(dev);
-   unsigned long flags;
int rc = ohci_suspend(hcd, do_wakeup);
 
if (rc)
return rc;
 
-   spin_lock_irqsave(&ohci->lock, flags);
-
if (exynos_ohci->otg)
exynos_ohci->otg->set_host(exynos_ohci->otg, &hcd->self);
 
@@ -208,8 +204,6 @@ static int exynos_ohci_suspend(struct device *dev)
 
clk_disable_unprepare(exynos_ohci->clk);
 
-   spin_unlock_irqrestore(&ohci->lock, flags);
-
return 0;
 }
 
-- 
1.7.10.4

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[PATCH V4 4/5] dt: exynos5250: Enable support for generic USB DRD phy

[Vivek Gautam]

Add device tree node for new usbdrd-phy driver, which
is based on generic phy framework.

Signed-off-by: Vivek Gautam 
---
 arch/arm/boot/dts/exynos5250.dtsi |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index b7dec41..92c6fcd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -530,6 +530,16 @@
};
};
 
+   usbdrd_phy: phy@1210 {
+   compatible = "samsung,exynos5250-usbdrd-phy";
+   reg = <0x1210 0x100>;
+   clocks = <&clock 286>, <&clock 1>;
+   clock-names = "phy", "ref";
+   samsung,syscon-phandle = <&pmu_system_controller>;
+   samsung,pmu-offset = <0x704>;
+   #phy-cells = <1>;
+   };
+
usb@1211 {
compatible = "samsung,exynos4210-ehci";
reg = <0x1211 0x100>;
-- 
1.7.10.4

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[PATCH V4 5/5] usb-phy: samsung-usb3: Remove older phy-samsung-usb3 driver

[Vivek Gautam]

Removing this older USB 3.0 DRD controller PHY driver, since
a new driver based on generic phy framework is now available.

Also removing the dt node for older driver from Exynos5250
device tree and updating the dt node for DWC3 controller.

Signed-off-by: Vivek Gautam 
---

NOTE: This patch should be merged only when the new USB 3.0
DRD phy controller driver is available in the tree from the
patches:
phy: Add new Exynos5 USB 3.0 PHY driver; and
dt: exynos5250: Enable support for generic USB DRD phy

 arch/arm/boot/dts/exynos5250.dtsi  |   17 +-
 drivers/usb/phy/phy-samsung-usb.h  |   83 -
 drivers/usb/phy/phy-samsung-usb3.c |  350 
 3 files changed, 2 insertions(+), 448 deletions(-)
 delete mode 100644 drivers/usb/phy/phy-samsung-usb3.c

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 92c6fcd..1cb1e91 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -512,21 +512,8 @@
compatible = "synopsys,dwc3";
reg = <0x1200 0x1>;
interrupts = <0 72 0>;
-   usb-phy = <&usb2_phy &usb3_phy>;
-   };
-   };
-
-   usb3_phy: usbphy@1210 {
-   compatible = "samsung,exynos5250-usb3phy";
-   reg = <0x1210 0x100>;
-   clocks = <&clock 1>, <&clock 286>;
-   clock-names = "ext_xtal", "usbdrd30";
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges;
-
-   usbphy-sys {
-   reg = <0x10040704 0x8>;
+   phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+   phy-names = "usb2-phy", "usb3-phy";
};
};
 
diff --git a/drivers/usb/phy/phy-samsung-usb.h 
b/drivers/usb/phy/phy-samsung-usb.h
index 68771bf..ced8b65 100644
--- a/drivers/usb/phy/phy-samsung-usb.h
+++ b/drivers/usb/phy/phy-samsung-usb.h
@@ -155,86 +155,6 @@
 
 #define EXYNOS5_PHY_OTG_TUNE   (0x40)
 
-/* EXYNOS5: USB 3.0 DRD */
-#define EXYNOS5_DRD_LINKSYSTEM (0x04)
-
-#define LINKSYSTEM_FLADJ_MASK  (0x3f << 1)
-#define LINKSYSTEM_FLADJ(_x)   ((_x) << 1)
-#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 << 27)
-
-#define EXYNOS5_DRD_PHYUTMI(0x08)
-
-#define PHYUTMI_OTGDISABLE (0x1 << 6)
-#define PHYUTMI_FORCESUSPEND   (0x1 << 1)
-#define PHYUTMI_FORCESLEEP (0x1 << 0)
-
-#define EXYNOS5_DRD_PHYPIPE(0x0c)
-
-#define EXYNOS5_DRD_PHYCLKRST  (0x10)
-
-#define PHYCLKRST_SSC_REFCLKSEL_MASK   (0xff << 23)
-#define PHYCLKRST_SSC_REFCLKSEL(_x)((_x) << 23)
-
-#define PHYCLKRST_SSC_RANGE_MASK   (0x03 << 21)
-#define PHYCLKRST_SSC_RANGE(_x)((_x) << 21)
-
-#define PHYCLKRST_SSC_EN   (0x1 << 20)
-#define PHYCLKRST_REF_SSP_EN   (0x1 << 19)
-#define PHYCLKRST_REF_CLKDIV2  (0x1 << 18)
-
-#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF   (0x19 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF  (0x02 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF(0x68 << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF(0x7d << 11)
-#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
-
-#define PHYCLKRST_FSEL_MASK(0x3f << 5)
-#define PHYCLKRST_FSEL(_x) ((_x) << 5)
-#define PHYCLKRST_FSEL_PAD_100MHZ  (0x27 << 5)
-#define PHYCLKRST_FSEL_PAD_24MHZ   (0x2a << 5)
-#define PHYCLKRST_FSEL_PAD_20MHZ   (0x31 << 5)
-#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
-
-#define PHYCLKRST_RETENABLEN   (0x1 << 4)
-
-#define PHYCLKRST_REFCLKSEL_MASK   (0x03 << 2)
-#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
-#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
-
-#define PHYCLKRST_PORTRESET(0x1 << 1)
-#define PHYCLKRST_COMMONONN(0x1 << 0)
-
-#define EXYNOS5_DRD_PHYREG0(0x14)
-#define EXYNOS5_DRD_PHYREG1(0x18)
-
-#define EXYNOS5_DRD_PHYPARAM0  (0x1c)
-
-#define PHYPARAM0_REF_USE_PAD  (0x1 << 31)
-#define PHYPARAM0_REF_LOSLEVEL_MASK(0x1f << 26)
-#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
-
-#define EXYNOS5_DRD_PHYPARAM1  (0x20)
-
-#define PHYPARAM1_PCS_TXDEEMPH_MASK(0x1f << 0)
-#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
-
-#define EXYNOS5_DRD_PHYTERM(0x24)
-
-#define EXYNOS5_DRD_PHYTEST(0x28)
-
-#define PHYTEST_POWERDOWN_SSP  (0x1 << 3)
-#define PHYTEST_POWERDOWN_HSP 

[PATCHv2 0/3] phy: Add exynos-simple-phy driver

[Tomasz Stanislawski]

Hello everyone,

The Samsung SoCs from Exynos family are enhanced with a bunch of devices that
provide functionality of a physical layer for interfaces like USB, HDMI, SATA,
etc. They are controlled by a simple interface, often a single bit that enables
and/or resets the physical layer.

An IP driver should to control such a controller in an abstract manner.
Therefore, such 'enablers' were implemented as clocks in older versions of
Linux kernel.  With the dawn of PHY subsystems, PHYs become a natural way of
exporting the 'enabler' functionality to drivers.  However, there is an
unexpected consequence. Some of those 1-bit PHYs were implemented as separate
drivers.  This means that one has to create a struct device, struct phy, its
phy provider and 100-150 lines of driver code to basically set one bit.

The DP phy driver is a good example:
https://lkml.org/lkml/2013/7/18/53

And simple-phy RFC (shares only driver code but not other resources):
https://lkml.org/lkml/2013/10/21/313

To avoid waste of resources I propose to create all such 1-bit phys from Exynos
SoC using a single device, driver and phy provider.

This patchset contains a proposed solution.

All comment are welcome.

Hopefully in future the functionality introduced by this patch may be merged
into a larger Power Management Unit (PMU) gluer driver.  On Samsusng SoC , the
PMU part contains a number of register barely linked to power management (like
clock gating, clock dividers, CPU resetting, etc.).  It may be tempting to
create a hybrid driver that export clocks/phys/etc that are controlled by PMU
unit.

Alternative solutions might be:
* exporting a regmap to the IP driver and allow the driver to control the PHY 
layer
  like in the patch:
  http://thread.gmane.org/gmane.linux.kernel.samsung-soc/28617/focus=28648

* create a dedicated power domain for hdmiphy

Regards,
Tomasz Stanislawski

Changelog:
v2:
* rename to exynos-simple-phy
* fix usage of devm_ioremap()
* add documentation for DT bindings
* add patches to client drivers

v1: initial version

Tomasz Stanislawski (3):
  phy: Add exynos-simple-phy driver
  drm: exynos: hdmi: use hdmiphy as PHY
  s5p-tv: hdmi: use hdmiphy as PHY

 .../devicetree/bindings/phy/samsung-phy.txt|   24 +++
 drivers/gpu/drm/exynos/exynos_hdmi.c   |   11 +-
 drivers/media/platform/s5p-tv/hdmi_drv.c   |   11 +-
 drivers/phy/Kconfig|5 +
 drivers/phy/Makefile   |1 +
 drivers/phy/exynos-simple-phy.c|  154 
 6 files changed, 196 insertions(+), 10 deletions(-)
 create mode 100644 drivers/phy/exynos-simple-phy.c

-- 
1.7.9.5

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[PATCHv2 1/3] phy: Add exynos-simple-phy driver

[Tomasz Stanislawski]

Add exynos-simple-phy driver to support a single register
PHY interfaces present on Exynos4 SoC.

Signed-off-by: Tomasz Stanislawski 
---
 .../devicetree/bindings/phy/samsung-phy.txt|   24 +++
 drivers/phy/Kconfig|5 +
 drivers/phy/Makefile   |1 +
 drivers/phy/exynos-simple-phy.c|  154 
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/phy/exynos-simple-phy.c

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt 
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index b422e38..f97c4c3 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -114,3 +114,27 @@ Example:
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
+
+Samsung S5P/EXYNOS SoC series SIMPLE PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+   - "samsung,exynos4210-simple-phy"
+   - "samsung,exynos4412-simple-phy"
+- reg : offset and length of the register set;
+- #phy-cells : from the generic phy bindings, must be 1;
+
+For "samsung,exynos4210-simple-phy" compatible PHYs the second cell in
+the PHY specifier identifies the PHY and its meaning is as follows:
+  0 - HDMI PHY,
+  1 - DAC PHY,
+  2 - ADC PHY,
+  3 - PCIE PHY.
+  4 - SATA PHY.
+
+For "samsung,exynos4412-simple-phy" compatible PHYs the second cell in
+the PHY specifier identifies the PHY and its meaning is as follows:
+  0 - HDMI PHY,
+  1 - ADC PHY,
+
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3bb05f1..65ab783 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -166,4 +166,9 @@ config PHY_XGENE
help
  This option enables support for APM X-Gene SoC multi-purpose PHY.
 
+config EXYNOS_SIMPLE_PHY
+   tristate "Exynos Simple PHY driver"
+   help
+ Support for 1-bit PHY controllers on SoCs from Exynos family.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2faf78e..88c5b60 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS4X12_USB2)  += phy-exynos4x12-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_EXYNOS_SIMPLE_PHY)+= exynos-simple-phy.o
diff --git a/drivers/phy/exynos-simple-phy.c b/drivers/phy/exynos-simple-phy.c
new file mode 100644
index 000..57ad338
--- /dev/null
+++ b/drivers/phy/exynos-simple-phy.c
@@ -0,0 +1,154 @@
+/*
+ * Exynos Simple PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tomasz Stanislawski 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define EXYNOS_PHY_ENABLE  (1 << 0)
+
+static int exynos_phy_power_on(struct phy *phy)
+{
+   void __iomem *reg = phy_get_drvdata(phy);
+   u32 val;
+
+   val = readl(reg);
+   val |= EXYNOS_PHY_ENABLE;
+   writel(val, reg);
+
+   return 0;
+}
+
+static int exynos_phy_power_off(struct phy *phy)
+{
+   void __iomem *reg = phy_get_drvdata(phy);
+   u32 val;
+
+   val = readl(reg);
+   val &= ~EXYNOS_PHY_ENABLE;
+   writel(val, reg);
+
+   return 0;
+}
+
+static struct phy_ops exynos_phy_ops = {
+   .power_on   = exynos_phy_power_on,
+   .power_off  = exynos_phy_power_off,
+   .owner  = THIS_MODULE,
+};
+
+static const u32 exynos4210_offsets[] = {
+   0x0700, /* HDMI_PHY */
+   0x070C, /* DAC_PHY */
+   0x0718, /* ADC_PHY */
+   0x071C, /* PCIE_PHY */
+   0x0720, /* SATA_PHY */
+   ~0, /* end mark */
+};
+
+static const u32 exynos4412_offsets[] = {
+   0x0700, /* HDMI_PHY */
+   0x0718, /* ADC_PHY */
+   ~0, /* end mark */
+};
+
+static const struct of_device_id exynos_phy_of_match[] = {
+   { .compatible = "samsung,exynos4210-simple-phy",
+ .data = exynos4210_offsets},
+   { .compatible = "samsung,exynos4412-simple-phy",
+ .data = exynos4412_offsets},
+   { },
+};
+MODULE_DEVICE_TABLE(of, exynos_phy_of_match);
+
+static struct phy *exynos_phy_xlate(struct device *dev,
+   struct of_phandle_args *args)
+{
+   struct phy **phys = dev_get_drvdata(dev);
+   int index = args->args[0];
+   int i;
+
+   /* verify if index is valid */
+   for (i = 0; i <= index; ++i)
+   if (!phys[i])
+   return ERR_PTR(-ENODEV);
+
+   return phys[index];
+}
+
+static int exynos_phy_

[PATCHv2 2/3] drm: exynos: hdmi: use hdmiphy as PHY

[Tomasz Stanislawski]

The HDMIPHY (physical interface) is controlled by a single
bit in a power controller's regiter. It was implemented
as clock. It was a simple but effective hack.

This patch makes HDMI driver to control HDMIPHY via PHY interface.

Signed-off-by: Tomasz Stanislawski 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c |   11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 9a6d652..ef1cdd0 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -74,8 +75,8 @@ struct hdmi_resources {
struct clk  *sclk_hdmi;
struct clk  *sclk_pixel;
struct clk  *sclk_hdmiphy;
-   struct clk  *hdmiphy;
struct clk  *mout_hdmi;
+   struct phy  *hdmiphy;
struct regulator_bulk_data  *regul_bulk;
int regul_count;
 };
@@ -1854,7 +1855,7 @@ static void hdmi_poweron(struct exynos_drm_display 
*display)
if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
DRM_DEBUG_KMS("failed to enable regulator bulk\n");
 
-   clk_prepare_enable(res->hdmiphy);
+   phy_power_on(res->hdmiphy);
clk_prepare_enable(res->hdmi);
clk_prepare_enable(res->sclk_hdmi);
 
@@ -1881,7 +1882,7 @@ static void hdmi_poweroff(struct exynos_drm_display 
*display)
 
clk_disable_unprepare(res->sclk_hdmi);
clk_disable_unprepare(res->hdmi);
-   clk_disable_unprepare(res->hdmiphy);
+   phy_power_off(res->hdmiphy);
regulator_bulk_disable(res->regul_count, res->regul_bulk);
 
pm_runtime_put_sync(hdata->dev);
@@ -1977,9 +1978,9 @@ static int hdmi_resources_init(struct hdmi_context *hdata)
DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
goto fail;
}
-   res->hdmiphy = devm_clk_get(dev, "hdmiphy");
+   res->hdmiphy = devm_phy_get(dev, "hdmiphy");
if (IS_ERR(res->hdmiphy)) {
-   DRM_ERROR("failed to get clock 'hdmiphy'\n");
+   DRM_ERROR("failed to get phy 'hdmiphy'\n");
goto fail;
}
res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
-- 
1.7.9.5

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[PATCHv2 3/3] s5p-tv: hdmi: use hdmiphy as PHY

[Tomasz Stanislawski]

The HDMIPHY (physical interface) is controlled by a single
bit in a power controller's regiter. It was implemented
as clock. It was a simple but effective hack.

This patch makes S5P-HDMI driver to control HDMIPHY via PHY interface.

Signed-off-by: Tomasz Stanislawski 
---
 drivers/media/platform/s5p-tv/hdmi_drv.c |   11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/s5p-tv/hdmi_drv.c 
b/drivers/media/platform/s5p-tv/hdmi_drv.c
index 534722c..8013e52 100644
--- a/drivers/media/platform/s5p-tv/hdmi_drv.c
+++ b/drivers/media/platform/s5p-tv/hdmi_drv.c
@@ -32,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -66,7 +67,7 @@ struct hdmi_resources {
struct clk *sclk_hdmi;
struct clk *sclk_pixel;
struct clk *sclk_hdmiphy;
-   struct clk *hdmiphy;
+   struct phy *hdmiphy;
struct regulator_bulk_data *regul_bulk;
int regul_count;
 };
@@ -586,7 +587,7 @@ static int hdmi_resource_poweron(struct hdmi_resources *res)
if (ret < 0)
return ret;
/* power-on hdmi physical interface */
-   clk_enable(res->hdmiphy);
+   phy_power_on(res->hdmiphy);
/* use VPP as parent clock; HDMIPHY is not working yet */
clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
/* turn clocks on */
@@ -600,7 +601,7 @@ static void hdmi_resource_poweroff(struct hdmi_resources 
*res)
/* turn clocks off */
clk_disable(res->sclk_hdmi);
/* power-off hdmiphy */
-   clk_disable(res->hdmiphy);
+   phy_power_off(res->hdmiphy);
/* turn HDMI power off */
regulator_bulk_disable(res->regul_count, res->regul_bulk);
 }
@@ -784,7 +785,7 @@ static void hdmi_resources_cleanup(struct hdmi_device *hdev)
/* kfree is NULL-safe */
kfree(res->regul_bulk);
if (!IS_ERR(res->hdmiphy))
-   clk_put(res->hdmiphy);
+   phy_put(res->hdmiphy);
if (!IS_ERR(res->sclk_hdmiphy))
clk_put(res->sclk_hdmiphy);
if (!IS_ERR(res->sclk_pixel))
@@ -835,7 +836,7 @@ static int hdmi_resources_init(struct hdmi_device *hdev)
dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n");
goto fail;
}
-   res->hdmiphy = clk_get(dev, "hdmiphy");
+   res->hdmiphy = phy_get(dev, "hdmiphy");
if (IS_ERR(res->hdmiphy)) {
dev_err(dev, "failed to get clock 'hdmiphy'\n");
goto fail;
-- 
1.7.9.5

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[PATCH V4 0/5] Add Exynos5 USB 3.0 phy driver based on generic PHY framework

[Vivek Gautam]

Based on 'next' branch of Kishon's phy tree (linux-phy).
Tested on 'usb-next' of Greg's usb tree.

Changes from V3:
1) Separated out the phy init sequences for utmi and pipe3 phys.
2) Changed the nomenclature across the phy to 'usbdrd-phy' to
   indicate USB 3.0 DRD PHY controller; and thereby changed the names   
 
   of functions correspondingly, including specific functions for
   utmi and pipe3 phys. 
 
3) Modified the DT nodes for the updated nomenclature.
4) Using BIT macro for single bit definitions.  
 
5) Keeping track of reference clock after getting till the removal of   
 
   phy, and getting the ref clock using devm_clk_get() api.
6) Removed aliases for mutiple channel PHYs, and instead using
   'samsung,pmu-offset' property for PHY power control register offset.
7) Keeping the phy_init() and phy_power_on() separately in order to
   align with phy handling in the consumer (DWC3).

Changes from v2:
1) Added support for multiple PHYs (UTMI+ and PIPE3) and   
   related changes in the driver structuring.
2) Added a xlate function to get the required phy out of
   number of PHYs in mutiple PHY scenerio.
3) Changed the names of few structures and variables to
   have a clearer meaning. 
4) Added 'usb3phy_config' structure to take care of mutiple
   phys for a SoC having 'exynos5_usb3phy_drv_data' driver data.  
5) Not deleting support for old driver 'phy-samsung-usb3' until
   required support for generic phy is added to DWC3.  
 
Changes from RFC patch-set:
1) fixes in documentation file
 - added provision for syscon interface for using PMU register.
 - added clock names and description
 - modified description style for 'compatible property'
 - made usb30_sclk as additional clock rather then making it optional, since
   it is actually an additional clock for Exynos5420 Soc.
2) fixes in phy-exynos5-usb3 driver file
 - removed unnecessary #ifndef around KHZ and MHZ definitions
 - removed 'samsung_cpu_type', 'usb3phy_state' enums; and merged necessary
   necessary from 'usb3phy_instance' structure to 'usb3phy_driver'.
 - changed name 'sclk_usbphy30' to 'usb30_sclk_100m' since this is the name
   indicated as input to the PHY block; and also added (!IS_ERR()) check for
   using usb30_sclk.
 - removed unnecessary 'state' check code.
 - moved 'of_device_id' structure definitions before 'probe()' to avoid
   unnecessary declaration.
 - added (pdev->dev.of_node == NULL) check at the starting of probe()
 - moved 'devm_of_phy_provider_register()' call to end of the probe().
 - removed 'label' for usb3drd phy.
 - corrected macros definition 'PHYCLKRST_MPLL_MULTIPLIER_50M_REF' from
   0x02 to 0x32 after confirming same from PHY's data sheet.
 - replaced pmu register handling, used for power-isolation, with syscon
   interface api's.
 - added '.init' and '.exit' callbacks and using them for one time
   PHY-initialization and deinitialization.
 - Filtering out the PHY 'power-on' and 'power-off' sequence to '.power_on"
   and ".power_off" callbacks.
 - Removed drivers/usb/phy/phy-samsung-usb3.c driver and related code.
3) fixes in dt files
 - added reference for 'samsung,syscon-phandle' to used for PMU register.
 - removed second register field which was earlier used for PMU.

Vivek Gautam (5):
  phy: Add new Exynos5 USB 3.0 PHY driver
  dt: exynos5420: Enable support for USB 3.0 PHY controller
  dt: exynos5420: Enable support for DWC3 controller
  dt: exynos5250: Enable support for generic USB DRD phy
  usb-phy: samsung-usb3: Remove older phy-samsung-usb3 driver

 .../devicetree/bindings/phy/samsung-phy.txt|   42 ++
 arch/arm/boot/dts/exynos5250.dtsi  |   21 +-
 arch/arm/boot/dts/exynos5420.dtsi  |   54 ++
 drivers/phy/Kconfig|   11 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-exynos5-usbdrd.c   |  668 
 drivers/usb/phy/phy-samsung-usb.h  |   83 ---
 drivers/usb/phy/phy-samsung-usb3.c |  350 --
 8 files changed, 785 insertions(+), 445 deletions(-)
 create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
 delete mode 100644 drivers/usb/phy/phy-samsung-usb3.c

-- 
1.7.10.4

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Re: AFTR does not work on arndale 5250

[Daniel Lezcano]

On 04/08/2014 03:32 PM, Vikas Sajjan wrote:

  Hi Daniel,

  I checked AFTR on v3.14 (
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/log/?id=refs/tags/v3.14)
  on exynos5250 based chromebook (exynos5250-snow.dtb)

I am able to hotplug CPU1  (echo 0 > /sys/devices/system/cpu/cpu1/online).
I can see, it enters exynos4_enter_core0_aftr() when I hotplug CPU1.


Hi,

thanks a lot for your help.

I reproduced it on my arndale board with linux-samsung/for-next and on 
v3.14.


Used the exynos_defconfig, enabled cpuidle and used exynos5250-arndale.dtb.

I unplugged the cpu1 and then => reboot

echo 0 > /sys/devices/system/cpu/cpu1/online
[   10.220448] IRQ153 no longer affine to CPU1
[   10.220595] CPU1: shutdown
# [0.00] PERCPU: Embedded 7 pages/cpu @ee7c1000 s8192 r8192 
d12288 u32768
[0.00] Built 1 zonelists in Zone order, mobility grouping on. 
Total pages: 516624
[0.00] Kernel command line: console=tty0 
console=ttySAC2,115200n8 drm_kms_helper.edid_firmware=edid-1920x1080.fw 
 root=UUID=fd363

[0.00] PID hash table entries: 4096 (order: 2, 16384 bytes)
[0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 
bytes)
[0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 
bytes)
[0.00] Memory: 2047332K/2072576K available (3678K kernel code, 
228K rwdata, 1148K rodata, 224K init, 263K bss, 25244K reserved, )

[0.00] Virtual kernel memory layout:
[0.00] vector  : 0x - 0x1000   (   4 kB)
[0.00] fixmap  : 0xfff0 - 0xfffe   ( 896 kB)
[0.00] vmalloc : 0xf000 - 0xff00   ( 240 MB)
[0.00] lowmem  : 0xc000 - 0xef80   ( 760 MB)
[0.00] pkmap   : 0xbfe0 - 0xc000   (   2 MB)
[0.00] modules : 0xbf00 - 0xbfe0   (  14 MB)
[0.00]   .text : 0xc0008000 - 0xc04bebfc   (4827 kB)
[0.00]   .init : 0xc04bf000 - 0xc04f7000   ( 224 kB)
[0.00]   .data : 0xc04f8000 - 0xc05312c0   ( 229 kB)
[0.00].bss : 0xc05312cc - 0xc0573274   ( 264 kB)
[0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[0.00] Preemptible hierarchical RCU implementation.
[0.00]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[0.00] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[0.00] NR_IRQS:16 nr_irqs:16 16
[0.00] Exynos5250: clock setup completed, armclk=10
[0.00] Architected cp15 timer(s) running at 24.00MHz (phys).
[0.00] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps 
every 2863311519744ns

[0.00] Switching to timer-based delay loop
[0.000162] Console: colour dummy device 80x30
[0.000510] console [tty0] enabled
[0.000537] Calibrating delay loop (skipped), value calculated using 
timer frequency.. 48.00 BogoMIPS (lpj=12)

[0.000568] pid_max: default: 32768 minimum: 301
[0.000793] Mount-cache hash table entries: 512
[0.013127] CPU: Testing write buffer coherency: ok
[0.013342] CPU0: update cpu_power 1024
[0.013361] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
[0.013389] Setting up static identity map for 0x4037df28 - 0x4037df80
[0.040384] CPU1: Booted secondary processor
[0.040423] CPU1: update cpu_power 1024
[0.040427] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
[0.040511] Brought up 2 CPUs
[0.040552] SMP: Total of 2 processors activated.
[0.040564] CPU: All CPU(s) started in HYP mode.
[0.040576] CPU: Virtualization extensions available.
[0.041035] devtmpfs: initialized
[0.044703] VFP support v0.3: implementor 41 architecture 4 part 30 
variant f rev 0

[0.045189] pinctrl core: initialized pinctrl subsystem
[0.045595] regulator-dummy: no parameters
[0.045937] NET: Registered protocol family 16
[0.046099] DMA: preallocated 256 KiB pool for atomic coherent 
allocations

[0.047025] cpuidle: using governor menu
[0.053567] exynos-audss-clk 381.audss-clock-controller: setup 
completed

[0.061129] EXYNOS5250 PMU Initialize
[0.073526] bio: create slab  at 0
[0.074229] MAIN_DC: no parameters
[0.074479] VDD_33ON_2.8V: 2800 mV
[0.074707] hdmi-en: no parameters
[0.076562] SCSI subsystem initialized
[0.077200] usbcore: registered new interface driver usbfs
[0.077339] usbcore: registered new interface driver hub
[0.077497] usbcore: registered new device driver usb
[0.077983] s3c-i2c 12c6.i2c: slave address 0x66
[0.078004] s3c-i2c 12c6.i2c: bus frequency set to 18 KHz
[0.140328] VDD_ALIVE_1.0V: 1100 mV
[0.160365] VDD_28IO_DP_1.35V: 1200 mV
[0.180403] VDD_COMMON1_1.8V: 1800 mV
[0.195432] VDD_IOPERI_1.8V: 1800 mV
[0.215469] VDD_EXT_1.8V: 1800 mV
[0.235505] VDD_MPLL_1.1V: 1100 mV
[0.255542] VDD_XPLL_1.1V: 1100 mV
[0.275579] VDD_COMMON2_1.0V: 1000 mV
[0.290609] VDD_33ON_3.0V: 3000 mV
[0.310644]

Re: AFTR does not work on arndale 5250

[Chander Kashyap]

Hi Daniel,

I have tested on v3.14 Stable on arndale board.
I have tested wit cramfs.

Last commit on tree is:

01d5f3b598b18a5035426c30801adf65822dbd0c

Below are the logs from the console.
$ uname -a
Linux (none) 3.14.0-00604-g0c6d388 #28 SMP PREEMPT Tue Apr 8 19:19:09
IST 2014 armv7l unknown

$ mount -t sysfs sys sys
/ $ echo 0 > /sys/devices/system/cpu/cpu1/online
[  152.439901] IRQ153 no longer affine to CPU1
[  152.440120] CPU1: shutdown

$ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
39
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
44
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
46
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
51
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
56
/ $ cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
61
/ $


It is working perfectly fine.

If still issue is there, please feel free to ask.

On 4 April 2014 18:36, Daniel Lezcano  wrote:
>
> Hi,
>
> I tried to make the idle AFTR state working on arndale 5250 but that leads
> to a kernel reboot and crash.
>
> How to reproduce ?
>
> echo 0 > /sys/devices/system/cpu/cpu1/online
>
> Reproductible on v3.14 and samsung/for-next
>
> Any ideas ?
>
> Thanks
>
>   -- Daniel
>
> --
>   Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:   Facebook |
>  Twitter |
>  Blog
>
> --
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> in
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Re: AFTR does not work on arndale 5250

[Vikas Sajjan]

 Hi Daniel,

 I checked AFTR on v3.14 (
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/log/?id=refs/tags/v3.14)
 on exynos5250 based chromebook (exynos5250-snow.dtb)

I am able to hotplug CPU1  (echo 0 > /sys/devices/system/cpu/cpu1/online).
I can see, it enters exynos4_enter_core0_aftr() when I hotplug CPU1.



On Tue, Apr 8, 2014 at 4:31 PM, Tomasz Figa  wrote:
> Hi Daniel,
>
>
> On 04.04.2014 15:06, Daniel Lezcano wrote:
>>
>>
>> Hi,
>>
>> I tried to make the idle AFTR state working on arndale 5250 but that
>> leads to a kernel reboot and crash.
>>
>> How to reproduce ?
>>
>> echo 0 > /sys/devices/system/cpu/cpu1/online
>>
>> Reproductible on v3.14 and samsung/for-next
>>
>> Any ideas ?
>
>
> Added some people that I know that have been working with Arndale.
>
> Best regards,
> Tomasz
>
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Re: [PATCH V3 15/17] ARM: exynos: cpuidle: Disable cpuidle for 5440

[Daniel Lezcano]

On 04/08/2014 02:51 PM, Amit Kucheria wrote:

On Tue, Apr 8, 2014 at 5:49 PM, Daniel Lezcano
mailto:daniel.lezc...@linaro.org>> wrote:

There is no point to register the cpuidle driver for the 5440 as it
has only
one WFI state which is the default idle function when the cpuidle
driver is
disabled.

By disabling cpuidle we prevent to enter to the governor computation for
nothing, thus saving a lot of processing time.

The only drawback is the statistic via sysfs on this state which is
lost but
it is meaningless and it could be retrieved from the ftrace easily.


So for the future, you'll only merge platform drivers that enable
something more than WFI?


Well, I already picked up a driver with only WFI because I knew the next 
idle states were in preparation. But adding a cpuidle driver just for 
WFI is no sense and if, for a reason I missed, it is really needed, I 
guess a generic WFI cpuidle driver for all platforms would be make much 
more sense.



Signed-off-by: Daniel Lezcano mailto:daniel.lezc...@linaro.org>>


In that case, Acked-by: Amit Kucheria mailto:amit.kuche...@linaro.org>>

---
  arch/arm/mach-exynos/cpuidle.c |5 -
  arch/arm/mach-exynos/exynos.c  |3 +++
  2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c
b/arch/arm/mach-exynos/cpuidle.c
index 4b94181..a1f111e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -16,8 +16,6 @@
  #include 
  #include 

-#include 
-
  #include "common.h"

  static int idle_finisher(unsigned long flags)
@@ -77,9 +75,6 @@ static int exynos_cpuidle_probe(struct
platform_device *pdev)
  {
 int ret;

-   if (soc_is_exynos5440())
-   exynos_idle_driver.state_count = 1;
-
 ret = cpuidle_register(&exynos_idle_driver, NULL);
 if (ret) {
 dev_err(&pdev->dev, "failed to register cpuidle
driver\n");
diff --git a/arch/arm/mach-exynos/exynos.c
b/arch/arm/mach-exynos/exynos.c
index b567361..fe8dac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,9 @@ static struct platform_device exynos_cpuidle = {

  void __init exynos_cpuidle_init(void)
  {
+   if (soc_is_exynos5440())
+   return;
+
 platform_device_register(&exynos_cpuidle);
  }

--
1.7.9.5


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[PATCH V3 07/17] ARM: exynos: cpuidle: Use the cpu_pm notifier

[Daniel Lezcano]

Use the cpu_pm_enter/exit notifier to group some pm code inside the pm file.

The save and restore code is duplicated across pm.c and cpuidle.c. By using
the cpu_pm notifier, we can factor out the routine.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   24 
 arch/arm/mach-exynos/pm.c  |   29 +
 2 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 6663349..7f1f4ef 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -65,26 +65,6 @@ static void exynos_set_wakeupmask(void)
__raw_writel(0xff3e, S5P_WAKEUP_MASK);
 }
 
-static unsigned int g_pwr_ctrl, g_diag_reg;
-
-static void save_cpu_arch_register(void)
-{
-   /*read power control register*/
-   asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
-   /*read diagnostic register*/
-   asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-   return;
-}
-
-static void restore_cpu_arch_register(void)
-{
-   /*write power control register*/
-   asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
-   /*write diagnostic register*/
-   asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-   return;
-}
-
 static int idle_finisher(unsigned long flags)
 {
exynos_set_wakeupmask();
@@ -106,8 +86,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 {
unsigned long tmp;
 
-   save_cpu_arch_register();
-
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
@@ -122,8 +100,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 #endif
cpu_pm_exit();
 
-   restore_cpu_arch_register();
-
/*
 * If PMU failed while entering sleep mode, WFI will be
 * ignored by PMU and then exiting cpu_do_idle().
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index adfdf4b..67d75fe 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -321,10 +322,38 @@ static const struct platform_suspend_ops 
exynos_suspend_ops = {
.valid  = suspend_valid_only_mem,
 };
 
+static int exynos_cpu_pm_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+   int cpu = smp_processor_id();
+
+   switch (cmd) {
+   case CPU_PM_ENTER:
+   if (cpu == 0) {
+   exynos_cpu_save_register();
+   }
+   break;
+
+   case CPU_PM_EXIT:
+   if (cpu == 0) {
+   exynos_cpu_restore_register();
+   }
+   break;
+   }
+
+   return NOTIFY_OK;
+}
+
+static struct notifier_block exynos_cpu_pm_notifier_block = {
+   .notifier_call = exynos_cpu_pm_notifier,
+};
+
 void __init exynos_pm_init(void)
 {
u32 tmp;
 
+   cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
+
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
 
-- 
1.7.9.5

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[PATCH V3 16/17] ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data

[Daniel Lezcano]

No more dependency on the arch code. The platform_data field is used to set the
PM callback as the other cpuidle drivers.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/common.h  |1 +
 arch/arm/mach-exynos/cpuidle.c |6 --
 arch/arm/mach-exynos/exynos.c  |5 +++--
 arch/arm/mach-exynos/pmu.c |6 ++
 4 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..7d9432e 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -62,5 +62,6 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_sys_powerdown_aftr(void);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index a1f111e..25d2fad 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -16,12 +16,12 @@
 #include 
 #include 
 
-#include "common.h"
+static void (*exynos_aftr)(void);
 
 static int idle_finisher(unsigned long flags)
 {
/* Set value of power down register for aftr mode */
-   exynos_sys_powerdown_conf(SYS_AFTR);
+   exynos_aftr();
cpu_do_idle();
return 1;
 }
@@ -75,6 +75,8 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
 {
int ret;
 
+   exynos_aftr = (void *)(pdev->dev.platform_data);
+
ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fe8dac8..a7ab561 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -221,8 +221,9 @@ void exynos_restart(enum reboot_mode mode, const char *cmd)
 }
 
 static struct platform_device exynos_cpuidle = {
-   .name   = "exynos_cpuidle",
-   .id = -1,
+   .name  = "exynos_cpuidle",
+   .dev.platform_data = exynos_sys_powerdown_aftr,
+   .id= -1,
 };
 
 void __init exynos_cpuidle_init(void)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce1..fd1ae22 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -389,6 +389,12 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
}
 }
 
+/* Set value of power down register for aftr mode */
+void exynos_sys_powerdown_aftr(void)
+{
+   exynos_sys_powerdown_conf(SYS_AFTR);
+}
+
 static int __init exynos_pmu_init(void)
 {
unsigned int value;
-- 
1.7.9.5

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[PATCH V3 06/17] ARM: exynos: cpuidle: Fix S5P_WAKEUP_STAT call

[Daniel Lezcano]

This function should be called only when the powerdown sequence fails.

Even if the current code does not hurt, by moving this line, we have the same
code than the one in pm.c.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cdfb1ae..6663349 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -134,11 +134,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+   /* Clear wakeup state register */
+   __raw_writel(0x0, S5P_WAKEUP_STAT);
}
 
-   /* Clear wakeup state register */
-   __raw_writel(0x0, S5P_WAKEUP_STAT);
-
return index;
 }
 
-- 
1.7.9.5

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[PATCH V3 04/17] ARM: exynos: cpuidle: encapsulate register access inside a function

[Daniel Lezcano]

That makes the code cleaner and encapsulted. The function will be reused in the
next patch.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/pm.c |   65 -
 1 file changed, 41 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ce..adfdf4b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -103,6 +103,42 @@ static int exynos_irq_set_wake(struct irq_data *data, 
unsigned int state)
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
+static void exynos_cpu_save_register(void)
+{
+   unsigned long tmp;
+
+   /* Save Power control register */
+   asm ("mrc p15, 0, %0, c15, c0, 0"
+: "=r" (tmp) : : "cc");
+
+   save_arm_register[0] = tmp;
+
+   /* Save Diagnostic register */
+   asm ("mrc p15, 0, %0, c15, c0, 1"
+: "=r" (tmp) : : "cc");
+
+   save_arm_register[1] = tmp;
+}
+
+static void exynos_cpu_restore_register(void)
+{
+   unsigned long tmp;
+
+   /* Restore Power control register */
+   tmp = save_arm_register[0];
+
+   asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+ : : "r" (tmp)
+ : "cc");
+
+   /* Restore Diagnostic register */
+   tmp = save_arm_register[1];
+
+   asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+ : : "r" (tmp)
+ : "cc");
+}
+
 static int exynos_cpu_suspend(unsigned long arg)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -162,17 +198,8 @@ static int exynos_pm_suspend(void)
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
-   if (!soc_is_exynos5250()) {
-   /* Save Power control register */
-   asm ("mrc p15, 0, %0, c15, c0, 0"
-: "=r" (tmp) : : "cc");
-   save_arm_register[0] = tmp;
-
-   /* Save Diagnostic register */
-   asm ("mrc p15, 0, %0, c15, c0, 1"
-: "=r" (tmp) : : "cc");
-   save_arm_register[1] = tmp;
-   }
+   if (!soc_is_exynos5250())
+   exynos_cpu_save_register();
 
return 0;
 }
@@ -196,19 +223,9 @@ static void exynos_pm_resume(void)
/* No need to perform below restore code */
goto early_wakeup;
}
-   if (!soc_is_exynos5250()) {
-   /* Restore Power control register */
-   tmp = save_arm_register[0];
-   asm volatile ("mcr p15, 0, %0, c15, c0, 0"
- : : "r" (tmp)
- : "cc");
-
-   /* Restore Diagnostic register */
-   tmp = save_arm_register[1];
-   asm volatile ("mcr p15, 0, %0, c15, c0, 1"
- : : "r" (tmp)
- : "cc");
-   }
+
+   if (!soc_is_exynos5250())
+   exynos_cpu_restore_register();
 
/* For release retention */
 
-- 
1.7.9.5

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[PATCH V3 13/17] ARM: exynos: cpuidle: Move clock setup to pm.c

[Daniel Lezcano]

One more step is moving the clock ratio setting at idle time in pm.c

The macro names have been changed to be consistent with the other macros
name in the file.

Note, the clock divider was working only when cpuidle was enabled because it
was in its init routine. With this change, the clock divider is set in the pm's
init routine, so it will also operate when the cpuidle driver is not set, which
is good.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c  |   54 ---
 arch/arm/mach-exynos/pm.c   |   35 +
 arch/arm/mach-exynos/regs-pmu.h |   19 ++
 3 files changed, 54 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cd27dbf..44d169b 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -37,25 +37,6 @@
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
 
-#define EXYNOS5_PWR_CTRL1  (S5P_VA_CMU + 0x01020)
-#define EXYNOS5_PWR_CTRL2  (S5P_VA_CMU + 0x01024)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE(1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE(1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI(1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI(1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN   (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN   (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO   (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO   (1 << 0)
-
 static int idle_finisher(unsigned long flags)
 {
 
@@ -97,38 +78,6 @@ static int exynos_enter_lowpower(struct cpuidle_device *dev,
return exynos_enter_core0_aftr(dev, drv, new_index);
 }
 
-static void __init exynos5_core_down_clk(void)
-{
-   unsigned int tmp;
-
-   /*
-* Enable arm clock down (in idle) and set arm divider
-* ratios in WFI/WFE state.
-*/
-   tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
- PWR_CTRL1_CORE1_DOWN_RATIO | \
- PWR_CTRL1_DIV2_DOWN_EN | \
- PWR_CTRL1_DIV1_DOWN_EN | \
- PWR_CTRL1_USE_CORE1_WFE| \
- PWR_CTRL1_USE_CORE0_WFE| \
- PWR_CTRL1_USE_CORE1_WFI| \
- PWR_CTRL1_USE_CORE0_WFI;
-   __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
-   /*
-* Enable arm clock up (on exiting idle). Set arm divider
-* ratios when not in idle along with the standby duration
-* ratios.
-*/
-   tmp = PWR_CTRL2_DIV2_UP_EN   | \
- PWR_CTRL2_DIV1_UP_EN   | \
- PWR_CTRL2_DUR_STANDBY2_VAL | \
- PWR_CTRL2_DUR_STANDBY1_VAL | \
- PWR_CTRL2_CORE2_UP_RATIO   | \
- PWR_CTRL2_CORE1_UP_RATIO;
-   __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
 static struct cpuidle_driver exynos_idle_driver = {
.name   = "exynos_idle",
.owner  = THIS_MODULE,
@@ -151,9 +100,6 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
 {
int ret;
 
-   if (soc_is_exynos5250())
-   exynos5_core_down_clk();
-
if (soc_is_exynos5440())
exynos_idle_driver.state_count = 1;
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 0e73591..90fb692 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -140,6 +140,38 @@ static void exynos_cpu_restore_register(void)
  : "cc");
 }
 
+static void __init exynos5_core_down_clk(void)
+{
+   unsigned int tmp;
+
+   /*
+* Enable arm clock down (in idle) and set arm divider
+* ratios in WFI/WFE state.
+*/
+   tmp = EXYNOS5_PWR_CTRL1_CORE2_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_CORE1_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_DIV2_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_DIV1_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE0_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFI| \
+ EXYNOS5_PWR_CTRL1_USE_CORE0_WFI;
+   __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+
+   /*
+* Enable arm clock up (on exiting idle). Set arm divider
+* ratios when not in idle along with the standby duration
+* ratios.
+*/
+   tmp = EXYNOS5_PWR_CTRL2_DIV2_UP_EN   | \
+ EXYNOS5_PWR_CTRL2

[PATCH V3 15/17] ARM: exynos: cpuidle: Disable cpuidle for 5440

[Daniel Lezcano]

There is no point to register the cpuidle driver for the 5440 as it has only
one WFI state which is the default idle function when the cpuidle driver is
disabled.

By disabling cpuidle we prevent to enter to the governor computation for
nothing, thus saving a lot of processing time.

The only drawback is the statistic via sysfs on this state which is lost but
it is meaningless and it could be retrieved from the ftrace easily.

Signed-off-by: Daniel Lezcano 
---
 arch/arm/mach-exynos/cpuidle.c |5 -
 arch/arm/mach-exynos/exynos.c  |3 +++
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4b94181..a1f111e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -16,8 +16,6 @@
 #include 
 #include 
 
-#include 
-
 #include "common.h"
 
 static int idle_finisher(unsigned long flags)
@@ -77,9 +75,6 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
 {
int ret;
 
-   if (soc_is_exynos5440())
-   exynos_idle_driver.state_count = 1;
-
ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b567361..fe8dac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,9 @@ static struct platform_device exynos_cpuidle = {
 
 void __init exynos_cpuidle_init(void)
 {
+   if (soc_is_exynos5440())
+   return;
+
platform_device_register(&exynos_cpuidle);
 }
 
-- 
1.7.9.5

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[PATCH V3 17/17] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle directory

[Daniel Lezcano]

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/Makefile  |1 -
 drivers/cpuidle/Kconfig.arm|6 ++
 drivers/cpuidle/Makefile   |1 +
 .../cpuidle.c => drivers/cpuidle/cpuidle-exynos.c  |0
 4 files changed, 7 insertions(+), 1 deletion(-)
 rename arch/arm/mach-exynos/cpuidle.c => drivers/cpuidle/cpuidle-exynos.c 
(100%)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index a656dbe..21bd364 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos.o
 
 obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
 
 obj-$(CONFIG_ARCH_EXYNOS)  += pmu.o
 
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index d988948..364c984 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -44,3 +44,9 @@ config ARM_AT91_CPUIDLE
depends on ARCH_AT91
help
  Select this to enable cpuidle for AT91 processors
+
+config ARM_EXYNOS_CPUIDLE
+   bool "Cpu Idle Driver for the Exynos processors"
+   depends on ARCH_EXYNOS
+   help
+ Select this to enable cpuidle for Exynos processors
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index f71ae1b..0d1540a 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_KIRKWOOD_CPUIDLE)+= cpuidle-kirkwood.o
 obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o
 obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o
 obj-$(CONFIG_ARM_AT91_CPUIDLE)  += cpuidle-at91.o
+obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+= cpuidle-exynos.o
 
 ###
 # POWERPC drivers
diff --git a/arch/arm/mach-exynos/cpuidle.c b/drivers/cpuidle/cpuidle-exynos.c
similarity index 100%
rename from arch/arm/mach-exynos/cpuidle.c
rename to drivers/cpuidle/cpuidle-exynos.c
-- 
1.7.9.5

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[PATCH V3 14/17] ARM: exynos: cpuidle: Move the boot vector in pm.c

[Daniel Lezcano]

As usual, move the boot vector setting in the pm.c file and use the cpu_pm
notifier to set it up.

Remove the unused headers.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   23 ---
 arch/arm/mach-exynos/pm.c  |   15 +++
 2 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 44d169b..4b94181 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -8,46 +8,23 @@
  * published by the Free Software Foundation.
 */
 
-#include 
-#include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include 
 
 #include 
 #include 
-#include 
 #include 
 
 #include 
-#include 
-
-#include 
 
 #include "common.h"
-#include "regs-pmu.h"
-
-#define REG_DIRECTGO_ADDR  (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
-#define REG_DIRECTGO_FLAG  (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-   S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
 
 static int idle_finisher(unsigned long flags)
 {
-
-   __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
-   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
-
cpu_do_idle();
-
return 1;
 }
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 90fb692..e4ecd8c 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -172,6 +172,20 @@ static void __init exynos5_core_down_clk(void)
__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
 }
 
+#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+   S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+   (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+
+#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+   S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+   (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+static void exynos_cpu_set_boot_vector(void)
+{
+   __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+   __raw_writel(S5P_CHECK_AFTR, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
 static int exynos_cpu_suspend(unsigned long arg)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -387,6 +401,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
exynos_cpu_save_register();
exynos_set_wakeupmask();
}
+   exynos_cpu_set_boot_vector();
break;
 
case CPU_PM_EXIT:
-- 
1.7.9.5

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[PATCH V3 05/17] ARM: exynos: cpuidle: Move some code inside the idle_finisher

[Daniel Lezcano]

Move the code around to differentiate different section of code and prepare it
to be factored out in the next patches.

The call order changed but hat doesn't have a side effect because they are
independent. The important call is cpu_do_idle() which must be done the last.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 16e3325..cdfb1ae 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -87,7 +87,16 @@ static void restore_cpu_arch_register(void)
 
 static int idle_finisher(unsigned long flags)
 {
+   exynos_set_wakeupmask();
+
+   __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+   /* Set value of power down register for aftr mode */
+   exynos_sys_powerdown_conf(SYS_AFTR);
+
cpu_do_idle();
+
return 1;
 }
 
@@ -97,14 +106,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 {
unsigned long tmp;
 
-   exynos_set_wakeupmask();
-
-   /* Set value of power down register for aftr mode */
-   exynos_sys_powerdown_conf(SYS_AFTR);
-
-   __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
-   __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
save_cpu_arch_register();
 
/* Setting Central Sequence Register for power down mode */
-- 
1.7.9.5

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[PATCH V3 09/17] ARM: exynos: cpuidle: Remove ifdef for scu_enable

[Daniel Lezcano]

The scu_enable function is already a noop in the scu's header file is
CONFIG_SMP=n, so no need to use these macros in the code.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/pm.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index aba577f..9773a00 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -244,7 +244,7 @@ static void exynos_pm_resume(void)
 
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-   if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
+   if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
 
 early_wakeup:
@@ -336,10 +336,8 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
 
case CPU_PM_EXIT:
if (cpu == 0) {
-#ifdef CONFIG_SMP
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
-#endif
exynos_cpu_restore_register();
}
break;
-- 
1.7.9.5

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[PATCH V3 12/17] ARM: exynos: cpuidle: Move S5P_CHECK_AFTR in a header

[Daniel Lezcano]

Move the S5P_CHECK_AFTR definition to the header it belongs to.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c  |2 --
 arch/arm/mach-exynos/regs-pmu.h |1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 81d7197..cd27dbf 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -37,8 +37,6 @@
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
 
-#define S5P_CHECK_AFTR 0xFCBA0D10
-
 #define EXYNOS5_PWR_CTRL1  (S5P_VA_CMU + 0x01020)
 #define EXYNOS5_PWR_CTRL2  (S5P_VA_CMU + 0x01024)
 
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..09c43c3 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -120,6 +120,7 @@
 #define S5P_INT_LOCAL_PWR_EN   0x7
 
 #define S5P_CHECK_SLEEP0x0BAD
+#define S5P_CHECK_AFTR 0xFCBA0D10
 
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWRS5P_PMUREG(0x1154)
-- 
1.7.9.5

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[PATCH V3 11/17] ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm notifier

[Daniel Lezcano]

The code to initiate and exit the powerdown sequence is the same in pm.c and
cpuidle.c.

Let's split the common part in the pm.c and reuse it from the cpu_pm notifier.

That is one more step forward to make the cpuidle driver arch indenpendant.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   21 -
 arch/arm/mach-exynos/pm.c  |   22 ++
 2 files changed, 18 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 01444ed..81d7197 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -76,31 +76,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
struct cpuidle_driver *drv,
int index)
 {
-   unsigned long tmp;
-
-   /* Setting Central Sequence Register for power down mode */
-   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-   tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
-   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
cpu_pm_exit();
 
-   /*
-* If PMU failed while entering sleep mode, WFI will be
-* ignored by PMU and then exiting cpu_do_idle().
-* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
-* in this situation.
-*/
-   tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-   if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
-   tmp |= S5P_CENTRAL_LOWPWR_CFG;
-   __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-   /* Clear wakeup state register */
-   __raw_writel(0x0, S5P_WAKEUP_STAT);
-   }
-
return index;
 }
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c8b3dc4..0e73591 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -184,15 +184,19 @@ static void exynos_pm_prepare(void)
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 }
 
-static int exynos_pm_suspend(void)
+static void exynos_pm_central_suspend(void)
 {
unsigned long tmp;
 
/* Setting Central Sequence Register for power down mode */
-
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_suspend(void)
+{
+   unsigned long tmp;
 
/* Setting SEQ_OPTION register */
 
@@ -205,7 +209,7 @@ static int exynos_pm_suspend(void)
return 0;
 }
 
-static void exynos_pm_resume(void)
+static int exynos_pm_central_resume(void)
 {
unsigned long tmp;
 
@@ -222,9 +226,17 @@ static void exynos_pm_resume(void)
/* clear the wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
-   goto early_wakeup;
+   return -1;
}
 
+   return 0;
+}
+
+static void exynos_pm_resume(void)
+{
+   if (exynos_pm_central_resume())
+   goto early_wakeup;
+
if (!soc_is_exynos5250())
exynos_cpu_restore_register();
 
@@ -336,6 +348,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
switch (cmd) {
case CPU_PM_ENTER:
if (cpu == 0) {
+   exynos_pm_central_suspend();
exynos_cpu_save_register();
exynos_set_wakeupmask();
}
@@ -346,6 +359,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
exynos_cpu_restore_register();
+   exynos_pm_central_resume();
}
break;
}
-- 
1.7.9.5

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[PATCH V3 10/17] ARM: exynos: cpuidle: Move exynos_set_wakeupmask in the cpu_pm notifier

[Daniel Lezcano]

Let's encapsulate more the PM code inside the PM file by moving the
'exynos_set_wakeupmask' function inside the pm.c and the call in the cpu_pm
notifier.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |7 ---
 arch/arm/mach-exynos/pm.c  |7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ce31004..01444ed 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -58,15 +58,8 @@
 #define PWR_CTRL2_CORE2_UP_RATIO   (1 << 4)
 #define PWR_CTRL2_CORE1_UP_RATIO   (1 << 0)
 
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(void)
-{
-   __raw_writel(0xff3e, S5P_WAKEUP_MASK);
-}
-
 static int idle_finisher(unsigned long flags)
 {
-   exynos_set_wakeupmask();
 
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 9773a00..c8b3dc4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -322,6 +322,12 @@ static const struct platform_suspend_ops 
exynos_suspend_ops = {
.valid  = suspend_valid_only_mem,
 };
 
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(void)
+{
+   __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+}
+
 static int exynos_cpu_pm_notifier(struct notifier_block *self,
  unsigned long cmd, void *v)
 {
@@ -331,6 +337,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
case CPU_PM_ENTER:
if (cpu == 0) {
exynos_cpu_save_register();
+   exynos_set_wakeupmask();
}
break;
 
-- 
1.7.9.5

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[PATCH V3 08/17] ARM: exynos: cpuidle: Move scu_enable in the cpu_pm notifier

[Daniel Lezcano]

We make the cpuidle code less arch dependent.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |6 --
 arch/arm/mach-exynos/pm.c  |4 
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 7f1f4ef..ce31004 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -18,7 +18,6 @@
 #include 
 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -93,11 +92,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device 
*dev,
 
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
-
-#ifdef CONFIG_SMP
-   if (!soc_is_exynos5250())
-   scu_enable(S5P_VA_SCU);
-#endif
cpu_pm_exit();
 
/*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 67d75fe..aba577f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -336,6 +336,10 @@ static int exynos_cpu_pm_notifier(struct notifier_block 
*self,
 
case CPU_PM_EXIT:
if (cpu == 0) {
+#ifdef CONFIG_SMP
+   if (!soc_is_exynos5250())
+   scu_enable(S5P_VA_SCU);
+#endif
exynos_cpu_restore_register();
}
break;
-- 
1.7.9.5

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[PATCH V3 02/17] ARM: exynos: cpuidle: use cpuidle_register

[Daniel Lezcano]

Use the cpuidle generic function 'cpuidle_register'. That saves us from some
extra lines of code and unneeded variables.

A side effect of this change is a bug fix where before the cpuidle driver was
registered for each_online_cpu and now it is for each_possible_cpu.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   18 ++
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 9623a05..b7cd75b 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -59,8 +59,6 @@
 #define PWR_CTRL2_CORE2_UP_RATIO   (1 << 4)
 #define PWR_CTRL2_CORE1_UP_RATIO   (1 << 0)
 
-static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
-
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 static void exynos4_set_wakeupmask(void)
 {
@@ -211,8 +209,7 @@ static struct cpuidle_driver exynos4_idle_driver = {
 
 static int exynos_cpuidle_probe(struct platform_device *pdev)
 {
-   int cpu_id, ret;
-   struct cpuidle_device *device;
+   int ret;
 
if (soc_is_exynos5250())
exynos5_core_down_clk();
@@ -220,23 +217,12 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
 
-   ret = cpuidle_register_driver(&exynos4_idle_driver);
+   ret = cpuidle_register(&exynos4_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
return ret;
}
 
-   for_each_online_cpu(cpu_id) {
-   device = &per_cpu(exynos4_cpuidle_device, cpu_id);
-   device->cpu = cpu_id;
-
-   ret = cpuidle_register_device(device);
-   if (ret) {
-   dev_err(&pdev->dev, "failed to register cpuidle 
device\n");
-   return ret;
-   }
-   }
-
return 0;
 }
 
-- 
1.7.9.5

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[PATCH V3 01/17] ARM: exynos: cpuidle: Prevent forward declaration

[Daniel Lezcano]

Move the structure below the 'exynos4_enter_lowpower' function so no more
need of forward declaration.

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   40 ++--
 1 file changed, 18 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index b530231..9623a05 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -59,30 +59,8 @@
 #define PWR_CTRL2_CORE2_UP_RATIO   (1 << 4)
 #define PWR_CTRL2_CORE1_UP_RATIO   (1 << 0)
 
-static int exynos4_enter_lowpower(struct cpuidle_device *dev,
-   struct cpuidle_driver *drv,
-   int index);
-
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
 
-static struct cpuidle_driver exynos4_idle_driver = {
-   .name   = "exynos4_idle",
-   .owner  = THIS_MODULE,
-   .states = {
-   [0] = ARM_CPUIDLE_WFI_STATE,
-   [1] = {
-   .enter  = exynos4_enter_lowpower,
-   .exit_latency   = 300,
-   .target_residency   = 10,
-   .flags  = CPUIDLE_FLAG_TIME_VALID,
-   .name   = "C1",
-   .desc   = "ARM power down",
-   },
-   },
-   .state_count = 2,
-   .safe_state_index = 0,
-};
-
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 static void exynos4_set_wakeupmask(void)
 {
@@ -213,6 +191,24 @@ static void __init exynos5_core_down_clk(void)
__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
 }
 
+static struct cpuidle_driver exynos4_idle_driver = {
+   .name   = "exynos4_idle",
+   .owner  = THIS_MODULE,
+   .states = {
+   [0] = ARM_CPUIDLE_WFI_STATE,
+   [1] = {
+   .enter  = exynos4_enter_lowpower,
+   .exit_latency   = 300,
+   .target_residency   = 10,
+   .flags  = CPUIDLE_FLAG_TIME_VALID,
+   .name   = "C1",
+   .desc   = "ARM power down",
+   },
+   },
+   .state_count = 2,
+   .safe_state_index = 0,
+};
+
 static int exynos_cpuidle_probe(struct platform_device *pdev)
 {
int cpu_id, ret;
-- 
1.7.9.5

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[PATCH V3 03/17] ARM: exynos: cpuidle: change function name prefix

[Daniel Lezcano]

The driver was initially written for exynos4 but the driver is used also for
exynos5.

Change the function prefix name exynos4 -> exynos

Signed-off-by: Daniel Lezcano 
Reviewed-by: Viresh Kumar 
Reviewed-by: Bartlomiej Zolnierkiewicz 
---
 arch/arm/mach-exynos/cpuidle.c |   20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index b7cd75b..16e3325 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -60,7 +60,7 @@
 #define PWR_CTRL2_CORE1_UP_RATIO   (1 << 0)
 
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos4_set_wakeupmask(void)
+static void exynos_set_wakeupmask(void)
 {
__raw_writel(0xff3e, S5P_WAKEUP_MASK);
 }
@@ -91,13 +91,13 @@ static int idle_finisher(unsigned long flags)
return 1;
 }
 
-static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+static int exynos_enter_core0_aftr(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
 {
unsigned long tmp;
 
-   exynos4_set_wakeupmask();
+   exynos_set_wakeupmask();
 
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
@@ -141,7 +141,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device 
*dev,
return index;
 }
 
-static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+static int exynos_enter_lowpower(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
 {
@@ -154,7 +154,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device 
*dev,
if (new_index == 0)
return arm_cpuidle_simple_enter(dev, drv, new_index);
else
-   return exynos4_enter_core0_aftr(dev, drv, new_index);
+   return exynos_enter_core0_aftr(dev, drv, new_index);
 }
 
 static void __init exynos5_core_down_clk(void)
@@ -189,13 +189,13 @@ static void __init exynos5_core_down_clk(void)
__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
 }
 
-static struct cpuidle_driver exynos4_idle_driver = {
-   .name   = "exynos4_idle",
+static struct cpuidle_driver exynos_idle_driver = {
+   .name   = "exynos_idle",
.owner  = THIS_MODULE,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE,
[1] = {
-   .enter  = exynos4_enter_lowpower,
+   .enter  = exynos_enter_lowpower,
.exit_latency   = 300,
.target_residency   = 10,
.flags  = CPUIDLE_FLAG_TIME_VALID,
@@ -215,9 +215,9 @@ static int exynos_cpuidle_probe(struct platform_device 
*pdev)
exynos5_core_down_clk();
 
if (soc_is_exynos5440())
-   exynos4_idle_driver.state_count = 1;
+   exynos_idle_driver.state_count = 1;
 
-   ret = cpuidle_register(&exynos4_idle_driver, NULL);
+   ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
return ret;
-- 
1.7.9.5

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[PATCH V3 00/17] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle

[Daniel Lezcano]

Changelog:

V3:
* Added patch   : "ARM: exynos: cpuidle: Disable cpuidle for 5440"
* Removed patch : "ARM: exynos: config: Enable cpuidle"
* Removed default ARM_EXYNOS4210_CPUIDLE=y
* Added comment about bug fix side effect 'for_each_possible_cpu'
V2: 
* Added comment in changelog for calls order (5/17)
* Call the powerdown only for cpu0 in the pm notifier
* Set the pm notifier for all boards

V1: initial post

This patchset relies on the cpm_pm notifier to initiate the powerdown sequence
operations from pm.c instead cpuidle.c. Thus the cpuidle driver is no longer
dependent from arch specific code as everything is called from the pm.c file.

The patchset applies on top of linux-samsung/for-next.

Tested on exynos4: 4210
Tested on exynos5: 5250 (without AFTR)

Daniel Lezcano (17):
  ARM: exynos: cpuidle: Prevent forward declaration
  ARM: exynos: cpuidle: use cpuidle_register
  ARM: exynos: cpuidle: change function name prefix
  ARM: exynos: cpuidle: encapsulate register access inside a function
  ARM: exynos: cpuidle: Move some code inside the idle_finisher
  ARM: exynos: cpuidle: Fix S5P_WAKEUP_STAT call
  ARM: exynos: cpuidle: Use the cpu_pm notifier
  ARM: exynos: cpuidle: Move scu_enable in the cpu_pm notifier
  ARM: exynos: cpuidle: Remove ifdef for scu_enable
  ARM: exynos: cpuidle: Move exynos_set_wakeupmask in the cpu_pm
notifier
  ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm
notifier
  ARM: exynos: cpuidle: Move S5P_CHECK_AFTR in a header
  ARM: exynos: cpuidle: Move clock setup to pm.c
  ARM: exynos: cpuidle: Move the boot vector in pm.c
  ARM: exynos: cpuidle: Disable cpuidle for 5440
  ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data
  ARM: exynos: cpuidle: Move the driver to drivers/cpuidle directory

 arch/arm/mach-exynos/Makefile|1 -
 arch/arm/mach-exynos/common.h|1 +
 arch/arm/mach-exynos/cpuidle.c   |  255 --
 arch/arm/mach-exynos/exynos.c|8 +-
 arch/arm/mach-exynos/pm.c|  177 +-
 arch/arm/mach-exynos/pmu.c   |6 +
 arch/arm/mach-exynos/regs-pmu.h  |   20 +++
 drivers/cpuidle/Kconfig.arm  |6 +
 drivers/cpuidle/Makefile |1 +
 drivers/cpuidle/cpuidle-exynos.c |   97 +++
 10 files changed, 285 insertions(+), 287 deletions(-)
 delete mode 100644 arch/arm/mach-exynos/cpuidle.c
 create mode 100644 drivers/cpuidle/cpuidle-exynos.c

-- 
1.7.9.5

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Re: AFTR does not work on arndale 5250

[Tomasz Figa]

Hi Daniel,

On 04.04.2014 15:06, Daniel Lezcano wrote:


Hi,

I tried to make the idle AFTR state working on arndale 5250 but that
leads to a kernel reboot and crash.

How to reproduce ?

echo 0 > /sys/devices/system/cpu/cpu1/online

Reproductible on v3.14 and samsung/for-next

Any ideas ?


Added some people that I know that have been working with Arndale.

Best regards,
Tomasz
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[PATCH] video: exynos: Add a dependency to the menu

[Jean Delvare]

All drivers under menu EXYNOS_VIDEO depend on either ARCH_S5PV210 or
ARCH_EXYNOS, so add these as dependencies to the menu itself. This
avoids presenting an empty and useless menu on other architectures.

Then drivers under the menu only need a dependency if they depend on
one of the supported architectures specifically.

Signed-off-by: Jean Delvare 
Cc: Jean-Christophe Plagniol-Villard 
Cc: Tomi Valkeinen 
Cc: Kukjin Kim 
---
 drivers/video/exynos/Kconfig |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-3.15-rc0.orig/drivers/video/exynos/Kconfig2014-04-07 
10:23:07.316226676 +0200
+++ linux-3.15-rc0/drivers/video/exynos/Kconfig 2014-04-08 11:50:17.406723187 
+0200
@@ -4,6 +4,7 @@
 
 menuconfig EXYNOS_VIDEO
bool "Exynos Video driver support"
+   depends on ARCH_S5PV210 || ARCH_EXYNOS
help
  This enables support for EXYNOS Video device.
 
@@ -15,7 +16,6 @@ if EXYNOS_VIDEO
 
 config EXYNOS_MIPI_DSI
bool "EXYNOS MIPI DSI driver support."
-   depends on ARCH_S5PV210 || ARCH_EXYNOS
select GENERIC_PHY
help
  This enables support for MIPI-DSI device.


-- 
Jean Delvare
SUSE L3 Support
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Re: [PATCH V2 17/17] ARM: exynos: config: Enable cpuidle

[Bartlomiej Zolnierkiewicz]

On Tuesday, April 08, 2014 09:27:04 AM Sachin Kamat wrote:
> On 8 April 2014 00:03, Olof Johansson  wrote:
> > On Mon, Apr 7, 2014 at 10:44 AM, Bartlomiej Zolnierkiewicz
> >  wrote:
> >>
> >> Hi,
> >>
> >> On Monday, April 07, 2014 09:28:39 AM Olof Johansson wrote:
> >>> On Fri, Apr 4, 2014 at 9:09 AM, Bartlomiej Zolnierkiewicz
> >>>  wrote:
> >>>
> >>> [...]
> >
> > Does 5420 even work upstream? I have hardware access but nothing that
> > will run an upstream kernel as far as I know. Maybe SLSI has an SMDK
> > they can help out with?
> 
> By working upstream if you mean being bootable, then yes I am able to boot 
> both
> SMDK and Arndale Octa boards based on 5420 with the current upstream kernel.
> CPU idle however doesn't work though. I get a crash when I hot plug out all
> secondary CPUs on SMDK.

Thanks for testing.  This behavior is an expected one given the current code
(=> we need to disable AFTR on 5420 for now).

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Javi Merino]

On Thu, Mar 20, 2014 at 02:45:54AM +, Naveen Krishna Ch wrote:
> Hello Tomasz,
> 
> On 20 March 2014 00:58, Tomasz Figa  wrote:
> > Hi Leela,
> >
> >
> > On 19.03.2014 12:19, Leela Krishna Amudala wrote:
> >>
> >> Hi All,
> >>
> >> I didn't see this series in mainline, Any comments for this ?
> >
> >
> > Naveen had posted v12 of this series and I believe all the patches got my
> > Reviewed-by.
> >
> > Best regards,
> > Tomasz
> Thanks for your reply.
> These patches are posted to the mailing list quite some time now.
> Anything i can do to speed up the process.

These patches create 5 thermal zones, one for each sensor.  Due to the
way the exynos code in drivers/thermal/samsung/exynos_thermal_common.c
registers thermal zones, each one gets a cpufreq_cooling_device.
Therefore you end up with 5 thermal zone each of which is controlling
the cpu frequency.

Wouldn't it be better to collate these 5 sensors to create one thermal
zone for the whole SoC?  Maybe a simplistic algorithm like reporting
the maximum temperature of all the sensors as the thermal zone
temperature is good enough.

Cheers,
Javi

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Re: [PATCH V2 17/17] ARM: exynos: config: Enable cpuidle

[Bartlomiej Zolnierkiewicz]

On Monday, April 07, 2014 11:33:57 AM Olof Johansson wrote:
> On Mon, Apr 7, 2014 at 10:44 AM, Bartlomiej Zolnierkiewicz
>  wrote:
> >
> > Hi,
> >
> > On Monday, April 07, 2014 09:28:39 AM Olof Johansson wrote:
> >> On Fri, Apr 4, 2014 at 9:09 AM, Bartlomiej Zolnierkiewicz
> >>  wrote:
> >>
> >> [...]
> >> >   I know that this is mainly our problem but the issue is widespread on
> >> >   our targets and I believe that adding some workaround for it in cpuidle
> >> >   core would be beneficial for the whole cpuidle subsystem.
> >
> > On the second look at the cpuidle code there is a "cpuidle.off" kernel
> > parameter which should be sufficient to workaround this particular issue
> > for now.
> >
> >> Yes, we need to find a way forward without you guys holding the whole
> >> platform hostage with out-of-tree code (here and in general, since I
> >> think there are more areas in which this applies).
> >
> > Please explain this more because I really don't know what you're meaning
> > here (at least in case of SRPOL I feel that there are no such issues).
> >
> > In this particular case we have a problem with a modified uboot bootloader
> > versions being broken and incompatible with the advanced AFTR cpuidle mode.
> > This is not the only / main issue preventing AFTR mode and thus EXYNOS
> > cpuidle driver from being used by default so I really think that the your
> > comment was unfair.
> 
> Holding off features for users of the platform because your firmware
> is too old (and you can't control the feature per platform) is going
> to get harder and harder, so being able to enable these kind of things
> at runtime will be important. I.e. as features go in, it's something
> that needs to be considered (runtime checking vs ifdef).

In this particular case runtime detection of broken uboot versions is not
possible, otherwise the issue would have been addressed a long time ago.

Anyway this is not the main problem here and we can deal with it on our
side (we will just use "cpuidle.off" on our affected targets).

> Calling that hostage taking? Yeah, maybe a little on the harsh side.
> But the problem definitely exists.

I don't agree that there is some kind of general problem on our side
and you've not provided any specific issues that would fall under this
category.

> >> >  Namely there
> >> >   should be some way of telling cpuidle subsystem to either disable
> >> >   particular state(s) or limit the max available state.  I think that 
> >> > this
> >> >   can be also useful for testing and development of other cpuidle 
> >> > drivers.
> >> >
> >> > For now please change this patch to add CONFIG_CPU_IDLE=n instead (since
> >> > the config option is "default y" it will be auto-enabled if there is no
> >> > entry in the defconfig)..
> >>
> >> Can the code be refactored such that even if CPU_IDLE is on, it won't
> >> actually do anything useful on the platforms that have problems above?
> >> I.e. determined at runtime, not build time?
> >
> > We can disable AFTR mode by default on EXYNOS4x12 SoCs with secure mode
> > enabled and EXYNOS5420 SoCs (I would like somebody with the hardware to
> > verify that AFTR mode is not working first so we have 100% certainty
> > that we don't regress here).
> 
> Does 5420 even work upstream? I have hardware access but nothing that
> will run an upstream kernel as far as I know. Maybe SLSI has an SMDK
> they can help out with?

I don't know the current status of 5420.  The initial support was added by
Linaro (I added Chander and Sachin to cc:).

If the upstream support is working to check the AFTR mode one needs to
enable cpuidle driver (CONFIG_CPU_IDLE=y) and offline all CPUs except CPU0
(through sysfs using "echo 0 > /sys/devices/system/cpu/cpuX/online").

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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Re: [PATCH v2 1/7] drm/exynos: add super device support

[Inki Dae]

2014-04-08 0:40 GMT+09:00, Tomasz Figa :
> On 07.04.2014 17:16, Inki Dae wrote:
>> Hi Andrzej,
>>
>> 2014-04-07 23:18 GMT+09:00 Andrzej Hajda :
>>> Hi Inki and Tomasz,
>>>
>>> On 04/06/2014 05:15 AM, Inki Dae wrote:
>>>
>>> (...)
 The code creating the list of components to wait for
 (exynos_drm_add_components()) doesn't seem to consider which sub-drivers
 are
 actually enabled in kernel config.

 Are you sure?

 exynos_drm_add_components() will try to attach components *added to
 component_lists. And these components will be added by only
 corresponding sub drivers to the component_lists and
 master->components.

 So in this case, if users disabled HDMI support then a commponent
 object for HDMI sub driver doesn't exists in the component_lists and
 master->components. This means that a component object for HDMI sub
 driver *cannot be attached to master object*.

 As a result, component_bind_add() will ignor component_bind call for
 HDMI sub driver so HDMI driver will not be bounded. The only
 components added by sub drivers will be bound, component->ops->bind().

 For more understanding, it seems like you need to look into below
 codes,

 static int exynos_drm_add_components(...)
 {
  ...
  for (i == 0;; i++) {
  ...
  node = of_parse_phandle(np, "ports", i);
  ...
  ret = component_master_add_child(m, compare_of, node);
  ...
  }
 }
>>>
>>> Hmm, In case HDMI driver is not present, HDMI device is not probed and
>>> HDMI component is not added, so component_master_add_child returns
>>> an error when it tries to add hdmi component and master is never brought
>>> up, am I correct?
>>>
>>
>> Ok, after that,
>>
>> ret = component_master_add(,..)
>> if (ret < 0)
>>   DRM_DEBUG_KMS("re-tried by last sub driver probed later.\n");
>>
>> As you can see above, if component_master_add() is failed, return 0,
>> *not error*. And then component_add() called by other kms drivers,
>> late probing of hdmi or fimd probing - if there is any kms driver
>> enabled - will try to bring up master again by calling
>> try_to_bring_up_master() from beginning.
>>
>> And if component_list is empty then it means that there is no any kms
>> driver enabled.
>>
>> Do you still think in that case, exynos drm initialization will be
>> failed?
>
> There will be no HDMI driver to call component_add(), because HDMI sub
> driver will be disabled in kernel config and any previous
> component_master_add_child() for the phandle pointing to HDMI node will
> wail, because such component will never be registered.
>
> The complete failure path is as follows:
>
> exynos_drm_platform_probe()
>   component_master_add()
>   try_to_bring_up_master()
>   exynos_drm_add_components()
>   // phandle to HDMI node
>   component_master_add_child()
>   = -ENXIO
>   = -ENXIO
>   = 0 // but no call to master->ops->bind(master->dev);
>   = 0
> = 0 // but Exynos DRM platform is not registered yet
>
> Now if any other late-probed sub-driver comes, the sequence will be as
> follows (let's take FIMD as an example):
>
> fimd_probe()
>   component_add()
>   try_to_bring_up_masters()
>   try_to_bring_up_master()
>   exynos_drm_add_components()
>   // phandle to HDMI node
>   component_master_add_child()
>   = -ENXIO
>   = -ENXIO
>   = 0 // but no call to   
>   // master->ops->bind(master->dev);
>   = 0
>   = 0
> = 0 // but Exynos DRM platform still not registered
>
> And the same for any late-probed driver, unless HDMI drivers loads, but
> there is no HDMI driver, because it is disabled in kernel config and not
> compiled in.
>

Ah, right. I missed that it gets phandle to hdmi, and compares the
phandle to one in component_list.
Yes, in this case, exynos drm driver will be failed because
component_list never has a component object for hdmi.
So this shouldn't return as long as there is any component - in
component_list - that can be attached to master.

Hm.. the foot of the candle is dark.

For this, I fixed and tested it like below,
for (i = 0;; i++) {
node = of_parse_phandle(np, "ports", i);
...
ret = component_master_add_child(...);
...
if (!ret)
attached_cnt++;
}

if (!attached_cnt)
return -ENXIO;
...

And one more thing, it seems that we could  resolve dt broken issue
easily by getting phandle to existing device node directly.

Thanks,
Inki Dae

> Best