Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi,
On 04/11/2014 10:46 AM, Olof Johansson wrote:
> On Thu, Apr 10, 2014 at 06:37:12PM +0900, Chanwoo Choi wrote:
>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses
>> Cortex-A7
>> dual cores and has a target speed of 1.0GHz.
>>
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/mach-exynos/Kconfig | 22 ++
>> arch/arm/mach-exynos/exynos.c| 1 +
>> arch/arm/plat-samsung/include/plat/cpu.h | 10 ++
>> 3 files changed, 33 insertions(+)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index fc8bf18..6da8a68 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>>
>> menu "SAMSUNG EXYNOS SoCs Support"
>>
>> +config ARCH_EXYNOS3
>> +bool "SAMSUNG EXYNOS3"
>> +select ARM_AMBA
>> +select CLKSRC_OF
>> +select HAVE_ARM_SCU if SMP
>> +select HAVE_SMP
>> +select PINCTRL
>> +select PM_GENERIC_DOMAINS if PM_RUNTIME
>> +help
>> + Samsung EXYNOS3 SoCs based systems
>> +
>> config ARCH_EXYNOS4
>> bool "SAMSUNG EXYNOS4"
>> default y
>> @@ -41,6 +52,17 @@ config ARCH_EXYNOS5
>>
>> comment "EXYNOS SoCs"
>>
>> +config SOC_EXYNOS3250
>> +bool "SAMSUNG EXYNOS3250"
>> +default y
>> +depends on ARCH_EXYNOS3
>> +select ARCH_HAS_BANDGAP
>> +select ARM_CPU_SUSPEND if PM
>> +select PINCTRL_EXYNOS
>> +select SAMSUNG_DMADEV
>> +help
>> + Enable EXYNOS3250 CPU support
>> +
>> config CPU_EXYNOS4210
>> bool "SAMSUNG EXYNOS4210"
>> default y
>> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
>> index b32a907..b134868 100644
>> --- a/arch/arm/mach-exynos/exynos.c
>> +++ b/arch/arm/mach-exynos/exynos.c
>> @@ -370,6 +370,7 @@ static void __init exynos_dt_machine_init(void)
>> }
>>
>> static char const *exynos_dt_compat[] __initconst = {
>> +"samsung,exynos3250",
>
> Please consider samsung,exynos3 instead, so you don't have to update this
> table
> for every SoC. We've talked about this before..
This patchset included only exynos3250.dtsi without exynos3.dtsi.
So, I added only "samsung,exynos3250" compatible name.
Do you prefer to add SoC version as following?
+ "samsung,exynos3",
+ "samsung,exynos3250",
or ?
+ "samsung,exynos3",
>
>> "samsung,exynos4",
>> "samsung,exynos4210",
>> "samsung,exynos4212",
>> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
>> b/arch/arm/plat-samsung/include/plat/cpu.h
>> index 5992b8d..3d808f6b 100644
>> --- a/arch/arm/plat-samsung/include/plat/cpu.h
>> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
>> @@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
>> #define S5PV210_CPU_ID 0x4311
>> #define S5PV210_CPU_MASK0xF000
>>
>> +#define EXYNOS3250_SOC_ID 0xE3472000
>> +#define EXYNOS3_SOC_MASK0xF000
>> +
>> #define EXYNOS4210_CPU_ID 0x4321
>> #define EXYNOS4212_CPU_ID 0x4322
>> #define EXYNOS4412_CPU_ID 0xE4412200
>> @@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
>> IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
>> IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
>> IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
>> +IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
>> IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
>> IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
>> IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
>> @@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
>> EXYNOS5_SOC_MASK)
>> # define soc_is_s5pv210() 0
>> #endif
>>
>> +#if defined(CONFIG_SOC_EXYNOS3250)
>> +# define soc_is_exynos3250()is_samsung_exynos3250()
>> +#else
>> +# define soc_is_exynos3250()0
>> +#endif
>
> In general, I think we have too much code littered with soc_is_() going
> on, so please try to avoid adding more for this SoC. Especially in cases where
> you just want to bail out of certain features where we might already have
> function pointers to control if a function is called or not, such as the
> firmware interfaces.
>
Do you prefer dt helper function such as following function instead of new
soc_is_xx() ?
- of_machine_is_compatible("samsung,exynos3250")
If you are OK, I'll use of_machine_is_compatible() instead of soc_is_xx().
Best Regards,
Chanwoo Choi
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Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi Sachin, On 04/11/2014 02:56 PM, Sachin Kamat wrote: > Hi Chanwoo, > > On 11 April 2014 11:24, Chanwoo Choi wrote: >> Hi Sachin, >> >> On 04/11/2014 12:56 PM, Sachin Kamat wrote: >>> Hi Chanwoo, >>> >>> On 10 April 2014 15:07, Chanwoo Choi wrote: This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7 dual cores and has a target speed of 1.0GHz. Signed-off-by: Chanwoo Choi Signed-off-by: Kyungmin Park --- arch/arm/mach-exynos/Kconfig | 22 ++ arch/arm/mach-exynos/exynos.c| 1 + arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ 3 files changed, 33 insertions(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index fc8bf18..6da8a68 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -11,6 +11,17 @@ if ARCH_EXYNOS menu "SAMSUNG EXYNOS SoCs Support" +config ARCH_EXYNOS3 + bool "SAMSUNG EXYNOS3" + select ARM_AMBA + select CLKSRC_OF + select HAVE_ARM_SCU if SMP + select HAVE_SMP + select PINCTRL + select PM_GENERIC_DOMAINS if PM_RUNTIME + help + Samsung EXYNOS3 SoCs based systems + config ARCH_EXYNOS4 bool "SAMSUNG EXYNOS4" default y @@ -41,6 +52,17 @@ config ARCH_EXYNOS5 comment "EXYNOS SoCs" +config SOC_EXYNOS3250 + bool "SAMSUNG EXYNOS3250" + default y + depends on ARCH_EXYNOS3 + select ARCH_HAS_BANDGAP + select ARM_CPU_SUSPEND if PM + select PINCTRL_EXYNOS + select SAMSUNG_DMADEV + help + Enable EXYNOS3250 CPU support >>> >>> There is a Kconfig consolidation patch submitted by me [1]. Please base your >>> code on that one to avoid merge conflicts. >>> >>> [1] http://article.gmane.org/gmane.linux.kernel.samsung-soc/28642 >>> >> >> Your patch is applied? I can't find merged patch on linux-samsung.git and >> arm-soc.git. >> If this patch is applied, I will rebase this patchset. Thanks. > > This patch hasn't been merged yet but has been agreed upon by Kukjin, > Tomasz and others. > You may follow the mailing list for details. > OK, I checked mailied list for your patch. As my previous reply, if your patch is merged, I'll rebase it. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 04/27] ARM: EXYNOS: Support secondary CPU boot of Exynos4212
Hi,
On 04/11/2014 2:14 PM, Chanwoo Choi wrote:
> >> {
> >> - exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> >> + if (soc_is_exynos4212())
> >> + exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
> >> + else
> >> + exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> >
> > /* */
>
> It's better to ask system lsi person. We don't know it well.
> I got the guide about secondary boot from system lsi.
> But, this patch was completely tested.
exynos_smc(SMC_CMD_CPU1BOOT, ...) is cpu hotplug SMC interface.
Exynos4212 is dual core processor.
Exynos4212 only have to boot cpu1 on smp boot.
So, Second parameter of exynos_smc is fixed by 0 which means cpu1.
It don't need to boot another cpu (ex. cpu2, cpu3 for quad core processor).
But In case of quad core processor (ex. Exynos4412),
It need to boot another cpu and specify parameter of booting core.
As I know, Exynos3250 is dual core.
So It can be included 1st condition too.
Sangbeom,
Thanks,
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Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi Chanwoo, On 11 April 2014 11:24, Chanwoo Choi wrote: > Hi Sachin, > > On 04/11/2014 12:56 PM, Sachin Kamat wrote: >> Hi Chanwoo, >> >> On 10 April 2014 15:07, Chanwoo Choi wrote: >>> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that >>> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses >>> Cortex-A7 >>> dual cores and has a target speed of 1.0GHz. >>> >>> Signed-off-by: Chanwoo Choi >>> Signed-off-by: Kyungmin Park >>> --- >>> arch/arm/mach-exynos/Kconfig | 22 ++ >>> arch/arm/mach-exynos/exynos.c| 1 + >>> arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ >>> 3 files changed, 33 insertions(+) >>> >>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig >>> index fc8bf18..6da8a68 100644 >>> --- a/arch/arm/mach-exynos/Kconfig >>> +++ b/arch/arm/mach-exynos/Kconfig >>> @@ -11,6 +11,17 @@ if ARCH_EXYNOS >>> >>> menu "SAMSUNG EXYNOS SoCs Support" >>> >>> +config ARCH_EXYNOS3 >>> + bool "SAMSUNG EXYNOS3" >>> + select ARM_AMBA >>> + select CLKSRC_OF >>> + select HAVE_ARM_SCU if SMP >>> + select HAVE_SMP >>> + select PINCTRL >>> + select PM_GENERIC_DOMAINS if PM_RUNTIME >>> + help >>> + Samsung EXYNOS3 SoCs based systems >>> + >>> config ARCH_EXYNOS4 >>> bool "SAMSUNG EXYNOS4" >>> default y >>> @@ -41,6 +52,17 @@ config ARCH_EXYNOS5 >>> >>> comment "EXYNOS SoCs" >>> >>> +config SOC_EXYNOS3250 >>> + bool "SAMSUNG EXYNOS3250" >>> + default y >>> + depends on ARCH_EXYNOS3 >>> + select ARCH_HAS_BANDGAP >>> + select ARM_CPU_SUSPEND if PM >>> + select PINCTRL_EXYNOS >>> + select SAMSUNG_DMADEV >>> + help >>> + Enable EXYNOS3250 CPU support >> >> There is a Kconfig consolidation patch submitted by me [1]. Please base your >> code on that one to avoid merge conflicts. >> >> [1] http://article.gmane.org/gmane.linux.kernel.samsung-soc/28642 >> > > Your patch is applied? I can't find merged patch on linux-samsung.git and > arm-soc.git. > If this patch is applied, I will rebase this patchset. Thanks. This patch hasn't been merged yet but has been agreed upon by Kukjin, Tomasz and others. You may follow the mailing list for details. -- With warm regards, Sachin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi Sachin, On 04/11/2014 12:56 PM, Sachin Kamat wrote: > Hi Chanwoo, > > On 10 April 2014 15:07, Chanwoo Choi wrote: >> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that >> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses >> Cortex-A7 >> dual cores and has a target speed of 1.0GHz. >> >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park >> --- >> arch/arm/mach-exynos/Kconfig | 22 ++ >> arch/arm/mach-exynos/exynos.c| 1 + >> arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ >> 3 files changed, 33 insertions(+) >> >> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig >> index fc8bf18..6da8a68 100644 >> --- a/arch/arm/mach-exynos/Kconfig >> +++ b/arch/arm/mach-exynos/Kconfig >> @@ -11,6 +11,17 @@ if ARCH_EXYNOS >> >> menu "SAMSUNG EXYNOS SoCs Support" >> >> +config ARCH_EXYNOS3 >> + bool "SAMSUNG EXYNOS3" >> + select ARM_AMBA >> + select CLKSRC_OF >> + select HAVE_ARM_SCU if SMP >> + select HAVE_SMP >> + select PINCTRL >> + select PM_GENERIC_DOMAINS if PM_RUNTIME >> + help >> + Samsung EXYNOS3 SoCs based systems >> + >> config ARCH_EXYNOS4 >> bool "SAMSUNG EXYNOS4" >> default y >> @@ -41,6 +52,17 @@ config ARCH_EXYNOS5 >> >> comment "EXYNOS SoCs" >> >> +config SOC_EXYNOS3250 >> + bool "SAMSUNG EXYNOS3250" >> + default y >> + depends on ARCH_EXYNOS3 >> + select ARCH_HAS_BANDGAP >> + select ARM_CPU_SUSPEND if PM >> + select PINCTRL_EXYNOS >> + select SAMSUNG_DMADEV >> + help >> + Enable EXYNOS3250 CPU support > > There is a Kconfig consolidation patch submitted by me [1]. Please base your > code on that one to avoid merge conflicts. > > [1] http://article.gmane.org/gmane.linux.kernel.samsung-soc/28642 > Your patch is applied? I can't find merged patch on linux-samsung.git and arm-soc.git. If this patch is applied, I will rebase this patchset. Thanks. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/10] ARM: EXYNOS: Move SYSREG definition into sys-reg specific file
On 04/02/2014 08:27 PM, Sylwester Nawrocki wrote: Hi, On 02/04/14 09:50, Pankaj Dubey wrote: From: Young-Gun Jang While making PMU (Power Mengement Unit) implementation device tree based, there are few offsets related with SYSREG present in regs-pmu.h, so let's make a new header file "regs-sys.h" to keep all such SYSREG related register definition and remove them from "regs-pmu.h" Signed-off-by: Young-Gun Jang Signed-off-by: Pankaj Dubey --- arch/arm/mach-exynos/exynos.c |1 + arch/arm/mach-exynos/pm.c |1 + arch/arm/mach-exynos/regs-pmu.h |3 --- arch/arm/mach-exynos/regs-sys.h | 22 ++ 4 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-exynos/regs-sys.h [...] diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h new file mode 100644 index 000..84332b0 --- /dev/null +++ b/arch/arm/mach-exynos/regs-sys.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS - system register definition + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_SYS_H +#define __ASM_ARCH_REGS_SYS_H __FILE__ + +#include + +#define S5P_SYSREG(x) (S3C_VA_SYS + (x)) + +/* For EXYNOS5 */ +#define EXYNOS5_SYS_I2C_CFGS5P_SYSREG(0x0234) Can this be defined as a regular register offset in a header file placed at include/linux/mfd/syscon/ ? I.e. can the mfd syscon driver be used instead of these hacks ? No. As currently SysRegs are being accessed via iodesc table and not via DT, it has dependency on "mach/map.h". We separated these definitions from "regs-pmu.h" as it does not belong to EXYNOS PMU IP. But this can be done once we make some way of accessing SysReg register sets via DT. -- Best Regards, Pankaj Dubey -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/2] drivers: mfd: Add support of exynos-pmu driver
Hi Bartlomiej,
Thanks for review.
On 04/03/2014 08:56 PM, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Wednesday, April 02, 2014 05:24:44 PM Pankaj Dubey wrote:
From: Younggun Jang
This driver is mainly used for setting misc bits of register from PMU IP
of Exynos SoC which will be required to configure before Suspend/Resume.
Currently all these settings are done in "arch/arm/mach-exynos/pmu.c" but
moving ahead for ARM64 based SoC support, there is a need of DT based
implementation of PMU driver.
PMU support for ARM32 EXYNOS SoCs is heavily SoC dependent and there
is very little code shared between diffirent SoCs. Unless PMU setup
for Samsung ARM64 SoCs is similar to some existing ARM32 EXYNOS SoCs
it may be better to just add a separate PMU driver for Samsung ARM64
SoCs. IOW it would be best to show that this patch series is really
useful before merging it.
We think it will be useful, but I will consider your point of making driver
which should have common piece of code to address various EXYNOS SoCs.
We are working on it, once it takes some proper shape I will post details here.
When it comes to the current patches it would be better to do changes
converting PMU support to be a platform driver first for the existing
arch/arm/mach-exynos/pmu.c file and then move+rename this file in
the separate patch. Currently the code changes are done at the same
time as the code movement which makes them difficult to review/verify.
OK, will do as you suggested in next version.
There are also some minor issues with the new code:
[...]
diff --git a/drivers/mfd/exynos-pmu.c b/drivers/mfd/exynos-pmu.c
new file mode 100644
index 000..24abd9b
--- /dev/null
+++ b/drivers/mfd/exynos-pmu.c
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2014-2015 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
2015?
Will fix this.
[...]
+static int __init exynos4210_pmu_init(void)
+{
+ exynos_pmu_config = exynos4210_pmu_config;
+ pmu_data->pmu_id = PMU_EXYNOS4210;
+ pr_info("EXYNOS4210 PMU Initialize\n");
+
+ return 0;
+}
+
+static int __init exynos4212_pmu_init(void)
+{
+ exynos_pmu_config = exynos4x12_pmu_config;
+ pmu_data->pmu_id = PMU_EXYNOS4212;
+ pr_info("EXYNOS4x12 PMU Initialize\n");
+
+ return 0;
+}
+
+static int __init exynos4412_pmu_init(void)
+{
+ exynos_pmu_config = exynos4x12_pmu_config;
+ pmu_data->pmu_id = PMU_EXYNOS4412;
+ pr_info("EXYNOS4412 PMU Initialize\n");
+
+ return 0;
+}
+
+static int __init exynos5250_pmu_init(void)
+{
+ unsigned int value;
+
+ /*
+* When SYS_WDTRESET is set, watchdog timer reset request
+* is ignored by power management unit.
+*/
+ value = __raw_readl(pmu_data->regs + EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ __raw_writel(value, pmu_data->regs + EXYNOS5_AUTO_WDTRESET_DISABLE);
+
+ value = __raw_readl(pmu_data->regs + EXYNOS5_MASK_WDTRESET_REQUEST);
+ value &= ~EXYNOS5_SYS_WDTRESET;
+ __raw_writel(value, pmu_data->regs + EXYNOS5_MASK_WDTRESET_REQUEST);
+
+ exynos_pmu_config = exynos5250_pmu_config;
+ pmu_data->pmu_id = PMU_EXYNOS5250;
+ pr_info("EXYNOS5250 PMU Initialize\n");
+
+ return 0;
+}
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id exynos_pmu_of_device_ids[] = {
+ {
+ .compatible = "samsung,exynos4210-pmu",
+ .data = (void *)exynos4210_pmu_init
+ },
+ {
+ .compatible = "samsung,exynos4212-pmu",
+ .data = (void *)exynos4212_pmu_init
+ },
+ {
+ .compatible = "samsung,exynos4412-pmu",
+ .data = (void *)exynos4412_pmu_init
+ },
+ {
+ .compatible = "samsung,exynos5250-pmu",
+ .data = (void *)exynos5250_pmu_init
+ },
+ {},
+};
+
+static int exynos_pmu_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ exynos_pmu_init_t exynos_pmu_init;
+ struct resource *res;
+
+ pmu_data = devm_kzalloc(&pdev->dev,
+ sizeof(struct exynos_pmu_data), GFP_KERNEL);
+ if (!pmu_data) {
+ dev_err(&pdev->dev, "exynos_pmu driver probe failed\n");
+ return -ENOMEM;
+ }
+
+ pmu_data->dev = &pdev->dev;
+
+ match = of_match_node(exynos_pmu_of_device_ids, pdev->dev.of_node);
+ exynos_pmu_init = match->data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pmu_data->regs = devm_ioremap_resource(&pdev->dev, res);
devm_ioremap_resouce() return value should be checked for errors with
if (IS_ERR(pmu_data->regs))
return PTR_ERR(pmu_data->regs);
Will take care.
+
+ exynos_pmu_init();
exynos*_pmu_init() methods should be void as they always return 0 and
the return value is ignored anyway.
Also they cannot be marked with __init as the
Re: [PATCH 04/27] ARM: EXYNOS: Support secondary CPU boot of Exynos4212
Hi,
On 04/11/2014 10:44 AM, Olof Johansson wrote:
> On Thu, Apr 10, 2014 at 06:37:15PM +0900, Chanwoo Choi wrote:
>> From: Kyungmin Park
>>
>> This patch fix the offset of CPU boot address and change parameter of smc
>> call
>> of SMC_CMD_CPU1BOOT command for Exynos4212.
>>
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/mach-exynos/firmware.c | 14 --
>> 1 file changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/firmware.c
>> b/arch/arm/mach-exynos/firmware.c
>> index 932129e..91a911d 100644
>> --- a/arch/arm/mach-exynos/firmware.c
>> +++ b/arch/arm/mach-exynos/firmware.c
>> @@ -18,6 +18,8 @@
>>
>> #include
>>
>> +#include
>> +
>> #include "smc.h"
>>
>> static int exynos_do_idle(void)
>> @@ -28,14 +30,22 @@ static int exynos_do_idle(void)
>>
>> static int exynos_cpu_boot(int cpu)
>> {
>> -exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>> +if (soc_is_exynos4212())
>> +exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
>> +else
>> +exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
>
> /* */
It's better to ask system lsi person. We don't know it well.
I got the guide about secondary boot from system lsi.
But, this patch was completely tested.
> if (soc_is_exynos4212())
> cpu = 0;
>
> ...and then do the call as before.
OK, I'll modify it as following:
static int exynos_cpu_boot(int cpu)
{
+ if (soc_is_exynos4212())
+ cpu = 0;
+
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
>
>
>> return 0;
>> }
>>
>> static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>> {
>> -void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
>> +void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
>>
>> +if (soc_is_exynos4212())
>> +goto out;
>> +else
>> +boot_reg += 4*cpu;
>
> if (!soc_is_exynos4212())
> boot_reg += 4 * cpu;
>
> That way you avoid a goto, especially since the "goto out" isn't actually
> an "out", it's still doing stuff at the end of the funciton.
>
OK, I'll remove goto statement and then modify it as your comment.
- void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+ void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
+
+ if (!soc_is_exynos4212())
+ boot_reg += 4*cpu;
Best Regards,
Chanwoo Choi
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Re: [PATCH 15/27] ARM: dts: exynos3250: Add uart dt node to support seiral ports
Hi, On 04/11/2014 01:03 PM, Sachin Kamat wrote: > On 10 April 2014 15:36, Chanwoo Choi wrote: >> This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP >> of Exynos4 SoC and has only two independent channels. >> >> Signed-off-by: Chanwoo Choi >> [Fix incorrect clock id by Tomasz Figa] >> Signed-off-by: Tomasz Figa >> Signed-off-by: Kyungmin Park >> --- > > typo in patch subject: s/seiral/serial > I'll fix it. Thanks. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 10/27] ARM: dts: exynos3250: Add new exynos3250.dtsi file
Hi,
On 04/11/2014 01:01 PM, Sachin Kamat wrote:
> Hi Chanwoo,
>
> On 10 April 2014 15:36, Chanwoo Choi wrote:
>> From: Tomasz Figa
>>
>> This patch add new exynos3250.dtsi to support Exynos3250 SoC and includes
>> chipid/sys_reg dt node.
>>
>> Signed-off-by: Tomasz Figa
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/boot/dts/exynos3250.dtsi | 34 ++
>> 1 file changed, 34 insertions(+)
>> create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>> b/arch/arm/boot/dts/exynos3250.dtsi
>> new file mode 100644
>> index 000..3c8cee6
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -0,0 +1,34 @@
>> +/*
>> + * Samsung's Exynos3250 SoC device tree source
>> + *
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
>> + * based board files can include this file and provide values for board
>> specfic
>> + * bindings.
>> + *
>> + * Note: This file does not include device nodes for all the controllers in
>> + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases,
>> additional
>> + * nodes can be added to this file.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> + compatible = "samsung,exynos3250";
>> +
>> + chipid@1000 {
>> + compatible = "samsung,exynos4210-chipid";
>> + reg = <0x1000 0x100>;
>> + };
>> +
>> + sys_reg: syscon@1001 {
>> + compatible = "samsung,exynos3-sysreg", "syscon";
>> + reg = <0x1001 0x400>;
>> + };
>> +};
>
> Shouldn't these be grouped under the soc node?
I don't understand accurate meaning.
Do you have to explain more detailed comment?
Best Regards,
Chanwoo Choi
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Re: [PATCH 12/27] ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
Hi, On 04/11/2014 01:00 PM, Olof Johansson wrote: > On Thu, Apr 10, 2014 at 07:06:02PM +0900, Chanwoo Choi wrote: >> This patch add interrupt-parent node to connected with GIC. >> All interrupt-related dt nodes need default interrupt-parent node. >> >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park > > There's no point in splitting these off in separate patches; fold them > into one patch that introduces the SoC dtsi, please. OK, I will consolidate following two patches into one patch. [PATCH 11/27] ARM: dts: exynos3250: Add GIC dt node for Exynos3250 [PATCH 12/27] ARM: dts: exynos3250: Add default interrupt-parent connected with GIC > > Also, you missed your sign-off on one or two of the previous ones, but that > won't be a problem once they're folded in. :) I'll add my sign-off to all the patches on next posting(v2). > > Finally, if the code is yours, and you're posting it, then Kyungmin should > probably have a Reviewed-by or Acked-by tag, not a Signed-off-by. See > Documentation/SubmittingPatches, section 12 and 13. > OK, I'll change from 'Signed-off-by' to 'Acked-by'. Thanks, Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 15/27] ARM: dts: exynos3250: Add uart dt node to support seiral ports
On 10 April 2014 15:36, Chanwoo Choi wrote: > This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP > of Exynos4 SoC and has only two independent channels. > > Signed-off-by: Chanwoo Choi > [Fix incorrect clock id by Tomasz Figa] > Signed-off-by: Tomasz Figa > Signed-off-by: Kyungmin Park > --- typo in patch subject: s/seiral/serial -- With warm regards, Sachin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 10/27] ARM: dts: exynos3250: Add new exynos3250.dtsi file
Hi Chanwoo,
On 10 April 2014 15:36, Chanwoo Choi wrote:
> From: Tomasz Figa
>
> This patch add new exynos3250.dtsi to support Exynos3250 SoC and includes
> chipid/sys_reg dt node.
>
> Signed-off-by: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 34 ++
> 1 file changed, 34 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
> b/arch/arm/boot/dts/exynos3250.dtsi
> new file mode 100644
> index 000..3c8cee6
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -0,0 +1,34 @@
> +/*
> + * Samsung's Exynos3250 SoC device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
> + * based board files can include this file and provide values for board
> specfic
> + * bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases,
> additional
> + * nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "samsung,exynos3250";
> +
> + chipid@1000 {
> + compatible = "samsung,exynos4210-chipid";
> + reg = <0x1000 0x100>;
> + };
> +
> + sys_reg: syscon@1001 {
> + compatible = "samsung,exynos3-sysreg", "syscon";
> + reg = <0x1001 0x400>;
> + };
> +};
Shouldn't these be grouped under the soc node?
--
With warm regards,
Sachin
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Re: [PATCH 12/27] ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
On Thu, Apr 10, 2014 at 07:06:02PM +0900, Chanwoo Choi wrote: > This patch add interrupt-parent node to connected with GIC. > All interrupt-related dt nodes need default interrupt-parent node. > > Signed-off-by: Chanwoo Choi > Signed-off-by: Kyungmin Park There's no point in splitting these off in separate patches; fold them into one patch that introduces the SoC dtsi, please. Also, you missed your sign-off on one or two of the previous ones, but that won't be a problem once they're folded in. :) Finally, if the code is yours, and you're posting it, then Kyungmin should probably have a Reviewed-by or Acked-by tag, not a Signed-off-by. See Documentation/SubmittingPatches, section 12 and 13. -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi Chanwoo, On 10 April 2014 15:07, Chanwoo Choi wrote: > This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that > is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses > Cortex-A7 > dual cores and has a target speed of 1.0GHz. > > Signed-off-by: Chanwoo Choi > Signed-off-by: Kyungmin Park > --- > arch/arm/mach-exynos/Kconfig | 22 ++ > arch/arm/mach-exynos/exynos.c| 1 + > arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ > 3 files changed, 33 insertions(+) > > diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig > index fc8bf18..6da8a68 100644 > --- a/arch/arm/mach-exynos/Kconfig > +++ b/arch/arm/mach-exynos/Kconfig > @@ -11,6 +11,17 @@ if ARCH_EXYNOS > > menu "SAMSUNG EXYNOS SoCs Support" > > +config ARCH_EXYNOS3 > + bool "SAMSUNG EXYNOS3" > + select ARM_AMBA > + select CLKSRC_OF > + select HAVE_ARM_SCU if SMP > + select HAVE_SMP > + select PINCTRL > + select PM_GENERIC_DOMAINS if PM_RUNTIME > + help > + Samsung EXYNOS3 SoCs based systems > + > config ARCH_EXYNOS4 > bool "SAMSUNG EXYNOS4" > default y > @@ -41,6 +52,17 @@ config ARCH_EXYNOS5 > > comment "EXYNOS SoCs" > > +config SOC_EXYNOS3250 > + bool "SAMSUNG EXYNOS3250" > + default y > + depends on ARCH_EXYNOS3 > + select ARCH_HAS_BANDGAP > + select ARM_CPU_SUSPEND if PM > + select PINCTRL_EXYNOS > + select SAMSUNG_DMADEV > + help > + Enable EXYNOS3250 CPU support There is a Kconfig consolidation patch submitted by me [1]. Please base your code on that one to avoid merge conflicts. [1] http://article.gmane.org/gmane.linux.kernel.samsung-soc/28642 -- With warm regards, Sachin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/5] drm/exynos: add support for apb mapped phys in hdmi driver
Thanks Tomasz,
On 10 April 2014 22:47, Tomasz Figa wrote:
> Hi Rahul,
>
> On 02.04.2014 19:13, Rahul Sharma wrote:
>>
>> From: Rahul Sharma
>>
>> Previous SoCs have hdmi phys which are accessible through
>> dedicated i2c lines. Newer SoCs have Apb mapped hdmi phys.
>> Hdmi driver is modified to support apb mapped phys.
>>
>> Signed-off-by: Rahul Sharma
>> ---
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 142
>> +-
>> drivers/gpu/drm/exynos/regs-hdmi.h |7 ++
>> 2 files changed, 96 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 5b2cfe7..5989770 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -33,6 +33,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -68,6 +69,8 @@ enum hdmi_type {
>>
>> struct hdmi_driver_data {
>> unsigned int type;
>> + const struct hdmiphy_config *phy_confs;
>> + unsigned int phy_conf_count;
>> unsigned int is_apb_phy:1;
>> };
>>
>> @@ -196,9 +199,12 @@ struct hdmi_context {
>> struct hdmi_resources res;
>>
>> int hpd_gpio;
>> + void __iomem*regs_hdmiphy;
>> struct regmap *pmureg;
>>
>> enum hdmi_type type;
>> + const struct hdmiphy_config *phy_confs;
>> + unsigned intphy_conf_count;
>> };
>>
>> struct hdmiphy_config {
>> @@ -206,14 +212,6 @@ struct hdmiphy_config {
>> u8 conf[32];
>> };
>>
>> -struct hdmi_driver_data exynos4212_hdmi_driver_data = {
>> - .type = HDMI_TYPE14,
>> -};
>> -
>> -struct hdmi_driver_data exynos5_hdmi_driver_data = {
>> - .type = HDMI_TYPE14,
>> -};
>> -
>> /* list of phy config settings */
>> static const struct hdmiphy_config hdmiphy_v13_configs[] = {
>> {
>> @@ -428,6 +426,21 @@ static const struct hdmiphy_config
>> hdmiphy_v14_configs[] = {
>> },
>> };
>>
>> +
>> +struct hdmi_driver_data exynos4212_hdmi_driver_data = {
>> + .type = HDMI_TYPE14,
>> + .phy_confs = hdmiphy_v14_configs,
>> + .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
>> + .is_apb_phy = 0,
>> +};
>> +
>> +struct hdmi_driver_data exynos5_hdmi_driver_data = {
>> + .type = HDMI_TYPE14,
>> + .phy_confs = hdmiphy_v13_configs,
>> + .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
>> + .is_apb_phy = 0,
>> +};
>> +
>> static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
>> {
>> return readl(hdata->regs + reg_id);
>> @@ -447,6 +460,48 @@ static inline void hdmi_reg_writemask(struct
>> hdmi_context *hdata,
>> writel(value, hdata->regs + reg_id);
>> }
>>
>> +static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
>> + u32 reg_offset, u8 value)
>> +{
>> + if (hdata->hdmiphy_port) {
>> + u8 buffer[2];
>> + int ret;
>> +
>> + buffer[0] = reg_offset;
>> + buffer[1] = value;
>> +
>> + ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
>> + if (ret == 2)
>> + return 0;
>> + return ret;
>> + } else {
>> + writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
>> + return 0;
>> + }
>> +}
>> +
>> +static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
>> + u32 reg_offset, const u8 *buf, u32 len)
>> +{
>> + if ((reg_offset + len) > 32)
>> + return -EINVAL;
>> +
>> + if (hdata->hdmiphy_port) {
>> + int ret;
>> +
>> + ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
>
>
> reg_offset doesn't seem to be used in I2C code path in any way. Are you sure
> this is correct?
>
yea ... reg_offset is not required for i2c write as first buffer in
buffer is taken as offset.
>> + if (ret == len)
>> + return 0;
>> + return ret;
>> + } else {
>> + int i;
>> + for (i = 0; i < len; i++)
>> + writeb(buf[i], hdata->regs_hdmiphy +
>> + ((reg_offset + i)<<2));
>> + return 0;
>> + }
>> +}
>
>
> I wonder if those functions couldn't be abstracted as two callbacks in
> hdmi_driver_data struct to eliminate such if clauses as above.
>
hmn...I can do that... but will it help in anyway. I will end up in changing
more code in probe, adding 4 callbacks. let me know if you want me to do
that.
Regards,
Rahul Sharma.
> --
> Best regards,
> Tomasz
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> http://lists.freedesktop.org/m
Re: [PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
On 04/11/2014 10:48 AM, Olof Johansson wrote: > On Thu, Apr 10, 2014 at 06:37:14PM +0900, Chanwoo Choi wrote: >> This patch add memory mapping for PMU (Power Management Unit) which is used >> for power control of Exynos3250. >> >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park > > Signed-off-by is in the wrong order, if Kyungmin wrote the patch and you're > just posting it... No, I implemented this patch and posted it. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] iio: adc: exynos_adc: Control special clock of ADC to support Exynos3250 ADC
This patch control special clock for ADC in Exynos series's FSYS block.
If special clock of ADC is registerd on clock list of common clk framework,
Exynos ADC drvier have to control this clock.
Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
- 'adc' clock: bus clock for ADC
Exynos3250 has additional 'sclk_tsadc' clock as following:
- 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
clock in FSYS_BLK.
Cc: Jonathan Cameron
Cc: Kukjin Kim
Cc: Naveen Krishna Chatradhi
Cc: linux-...@vger.kernel.org
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
drivers/iio/adc/exynos_adc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index d25b262..4cd1975 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -88,6 +88,7 @@ struct exynos_adc {
void __iomem*regs;
void __iomem*enable_reg;
struct clk *clk;
+ struct clk *sclk;
unsigned intirq;
struct regulator*vdd;
@@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
goto err_irq;
}
+ info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
+ if (IS_ERR(info->sclk)) {
+ dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
+ PTR_ERR(info->sclk));
+ info->sclk = NULL;
+ }
+
info->vdd = devm_regulator_get(&pdev->dev, "vdd");
if (IS_ERR(info->vdd)) {
dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
@@ -341,6 +349,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
goto err_iio_dev;
clk_prepare_enable(info->clk);
+ clk_prepare_enable(info->sclk);
exynos_adc_hw_init(info);
@@ -357,6 +366,7 @@ err_of_populate:
exynos_adc_remove_devices);
regulator_disable(info->vdd);
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
err_iio_dev:
iio_device_unregister(indio_dev);
err_irq:
@@ -373,6 +383,7 @@ static int exynos_adc_remove(struct platform_device *pdev)
exynos_adc_remove_devices);
regulator_disable(info->vdd);
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
writel(0, info->enable_reg);
iio_device_unregister(indio_dev);
free_irq(info->irq, info);
@@ -398,6 +409,7 @@ static int exynos_adc_suspend(struct device *dev)
}
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
writel(0, info->enable_reg);
regulator_disable(info->vdd);
@@ -416,6 +428,7 @@ static int exynos_adc_resume(struct device *dev)
writel(1, info->enable_reg);
clk_prepare_enable(info->clk);
+ clk_prepare_enable(info->sclk);
exynos_adc_hw_init(info);
--
1.8.0
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Re: [PATCH 2/5] drm/exynos: use regmap interface to set hdmiphy control bit in pmu
Thanks Tomasz,
This patch is not longer required after rebasing to Tomasz Stanislawski's
Simple Phy patches.
Regards,
Rahul Sharma.
On 10 April 2014 22:30, Tomasz Figa wrote:
> Hi Rahul,
>
> On 02.04.2014 19:13, Rahul Sharma wrote:
>>
>> From: Rahul Sharma
>>
>> Hdmiphy control bit needs to be set before setting the resolution
>> to hdmi hardware. This was handled using dummy hdmiphy clock which
>> is removed now.
>>
>> PMU is already defined as system controller for exynos SoC. Registers
>> of PMU are accessed using regmap interfaces.
>>
>> Devicetree binding document for hdmi is also updated.
>>
>> Signed-off-by: Rahul Sharma
>> ---
>> .../devicetree/bindings/video/exynos_hdmi.txt |2 ++
>> drivers/gpu/drm/exynos/exynos_hdmi.c | 17
>> +
>> drivers/gpu/drm/exynos/regs-hdmi.h |4
>> 3 files changed, 23 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> index f9187a2..243a499 100644
>> --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
>> @@ -27,6 +27,7 @@ Required properties:
>> "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
>> - ddc: phandle to the hdmi ddc node
>> - phy: phandle to the hdmi phy node
>> +- samsung,syscon-phandle: phandle for system controller node for PMU.
>>
>> Example:
>>
>> @@ -37,4 +38,5 @@ Example:
>> hpd-gpio = <&gpx3 7 1>;
>> ddc = <&hdmi_ddc_node>;
>> phy = <&hdmi_phy_node>;
>> + samsung,syscon-phandle = <&pmu_system_controller>;
>> };
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 23abfa0..47b8c06 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -36,6 +36,8 @@
>> #include
>> #include
>> #include
>> +#include
>> +#include
>>
>> #include
>>
>> @@ -194,6 +196,7 @@ struct hdmi_context {
>> struct hdmi_resources res;
>>
>> int hpd_gpio;
>> + struct regmap *pmureg;
>>
>> enum hdmi_type type;
>> };
>> @@ -1853,6 +1856,9 @@ static void hdmi_poweron(struct exynos_drm_display
>> *display)
>> if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
>> DRM_DEBUG_KMS("failed to enable regulator bulk\n");
>>
>> + /* set pmu hdmiphy control bit to enable hdmiphy */
>> + regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
>> + PMU_HDMI_PHY_ENABLE_BIT, 1);
>> clk_prepare_enable(res->hdmi);
>> clk_prepare_enable(res->sclk_hdmi);
>>
>> @@ -1879,6 +1885,10 @@ static void hdmi_poweroff(struct exynos_drm_display
>> *display)
>>
>> clk_disable_unprepare(res->sclk_hdmi);
>> clk_disable_unprepare(res->hdmi);
>
>
> nit: Blank line would beautify the code a bit.
>
>> + /* reset pmu hdmiphy control bit to disable hdmiphy */
>> + regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
>> + PMU_HDMI_PHY_ENABLE_BIT, 0);
>> +
>> regulator_bulk_disable(res->regul_count, res->regul_bulk);
>>
>> pm_runtime_put_sync(hdata->dev);
>> @@ -2128,6 +2138,13 @@ static int hdmi_probe(struct platform_device *pdev)
>> goto err_hdmiphy;
>> }
>>
>> + hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
>> + "samsung,syscon-phandle");
>> + if (IS_ERR_OR_NULL(hdata->pmureg)) {
>
>
> IS_ERR() is the correct macro to check return value of this function.
>
>> + DRM_ERROR("syscon regmap lookup failed.\n");
>> + goto err_hdmiphy;
>> + }
>> +
>> pm_runtime_enable(dev);
>>
>> hdmi_display.ctx = hdata;
>> diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h
>> b/drivers/gpu/drm/exynos/regs-hdmi.h
>> index ef1b3eb..9811d6f 100644
>> --- a/drivers/gpu/drm/exynos/regs-hdmi.h
>> +++ b/drivers/gpu/drm/exynos/regs-hdmi.h
>> @@ -578,4 +578,8 @@
>> #define HDMI_TG_VACT_ST4_HHDMI_TG_BASE(0x0074)
>> #define HDMI_TG_3DHDMI_TG_BASE(0x00F0)
>>
>> +/* PMU Registers for PHY */
>> +#define PMU_HDMI_PHY_CONTROL 0x700
>> +#define PMU_HDMI_PHY_ENABLE_BIT(1<<0)
>
>
> BIT() macro could be used instead of open coding the shift.
>
> Best regards,
> Tomasz
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Re: [PATCH 1/5] drm/exynos: remove dummy hdmiphy clock from hdmi driver
Hi Tomasz,
On 10 April 2014 21:02, Tomasz Figa wrote:
> Hi Rahul,
>
> On 02.04.2014 19:13, Rahul Sharma wrote:
>>
>> From: Rahul Sharma
>>
>> Exynos drm hdmi driver used to get dummy hdmiphy clock to
>> control the PMU bit for hdmiphy. This clock is removed
>> during CCF migration. This should also be cleaned from
>> hdmi driver.
>>
>> Signed-off-by: Rahul Sharma
>> ---
>> drivers/gpu/drm/exynos/exynos_hdmi.c |8
>> 1 file changed, 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> index 25bf65a..23abfa0 100644
>> --- a/drivers/gpu/drm/exynos/exynos_hdmi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
>> @@ -74,7 +74,6 @@ struct hdmi_resources {
>> struct clk *sclk_hdmi;
>> struct clk *sclk_pixel;
>> struct clk *sclk_hdmiphy;
>> - struct clk *hdmiphy;
>> struct clk *mout_hdmi;
>> struct regulator_bulk_data *regul_bulk;
>> int regul_count;
>> @@ -1854,7 +1853,6 @@ static void hdmi_poweron(struct exynos_drm_display
>> *display)
>> if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
>> DRM_DEBUG_KMS("failed to enable regulator bulk\n");
>>
>> - clk_prepare_enable(res->hdmiphy);
>> clk_prepare_enable(res->hdmi);
>> clk_prepare_enable(res->sclk_hdmi);
>>
>> @@ -1881,7 +1879,6 @@ static void hdmi_poweroff(struct exynos_drm_display
>> *display)
>>
>> clk_disable_unprepare(res->sclk_hdmi);
>> clk_disable_unprepare(res->hdmi);
>> - clk_disable_unprepare(res->hdmiphy);
>> regulator_bulk_disable(res->regul_count, res->regul_bulk);
>>
>> pm_runtime_put_sync(hdata->dev);
>> @@ -1977,11 +1974,6 @@ static int hdmi_resources_init(struct hdmi_context
>> *hdata)
>> DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
>> goto fail;
>> }
>> - res->hdmiphy = devm_clk_get(dev, "hdmiphy");
>> - if (IS_ERR(res->hdmiphy)) {
>> - DRM_ERROR("failed to get clock 'hdmiphy'\n");
>> - goto fail;
>> - }
>> res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
>> if (IS_ERR(res->mout_hdmi)) {
>> DRM_ERROR("failed to get clock 'mout_hdmi'\n");
>>
>
> This patch makes the series non-bisectable. If you remove handling of this
> dummy clock until you add proper support for PHY isolation setting, then at
> this point you end up with non-working code.
>
> You should first provide new infrastructure in parallel to existing one,
> then move all users to new one and only then drop the old one.
>
Actually, this is dead code since CCF migration. After this patch we will get
probe success but no UI. I will take care about bisection in my series.
Currently planning to discard first 2 patches and rebase on Tomasz
Stanislawski's
1 bit phy patches.
Regards,
Rahul Sharma
> Best regards,
> Tomasz
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 03/27] ARM: EXYNOS: Add IO mapping for PMU of Exynos3250
On Thu, Apr 10, 2014 at 06:37:14PM +0900, Chanwoo Choi wrote: > This patch add memory mapping for PMU (Power Management Unit) which is used > for power control of Exynos3250. > > Signed-off-by: Chanwoo Choi > Signed-off-by: Kyungmin Park Signed-off-by is in the wrong order, if Kyungmin wrote the patch and you're just posting it... -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
On Thu, Apr 10, 2014 at 06:37:12PM +0900, Chanwoo Choi wrote:
> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses
> Cortex-A7
> dual cores and has a target speed of 1.0GHz.
>
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/mach-exynos/Kconfig | 22 ++
> arch/arm/mach-exynos/exynos.c| 1 +
> arch/arm/plat-samsung/include/plat/cpu.h | 10 ++
> 3 files changed, 33 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index fc8bf18..6da8a68 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -11,6 +11,17 @@ if ARCH_EXYNOS
>
> menu "SAMSUNG EXYNOS SoCs Support"
>
> +config ARCH_EXYNOS3
> + bool "SAMSUNG EXYNOS3"
> + select ARM_AMBA
> + select CLKSRC_OF
> + select HAVE_ARM_SCU if SMP
> + select HAVE_SMP
> + select PINCTRL
> + select PM_GENERIC_DOMAINS if PM_RUNTIME
> + help
> + Samsung EXYNOS3 SoCs based systems
> +
> config ARCH_EXYNOS4
> bool "SAMSUNG EXYNOS4"
> default y
> @@ -41,6 +52,17 @@ config ARCH_EXYNOS5
>
> comment "EXYNOS SoCs"
>
> +config SOC_EXYNOS3250
> + bool "SAMSUNG EXYNOS3250"
> + default y
> + depends on ARCH_EXYNOS3
> + select ARCH_HAS_BANDGAP
> + select ARM_CPU_SUSPEND if PM
> + select PINCTRL_EXYNOS
> + select SAMSUNG_DMADEV
> + help
> + Enable EXYNOS3250 CPU support
> +
> config CPU_EXYNOS4210
> bool "SAMSUNG EXYNOS4210"
> default y
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index b32a907..b134868 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -370,6 +370,7 @@ static void __init exynos_dt_machine_init(void)
> }
>
> static char const *exynos_dt_compat[] __initconst = {
> + "samsung,exynos3250",
Please consider samsung,exynos3 instead, so you don't have to update this table
for every SoC. We've talked about this before..
> "samsung,exynos4",
> "samsung,exynos4210",
> "samsung,exynos4212",
> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
> b/arch/arm/plat-samsung/include/plat/cpu.h
> index 5992b8d..3d808f6b 100644
> --- a/arch/arm/plat-samsung/include/plat/cpu.h
> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
> @@ -43,6 +43,9 @@ extern unsigned long samsung_cpu_id;
> #define S5PV210_CPU_ID 0x4311
> #define S5PV210_CPU_MASK 0xF000
>
> +#define EXYNOS3250_SOC_ID 0xE3472000
> +#define EXYNOS3_SOC_MASK0xF000
> +
> #define EXYNOS4210_CPU_ID0x4321
> #define EXYNOS4212_CPU_ID0x4322
> #define EXYNOS4412_CPU_ID0xE4412200
> @@ -68,6 +71,7 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
> IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
> IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
> IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
> +IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
> IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
> @@ -126,6 +130,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID,
> EXYNOS5_SOC_MASK)
> # define soc_is_s5pv210()0
> #endif
>
> +#if defined(CONFIG_SOC_EXYNOS3250)
> +# define soc_is_exynos3250()is_samsung_exynos3250()
> +#else
> +# define soc_is_exynos3250()0
> +#endif
In general, I think we have too much code littered with soc_is_() going
on, so please try to avoid adding more for this SoC. Especially in cases where
you just want to bail out of certain features where we might already have
function pointers to control if a function is called or not, such as the
firmware interfaces.
-Olof
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Re: [PATCH 04/27] ARM: EXYNOS: Support secondary CPU boot of Exynos4212
On Thu, Apr 10, 2014 at 06:37:15PM +0900, Chanwoo Choi wrote:
> From: Kyungmin Park
>
> This patch fix the offset of CPU boot address and change parameter of smc call
> of SMC_CMD_CPU1BOOT command for Exynos4212.
>
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/mach-exynos/firmware.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 932129e..91a911d 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -18,6 +18,8 @@
>
> #include
>
> +#include
> +
> #include "smc.h"
>
> static int exynos_do_idle(void)
> @@ -28,14 +30,22 @@ static int exynos_do_idle(void)
>
> static int exynos_cpu_boot(int cpu)
> {
> - exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
> + if (soc_is_exynos4212())
> + exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
> + else
> + exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
/* */
if (soc_is_exynos4212())
cpu = 0;
...and then do the call as before.
> return 0;
> }
>
> static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
> {
> - void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
> + void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
>
> + if (soc_is_exynos4212())
> + goto out;
> + else
> + boot_reg += 4*cpu;
if (!soc_is_exynos4212())
boot_reg += 4 * cpu;
That way you avoid a goto, especially since the "goto out" isn't actually
an "out", it's still doing stuff at the end of the funciton.
> +out:
> __raw_writel(boot_addr, boot_reg);
> return 0;
> }
> --
> 1.8.0
>
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Re: [PATCH 01/27] ARM: EXYNOS: Add Exynos3250 SoC ID
Hi, On 04/10/2014 06:43 PM, Arnd Bergmann wrote: > On Thursday 10 April 2014 18:28:18 Chanwoo Choi wrote: >> This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that >> is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses >> Cortex-A7 >> dual cores and has a target speed of 1.0GHz. >> >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park >> --- >> arch/arm/mach-exynos/Kconfig | 22 ++ >> arch/arm/mach-exynos/exynos.c| 1 + >> arch/arm/plat-samsung/include/plat/cpu.h | 10 ++ >> 3 files changed, 33 insertions(+) >> >> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig >> index fc8bf18..6da8a68 100644 >> --- a/arch/arm/mach-exynos/Kconfig >> +++ b/arch/arm/mach-exynos/Kconfig >> @@ -11,6 +11,17 @@ if ARCH_EXYNOS >> >> menu "SAMSUNG EXYNOS SoCs Support" >> >> +config ARCH_EXYNOS3 >> +bool "SAMSUNG EXYNOS3" >> +select ARM_AMBA >> +select CLKSRC_OF >> +select HAVE_ARM_SCU if SMP >> +select HAVE_SMP >> +select PINCTRL >> +select PM_GENERIC_DOMAINS if PM_RUNTIME >> +help >> + Samsung EXYNOS3 SoCs based systems >> + > > Isn't S5PV210 also called an Exynos3 these days? Are we going to get > any conflicts here when merging that code into Exynos as Tomasz has > suggested in the past? I knew. But, S5PV210/S5PC110 has not yet included in Exynos3 category on mainline. Need opinion of Exynos SoC Maintainer to clear this ambiguous stuff. Dear Kukjin and Tomasz, I need your opinion about this patch. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250
Hi, On 04/11/2014 04:17 AM, Tomasz Figa wrote: > Hi, > > On 10.04.2014 20:42, Linus Walleij wrote: >> On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi wrote: >> >>> From: Tomasz Figa >>> >>> This patch adds driver data (bank list and EINT layout) for Exynos3250 >>> to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional >>> input/output >>> ports. There are 23 general port groups. >>> >>> Signed-off-by: Tomasz Figa >>> Signed-off-by: Kyungmin Park >> >> Ugh can Tomasz send out his patches himself, I get confused... >> It was also sent two times, the second time with CC:s added. >> Tomasz, shall I merge this? > > I'm fine with this patch being sent by Chanwoo, although he should have > probably added his sign-off to the list, as the person sending it. > > Chanwoo, can you make sure that there is your sign-off on all the patches > from this series? > OK, I'll add my sign-off to all the patches on next posting(v2). Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On 04/10/2014 09:07 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi
> wrote:
>> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi
>>> wrote:
This patch decide proper lowpower mode of either a15 or a9 according to
own ID
from Main ID register.
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/mach-exynos/hotplug.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/hotplug.c
b/arch/arm/mach-exynos/hotplug.c
index 5eead53..36d3db6 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
int primary_part = 0;
/*
- * we're ready for shutdown now, so do it.
- * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+ * we're ready for shutdown now, so do it. Exynos4 is A9 based
+ * while Exynos5 is A15/Exynos7 is A7; check the CPU part
* number by reading the Main ID register and then perform the
* appropriate sequence for entering low power.
*/
asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>>>
>>> While you're touching that code, how about using:
>>>
>>> primary_part = read_cpuid(CPUID_ID);
>>
>> Or,
>> I suggest read_cpuid_part_number() instead of assembler directly.
>>
>> primary_part = read_cpuid_part_number();
>
> Yup, even better.
>
>>>
- if ((primary_part & 0xfff0) == 0xc0f0)
+
+ /*
+ * Main ID register of Cortex series
+ * - Cortex-a7 : 0x410F_C07x
+ * - Cortex-a15 : 0x410F_C0Fx
+ */
+ primary_part = primary_part & 0xfff0;
+ if (primary_part == 0xc0f0 || primary_part == 0xc070)
>>>
>>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>>
>> OK I'll use this defined constant as following:
>>
>> switch (primary_part)
>> case ARM_CPU_PART_CORTEX_A7:
>> case ARM_CPU_PART_CORTEX_A15:
>> cpu_enter_lowpower_a15();
>> break;
>> default:
>> cpu_enter_lowpower_a9();
>> break;
>> }
>
> Looks good.
>
Thanks for your review.
Best Regards,
Chanwoo Choi
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Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250
Hi, On 10.04.2014 20:42, Linus Walleij wrote: On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi wrote: From: Tomasz Figa This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Ugh can Tomasz send out his patches himself, I get confused... It was also sent two times, the second time with CC:s added. Tomasz, shall I merge this? I'm fine with this patch being sent by Chanwoo, although he should have probably added his sign-off to the list, as the person sending it. Chanwoo, can you make sure that there is your sign-off on all the patches from this series? Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/27] pinctrl: exynos: Add driver data for Exynos3250
On Thu, Apr 10, 2014 at 11:28 AM, Chanwoo Choi wrote: > From: Tomasz Figa > > This patch adds driver data (bank list and EINT layout) for Exynos3250 > to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional > input/output > ports. There are 23 general port groups. > > Signed-off-by: Tomasz Figa > Signed-off-by: Kyungmin Park Ugh can Tomasz send out his patches himself, I get confused... It was also sent two times, the second time with CC:s added. Tomasz, shall I merge this? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/5] drm/exynos: add support for apb mapped phys in hdmi driver
Hi Rahul,
On 02.04.2014 19:13, Rahul Sharma wrote:
From: Rahul Sharma
Previous SoCs have hdmi phys which are accessible through
dedicated i2c lines. Newer SoCs have Apb mapped hdmi phys.
Hdmi driver is modified to support apb mapped phys.
Signed-off-by: Rahul Sharma
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 142 +-
drivers/gpu/drm/exynos/regs-hdmi.h |7 ++
2 files changed, 96 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5b2cfe7..5989770 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -68,6 +69,8 @@ enum hdmi_type {
struct hdmi_driver_data {
unsigned int type;
+ const struct hdmiphy_config *phy_confs;
+ unsigned int phy_conf_count;
unsigned int is_apb_phy:1;
};
@@ -196,9 +199,12 @@ struct hdmi_context {
struct hdmi_resources res;
int hpd_gpio;
+ void __iomem*regs_hdmiphy;
struct regmap *pmureg;
enum hdmi_type type;
+ const struct hdmiphy_config *phy_confs;
+ unsigned intphy_conf_count;
};
struct hdmiphy_config {
@@ -206,14 +212,6 @@ struct hdmiphy_config {
u8 conf[32];
};
-struct hdmi_driver_data exynos4212_hdmi_driver_data = {
- .type = HDMI_TYPE14,
-};
-
-struct hdmi_driver_data exynos5_hdmi_driver_data = {
- .type = HDMI_TYPE14,
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -428,6 +426,21 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] =
{
},
};
+
+struct hdmi_driver_data exynos4212_hdmi_driver_data = {
+ .type = HDMI_TYPE14,
+ .phy_confs = hdmiphy_v14_configs,
+ .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
+ .is_apb_phy = 0,
+};
+
+struct hdmi_driver_data exynos5_hdmi_driver_data = {
+ .type = HDMI_TYPE14,
+ .phy_confs = hdmiphy_v13_configs,
+ .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
+ .is_apb_phy = 0,
+};
+
static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
{
return readl(hdata->regs + reg_id);
@@ -447,6 +460,48 @@ static inline void hdmi_reg_writemask(struct hdmi_context
*hdata,
writel(value, hdata->regs + reg_id);
}
+static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
+ u32 reg_offset, u8 value)
+{
+ if (hdata->hdmiphy_port) {
+ u8 buffer[2];
+ int ret;
+
+ buffer[0] = reg_offset;
+ buffer[1] = value;
+
+ ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
+ if (ret == 2)
+ return 0;
+ return ret;
+ } else {
+ writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
+ return 0;
+ }
+}
+
+static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
+ u32 reg_offset, const u8 *buf, u32 len)
+{
+ if ((reg_offset + len) > 32)
+ return -EINVAL;
+
+ if (hdata->hdmiphy_port) {
+ int ret;
+
+ ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
reg_offset doesn't seem to be used in I2C code path in any way. Are you
sure this is correct?
+ if (ret == len)
+ return 0;
+ return ret;
+ } else {
+ int i;
+ for (i = 0; i < len; i++)
+ writeb(buf[i], hdata->regs_hdmiphy +
+ ((reg_offset + i)<<2));
+ return 0;
+ }
+}
I wonder if those functions couldn't be abstracted as two callbacks in
hdmi_driver_data struct to eliminate such if clauses as above.
--
Best regards,
Tomasz
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Re: [PATCH 3/5] drm/exynos: remove unnecessary read for phy configuration values
On 02.04.2014 19:13, Rahul Sharma wrote:
From: Rahul Sharma
Cleaning up unnecessary i2c read call after hdmiphy configuration.
This check is redundant since check for hdmiphy pll lock status
confirms the correct settings for phy.
Signed-off-by: Rahul Sharma
Signed-off-by: Daniel Kurtz
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 47b8c06..5b2cfe7 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1518,7 +1518,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
const u8 *hdmiphy_data;
u8 buffer[32];
u8 operation[2];
- u8 read_buffer[32] = {0, };
int ret;
int i;
@@ -1558,15 +1557,6 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
return;
}
- ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
- if (ret < 0) {
- DRM_ERROR("failed to read hdmiphy config\n");
- return;
- }
-
- for (i = 0; i < ret; i++)
- DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
- "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
}
static void hdmi_conf_apply(struct hdmi_context *hdata)
Reviewed-by: Tomasz Figa
--
Best regards,
Tomasz
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Re: [PATCH 2/5] drm/exynos: use regmap interface to set hdmiphy control bit in pmu
Hi Rahul,
On 02.04.2014 19:13, Rahul Sharma wrote:
From: Rahul Sharma
Hdmiphy control bit needs to be set before setting the resolution
to hdmi hardware. This was handled using dummy hdmiphy clock which
is removed now.
PMU is already defined as system controller for exynos SoC. Registers
of PMU are accessed using regmap interfaces.
Devicetree binding document for hdmi is also updated.
Signed-off-by: Rahul Sharma
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 ++
drivers/gpu/drm/exynos/exynos_hdmi.c | 17 +
drivers/gpu/drm/exynos/regs-hdmi.h |4
3 files changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index f9187a2..243a499 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -27,6 +27,7 @@ Required properties:
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
- ddc: phandle to the hdmi ddc node
- phy: phandle to the hdmi phy node
+- samsung,syscon-phandle: phandle for system controller node for PMU.
Example:
@@ -37,4 +38,5 @@ Example:
hpd-gpio = <&gpx3 7 1>;
ddc = <&hdmi_ddc_node>;
phy = <&hdmi_phy_node>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 23abfa0..47b8c06 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -36,6 +36,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -194,6 +196,7 @@ struct hdmi_context {
struct hdmi_resources res;
int hpd_gpio;
+ struct regmap *pmureg;
enum hdmi_type type;
};
@@ -1853,6 +1856,9 @@ static void hdmi_poweron(struct exynos_drm_display
*display)
if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
DRM_DEBUG_KMS("failed to enable regulator bulk\n");
+ /* set pmu hdmiphy control bit to enable hdmiphy */
+ regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
+ PMU_HDMI_PHY_ENABLE_BIT, 1);
clk_prepare_enable(res->hdmi);
clk_prepare_enable(res->sclk_hdmi);
@@ -1879,6 +1885,10 @@ static void hdmi_poweroff(struct exynos_drm_display
*display)
clk_disable_unprepare(res->sclk_hdmi);
clk_disable_unprepare(res->hdmi);
nit: Blank line would beautify the code a bit.
+ /* reset pmu hdmiphy control bit to disable hdmiphy */
+ regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
+ PMU_HDMI_PHY_ENABLE_BIT, 0);
+
regulator_bulk_disable(res->regul_count, res->regul_bulk);
pm_runtime_put_sync(hdata->dev);
@@ -2128,6 +2138,13 @@ static int hdmi_probe(struct platform_device *pdev)
goto err_hdmiphy;
}
+ hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,syscon-phandle");
+ if (IS_ERR_OR_NULL(hdata->pmureg)) {
IS_ERR() is the correct macro to check return value of this function.
+ DRM_ERROR("syscon regmap lookup failed.\n");
+ goto err_hdmiphy;
+ }
+
pm_runtime_enable(dev);
hdmi_display.ctx = hdata;
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h
b/drivers/gpu/drm/exynos/regs-hdmi.h
index ef1b3eb..9811d6f 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -578,4 +578,8 @@
#define HDMI_TG_VACT_ST4_HHDMI_TG_BASE(0x0074)
#define HDMI_TG_3DHDMI_TG_BASE(0x00F0)
+/* PMU Registers for PHY */
+#define PMU_HDMI_PHY_CONTROL 0x700
+#define PMU_HDMI_PHY_ENABLE_BIT(1<<0)
BIT() macro could be used instead of open coding the shift.
Best regards,
Tomasz
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Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c
On 10.04.2014 16:23, Daniel Lezcano wrote: On 04/10/2014 03:57 PM, Tomasz Figa wrote: Hi Daniel, On 10.04.2014 11:55, Daniel Lezcano wrote: One more step is moving the clock ratio setting at idle time in pm.c The macro names have been changed to be consistent with the other macros name in the file. Note, the clock divider was working only when cpuidle was enabled because it was in its init routine. With this change, the clock divider is set in the pm's init routine, so it will also operate when the cpuidle driver is not set, which is good. Signed-off-by: Daniel Lezcano Reviewed-by: Viresh Kumar Reviewed-by: Bartlomiej Zolnierkiewicz Reviewed-by: Tomasz Figa --- arch/arm/mach-exynos/cpuidle.c | 54 --- arch/arm/mach-exynos/pm.c | 35 + arch/arm/mach-exynos/regs-pmu.h | 19 ++ 3 files changed, 54 insertions(+), 54 deletions(-) Sorry that I didn't mention that before, but now I recall that there was already a similar patch moving this code to Exynos5250 clock driver, which is the best place for setup of any CMU registers and a step towards removing one more static IO mapping. Yes, Bartlomiej mentioned it. Is it possible to merge this mentioned patch or to give a pointer to it so I can integrate it into the patchset ? http://marc.info/?l=linux-arm-kernel&m=138147021207626&w=2 I wonder if it still applies cleanly, though... Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/5] drm/exynos: remove dummy hdmiphy clock from hdmi driver
Hi Rahul,
On 02.04.2014 19:13, Rahul Sharma wrote:
From: Rahul Sharma
Exynos drm hdmi driver used to get dummy hdmiphy clock to
control the PMU bit for hdmiphy. This clock is removed
during CCF migration. This should also be cleaned from
hdmi driver.
Signed-off-by: Rahul Sharma
---
drivers/gpu/drm/exynos/exynos_hdmi.c |8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 25bf65a..23abfa0 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -74,7 +74,6 @@ struct hdmi_resources {
struct clk *sclk_hdmi;
struct clk *sclk_pixel;
struct clk *sclk_hdmiphy;
- struct clk *hdmiphy;
struct clk *mout_hdmi;
struct regulator_bulk_data *regul_bulk;
int regul_count;
@@ -1854,7 +1853,6 @@ static void hdmi_poweron(struct exynos_drm_display
*display)
if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
DRM_DEBUG_KMS("failed to enable regulator bulk\n");
- clk_prepare_enable(res->hdmiphy);
clk_prepare_enable(res->hdmi);
clk_prepare_enable(res->sclk_hdmi);
@@ -1881,7 +1879,6 @@ static void hdmi_poweroff(struct exynos_drm_display
*display)
clk_disable_unprepare(res->sclk_hdmi);
clk_disable_unprepare(res->hdmi);
- clk_disable_unprepare(res->hdmiphy);
regulator_bulk_disable(res->regul_count, res->regul_bulk);
pm_runtime_put_sync(hdata->dev);
@@ -1977,11 +1974,6 @@ static int hdmi_resources_init(struct hdmi_context
*hdata)
DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
goto fail;
}
- res->hdmiphy = devm_clk_get(dev, "hdmiphy");
- if (IS_ERR(res->hdmiphy)) {
- DRM_ERROR("failed to get clock 'hdmiphy'\n");
- goto fail;
- }
res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
if (IS_ERR(res->mout_hdmi)) {
DRM_ERROR("failed to get clock 'mout_hdmi'\n");
This patch makes the series non-bisectable. If you remove handling of
this dummy clock until you add proper support for PHY isolation setting,
then at this point you end up with non-working code.
You should first provide new infrastructure in parallel to existing one,
then move all users to new one and only then drop the old one.
Best regards,
Tomasz
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Re: [PATCH v2 2/2] usb: ehci-platform: Return immediately from suspend if ehci_suspend fails
On Thu, 10 Apr 2014, Vivek Gautam wrote: > Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race' > adds a check for possible race between suspend and wakeup interrupt, > and thereby it returns -EBUSY as error code if there's a wakeup > interrupt. > So the platform host controller should not proceed further with > its suspend callback, rather should return immediately to avoid > powering down the essential things, like phy. > > Signed-off-by: Vivek Gautam > Cc: Alan Stern > Cc: Hauke Mehrtens > Cc: Hans de Goede > --- > > Changes from v1: > -- Removed unnecessary change 'return 0' > > drivers/usb/host/ehci-platform.c |2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/usb/host/ehci-platform.c > b/drivers/usb/host/ehci-platform.c > index b3a0e11..c7dd93a 100644 > --- a/drivers/usb/host/ehci-platform.c > +++ b/drivers/usb/host/ehci-platform.c > @@ -303,6 +303,8 @@ static int ehci_platform_suspend(struct device *dev) > int ret; > > ret = ehci_suspend(hcd, do_wakeup); > + if (ret) > + return ret; > > if (pdata->power_suspend) > pdata->power_suspend(pdev); Acked-by: Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/2] usb: ehci-exynos: Return immediately from suspend if ehci_suspend fails
On Thu, 10 Apr 2014, Vivek Gautam wrote: > Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race' > adds a check for possible race between suspend and wakeup interrupt, > and thereby it returns -EBUSY as error code if there's a wakeup > interrupt. > So the platform host controller should not proceed further with > its suspend callback, rather should return immediately to avoid > powering down the essential things, like phy. > > Signed-off-by: Vivek Gautam > Acked-by: Jingoo Han > Cc: Alan Stern > --- > > Changes from v1: > -- Removed unnecessary change 'return 0' > > drivers/usb/host/ehci-exynos.c |2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c > index d1d8c47..7f425ac 100644 > --- a/drivers/usb/host/ehci-exynos.c > +++ b/drivers/usb/host/ehci-exynos.c > @@ -212,6 +212,8 @@ static int exynos_ehci_suspend(struct device *dev) > int rc; > > rc = ehci_suspend(hcd, do_wakeup); > + if (rc) > + return rc; > > if (exynos_ehci->otg) > exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self); Acked-by: Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c
On 04/10/2014 03:57 PM, Tomasz Figa wrote:
Hi Daniel,
On 10.04.2014 11:55, Daniel Lezcano wrote:
One more step is moving the clock ratio setting at idle time in pm.c
The macro names have been changed to be consistent with the other macros
name in the file.
Note, the clock divider was working only when cpuidle was enabled
because it
was in its init routine. With this change, the clock divider is set in
the pm's
init routine, so it will also operate when the cpuidle driver is not
set, which
is good.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 54
---
arch/arm/mach-exynos/pm.c | 35 +
arch/arm/mach-exynos/regs-pmu.h | 19 ++
3 files changed, 54 insertions(+), 54 deletions(-)
Sorry that I didn't mention that before, but now I recall that there was
already a similar patch moving this code to Exynos5250 clock driver,
which is the best place for setup of any CMU registers and a step
towards removing one more static IO mapping.
Yes, Bartlomiej mentioned it.
Is it possible to merge this mentioned patch or to give a pointer to it
so I can integrate it into the patchset ?
Also one more thing below.
[ ... ]
{
#ifdef CONFIG_CACHE_L2X0
@@ -244,6 +276,9 @@ static void exynos_pm_resume(void)
s3c_pm_do_restore_core(exynos_core_save,
ARRAY_SIZE(exynos_core_save));
+if (soc_is_exynos5250())
+exynos5_core_down_clk();
+
Originally this code was executed at system boot-up, but now it is
happening on resume from sleep. Is this change desired?
Argh ! Sounds like I got a bad fuzz there.
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Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c
Hi Daniel,
On 10.04.2014 11:55, Daniel Lezcano wrote:
One more step is moving the clock ratio setting at idle time in pm.c
The macro names have been changed to be consistent with the other macros
name in the file.
Note, the clock divider was working only when cpuidle was enabled because it
was in its init routine. With this change, the clock divider is set in the pm's
init routine, so it will also operate when the cpuidle driver is not set, which
is good.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 54 ---
arch/arm/mach-exynos/pm.c | 35 +
arch/arm/mach-exynos/regs-pmu.h | 19 ++
3 files changed, 54 insertions(+), 54 deletions(-)
Sorry that I didn't mention that before, but now I recall that there was
already a similar patch moving this code to Exynos5250 clock driver,
which is the best place for setup of any CMU registers and a step
towards removing one more static IO mapping.
Also one more thing below.
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ce31004..97a441f 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -39,25 +39,6 @@
#define S5P_CHECK_AFTR0xFCBA0D10
-#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020)
-#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE(1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE(1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI(1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI(1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
-
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(void)
{
@@ -127,38 +108,6 @@ static int exynos_enter_lowpower(struct cpuidle_device
*dev,
return exynos_enter_core0_aftr(dev, drv, new_index);
}
-static void __init exynos5_core_down_clk(void)
-{
- unsigned int tmp;
-
- /*
-* Enable arm clock down (in idle) and set arm divider
-* ratios in WFI/WFE state.
-*/
- tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
- PWR_CTRL1_CORE1_DOWN_RATIO | \
- PWR_CTRL1_DIV2_DOWN_EN | \
- PWR_CTRL1_DIV1_DOWN_EN | \
- PWR_CTRL1_USE_CORE1_WFE| \
- PWR_CTRL1_USE_CORE0_WFE| \
- PWR_CTRL1_USE_CORE1_WFI| \
- PWR_CTRL1_USE_CORE0_WFI;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
- /*
-* Enable arm clock up (on exiting idle). Set arm divider
-* ratios when not in idle along with the standby duration
-* ratios.
-*/
- tmp = PWR_CTRL2_DIV2_UP_EN | \
- PWR_CTRL2_DIV1_UP_EN | \
- PWR_CTRL2_DUR_STANDBY2_VAL | \
- PWR_CTRL2_DUR_STANDBY1_VAL | \
- PWR_CTRL2_CORE2_UP_RATIO | \
- PWR_CTRL2_CORE1_UP_RATIO;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
static struct cpuidle_driver exynos_idle_driver = {
.name = "exynos_idle",
.owner = THIS_MODULE,
@@ -181,9 +130,6 @@ static int exynos_cpuidle_probe(struct platform_device
*pdev)
{
int ret;
- if (soc_is_exynos5250())
- exynos5_core_down_clk();
-
if (soc_is_exynos5440())
exynos_idle_driver.state_count = 1;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 9773a00..c4138bf 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -140,6 +140,38 @@ static void exynos_cpu_restore_register(void)
: "cc");
}
+static void __init exynos5_core_down_clk(void)
+{
+ unsigned int tmp;
+
+ /*
+* Enable arm clock down (in idle) and set arm divider
+* ratios in WFI/WFE state.
+*/
+ tmp = EXYNOS5_PWR_CTRL1_CORE2_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_CORE1_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_DIV2_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_DIV1_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE0_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFI| \
+
[PATCH] usb: ohci-exynos: Add facility to use phy provided by the generic phy framework
Add support to consume phy provided by Generic phy framework.
Keeping the support for older usb-phy intact right now, in order
to prevent any functionality break in absence of relevant
device tree side change for ohci-exynos.
Once we move to new phy in the device nodes for ohci, we can
remove the support for older phys.
Signed-off-by: Vivek Gautam
Cc: Jingoo Han
Cc: Alan Stern
---
Based on 'usb-next' branch of Greg's usb tree.
Tested with local dt patches, similar to ehci dt changes posted by Kamil[1].
Tested on Exynos5250 smdk.
[1] [PATCH v6 4/8] dts: Add usb2phy to Exynos 5250
https://lkml.org/lkml/2014/1/29/302
.../devicetree/bindings/usb/exynos-usb.txt | 14
drivers/usb/host/ohci-exynos.c | 79 ++--
2 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index d967ba1..ef0bc09 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -38,6 +38,10 @@ Required properties:
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
+ - port: if in the SoC there are OHCI phys, they should be listed here.
+One phy per port. Each port should have its reg entry with a consecutive
+number. Also it should contain phys and phy-names entries specifying the
+phy used by the port.
Example:
usb@1212 {
@@ -47,6 +51,16 @@ Example:
clocks = <&clock 285>;
clock-names = "usbhost";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ phys = <&usb2phy 1>;
+ phy-names = "host";
+ status = "disabled";
+ };
+
};
DWC3
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 68588d8..52eb821 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,6 +38,7 @@ struct exynos_ohci_hcd {
struct clk *clk;
struct usb_phy *phy;
struct usb_otg *otg;
+ struct phy *phy_g;
};
static void exynos_ohci_phy_enable(struct platform_device *pdev)
@@ -57,12 +59,26 @@ static void exynos_ohci_phy_disable(struct platform_device
*pdev)
usb_phy_shutdown(exynos_ohci->phy);
}
+static int exynos_ohci_phyg_on(struct phy *phy, bool on)
+{
+ int ret = 0;
+
+ if (phy) {
+ if (on)
+ ret = phy_power_on(phy);
+ else
+ ret = phy_power_off(phy);
+ }
+
+ return ret;
+}
+
static int exynos_ohci_probe(struct platform_device *pdev)
{
struct exynos_ohci_hcd *exynos_ohci;
struct usb_hcd *hcd;
struct resource *res;
- struct usb_phy *phy;
+ struct device_node *child;
int irq;
int err;
@@ -88,16 +104,49 @@ static int exynos_ohci_probe(struct platform_device *pdev)
"samsung,exynos5440-ohci"))
goto skip_phy;
- phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(phy)) {
- usb_put_hcd(hcd);
- dev_warn(&pdev->dev, "no platform data or transceiver
defined\n");
- return -EPROBE_DEFER;
+ exynos_ohci->phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(exynos_ohci->phy)) {
+ err = PTR_ERR(exynos_ohci->phy);
+ if (err == -ENXIO || err == -ENODEV) {
+ exynos_ohci->phy = NULL;
+ } else if (err == -EPROBE_DEFER) {
+ usb_put_hcd(hcd);
+ return err;
+ } else {
+ dev_err(&pdev->dev, "no usb2 phy configured\n");
+ usb_put_hcd(hcd);
+ return err;
+ }
} else {
- exynos_ohci->phy = phy;
- exynos_ohci->otg = phy->otg;
+ exynos_ohci->otg = exynos_ohci->phy->otg;
}
+ /* Getting generic phy:
+* We are keeping both types of phys as a part of transiting OHCI
+* to generic phy framework, so that in absence of supporting dts
+* changes the functionality doesn't break.
+* Once we move the ohci dt nodes to use new generic phys,
+* we can remove support for older PHY in this driver.
+*/
+ child = of_get_next_child(pdev->dev.of_node, NULL);
+ exynos_ohci->phy_g = devm_of_phy_get(&pdev->dev, child, 0);
+ of_node_put(child);
+ if (IS_ERR(exynos_ohci->phy_g)) {
+ err = PTR_ERR(exynos_ohci->phy_g);
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10, 2014 at 11:04:59AM +0100, Marc Zyngier wrote: > On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi > wrote: > > This patch declare coretex-a7's irqchip to initialze gic from dt > > with "arm,cortex-a7-gic" data. > > > > Cc: Thomas Gleixner > > Signed-off-by: Chanwoo Choi > > Signed-off-by: Kyungmin Park > > --- > > drivers/irqchip/irq-gic.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > > index 4300b66..8e906e4 100644 > > --- a/drivers/irqchip/irq-gic.c > > +++ b/drivers/irqchip/irq-gic.c > > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct > > device_node *parent) > > } > > IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); > > IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); > > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); > > IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); > > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); > > Frankly, this patch adds no value. Are we going to add > "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", > "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... > > Instead, how about defining a generic "arm,gic" property, and mandate > that new DT files are using that? We can always use a more precise > compatible for quirks. Nit: s/property/compatible/ As mentioned elsewhere, "arm,gic-v2" would seem to fit the bill (and we can have "arm,gic" or "arm,gic-v1" for v1). > Mark, what do you think? I think this has been discussed in the past > already. It's been repeatedly brought up and agreed on, it's just that no-one's implemented it. I agree that having an "arm,gic-v2" binding that people can place in their compatible list is a sensible thing to do, and I'd be happy to Ack patches implementing it. Cheers, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] ARM: dts: Fix SPI interrupt numbers for Exynos5420
Updated as per the user manual.
Signed-off-by: Sachin Kamat
---
arch/arm/boot/dts/exynos5420.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..6f662b5cc90d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -385,7 +385,7 @@
spi_0: spi@12d2 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d2 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <0 68 0>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -401,7 +401,7 @@
spi_1: spi@12d3 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d3 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <0 69 0>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -417,7 +417,7 @@
spi_2: spi@12d4 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d4 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 70 0>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
--
1.7.9.5
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Re: [PATCH v12 1/4] thermal: samsung: replace inten_ bit fields with intclr_
Hi,
Zhang, could you please review/merge this patchset?
[ We have been waiting for a review for over 3 months now.. ]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
On Friday, February 07, 2014 03:03:46 PM Naveen Krishna Ch wrote:
> Hello All,
>
> On 2 January 2014 08:03, Zhang Rui wrote:
> > On Thu, 2013-12-19 at 11:35 +0530, Naveen Krishna Chatradhi wrote:
> >> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> >> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> >> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only
> >> used
> >> to configure intclr related registers.
> >>
> >> Description of H/W:
> >> The offset for the bits in the CLEAR register are not consistent across TMU
> >> modules in Exynso5250, 5420 and 5440.
> >>
> >> On Exynos5250, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT registers and at an offset of
> >> 12 in INTCLEAR register.
> >>
> >> On Exynos5420, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT and INTCLEAR registers.
> >>
> >> On Exynos5440,
> >> the FALL_IRQEN bits are at an offset of 4
> >> and the RISE_IRQEN bits are at an offset of 0
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi
> >> Acked-by: Amit Daniel Kachhap
> >> Reviewed-by: Bartlomiej Zolnierkiewicz
> >> Reviewed-by: Tomasz Figa
> >
> > Eduardo,
> >
> > what do you think of this patch set?
> >
> > thanks,
> > rui
> >> ---
> >> Changes since v11:
> >> Added Reviewed by Tomasz
> >>
> >> Changes since v10:
> >> None
> >>
> >> drivers/thermal/samsung/exynos_tmu.c |6 +++---
> >> drivers/thermal/samsung/exynos_tmu.h | 16
> >> drivers/thermal/samsung/exynos_tmu_data.c | 18 +-
> >> drivers/thermal/samsung/exynos_tmu_data.h |4 ++--
> >> 4 files changed, 22 insertions(+), 22 deletions(-)
> >>
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.c
> >> b/drivers/thermal/samsung/exynos_tmu.c
> >> index 32f38b9..c493245 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu.c
> >> @@ -237,7 +237,7 @@ skip_calib_data:
> >> writeb(pdata->trigger_levels[i], data->base +
> >> reg->threshold_th0 + i * sizeof(reg->threshold_th0));
> >>
> >> - writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
> >> + writel(reg->intclr_rise_mask, data->base +
> >> reg->tmu_intclear);
> >> } else {
> >> /* Write temperature code for rising and falling threshold */
> >> for (i = 0;
> >> @@ -264,8 +264,8 @@ skip_calib_data:
> >> writel(falling_threshold,
> >> data->base + reg->threshold_th1);
> >>
> >> - writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> >> - (reg->inten_fall_mask << reg->inten_fall_shift),
> >> + writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
> >> + (reg->intclr_fall_mask << reg->intclr_fall_shift),
> >> data->base + reg->tmu_intclear);
> >>
> >> /* if last threshold limit is also present */
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.h
> >> b/drivers/thermal/samsung/exynos_tmu.h
> >> index 3fb6554..980859a 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu.h
> >> @@ -122,10 +122,6 @@ enum soc_type {
> >> * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
> >> * @tmu_inten: register containing the different threshold interrupt
> >> enable bits.
> >> - * @inten_rise_shift: shift bits of all rising interrupt bits.
> >> - * @inten_rise_mask: mask bits of all rising interrupt bits.
> >> - * @inten_fall_shift: shift bits of all rising interrupt bits.
> >> - * @inten_fall_mask: mask bits of all rising interrupt bits.
> >> * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
> >> * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
> >> * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
> >> @@ -136,6 +132,10 @@ enum soc_type {
> >> * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
> >> * @tmu_intstat: Register containing the interrupt status values.
> >> * @tmu_intclear: Register for clearing the raised interrupt status.
> >> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> >> + * @intclr_rise_shift: shift bits of all rising interrupt bits.
> >> + * @intclr_rise_mask: mask bits of all rising interrupt bits.
> >> + * @intclr_fall_mask: mask bits of all rising interrupt bits.
> >> * @emul_con: TMU emulation controller register.
> >> * @emul_temp_shift: shift bits of emulation temperature.
> >> * @emul_time_shift: shift bits of emulation time.
> >>
Re: [PATCH 2/6] ARM: EXYNOS: Staticize exynos_subsys
On 10 April 2014 18:02, Tomasz Figa wrote:
> On 10.04.2014 11:22, Sachin Kamat wrote:
>>
>> Hi Tomasz,
>>
>> On 10 April 2014 14:47, Tomasz Figa wrote:
>>>
>>> Hi Sachin,
>>>
>>>
>>> On 10.04.2014 10:24, Sachin Kamat wrote:
'exynos_subsys' is now local to this file. Make it static
and remove the declaration from header file.
Signed-off-by: Sachin Kamat
---
arch/arm/mach-exynos/exynos.c|2 +-
arch/arm/plat-samsung/include/plat/cpu.h |1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c
b/arch/arm/mach-exynos/exynos.c
index 6a5fe18ec9b1..0ef42b9efd36 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -284,7 +284,7 @@ void __init exynos_init_io(void)
of_scan_flat_dt(exynos_fdt_map_sysram, NULL);
}
-struct bus_type exynos_subsys = {
+static struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8dd9b89..930b4be832cd 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -239,7 +239,6 @@ extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5p64x0_subsys;
extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos_subsys;
extern void (*s5pc1xx_idle)(void);
>>>
>>> This struct and registration of it do not seem to be needed for anything
>>> anymore. Would you consider removing it instead?
>>
>>
>> I had considered removing that while I was doing other code consolidation
>> of this file. However I found that without this, the system failed to
>> boot. I
>> did not look much into it then. Probably I can revisit it and if it
>> doesn't cause
>> any boot issue, will remove it.
>>
>
> Hmm, I don't see why it could break anything as I can't find any users of
> it. Anyway I just tested removing this code on Exynos4412-trats2 board and
> didn't find any problems.
Thanks for testing. Let me check at my end on other boards and if it
doesn't cause
any problem, will remove this.
--
With warm regards,
Sachin
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Re: [PATCH 2/6] ARM: EXYNOS: Staticize exynos_subsys
On 10.04.2014 11:22, Sachin Kamat wrote:
Hi Tomasz,
On 10 April 2014 14:47, Tomasz Figa wrote:
Hi Sachin,
On 10.04.2014 10:24, Sachin Kamat wrote:
'exynos_subsys' is now local to this file. Make it static
and remove the declaration from header file.
Signed-off-by: Sachin Kamat
---
arch/arm/mach-exynos/exynos.c|2 +-
arch/arm/plat-samsung/include/plat/cpu.h |1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6a5fe18ec9b1..0ef42b9efd36 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -284,7 +284,7 @@ void __init exynos_init_io(void)
of_scan_flat_dt(exynos_fdt_map_sysram, NULL);
}
-struct bus_type exynos_subsys = {
+static struct bus_type exynos_subsys = {
.name = "exynos-core",
.dev_name = "exynos-core",
};
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8dd9b89..930b4be832cd 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -239,7 +239,6 @@ extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
extern struct bus_type s5p64x0_subsys;
extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos_subsys;
extern void (*s5pc1xx_idle)(void);
This struct and registration of it do not seem to be needed for anything
anymore. Would you consider removing it instead?
I had considered removing that while I was doing other code consolidation
of this file. However I found that without this, the system failed to boot. I
did not look much into it then. Probably I can revisit it and if it
doesn't cause
any boot issue, will remove it.
Hmm, I don't see why it could break anything as I can't find any users
of it. Anyway I just tested removing this code on Exynos4412-trats2
board and didn't find any problems.
Best regards,
Tomasz
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Re: [PATCH] thermal: offer Samsung thermal support only when ARCH_EXYNOS is defined
Hi, Zhang, could you please pick this patch up to your tree? [ Eduardos's tree hasn't been updated for over 4 months and seems to be dead.. ] Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics On Tuesday, November 26, 2013 09:22:31 AM Eduardo Valentin wrote: > On 26-11-2013 02:07, Amit Kachhap wrote: > > On 10/4/13, Bartlomiej Zolnierkiewicz wrote: > >> Menu for Samsung thermal support is visible on all Samsung > >> platforms while thermal drivers are currently available only > >> for EXYNOS SoCs. Fix it by replacing PLAT_SAMSUNG dependency > >> with ARCH_EXYNOS one. > >> > >> Signed-off-by: Bartlomiej Zolnierkiewicz > >> Signed-off-by: Kyungmin Park > > Looks good, so > > Acked-by: Amit Daniel Kachhap > > I will be queuing this one in my tree. > > Thanks Bartlomiej. > > > > >> --- > >> drivers/thermal/Kconfig | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > >> index a709c63..05cf95c 100644 > >> --- a/drivers/thermal/Kconfig > >> +++ b/drivers/thermal/Kconfig > >> @@ -198,7 +198,7 @@ source "drivers/thermal/ti-soc-thermal/Kconfig" > >> endmenu > >> > >> menu "Samsung thermal drivers" > >> -depends on PLAT_SAMSUNG > >> +depends on ARCH_EXYNOS > >> source "drivers/thermal/samsung/Kconfig" > >> endmenu > >> > >> -- > >> 1.8.2.3 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On Thu, Apr 10 2014 at 11:56:33 am BST, Chanwoo Choi
wrote:
> On 04/10/2014 06:51 PM, Marc Zyngier wrote:
>> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi
>> wrote:
>>> This patch decide proper lowpower mode of either a15 or a9 according to own
>>> ID
>>> from Main ID register.
>>>
>>> Signed-off-by: Chanwoo Choi
>>> Signed-off-by: Kyungmin Park
>>> ---
>>> arch/arm/mach-exynos/hotplug.c | 13 ++---
>>> 1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>>> index 5eead53..36d3db6 100644
>>> --- a/arch/arm/mach-exynos/hotplug.c
>>> +++ b/arch/arm/mach-exynos/hotplug.c
>>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>>> int primary_part = 0;
>>>
>>> /*
>>> -* we're ready for shutdown now, so do it.
>>> -* Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>>> +* we're ready for shutdown now, so do it. Exynos4 is A9 based
>>> +* while Exynos5 is A15/Exynos7 is A7; check the CPU part
>>> * number by reading the Main ID register and then perform the
>>> * appropriate sequence for entering low power.
>>> */
>>> asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>>
>> While you're touching that code, how about using:
>>
>> primary_part = read_cpuid(CPUID_ID);
>
> Or,
> I suggest read_cpuid_part_number() instead of assembler directly.
>
> primary_part = read_cpuid_part_number();
Yup, even better.
>>
>>> - if ((primary_part & 0xfff0) == 0xc0f0)
>>> +
>>> + /*
>>> +* Main ID register of Cortex series
>>> +* - Cortex-a7 : 0x410F_C07x
>>> +* - Cortex-a15 : 0x410F_C0Fx
>>> +*/
>>> + primary_part = primary_part & 0xfff0;
>>> + if (primary_part == 0xc0f0 || primary_part == 0xc070)
>>
>> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
>
> OK I'll use this defined constant as following:
>
> switch (primary_part)
> case ARM_CPU_PART_CORTEX_A7:
> case ARM_CPU_PART_CORTEX_A15:
> cpu_enter_lowpower_a15();
> break;
> default:
> cpu_enter_lowpower_a9();
> break;
> }
Looks good.
M.
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Re: [PATCH V4 1/5] phy: Add new Exynos5 USB 3.0 PHY driver
On Wed, Apr 9, 2014 at 7:03 PM, Tomasz Figa wrote:
> On 09.04.2014 13:49, Vivek Gautam wrote:
>>
>> Hi,
>>
>>
>> On Wed, Apr 9, 2014 at 4:36 PM, Tomasz Figa wrote:
>>>
>>> Hi Vivek,
>>>
>>> Please see my comments inline.
>>>
>>>
>>> On 08.04.2014 16:36, Vivek Gautam wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Thereby, removing old phy-samsung-usb3 driver and related code
used untill now which was based on usb/phy framework.
Signed-off-by: Vivek Gautam
---
.../devicetree/bindings/phy/samsung-phy.txt| 42 ++
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
drivers/phy/phy-exynos5-usbdrd.c | 668
4 files changed, 722 insertions(+)
create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
>>>
>>>
>>>
>>> [snip]
>>>
>>>
+ Additional clock required for Exynos5420:
+ - usb30_sclk_100m: Additional special clock used for PHY
operation
+ depicted as 'sclk_usbphy30' in CMU of
Exynos5420.
>>>
>>>
>>>
>>> Are you sure this isn't simply a gate for the ref clock, as it can be
>>> found
>>> on another SoC that is not upstream yet? I don't have documentation for
>>> Exynos 5420 so I can't tell, but I'd like to ask you to recheck this.
>>
>>
>>> From what i can see in the manual :
>>
>> sclk_usbphy30 is derived from OSCCLK.
>> It is coming from a MUX (default input line to this is OSCCLK) and
>> then through a DIV
>> there's this gate.
>>
>>{OSCCLK + other sources} --->[MUX] ---> [DIV] --> [GATE for
>> sclk_usbphy30]
>>
>> the {rate of sclk_usbphy30} == OSCCLK
>>
>> However the 'ref' clock that we have been using is the actual oscillator
>> clock.
>> And on SoC Exynos5250, we don't have any such gate (sclk_usbphy30).
>> So should this mean that ref clock and sclk_usbphy30 are still be
>> controlled by
>> two different gates ?
>>
>
> Is there maybe a diagram of PHY input clocks in the datasheet, like for USB
> 2.0 PHY in Exynos4210/4412/5250 datasheets in the chapter about USB2.0
> Device? Something like:
>
>
> ||
> | ___|
> XusbXTI | Phy_fsel[2:0]| ___ |
>___[X]___|| __|_|___|\__|_|
> | | _v___ | _ ^ | |/ | |
> _ | | || | | | | ___ | |
> ___| | || | | | | | |_|_|
> |___| | | X 0 ||_| PLL |__|_|_|CLK|_|_|
> _ | | | | || |DIV|_|_|
> |___[X] | |_| 12 |_|480 | |___| | |
> | MHz MHz |Digital| |
> XusbXTO | USB PHY|___| |
> ||
>
>
Below is the block diagram given for DRD controller.
___
||
| |
| | PHY | |
| | controller |-|---
| |__ | | |
||
|
| USB 3.0 | V
| DRD |
---
|Controller | |
|
||USB30_SCLK_100M| USB 3.0 DRD |
| | --->
| PHY |
| | Link cont. | | |
|
| - |
| |
|___| |_|
Does this help ?
So, USB30_SCLK_100M is the SCLK that we are talking in the driver. I
don't see any reference to XXTI in the USB 3.0 DRD controller chapter
(in both Exynos5250 and 5420)
In addition to this there's one more point to be noticed here.
On Exynos5420 system, the sclk_usbphy300 (which is the sclk_usbphy30
for USB DRD channel 0), is also the PICO phy clock, i.e. USB 2.0 phy
clock.
So we should add a similar clk_get() for this clock in the
phy-exynos5250-usb2 driver too, to support Exynos5420.
>
> Best regards,
> Tomasz
> --
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> the body of a message to majord...@vger.kernel.org
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--
Best Regards
Vivek Gautam
Samsung R&D Institu
Re: [PATCH 21/27] ARM: dts: exynos3250: Add PMU dt data
Hi,
On 04/10/2014 07:23 PM, Chanho Park wrote:
> Hi,
>
>> -Original Message-
>> From: linux-arm-kernel [mailto:linux-arm-kernel-
>> boun...@lists.infradead.org] On Behalf Of Chanwoo Choi
>> Sent: Thursday, April 10, 2014 7:06 PM
>> To: kgene@samsung.com; t.f...@samsung.com; linux-samsung-
>> s...@vger.kernel.org
>> Cc: hyunhee@samsung.com; sw0312@samsung.com; linux-
>> ker...@vger.kernel.org; yj44@samsung.com; inki@samsung.com;
>> cw00.c...@samsung.com; kyungmin.p...@samsung.com; linux-arm-
>> ker...@lists.infradead.org
>> Subject: [PATCH 21/27] ARM: dts: exynos3250: Add PMU dt data
>>
>> From: Hyunhee Kim
>>
>> ARM CPU has its own PMU (Performance Monitoring Unit). This patch add
>> PMU dt
>> data to support PMU for CPU. Exynos3250 has four PMU interrupts.
>>
>> Signed-off-by: Hyunhee Kim
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/boot/dts/exynos3250.dtsi | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
>> b/arch/arm/boot/dts/exynos3250.dtsi
>> index ceed761..2f0ca32 100644
>> --- a/arch/arm/boot/dts/exynos3250.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250.dtsi
>> @@ -280,4 +280,9 @@
>> pinctrl-0 = <&i2c7_bus>;
>> status = "disabled";
>> };
>> +
>> +pmu {
>> +compatible = "arm,cortex-a7-pmu";
>> +interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
>> +};
>
> As I know, the exynos3250 has two CPU cores. Why does it have four pmu
> interrupts?
> IMO it is sufficient it has only two interrupts.
OK, I'll fix it using only two interrupt for dual-core.
Best Regards,
Chanwoo Choi
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Re: [PATCH] phy: exynos5-usbdrd: Add facility to toggle vbus gpio on/off
Hi, On Wed, Apr 9, 2014 at 6:08 PM, Tomasz Figa wrote: > Hi, > > > On 09.04.2014 14:24, Vivek Gautam wrote: >> >> Hi Sylwester, >> >> >> On Wed, Apr 9, 2014 at 5:41 PM, Sylwester Nawrocki >> wrote: >>> >>> Hi Vivek, >>> >>> On 09/04/14 13:54, Vivek Gautam wrote: Adding support to enable/disable VBUS hooked to a gpio to enable vbus supply on the port. >>> >>> >>> Does the GPIO control a fixed voltage regulator ? If so, shouldn't >>> it be modelled by the regulator API instead ? >> >> >> No, this GPIO controls a 'current limiting power distribution switch', >> which gives the output vbus to usb controller. >> Should i model this as a fixed regulator ? > > > If I understand this correctly, this is just a switch that lets you control > whether vbus is provided to the USB connector or not. If so, this doesn't > look like an Exynos-specific thing at all and should rather be modeled on > higher level. You are right. The Vbus to the USB connector is given through this a switch which current limiting capabilities. This switch just provides the 5V at its input to its output based on the state of Enable pin (which is the GPIO we are talking in this patch). So can you please suggest on how this should be handled ? > > Best regards, > Tomasz > -- > To unsubscribe from this list: send the line "unsubscribe linux-usb" in > > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On 04/10/2014 06:51 PM, Marc Zyngier wrote:
> On Thu, Apr 10 2014 at 10:28:23 am BST, Chanwoo Choi
> wrote:
>> This patch decide proper lowpower mode of either a15 or a9 according to own
>> ID
>> from Main ID register.
>>
>> Signed-off-by: Chanwoo Choi
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/mach-exynos/hotplug.c | 13 ++---
>> 1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
>> index 5eead53..36d3db6 100644
>> --- a/arch/arm/mach-exynos/hotplug.c
>> +++ b/arch/arm/mach-exynos/hotplug.c
>> @@ -135,13 +135,20 @@ void __ref exynos_cpu_die(unsigned int cpu)
>> int primary_part = 0;
>>
>> /*
>> - * we're ready for shutdown now, so do it.
>> - * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
>> + * we're ready for shutdown now, so do it. Exynos4 is A9 based
>> + * while Exynos5 is A15/Exynos7 is A7; check the CPU part
>> * number by reading the Main ID register and then perform the
>> * appropriate sequence for entering low power.
>> */
>> asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
>
> While you're touching that code, how about using:
>
> primary_part = read_cpuid(CPUID_ID);
Or,
I suggest read_cpuid_part_number() instead of assembler directly.
primary_part = read_cpuid_part_number();
>
>> -if ((primary_part & 0xfff0) == 0xc0f0)
>> +
>> +/*
>> + * Main ID register of Cortex series
>> + * - Cortex-a7 : 0x410F_C07x
>> + * - Cortex-a15 : 0x410F_C0Fx
>> + */
>> +primary_part = primary_part & 0xfff0;
>> +if (primary_part == 0xc0f0 || primary_part == 0xc070)
>
> ARM_CPU_PART_CORTEX_A15, ARM_CPU_PART_CORTEX_A7
OK I'll use this defined constant as following:
switch (primary_part)
case ARM_CPU_PART_CORTEX_A7:
case ARM_CPU_PART_CORTEX_A15:
cpu_enter_lowpower_a15();
break;
default:
cpu_enter_lowpower_a9();
break;
}
>
>> cpu_enter_lowpower_a15();
>> else
>> cpu_enter_lowpower_a9();
>
Best Regards,
Chanwoo Choi
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Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:42:56 am BST, armdev wrote: > On 10-Apr-2014, at 4:11 pm, Marc Zyngier wrote: > >> On Thu, Apr 10 2014 at 11:30:41 am BST, armdev wrote: >>> On 10-Apr-2014, at 3:51 pm, Marc Zyngier wrote: >>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev wrote: > On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: > >> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi >> wrote: >>> This patch declare coretex-a7's irqchip to initialze gic from dt >>> with "arm,cortex-a7-gic" data. >>> >>> Cc: Thomas Gleixner >>> Signed-off-by: Chanwoo Choi >>> Signed-off-by: Kyungmin Park >>> --- >>> drivers/irqchip/irq-gic.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >>> index 4300b66..8e906e4 100644 >>> --- a/drivers/irqchip/irq-gic.c >>> +++ b/drivers/irqchip/irq-gic.c >>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct >>> device_node *parent) >>> } >>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); >>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); >>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); >>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); >>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); >> >> Frankly, this patch adds no value. Are we going to add >> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", >> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... >> >> Instead, how about defining a generic "arm,gic" property, and mandate >> that new DT files are using that? We can always use a more precise >> compatible for quirks. >> > > How about keeping it simple and tied to arm gic versions > arm,gicv1, arm,gicv2, arm,gicv2ve That's a variation on the same theme. As for GICv2, we don't need to distinguish between having the Virtualization Extentions, the binding already allows you to tell one from the other. >>> So if there be just 2 types of gic, it would be simple. >> >> Not exactly. We just happen to support two revisions of the GIC >> architecture with the same binding. GICv3 has an entierely separate >> binding. >> >>> gicv1 - 2 address sets (gicc and gicd) >> >> Yes. >> >>> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? >> >> No. >> >> The presence of the GICV, GICH and maintenance interrupt are indicative >> of the support for the Virtualization Extentions. GICv2 itself can >> perfectly be built without it. > > then does gicv2-ve makes sense ? Read what I just wrote. You find the GICV region, you have the VE extensions. You don't find them, they are not present. No need for an overloaded compatible string, they both conform to the same *Architecture Spec*. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:37:12 am BST, Chanho Park wrote: > Hi, > >> -Original Message- >> From: linux-arm-kernel [mailto:linux-arm-kernel- >> boun...@lists.infradead.org] On Behalf Of Marc Zyngier >> Sent: Thursday, April 10, 2014 7:05 PM >> To: Chanwoo Choi >> Cc: mark.rutl...@arm.com; linux-samsung-soc@vger.kernel.org; >> t.f...@samsung.com; hyunhee@samsung.com; sw0312@samsung.com; >> linux-ker...@vger.kernel.org; yj44@samsung.com; inki@samsung.com; >> kyungmin.p...@samsung.com; kgene@samsung.com; Thomas Gleixner; >> linux-arm-ker...@lists.infradead.org >> Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to >> initialize gic from dt >> >> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi >> wrote: >> > This patch declare coretex-a7's irqchip to initialze gic from dt >> > with "arm,cortex-a7-gic" data. >> > >> > Cc: Thomas Gleixner >> > Signed-off-by: Chanwoo Choi >> > Signed-off-by: Kyungmin Park >> > --- >> > drivers/irqchip/irq-gic.c | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >> > index 4300b66..8e906e4 100644 >> > --- a/drivers/irqchip/irq-gic.c >> > +++ b/drivers/irqchip/irq-gic.c >> > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct >> device_node *parent) >> > } >> > IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); >> > IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); >> > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); >> > IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); >> > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); >> >> Frankly, this patch adds no value. Are we going to add >> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", >> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... >> >> Instead, how about defining a generic "arm,gic" property, and mandate >> that new DT files are using that? We can always use a more precise >> compatible for quirks. > > I prefer it would be arm,gicv2 instead arm-gic. If you prefer, fine by me. Consider spelling it "arm,gic-v2", which seems to be the current convention for version numbers. > In case of GICv3 of arm64, it can be arm,gicv3. GICv3 and arm64 are independent of each other, and the binding has already been specified as "arm,gic-v3". M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On 10-Apr-2014, at 4:11 pm, Marc Zyngier wrote: > On Thu, Apr 10 2014 at 11:30:41 am BST, armdev wrote: >> On 10-Apr-2014, at 3:51 pm, Marc Zyngier wrote: >> >>> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev wrote: On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: > On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi > wrote: >> This patch declare coretex-a7's irqchip to initialze gic from dt >> with "arm,cortex-a7-gic" data. >> >> Cc: Thomas Gleixner >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park >> --- >> drivers/irqchip/irq-gic.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >> index 4300b66..8e906e4 100644 >> --- a/drivers/irqchip/irq-gic.c >> +++ b/drivers/irqchip/irq-gic.c >> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct >> device_node *parent) >> } >> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); >> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); >> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); >> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); >> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); > > Frankly, this patch adds no value. Are we going to add > "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", > "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... > > Instead, how about defining a generic "arm,gic" property, and mandate > that new DT files are using that? We can always use a more precise > compatible for quirks. > How about keeping it simple and tied to arm gic versions arm,gicv1, arm,gicv2, arm,gicv2ve >>> >>> That's a variation on the same theme. As for GICv2, we don't need to >>> distinguish between having the Virtualization Extentions, the binding >>> already allows you to tell one from the other. >>> >> So if there be just 2 types of gic, it would be simple. > > Not exactly. We just happen to support two revisions of the GIC > architecture with the same binding. GICv3 has an entierely separate > binding. > >> gicv1 - 2 address sets (gicc and gicd) > > Yes. > >> gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? > > No. > > The presence of the GICV, GICH and maintenance interrupt are indicative > of the support for the Virtualization Extentions. GICv2 itself can > perfectly be built without it. then does gicv2-ve makes sense ? > > M. > -- > Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:30:41 am BST, armdev wrote: > On 10-Apr-2014, at 3:51 pm, Marc Zyngier wrote: > >> On Thu, Apr 10 2014 at 11:09:02 am BST, armdev wrote: >>> On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: >>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi wrote: > This patch declare coretex-a7's irqchip to initialze gic from dt > with "arm,cortex-a7-gic" data. > > Cc: Thomas Gleixner > Signed-off-by: Chanwoo Choi > Signed-off-by: Kyungmin Park > --- > drivers/irqchip/irq-gic.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index 4300b66..8e906e4 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct > device_node *parent) > } > IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); > IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); > IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); Frankly, this patch adds no value. Are we going to add "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic "arm,gic" property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. >>> >>> How about keeping it simple and tied to arm gic versions >>> arm,gicv1, arm,gicv2, arm,gicv2ve >> >> That's a variation on the same theme. As for GICv2, we don't need to >> distinguish between having the Virtualization Extentions, the binding >> already allows you to tell one from the other. >> > So if there be just 2 types of gic, it would be simple. Not exactly. We just happen to support two revisions of the GIC architecture with the same binding. GICv3 has an entierely separate binding. > gicv1 - 2 address sets (gicc and gicd) Yes. > gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? No. The presence of the GICV, GICH and maintenance interrupt are indicative of the support for the Virtualization Extentions. GICv2 itself can perfectly be built without it. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/27] ARM: EXYNOS:: Enter a15 lowpower mode for Exynos3250 based on Cortex-a7
On 04/10/2014 06:40 PM, Arnd Bergmann wrote: > On Thursday 10 April 2014 18:28:23 Chanwoo Choi wrote: >> +* while Exynos5 is A15/Exynos7 is A7; check the CPU part >> > > Exynos7 -> Exynos3 ? > You're right. I'll fix it. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
Hi, > -Original Message- > From: linux-arm-kernel [mailto:linux-arm-kernel- > boun...@lists.infradead.org] On Behalf Of Marc Zyngier > Sent: Thursday, April 10, 2014 7:05 PM > To: Chanwoo Choi > Cc: mark.rutl...@arm.com; linux-samsung-soc@vger.kernel.org; > t.f...@samsung.com; hyunhee@samsung.com; sw0312@samsung.com; > linux-ker...@vger.kernel.org; yj44@samsung.com; inki@samsung.com; > kyungmin.p...@samsung.com; kgene@samsung.com; Thomas Gleixner; > linux-arm-ker...@lists.infradead.org > Subject: Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to > initialize gic from dt > > On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi > wrote: > > This patch declare coretex-a7's irqchip to initialze gic from dt > > with "arm,cortex-a7-gic" data. > > > > Cc: Thomas Gleixner > > Signed-off-by: Chanwoo Choi > > Signed-off-by: Kyungmin Park > > --- > > drivers/irqchip/irq-gic.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > > index 4300b66..8e906e4 100644 > > --- a/drivers/irqchip/irq-gic.c > > +++ b/drivers/irqchip/irq-gic.c > > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct > device_node *parent) > > } > > IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); > > IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); > > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); > > IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); > > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); > > Frankly, this patch adds no value. Are we going to add > "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", > "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... > > Instead, how about defining a generic "arm,gic" property, and mandate > that new DT files are using that? We can always use a more precise > compatible for quirks. I prefer it would be arm,gicv2 instead arm-gic. In case of GICv3 of arm64, it can be arm,gicv3. Best Regards, Chanho Park -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] phy: exynos5-usbdrd: Add facility to toggle vbus gpio on/off
Hi Kishon,
On Thu, Apr 10, 2014 at 2:39 PM, Kishon Vijay Abraham I wrote:
> Hi.
>
> On Wednesday 09 April 2014 05:24 PM, Vivek Gautam wrote:
>> Adding support to enable/disable VBUS hooked to a gpio
>> to enable vbus supply on the port.
>>
>> Signed-off-by: Vivek Gautam
>> ---
>>
>> Based on 'phy-exynos5-usbdrd' patches:
>> [PATCH V4 0/5] Add Exynos5 USB 3.0 phy driver based on generic PHY framework
>> http://www.spinics.net/lists/linux-usb/msg105507.html
>>
>> drivers/phy/phy-exynos5-usbdrd.c | 18 ++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/phy/phy-exynos5-usbdrd.c
>> b/drivers/phy/phy-exynos5-usbdrd.c
>> index ff54a7c..5ca7485 100644
>> --- a/drivers/phy/phy-exynos5-usbdrd.c
>> +++ b/drivers/phy/phy-exynos5-usbdrd.c
>> @@ -18,6 +18,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -176,6 +177,7 @@ struct exynos5_usbdrd_phy {
>> struct clk *ref_clk;
>> unsigned long ref_rate;
>> unsigned int refclk_reg;
>> + int gpio;
>> };
>>
>> #define to_usbdrd_phy(inst) \
>> @@ -460,6 +462,9 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
>> if (!IS_ERR(phy_drd->usb30_sclk))
>> clk_prepare_enable(phy_drd->usb30_sclk);
>>
>> + /* Toggle VBUS gpio - on */
>> + gpio_set_value(phy_drd->gpio, 1);
>> +
>> /* Power-on PHY*/
>> inst->phy_cfg->phy_isol(inst, 0);
>>
>> @@ -476,6 +481,9 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
>> /* Power-off the PHY */
>> inst->phy_cfg->phy_isol(inst, 1);
>>
>> + /* Toggle VBUS gpio - off */
>> + gpio_set_value(phy_drd->gpio, 0);
>> +
>> if (!IS_ERR(phy_drd->usb30_sclk))
>> clk_disable_unprepare(phy_drd->usb30_sclk);
>>
>> @@ -585,6 +593,16 @@ static int exynos5_usbdrd_phy_probe(struct
>> platform_device *pdev)
>>
>> phy_drd->drv_data = drv_data;
>>
>> + /* Get required GPIO for vbus */
>> + phy_drd->gpio = of_get_named_gpio(dev->of_node,
>> + "samsung,vbus-gpio", 0);
>
> Is this dt property documented somewhere?
>> + if (!gpio_is_valid(phy_drd->gpio))
>> + dev_dbg(dev, "no usbdrd-phy vbus gpio defined\n");
>
> No return here? Can the PHY be functional even without the VBUS?
On few boards, the switch IC's enable may no be controlled by a GPIO,
rather enabled by default.
So in those cases we may not want to stop PHY probe, when the VBUS
GPIO is not present.
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On 10-Apr-2014, at 3:51 pm, Marc Zyngier wrote: > On Thu, Apr 10 2014 at 11:09:02 am BST, armdev wrote: >> On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: >> >>> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi >>> wrote: This patch declare coretex-a7's irqchip to initialze gic from dt with "arm,cortex-a7-gic" data. Cc: Thomas Gleixner Signed-off-by: Chanwoo Choi Signed-off-by: Kyungmin Park --- drivers/irqchip/irq-gic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4300b66..8e906e4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) } IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); >>> >>> Frankly, this patch adds no value. Are we going to add >>> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", >>> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... >>> >>> Instead, how about defining a generic "arm,gic" property, and mandate >>> that new DT files are using that? We can always use a more precise >>> compatible for quirks. >>> >> >> How about keeping it simple and tied to arm gic versions >> arm,gicv1, arm,gicv2, arm,gicv2ve > > That's a variation on the same theme. As for GICv2, we don't need to > distinguish between having the Virtualization Extentions, the binding > already allows you to tell one from the other. > So if there be just 2 types of gic, it would be simple. gicv1 - 2 address sets (gicc and gicd) gicv2 - 4 sets (gicc gicd gicv gich) and 1 maintenance interrupt. Right? > M. > -- > Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] usb: ehci-exynos: Return immediately from suspend if ehci_suspend fails
Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race' adds a check for possible race between suspend and wakeup interrupt, and thereby it returns -EBUSY as error code if there's a wakeup interrupt. So the platform host controller should not proceed further with its suspend callback, rather should return immediately to avoid powering down the essential things, like phy. Signed-off-by: Vivek Gautam Acked-by: Jingoo Han Cc: Alan Stern --- Changes from v1: -- Removed unnecessary change 'return 0' drivers/usb/host/ehci-exynos.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index d1d8c47..7f425ac 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -212,6 +212,8 @@ static int exynos_ehci_suspend(struct device *dev) int rc; rc = ehci_suspend(hcd, do_wakeup); + if (rc) + return rc; if (exynos_ehci->otg) exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self); -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/2] usb: ehci-platform: Return immediately from suspend if ehci_suspend fails
Patch 'b8efdaf USB: EHCI: add check for wakeup/suspend race' adds a check for possible race between suspend and wakeup interrupt, and thereby it returns -EBUSY as error code if there's a wakeup interrupt. So the platform host controller should not proceed further with its suspend callback, rather should return immediately to avoid powering down the essential things, like phy. Signed-off-by: Vivek Gautam Cc: Alan Stern Cc: Hauke Mehrtens Cc: Hans de Goede --- Changes from v1: -- Removed unnecessary change 'return 0' drivers/usb/host/ehci-platform.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c index b3a0e11..c7dd93a 100644 --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c @@ -303,6 +303,8 @@ static int ehci_platform_suspend(struct device *dev) int ret; ret = ehci_suspend(hcd, do_wakeup); + if (ret) + return ret; if (pdata->power_suspend) pdata->power_suspend(pdev); -- 1.7.10.4 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 21/27] ARM: dts: exynos3250: Add PMU dt data
Hi,
> -Original Message-
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> boun...@lists.infradead.org] On Behalf Of Chanwoo Choi
> Sent: Thursday, April 10, 2014 7:06 PM
> To: kgene@samsung.com; t.f...@samsung.com; linux-samsung-
> s...@vger.kernel.org
> Cc: hyunhee@samsung.com; sw0312@samsung.com; linux-
> ker...@vger.kernel.org; yj44@samsung.com; inki@samsung.com;
> cw00.c...@samsung.com; kyungmin.p...@samsung.com; linux-arm-
> ker...@lists.infradead.org
> Subject: [PATCH 21/27] ARM: dts: exynos3250: Add PMU dt data
>
> From: Hyunhee Kim
>
> ARM CPU has its own PMU (Performance Monitoring Unit). This patch add
> PMU dt
> data to support PMU for CPU. Exynos3250 has four PMU interrupts.
>
> Signed-off-by: Hyunhee Kim
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/boot/dts/exynos3250.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250.dtsi
> b/arch/arm/boot/dts/exynos3250.dtsi
> index ceed761..2f0ca32 100644
> --- a/arch/arm/boot/dts/exynos3250.dtsi
> +++ b/arch/arm/boot/dts/exynos3250.dtsi
> @@ -280,4 +280,9 @@
> pinctrl-0 = <&i2c7_bus>;
> status = "disabled";
> };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
> + };
As I know, the exynos3250 has two CPU cores. Why does it have four pmu
interrupts?
IMO it is sufficient it has only two interrupts.
Best Regards,
Chanho Park
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Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 11:09:02 am BST, armdev wrote: > On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: > >> On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi >> wrote: >>> This patch declare coretex-a7's irqchip to initialze gic from dt >>> with "arm,cortex-a7-gic" data. >>> >>> Cc: Thomas Gleixner >>> Signed-off-by: Chanwoo Choi >>> Signed-off-by: Kyungmin Park >>> --- >>> drivers/irqchip/irq-gic.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >>> index 4300b66..8e906e4 100644 >>> --- a/drivers/irqchip/irq-gic.c >>> +++ b/drivers/irqchip/irq-gic.c >>> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct >>> device_node *parent) >>> } >>> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); >>> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); >>> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); >>> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); >>> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); >> >> Frankly, this patch adds no value. Are we going to add >> "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", >> "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... >> >> Instead, how about defining a generic "arm,gic" property, and mandate >> that new DT files are using that? We can always use a more precise >> compatible for quirks. >> > > How about keeping it simple and tied to arm gic versions > arm,gicv1, arm,gicv2, arm,gicv2ve That's a variation on the same theme. As for GICv2, we don't need to distinguish between having the Virtualization Extentions, the binding already allows you to tell one from the other. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 13/27] ARM: dts: exynos3250: Add pin control device tree data
From: Tomasz Figa
This patch adds device tree nodes for pin controllers of Exynos3250
along with definitions of pin banks, external interrupt layout and
avaiable functions.
Signed-off-by: Tomasz Figa
[Fix bug about pinctrl lable by Chanwoo Choi]
Signed-off-by: Chanwoo Choi
[Fix the sd_bus8 gpio configuration by Jaehoon Chung]
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 477 ++
arch/arm/boot/dts/exynos3250.dtsi | 24 ++
2 files changed, 501 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos3250-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
new file mode 100644
index 000..976490b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -0,0 +1,477 @@
+/*
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as
device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1140 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpa0-0", "gpa0-1";
+ samsung,pin-function = <0x2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = "gpa0-2", "gpa0-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpa0-4", "gpa0-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = "gpa0-6", "gpa0-7";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = "gpa1-2", "gpa1-3";
+ samsung,pin-function = <3>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = "gpb-0", "gpb-1";
+ samsung,pin-function = <
[PATCH 09/27] clk: samsung: exynos3250: Add clocks using common clock framework
From: Tomasz Figa This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Cc: Mike Turquette Cc: Kukjin Kim Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Hyunhee Kim Signed-off-by: Sylwester Nawrocki Signed-off-by: Inki Dae Signed-off-by: Seung-Woo Kim Signed-off-by: Jaehoon Chung Signed-off-by: Karol Wrona Signed-off-by: YoungJun Cho Signed-off-by: Kyungmin Park --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos3250.c | 785 + include/dt-bindings/clock/exynos3250.h | 256 +++ 3 files changed, 1042 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos3250.c create mode 100644 include/dt-bindings/clock/exynos3250.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..d120797 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c new file mode 100644 index 000..0574a76 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos3250 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +#define SRC_LEFTBUS0x4200 +#define DIV_LEFTBUS0x4500 +#define GATE_IP_LEFTBUS0x4800 +#define SRC_RIGHTBUS 0x8200 +#define DIV_RIGHTBUS 0x8500 +#define GATE_IP_RIGHTBUS 0x8800 +#define GATE_IP_PERIR 0x8960 +#define MPLL_LOCK 0xc010 +#define MPLL_CON0 0xc110 +#define VPLL_LOCK 0xc020 +#define VPLL_CON0 0xc120 +#define UPLL_LOCK 0xc030 +#define UPLL_CON0 0xc130 +#define SRC_TOP0 0xc210 +#define SRC_TOP1 0xc214 +#define SRC_CAM0xc220 +#define SRC_MFC0xc228 +#define SRC_G3D0xc22c +#define SRC_LCD0xc234 +#define SRC_ISP0xc238 +#define SRC_FSYS 0xc240 +#define SRC_PERIL0 0xc250 +#define SRC_PERIL1 0xc254 +#define SRC_MASK_TOP 0xc310 +#define SRC_MASK_CAM 0xc320 +#define SRC_MASK_LCD 0xc334 +#define SRC_MASK_ISP 0xc338 +#define SRC_MASK_FSYS 0xc340 +#define SRC_MASK_PERIL00xc350 +#define SRC_MASK_PERIL10xc354 +#define DIV_TOP0xc510 +#define DIV_CAM0xc520 +#define DIV_MFC0xc528 +#define DIV_G3D0xc52c +#define DIV_LCD0xc534 +#define DIV_ISP0xc538 +#define DIV_FSYS0 0xc540 +#define DIV_FSYS1 0xc544 +#define DIV_FSYS2 0xc548 +#define DIV_PERIL0 0xc550 +#define DIV_PERIL1 0xc554 +#define DIV_PERIL3 0xc55c +#define DIV_PERIL4 0xc560 +#define DIV_PERIL5 0xc564 +#define DIV_CAM1 0xc568 +#define CLKDIV2_RATIO 0xc580 +#define GATE_SCLK_CAM 0xc820 +#define GATE_SCLK_MFC 0xc828 +#define GATE_SCLK_G3D 0xc82c +#define GATE_SCLK_LCD 0xc834 +#define GATE_SCLK_ISP_TOP 0xc838 +#define GATE_SCLK_FSYS 0xc840 +#define GATE_SCLK_PERIL0xc850 +#define GATE_IP_CAM0xc920 +#define GATE_IP_MFC0xc928 +#define GATE_IP_G3D0xc92c +#define GATE_IP_LCD0xc934 +#define GATE_IP_ISP0xc938 +#define GATE_IP_FSYS 0xc940 +#define GATE_IP_PERIL 0xc950 +#define GATE_BLOCK 0xc970 +#define APLL_LOCK 0x14000 +#define APLL_CON0 0x14100 +#define SRC_CPU0x14200 +#define DIV_CPU0 0x14
[PATCH 10/27] ARM: dts: exynos3250: Add new exynos3250.dtsi file
From: Tomasz Figa
This patch add new exynos3250.dtsi to support Exynos3250 SoC and includes
chipid/sys_reg dt node.
Signed-off-by: Tomasz Figa
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos3250.dtsi
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
new file mode 100644
index 000..3c8cee6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Samsung's Exynos3250 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "samsung,exynos3250";
+
+ chipid@1000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x1000 0x100>;
+ };
+
+ sys_reg: syscon@1001 {
+ compatible = "samsung,exynos3-sysreg", "syscon";
+ reg = <0x1001 0x400>;
+ };
+};
--
1.8.0
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[PATCH 14/27] ARM: dts: exynos3250: Add device tree nodes for clock controllers
From: Tomasz Figa
This patch add dt node of clock controllers to support Exynos3250 SoC.
Exynos3250's clock drvier divide into two scope for clock controller as
following:
- 'cmu' clock-controller includes CMU_LEFTBUS/RIGHTBUS/TOP/CPU/ISP/ACP clocks
Signed-off-by: Tomasz Figa
[Modify base address of clock and remove unnecessary dt node by Chanwoo Choi]
Signed-off-by: Chanwoo Choi
[Include exynos3250 clock header file by Hyunhee Kim]
Signed-off-by: Hyunhee Kim
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index dba3218..758913e 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -19,6 +19,7 @@
#include "skeleton.dtsi"
#include "exynos3250-pinctrl.dtsi"
+#include
/ {
compatible = "samsung,exynos3250";
@@ -39,6 +40,12 @@
reg = <0x1001 0x400>;
};
+ cmu: clock-controller@1003 {
+ compatible = "samsung,exynos3250-cmu";
+ reg = <0x1003 0x2>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
1.8.0
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[PATCH 25/27] ARM: dts: exynos3250: Add RTC dt node
From: Tomasz Figa
This patch add rtc dt node for Real Time Clock (RTC) which operates with
a backup battery when the system is off and performs the function of an alarm.
Exynos3250's RTC has following rtc interrupt
- ALARM_INT (alarm interrupt)
- ALAREM_WK (alarm wake-up)
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index c8bd33cf..a61940f 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -88,6 +88,13 @@
#clock-cells = <1>;
};
+ rtc@1007 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x1007 0x100>;
+ interrupts = <0 73 0>, <0 74 0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
--
1.8.0
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[PATCH 21/27] ARM: dts: exynos3250: Add PMU dt data
From: Hyunhee Kim
ARM CPU has its own PMU (Performance Monitoring Unit). This patch add PMU dt
data to support PMU for CPU. Exynos3250 has four PMU interrupts.
Signed-off-by: Hyunhee Kim
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index ceed761..2f0ca32 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -280,4 +280,9 @@
pinctrl-0 = <&i2c7_bus>;
status = "disabled";
};
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
+ };
};
--
1.8.0
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[PATCH 27/27] ARM: dts: exynos3250: Add CPUs dt node for Exynos3250
This patch add CPUs dt node for Exynos3250 which uses the Cortex-A7 dual core.
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 192770a..cb87087 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,23 @@
i2c7 = &i2c_7;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ };
+ };
+
fixed-rate-clocks {
compatible = "simple-bus";
#address-cells = <1>;
--
1.8.0
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[PATCH 26/27] ARM: dts: exynos3250: Add power domain dt nodes
From: Inki Dae
This patch add CAM/MFC/G3D/LCD0/ISP power domain nodes for Exynos3250.
Signed-off-by: Inki Dae
[add CAM/MFC power domain node by Bartlomiej Zolnierkiewicz]
Signed-off-by: Bartlomiej Zolnierkiewicz
[add ISP power domain node by Bartlomiej Zolnierkiewicz]
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index a61940f..192770a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -82,6 +82,31 @@
reg = <0x1001 0x400>;
};
+ pd_cam: cam-power-domain@10023C00 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C00 0x20>;
+ };
+
+ pd_mfc: mfc-power-domain@10023C40 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C40 0x20>;
+ };
+
+ pd_g3d: g3d-power-domain@10023C60 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C60 0x20>;
+ };
+
+ pd_lcd0: lcd0-power-domain@10023C80 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023C80 0x20>;
+ };
+
+ pd_isp: isp-power-domain@10023CA0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10023CA0 0x20>;
+ };
+
cmu: clock-controller@1003 {
compatible = "samsung,exynos3250-cmu";
reg = <0x1003 0x2>;
--
1.8.0
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[PATCH 24/27] ARM: dts: exynos3250: Add pwm dt node to support PWM Timer
From: Tomasz Figa
This patch add pwm dt node to support PWM (Pulse Width Modulation) timer.
Exynos uses same IP of Exynos4210 and has five 32-bit PWM timers.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 03e7931..c8bd33cf 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -345,6 +345,15 @@
status = "disabled";
};
+ pwm: pwm@139D {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x139D 0x1000>;
+ interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+<0 107 0>, <0 108 0>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
--
1.8.0
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[PATCH 22/27] ARM: dts: exynos3250: Add amba and pdma dt node
From: Tomasz Figa
This patch add amba and pdma dt node to support bus on Exynos3250.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2f0ca32..b8e5ae13 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -148,6 +148,36 @@
status = "disabled";
};
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma0: pdma@1268 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1268 0x1000>;
+ interrupts = <0 138 0>;
+ clocks = <&cmu CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@1269 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x1269 0x1000>;
+ interrupts = <0 139 0>;
+ clocks = <&cmu CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
adc: adc@126C {
compatible = "samsung,exynos-adc-v2";
reg = <0x126C 0x100>, <0x10020718 0x4>;
--
1.8.0
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[PATCH 18/27] ARM: dts: exynos3250: Add i2c dt node
From: Inki Dae
Add the DTS nodes for all th i2c busses in the Exynos3250 SoC.
Signed-off-by: Inki Dae
[Add i2c alias by Tomasz Figa]
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 112 ++
1 file changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index c5e6917..a16c3ea 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -28,6 +28,14 @@
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
+ i2c0 = &i2c_0;
+ i2c1 = &i2c_1;
+ i2c2 = &i2c_2;
+ i2c3 = &i2c_3;
+ i2c4 = &i2c_4;
+ i2c5 = &i2c_5;
+ i2c6 = &i2c_6;
+ i2c7 = &i2c_7;
};
chipid@1000 {
@@ -112,4 +120,108 @@
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
+
+ i2c_0: i2c@1386 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x1386 0x100>;
+ interrupts = <0 113 0>;
+ clocks = <&cmu CLK_I2C0>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_bus>;
+ status = "disabled";
+ };
+
+ i2c_1: i2c@1387 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x1387 0x100>;
+ interrupts = <0 114 0>;
+ clocks = <&cmu CLK_I2C1>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_bus>;
+ status = "disabled";
+ };
+
+ i2c_2: i2c@1388 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x1388 0x100>;
+ interrupts = <0 115 0>;
+ clocks = <&cmu CLK_I2C2>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_bus>;
+ status = "disabled";
+ };
+
+ i2c_3: i2c@1389 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x1389 0x100>;
+ interrupts = <0 116 0>;
+ clocks = <&cmu CLK_I2C3>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_bus>;
+ status = "disabled";
+ };
+
+ i2c_4: i2c@138A {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138A 0x100>;
+ interrupts = <0 117 0>;
+ clocks = <&cmu CLK_I2C4>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_bus>;
+ status = "disabled";
+ };
+
+ i2c_5: i2c@138B {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138B 0x100>;
+ interrupts = <0 118 0>;
+ clocks = <&cmu CLK_I2C5>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_bus>;
+ status = "disabled";
+ };
+
+ i2c_6: i2c@138C {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138C 0x100>;
+ interrupts = <0 119 0>;
+ clocks = <&cmu CLK_I2C6>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_bus>;
+ status = "disabled";
+ };
+
+ i2c_7: i2c@138D {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x138D 0x100>;
+ interrupts = <0 120 0>;
+ clocks = <&cmu CLK_I2C7>;
+ clock-names = "i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_bus>;
+ status = "disabled";
+ };
};
--
1.8.0
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[PATCH 15/27] ARM: dts: exynos3250: Add uart dt node to support seiral ports
This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP
of Exynos4 SoC and has only two independent channels.
Signed-off-by: Chanwoo Choi
[Fix incorrect clock id by Tomasz Figa]
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 758913e..d17ed54 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -74,4 +74,22 @@
reg = <0x1140 0x1000>;
interrupts = <0 240 0>;
};
+
+ serial@1380 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x1380 0x100>;
+ interrupts = <0 109 0>;
+ clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial@1381 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x1381 0x100>;
+ interrupts = <0 110 0>;
+ clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
};
--
1.8.0
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[PATCH 20/27] ARM: dts: exynos3250: Move definitions of external clocks to SoC dtsi
From: Tomasz Figa
This allows proper ordering of clock registration and is still correct,
because list of external clocks is SoC-specific, just their frequencies
and availability are board-specific.
Signed-off-by: Tomasz Figa
Signed-off-by: Hyunhee Kim
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 587a124..ceed761 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -40,6 +40,36 @@
i2c7 = &i2c_7;
};
+ fixed-rate-clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xusbxti: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xusbxti";
+ };
+
+ xxti: clock@1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xxti";
+ };
+
+ xtcxo: clock@2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xtcxo";
+ };
+ };
+
chipid@1000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x1000 0x100>;
--
1.8.0
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[PATCH 19/27] ARM: dts: exynos3250: Add Mobile Storage Host Card
From: Kyungmin Park
This patch add MSHC (Mobile Storage Host Controller) dt node which is an
interface between the system and SD/MMC card. mshc dt node is used for dw_mmc
device driver to operate SD/MMC card.
Signed-off-by: Kyungmin Park
[Modify the sdr/ddr timing for eMMC by Jaehoon Chung]
Signed-off-by: Jaehoon Chung
---
arch/arm/boot/dts/exynos3250.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index a16c3ea..587a124 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -28,6 +28,8 @@
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
+ mshc0 = &mshc_0;
+ mshc1 = &mshc_1;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
@@ -92,6 +94,30 @@
interrupts = <0 240 0>;
};
+ mshc_0: mshc@1251 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x1251 0x1000>;
+ interrupts = <0 142 0>;
+ clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mshc_1: mshc@1252 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x1252 0x1000>;
+ interrupts = <0 143 0>;
+ clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
adc: adc@126C {
compatible = "samsung,exynos-adc-v2";
reg = <0x126C 0x100>, <0x10020718 0x4>;
--
1.8.0
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Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On 10-Apr-2014, at 3:34 pm, Marc Zyngier wrote: > On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi > wrote: >> This patch declare coretex-a7's irqchip to initialze gic from dt >> with "arm,cortex-a7-gic" data. >> >> Cc: Thomas Gleixner >> Signed-off-by: Chanwoo Choi >> Signed-off-by: Kyungmin Park >> --- >> drivers/irqchip/irq-gic.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >> index 4300b66..8e906e4 100644 >> --- a/drivers/irqchip/irq-gic.c >> +++ b/drivers/irqchip/irq-gic.c >> @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct >> device_node *parent) >> } >> IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); >> IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); >> +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); >> IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); >> IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); > > Frankly, this patch adds no value. Are we going to add > "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", > "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... > > Instead, how about defining a generic "arm,gic" property, and mandate > that new DT files are using that? We can always use a more precise > compatible for quirks. > How about keeping it simple and tied to arm gic versions arm,gicv1, arm,gicv2, arm,gicv2ve > Mark, what do you think? I think this has been discussed in the past > already. > > M. > -- > Jazz is not dead. It just smells funny. > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 17/27] ARM: dts: exynos3250: Add ADC dt node to read analog raw data
This patch add ADC (Analog to Digital Converter) dt node to get raw data with
IIO subsystem. Usually, ADC is used to check temperature, jack type and so on.
Exynos3250 includes ADCv2 which is different from ADCv1 for Exynos4 SoC.
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2013d0d..c5e6917 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -84,6 +84,17 @@
interrupts = <0 240 0>;
};
+ adc: adc@126C {
+ compatible = "samsung,exynos-adc-v2";
+ reg = <0x126C 0x100>, <0x10020718 0x4>;
+ interrupts = <0 137 0>;
+ clock-names = "adc", "sclk_tsadc";
+ clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
+
serial@1380 {
compatible = "samsung,exynos4210-uart";
reg = <0x1380 0x100>;
--
1.8.0
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[PATCH 16/27] ARM: dts: exynos3250: Add MCT dt node
This patch add MCT (Multi Core Timer) dt node with "samsung,exynos4210-mct"
compatible name bacause Exynos3250 uses SPI interrput type. And Exynos3250
provide one global timer and four local timers for Multi Core CPU.
Signed-off-by: Chanwoo Choi
[Fix incorrect irq number of MCT and remove unnecessary code by Tomasz Figa]
Signed-off-by: Tomasz Figa
Signed-off-by: Hyunhee Kim
---
arch/arm/boot/dts/exynos3250.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index d17ed54..2013d0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -57,6 +57,15 @@
interrupts = <1 9 0xf04>;
};
+ mct@1005 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x1005 0x800>;
+ interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
+<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+ clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
+ clock-names = "fin_pll", "mct";
+ };
+
pinctrl_1: pinctrl@1100 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x1100 0x1000>;
--
1.8.0
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[PATCH 12/27] ARM: dts: exynos3250: Add default interrupt-parent connected with GIC
This patch add interrupt-parent node to connected with GIC.
All interrupt-related dt nodes need default interrupt-parent node.
Signed-off-by: Chanwoo Choi
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index fe8960e..13efdbed 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -21,6 +21,7 @@
/ {
compatible = "samsung,exynos3250";
+ interrupt-parent = <&gic>;
chipid@1000 {
compatible = "samsung,exynos4210-chipid";
--
1.8.0
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[PATCH 23/27] ARM: dts: exynos3250: Add spi dt node to support spi bus
From: Tomasz Figa
This patch add spi dt node to support SPI (Serial Peripheral Interface) bus.
SPI in Exynos3250 transfers serial data by using various peripherals. Exynos3250
has two independent interface (spi0/1).
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index b8e5ae13..03e7931 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -30,6 +30,8 @@
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
@@ -311,6 +313,38 @@
status = "disabled";
};
+ spi_0: spi@1392 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x1392 0x100>;
+ interrupts = <0 121 0>;
+ dmas = <&pdma0 7>, <&pdma0 6>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
+
+ spi_1: spi@1393 {
+ compatible = "samsung,exynos4210-spi";
+ reg = <0x1393 0x100>;
+ interrupts = <0 122 0>;
+ dmas = <&pdma1 7>, <&pdma1 6>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
--
1.8.0
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[PATCH 11/27] ARM: dts: exynos3250: Add GIC dt node for Exynos3250
From: Tomasz Figa
This patch adds device tree node for GIC interrupt controller
on Exynos3250.
Signed-off-by: Tomasz Figa
Signed-off-by: Kyungmin Park
---
arch/arm/boot/dts/exynos3250.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 3c8cee6..fe8960e 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -31,4 +31,15 @@
compatible = "samsung,exynos3-sysreg", "syscon";
reg = <0x1001 0x400>;
};
+
+ gic: interrupt-controller@10481000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10481000 0x1000>,
+ <0x10482000 0x1000>,
+ <0x10484000 0x2000>,
+ <0x10486000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
};
--
1.8.0
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Re: [PATCH 07/27] irqchip: Declare cortex-a7's irqchip to initialize gic from dt
On Thu, Apr 10 2014 at 10:28:24 am BST, Chanwoo Choi wrote: > This patch declare coretex-a7's irqchip to initialze gic from dt > with "arm,cortex-a7-gic" data. > > Cc: Thomas Gleixner > Signed-off-by: Chanwoo Choi > Signed-off-by: Kyungmin Park > --- > drivers/irqchip/irq-gic.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > index 4300b66..8e906e4 100644 > --- a/drivers/irqchip/irq-gic.c > +++ b/drivers/irqchip/irq-gic.c > @@ -1069,6 +1069,7 @@ gic_of_init(struct device_node *node, struct > device_node *parent) > } > IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); > IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); > +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); > IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); > IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); Frankly, this patch adds no value. Are we going to add "arm,cortex-a12-gic", "arm,cortex-a17-gic", "arm,cortex-a53-gic", "arm,cortex-a57-gic"? And that's just to mention the ARM Ltd cores... Instead, how about defining a generic "arm,gic" property, and mandate that new DT files are using that? We can always use a more precise compatible for quirks. Mark, what do you think? I think this has been discussed in the past already. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure SYSRAM of Exynos3250
Hi Arnd, > -Original Message- > From: linux-arm-kernel [mailto:linux-arm-kernel- > boun...@lists.infradead.org] On Behalf Of Arnd Bergmann > Sent: Thursday, April 10, 2014 6:45 PM > To: linux-arm-ker...@lists.infradead.org > Cc: kgene@samsung.com; t.f...@samsung.com; hyunhee@samsung.com; > sw0312@samsung.com; linux-ker...@vger.kernel.org; > yj44@samsung.com; inki@samsung.com; Chanwoo Choi; > kyungmin.p...@samsung.com; linux-samsung-soc@vger.kernel.org > Subject: Re: [PATCH 02/27] ARM: EXYNOS: Add IO mapping for non-secure > SYSRAM of Exynos3250 > > On Thursday 10 April 2014 18:28:19 Chanwoo Choi wrote: > > > > The non-secure SYSRAM is used for secondary CPU bring-up. This patch > add > > IO mapping for non-scure SYSRAM. > > > > Signed-off-by: Chanwoo Choi > > Signed-off-by: Kyungmin Park > > I really don't want to see any further static mappings here. We had the > same discussion for the previous Exynos chip that was submitted, so > please > describe the SYSRAM in DT, and start thinking about the other static > mappings > that can be removed. Sachin already submitted the DT support[1] for SYSRAM area. [1] : http://www.spinics.net/lists/linux-samsung-soc/msg27647.html > > Arnd > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 20/20] ARM: exynos: cpuidle: Move the driver to drivers/cpuidle directory
Signed-off-by: Daniel Lezcano Reviewed-by: Viresh Kumar Reviewed-by: Bartlomiej Zolnierkiewicz Reviewed-by: Tomasz Figa --- arch/arm/mach-exynos/Makefile |1 - drivers/cpuidle/Kconfig.arm|6 ++ drivers/cpuidle/Makefile |1 + .../cpuidle.c => drivers/cpuidle/cpuidle-exynos.c |0 4 files changed, 7 insertions(+), 1 deletion(-) rename arch/arm/mach-exynos/cpuidle.c => drivers/cpuidle/cpuidle-exynos.c (100%) diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index a656dbe..21bd364 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos.o obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_EXYNOS) += pmu.o diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index d988948..364c984 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -44,3 +44,9 @@ config ARM_AT91_CPUIDLE depends on ARCH_AT91 help Select this to enable cpuidle for AT91 processors + +config ARM_EXYNOS_CPUIDLE + bool "Cpu Idle Driver for the Exynos processors" + depends on ARCH_EXYNOS + help + Select this to enable cpuidle for Exynos processors diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index f71ae1b..0d1540a 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_KIRKWOOD_CPUIDLE)+= cpuidle-kirkwood.o obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o +obj-$(CONFIG_ARM_EXYNOS_CPUIDLE)+= cpuidle-exynos.o ### # POWERPC drivers diff --git a/arch/arm/mach-exynos/cpuidle.c b/drivers/cpuidle/cpuidle-exynos.c similarity index 100% rename from arch/arm/mach-exynos/cpuidle.c rename to drivers/cpuidle/cpuidle-exynos.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 15/20] ARM: exynos: cpuidle: Move the AFTR state function into pm.c
In order to remove depedency on pm code, let's move the 'exynos_enter_aftr'
function into the pm.c file as well as the other helper functions.
Signed-off-by: Daniel Lezcano
---
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/cpuidle.c | 29 -
arch/arm/mach-exynos/pm.c | 29 +
3 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83..30123a0 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -62,5 +62,6 @@ struct exynos_pmu_conf {
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_enter_aftr(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 0d3c839..5c5a4d1 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -30,35 +30,6 @@
#include "common.h"
#include "regs-pmu.h"
-#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
-#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
-
-#define S5P_CHECK_AFTR 0xFCBA0D10
-
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(long mask)
-{
- __raw_writel(mask, S5P_WAKEUP_MASK);
-}
-
-static void exynos_cpu_set_boot_vector(long flags)
-{
- __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(flags, REG_DIRECTGO_FLAG);
-}
-
-static void exynos_enter_aftr(void)
-{
- exynos_set_wakeupmask(0xff3e);
- exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
static int idle_finisher(unsigned long flags)
{
exynos_enter_aftr();
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c4138bf..f75d9b9 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -101,6 +101,35 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
return -ENOENT;
}
+#define EXYNOS_BOOT_VECTOR_ADDR(samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+#define EXYNOS_BOOT_VECTOR_FLAG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
+ S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+ (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+#define S5P_CHECK_AFTR 0xFCBA0D10
+
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+ __raw_writel(mask, S5P_WAKEUP_MASK);
+}
+
+static void exynos_cpu_set_boot_vector(long flags)
+{
+ __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+ __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
+void exynos_enter_aftr(void)
+{
+ exynos_set_wakeupmask(0xff3e);
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+ /* Set value of power down register for aftr mode */
+ exynos_sys_powerdown_conf(SYS_AFTR);
+}
+
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
--
1.7.9.5
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[PATCH V4 16/20] ARM: exynos: cpuidle: Move the power sequence call in the cpu_pm notifier
The code to initiate and exit the powerdown sequence is the same in pm.c and
cpuidle.c.
Let's split the common part in the pm.c and reuse it from the cpu_pm notifier.
That is one more step forward to make the cpuidle driver arch indenpendant.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/cpuidle.c | 22 --
arch/arm/mach-exynos/pm.c | 24
2 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 5c5a4d1..0651293 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -28,7 +28,6 @@
#include
#include "common.h"
-#include "regs-pmu.h"
static int idle_finisher(unsigned long flags)
{
@@ -42,31 +41,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
struct cpuidle_driver *drv,
int index)
{
- unsigned long tmp;
-
- /* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
- tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
cpu_pm_exit();
- /*
-* If PMU failed while entering sleep mode, WFI will be
-* ignored by PMU and then exiting cpu_do_idle().
-* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
-* in this situation.
-*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
- if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
- tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
- /* Clear wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
- }
-
return index;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f75d9b9..a943e97 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -245,15 +245,21 @@ static void exynos_pm_prepare(void)
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
-static int exynos_pm_suspend(void)
+static void exynos_pm_central_suspend(void)
{
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
-
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_suspend(void)
+{
+ unsigned long tmp;
+
+ exynos_pm_central_suspend();
/* Setting SEQ_OPTION register */
@@ -266,7 +272,7 @@ static int exynos_pm_suspend(void)
return 0;
}
-static void exynos_pm_resume(void)
+static int exynos_pm_central_resume(void)
{
unsigned long tmp;
@@ -283,9 +289,17 @@ static void exynos_pm_resume(void)
/* clear the wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
- goto early_wakeup;
+ return -1;
}
+ return 0;
+}
+
+static void exynos_pm_resume(void)
+{
+ if (exynos_pm_central_resume())
+ goto early_wakeup;
+
if (!soc_is_exynos5250())
exynos_cpu_restore_register();
@@ -394,6 +408,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block
*self,
switch (cmd) {
case CPU_PM_ENTER:
if (cpu == 0) {
+ exynos_pm_central_suspend();
exynos_cpu_save_register();
}
break;
@@ -403,6 +418,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block
*self,
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
exynos_cpu_restore_register();
+ exynos_pm_central_resume();
}
break;
}
--
1.7.9.5
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[PATCH V4 14/20] ARM: exynos: cpuidle: Encapsulate the AFTR code into a function
Let's encapsulate the AFTR state specific call into a single function.
Signed-off-by: Daniel Lezcano
---
arch/arm/mach-exynos/cpuidle.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index d7091e0..0d3c839 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -51,13 +51,17 @@ static void exynos_cpu_set_boot_vector(long flags)
__raw_writel(flags, REG_DIRECTGO_FLAG);
}
-static int idle_finisher(unsigned long flags)
+static void exynos_enter_aftr(void)
{
exynos_set_wakeupmask(0xff3e);
exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
+}
+static int idle_finisher(unsigned long flags)
+{
+ exynos_enter_aftr();
cpu_do_idle();
return 1;
--
1.7.9.5
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[PATCH V4 09/20] ARM: exynos: cpuidle: Remove ifdef for scu_enable
The scu_enable function is already a noop in the scu's header file is
CONFIG_SMP=n, so no need to use these macros in the code.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/pm.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index aba577f..9773a00 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -244,7 +244,7 @@ static void exynos_pm_resume(void)
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
- if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
+ if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
early_wakeup:
@@ -336,10 +336,8 @@ static int exynos_cpu_pm_notifier(struct notifier_block
*self,
case CPU_PM_EXIT:
if (cpu == 0) {
-#ifdef CONFIG_SMP
if (!soc_is_exynos5250())
scu_enable(S5P_VA_SCU);
-#endif
exynos_cpu_restore_register();
}
break;
--
1.7.9.5
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[PATCH V4 08/20] ARM: exynos: cpuidle: Move scu_enable in the cpu_pm notifier
We make the cpuidle code less arch dependent.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c |6 --
arch/arm/mach-exynos/pm.c |4
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 7f1f4ef..ce31004 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -18,7 +18,6 @@
#include
#include
-#include
#include
#include
#include
@@ -93,11 +92,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
-
-#ifdef CONFIG_SMP
- if (!soc_is_exynos5250())
- scu_enable(S5P_VA_SCU);
-#endif
cpu_pm_exit();
/*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 67d75fe..aba577f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -336,6 +336,10 @@ static int exynos_cpu_pm_notifier(struct notifier_block
*self,
case CPU_PM_EXIT:
if (cpu == 0) {
+#ifdef CONFIG_SMP
+ if (!soc_is_exynos5250())
+ scu_enable(S5P_VA_SCU);
+#endif
exynos_cpu_restore_register();
}
break;
--
1.7.9.5
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[PATCH V4 11/20] ARM: exynos: cpuidle: Pass wakeup mask parameter to function
Pass the wakeup mask to 'exynos_set_wakeupmask' as this function could be used
for different idle states with different mask.
Signed-off-by: Daniel Lezcano
---
arch/arm/mach-exynos/cpuidle.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 97a441f..ddbb2c5 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -40,14 +40,14 @@
#define S5P_CHECK_AFTR 0xFCBA0D10
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(void)
+static void exynos_set_wakeupmask(long mask)
{
- __raw_writel(0xff3e, S5P_WAKEUP_MASK);
+ __raw_writel(mask, S5P_WAKEUP_MASK);
}
static int idle_finisher(unsigned long flags)
{
- exynos_set_wakeupmask();
+ exynos_set_wakeupmask(0xff3e);
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
--
1.7.9.5
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[PATCH V4 05/20] ARM: exynos: cpuidle: Move some code inside the idle_finisher
Move the code around to differentiate different section of code and prepare it
to be factored out in the next patches.
The call order changed but hat doesn't have a side effect because they are
independent. The important call is cpu_do_idle() which must be done the last.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 16e3325..cdfb1ae 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -87,7 +87,16 @@ static void restore_cpu_arch_register(void)
static int idle_finisher(unsigned long flags)
{
+ exynos_set_wakeupmask();
+
+ __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+ __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+ /* Set value of power down register for aftr mode */
+ exynos_sys_powerdown_conf(SYS_AFTR);
+
cpu_do_idle();
+
return 1;
}
@@ -97,14 +106,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
{
unsigned long tmp;
- exynos_set_wakeupmask();
-
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
-
- __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
save_cpu_arch_register();
/* Setting Central Sequence Register for power down mode */
--
1.7.9.5
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[PATCH V4 13/20] ARM: exynos: cpuidle: Disable cpuidle for 5440
There is no point to register the cpuidle driver for the 5440 as it has only
one WFI state which is the default idle function when the cpuidle driver is
disabled.
By disabling cpuidle we prevent to enter to the governor computation for
nothing, thus saving a lot of processing time.
The only drawback is the statistic via sysfs on this state which is lost but
it is meaningless and it could be retrieved from the ftrace easily.
Signed-off-by: Daniel Lezcano
Reviewed-by: Tomasz Figa
Acked-by: Amit Kucheria
---
arch/arm/mach-exynos/cpuidle.c |3 ---
arch/arm/mach-exynos/exynos.c |3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ed7a439..d7091e0 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -133,9 +133,6 @@ static int exynos_cpuidle_probe(struct platform_device
*pdev)
{
int ret;
- if (soc_is_exynos5440())
- exynos_idle_driver.state_count = 1;
-
ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b567361..fe8dac8 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,9 @@ static struct platform_device exynos_cpuidle = {
void __init exynos_cpuidle_init(void)
{
+ if (soc_is_exynos5440())
+ return;
+
platform_device_register(&exynos_cpuidle);
}
--
1.7.9.5
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[PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c
One more step is moving the clock ratio setting at idle time in pm.c
The macro names have been changed to be consistent with the other macros
name in the file.
Note, the clock divider was working only when cpuidle was enabled because it
was in its init routine. With this change, the clock divider is set in the pm's
init routine, so it will also operate when the cpuidle driver is not set, which
is good.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 54 ---
arch/arm/mach-exynos/pm.c | 35 +
arch/arm/mach-exynos/regs-pmu.h | 19 ++
3 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ce31004..97a441f 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -39,25 +39,6 @@
#define S5P_CHECK_AFTR 0xFCBA0D10
-#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020)
-#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE(1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE(1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI(1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI(1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
-
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(void)
{
@@ -127,38 +108,6 @@ static int exynos_enter_lowpower(struct cpuidle_device
*dev,
return exynos_enter_core0_aftr(dev, drv, new_index);
}
-static void __init exynos5_core_down_clk(void)
-{
- unsigned int tmp;
-
- /*
-* Enable arm clock down (in idle) and set arm divider
-* ratios in WFI/WFE state.
-*/
- tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
- PWR_CTRL1_CORE1_DOWN_RATIO | \
- PWR_CTRL1_DIV2_DOWN_EN | \
- PWR_CTRL1_DIV1_DOWN_EN | \
- PWR_CTRL1_USE_CORE1_WFE| \
- PWR_CTRL1_USE_CORE0_WFE| \
- PWR_CTRL1_USE_CORE1_WFI| \
- PWR_CTRL1_USE_CORE0_WFI;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-
- /*
-* Enable arm clock up (on exiting idle). Set arm divider
-* ratios when not in idle along with the standby duration
-* ratios.
-*/
- tmp = PWR_CTRL2_DIV2_UP_EN | \
- PWR_CTRL2_DIV1_UP_EN | \
- PWR_CTRL2_DUR_STANDBY2_VAL | \
- PWR_CTRL2_DUR_STANDBY1_VAL | \
- PWR_CTRL2_CORE2_UP_RATIO | \
- PWR_CTRL2_CORE1_UP_RATIO;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-
static struct cpuidle_driver exynos_idle_driver = {
.name = "exynos_idle",
.owner = THIS_MODULE,
@@ -181,9 +130,6 @@ static int exynos_cpuidle_probe(struct platform_device
*pdev)
{
int ret;
- if (soc_is_exynos5250())
- exynos5_core_down_clk();
-
if (soc_is_exynos5440())
exynos_idle_driver.state_count = 1;
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 9773a00..c4138bf 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -140,6 +140,38 @@ static void exynos_cpu_restore_register(void)
: "cc");
}
+static void __init exynos5_core_down_clk(void)
+{
+ unsigned int tmp;
+
+ /*
+* Enable arm clock down (in idle) and set arm divider
+* ratios in WFI/WFE state.
+*/
+ tmp = EXYNOS5_PWR_CTRL1_CORE2_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_CORE1_DOWN_RATIO | \
+ EXYNOS5_PWR_CTRL1_DIV2_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_DIV1_DOWN_EN | \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE0_WFE| \
+ EXYNOS5_PWR_CTRL1_USE_CORE1_WFI| \
+ EXYNOS5_PWR_CTRL1_USE_CORE0_WFI;
+ __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+
+ /*
+* Enable arm clock up (on exiting idle). Set arm divider
+* ratios when not in idle along with the standby duration
+* ratios.
+*/
+ tmp = EXYNOS5_PWR_CTRL2_DIV2_UP_EN | \
+ EXYNOS5_PWR_CTRL2_DIV1_UP_EN
[PATCH V4 17/20] ARM: exynos: cpuidle: Move S5P_CHECK_SLEEP into pm.c
This macro is only used there. Signed-off-by: Daniel Lezcano --- arch/arm/mach-exynos/pm.c |3 ++- arch/arm/mach-exynos/regs-pmu.h |2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a943e97..aa23662 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -108,7 +108,8 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) -#define S5P_CHECK_AFTR 0xFCBA0D10 +#define S5P_CHECK_AFTR 0xFCBA0D10 +#define S5P_CHECK_SLEEP 0x0BAD /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ static void exynos_set_wakeupmask(long mask) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 35c4eb3..d7803c4 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -119,8 +119,6 @@ #define S5P_CORE_LOCAL_PWR_EN 0x3 #define S5P_INT_LOCAL_PWR_EN 0x7 -#define S5P_CHECK_SLEEP0x0BAD - /* Only for EXYNOS4210 */ #define S5P_CMU_CLKSTOP_LCD1_LOWPWRS5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 06/20] ARM: exynos: cpuidle: Fix S5P_WAKEUP_STAT call
This function should be called only when the powerdown sequence fails.
Even if the current code does not hurt, by moving this line, we have the same
code than the one in pm.c.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index cdfb1ae..6663349 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -134,11 +134,10 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* Clear wakeup state register */
+ __raw_writel(0x0, S5P_WAKEUP_STAT);
}
- /* Clear wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
-
return index;
}
--
1.7.9.5
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[PATCH V4 12/20] ARM: exynos: cpuidle: Encapsulate boot vector code into a function
Signed-off-by: Daniel Lezcano
---
arch/arm/mach-exynos/cpuidle.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index ddbb2c5..ed7a439 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -45,13 +45,16 @@ static void exynos_set_wakeupmask(long mask)
__raw_writel(mask, S5P_WAKEUP_MASK);
}
+static void exynos_cpu_set_boot_vector(long flags)
+{
+ __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
+ __raw_writel(flags, REG_DIRECTGO_FLAG);
+}
+
static int idle_finisher(unsigned long flags)
{
exynos_set_wakeupmask(0xff3e);
-
- __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
--
1.7.9.5
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[PATCH V4 07/20] ARM: exynos: cpuidle: Use the cpu_pm notifier
Use the cpu_pm_enter/exit notifier to group some pm code inside the pm file.
The save and restore code is duplicated across pm.c and cpuidle.c. By using
the cpu_pm notifier, we can factor out the routine.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 24
arch/arm/mach-exynos/pm.c | 29 +
2 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 6663349..7f1f4ef 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -65,26 +65,6 @@ static void exynos_set_wakeupmask(void)
__raw_writel(0xff3e, S5P_WAKEUP_MASK);
}
-static unsigned int g_pwr_ctrl, g_diag_reg;
-
-static void save_cpu_arch_register(void)
-{
- /*read power control register*/
- asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
- /*read diagnostic register*/
- asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
- return;
-}
-
-static void restore_cpu_arch_register(void)
-{
- /*write power control register*/
- asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
- /*write diagnostic register*/
- asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
- return;
-}
-
static int idle_finisher(unsigned long flags)
{
exynos_set_wakeupmask();
@@ -106,8 +86,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
{
unsigned long tmp;
- save_cpu_arch_register();
-
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
@@ -122,8 +100,6 @@ static int exynos_enter_core0_aftr(struct cpuidle_device
*dev,
#endif
cpu_pm_exit();
- restore_cpu_arch_register();
-
/*
* If PMU failed while entering sleep mode, WFI will be
* ignored by PMU and then exiting cpu_do_idle().
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index adfdf4b..67d75fe 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -321,10 +322,38 @@ static const struct platform_suspend_ops
exynos_suspend_ops = {
.valid = suspend_valid_only_mem,
};
+static int exynos_cpu_pm_notifier(struct notifier_block *self,
+ unsigned long cmd, void *v)
+{
+ int cpu = smp_processor_id();
+
+ switch (cmd) {
+ case CPU_PM_ENTER:
+ if (cpu == 0) {
+ exynos_cpu_save_register();
+ }
+ break;
+
+ case CPU_PM_EXIT:
+ if (cpu == 0) {
+ exynos_cpu_restore_register();
+ }
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block exynos_cpu_pm_notifier_block = {
+ .notifier_call = exynos_cpu_pm_notifier,
+};
+
void __init exynos_pm_init(void)
{
u32 tmp;
+ cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
+
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
--
1.7.9.5
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[PATCH V4 18/20] ARM: exynos: cpuidle: Pass the AFTR callback to the platform_data
No more dependency on the arch code. The platform_data field is used to set the
PM callback as the other cpuidle drivers.
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/cpuidle.c |4 +++-
arch/arm/mach-exynos/exynos.c |5 +++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 0651293..ef592ad 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -27,7 +27,7 @@
#include
-#include "common.h"
+static void (*exynos_enter_aftr)(void);
static int idle_finisher(unsigned long flags)
{
@@ -86,6 +86,8 @@ static int exynos_cpuidle_probe(struct platform_device *pdev)
{
int ret;
+ exynos_enter_aftr = (void *)(pdev->dev.platform_data);
+
ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fe8dac8..d22f0e4 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -221,8 +221,9 @@ void exynos_restart(enum reboot_mode mode, const char *cmd)
}
static struct platform_device exynos_cpuidle = {
- .name = "exynos_cpuidle",
- .id = -1,
+ .name = "exynos_cpuidle",
+ .dev.platform_data = exynos_enter_aftr,
+ .id= -1,
};
void __init exynos_cpuidle_init(void)
--
1.7.9.5
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[PATCH V4 19/20] ARM: exynos: cpuidle: Cleanup all unneeded headers from cpuidle.c
Signed-off-by: Daniel Lezcano --- arch/arm/mach-exynos/cpuidle.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ef592ad..52ef229a 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -8,25 +8,15 @@ * published by the Free Software Foundation. */ -#include -#include #include #include -#include #include -#include #include #include #include -#include #include -#include -#include - -#include - static void (*exynos_enter_aftr)(void); static int idle_finisher(unsigned long flags) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 03/20] ARM: exynos: cpuidle: Change function name prefix
The driver was initially written for exynos4 but the driver is used also for
exynos5.
Change the function prefix name exynos4 -> exynos
Signed-off-by: Daniel Lezcano
Reviewed-by: Viresh Kumar
Reviewed-by: Bartlomiej Zolnierkiewicz
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/cpuidle.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index b7cd75b..16e3325 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -60,7 +60,7 @@
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos4_set_wakeupmask(void)
+static void exynos_set_wakeupmask(void)
{
__raw_writel(0xff3e, S5P_WAKEUP_MASK);
}
@@ -91,13 +91,13 @@ static int idle_finisher(unsigned long flags)
return 1;
}
-static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+static int exynos_enter_core0_aftr(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
unsigned long tmp;
- exynos4_set_wakeupmask();
+ exynos_set_wakeupmask();
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
@@ -141,7 +141,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device
*dev,
return index;
}
-static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+static int exynos_enter_lowpower(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
@@ -154,7 +154,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device
*dev,
if (new_index == 0)
return arm_cpuidle_simple_enter(dev, drv, new_index);
else
- return exynos4_enter_core0_aftr(dev, drv, new_index);
+ return exynos_enter_core0_aftr(dev, drv, new_index);
}
static void __init exynos5_core_down_clk(void)
@@ -189,13 +189,13 @@ static void __init exynos5_core_down_clk(void)
__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
}
-static struct cpuidle_driver exynos4_idle_driver = {
- .name = "exynos4_idle",
+static struct cpuidle_driver exynos_idle_driver = {
+ .name = "exynos_idle",
.owner = THIS_MODULE,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE,
[1] = {
- .enter = exynos4_enter_lowpower,
+ .enter = exynos_enter_lowpower,
.exit_latency = 300,
.target_residency = 10,
.flags = CPUIDLE_FLAG_TIME_VALID,
@@ -215,9 +215,9 @@ static int exynos_cpuidle_probe(struct platform_device
*pdev)
exynos5_core_down_clk();
if (soc_is_exynos5440())
- exynos4_idle_driver.state_count = 1;
+ exynos_idle_driver.state_count = 1;
- ret = cpuidle_register(&exynos4_idle_driver, NULL);
+ ret = cpuidle_register(&exynos_idle_driver, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
return ret;
--
1.7.9.5
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