Re: [PATCH 2/7] mfd: cros_ec: spi: Add mutex to cros_ec_spi

[Simon Glass]

Hi Doug,

On 18 April 2014 15:15, Doug Anderson  wrote:
>
> Simon,
>
> On Fri, Apr 18, 2014 at 10:28 AM, Simon Glass  wrote:
> > Hi Doug,
> >
> > On 17 April 2014 11:59, Doug Anderson  wrote:
> >> The main transfer function for cros_ec_spi can be called by more than
> >> one client at a time.  Make sure that those clients don't stomp on
> >> each other by locking the bus for the duration of the transfer
> >> function.
> >
> > Is there no lock at the cros_ec layer?
>
> Not with what's upstream.
>
> Locally in the Chromium OS tree:
>
> * You can see that Bill removed the dev_lock at
>  since it wasn't
> used.
>
> * Andrew moved to a common locking scheme later in
>  (thus adding
> roughly the same lock back and using it), but in order to do that
> we've got a dozen pathces in between, some of which are big
> reorganizations.  This includes at least:
>
> 6820b91 CHROMIUM: cros_ec: Tweak struct cros_ec_device for clarity
> 5e8e562 CHROMIUM: Use struct cros_ec_command to communicate with the EC
> 9e7db82 CHROMIUM: cleanup: remove unused fields from struct cros_ec_device
> 866e62d CHROMIUM: cleanup: Remove EC wrapper functions.
> 8a372b2 cros_ec: move locking into cros_ec_cmd_xfer
> 981c4aa cros_ec: stop calling ->cmd_xfer() directly
>
> I think we should take in some of those other changes but I'd rather
> get correctness in first (since people are wanting to use this driver
> in upstream kernel) and get cleanups posted after this lands.  I was
> also trying not to spam the list with a 20-patch series...

That explains it, thank you. I should have guessed that for myself.

Reviewed-by: Simon Glass 

Regards,
Simon
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Re: [PATCH 2/7] mfd: cros_ec: spi: Add mutex to cros_ec_spi

[Doug Anderson]

Simon,

On Fri, Apr 18, 2014 at 10:28 AM, Simon Glass  wrote:
> Hi Doug,
>
> On 17 April 2014 11:59, Doug Anderson  wrote:
>> The main transfer function for cros_ec_spi can be called by more than
>> one client at a time.  Make sure that those clients don't stomp on
>> each other by locking the bus for the duration of the transfer
>> function.
>
> Is there no lock at the cros_ec layer?

Not with what's upstream.

Locally in the Chromium OS tree:

* You can see that Bill removed the dev_lock at
 since it wasn't
used.

* Andrew moved to a common locking scheme later in
 (thus adding
roughly the same lock back and using it), but in order to do that
we've got a dozen pathces in between, some of which are big
reorganizations.  This includes at least:

6820b91 CHROMIUM: cros_ec: Tweak struct cros_ec_device for clarity
5e8e562 CHROMIUM: Use struct cros_ec_command to communicate with the EC
9e7db82 CHROMIUM: cleanup: remove unused fields from struct cros_ec_device
866e62d CHROMIUM: cleanup: Remove EC wrapper functions.
8a372b2 cros_ec: move locking into cros_ec_cmd_xfer
981c4aa cros_ec: stop calling ->cmd_xfer() directly

I think we should take in some of those other changes but I'd rather
get correctness in first (since people are wanting to use this driver
in upstream kernel) and get cleanups posted after this lands.  I was
also trying not to spam the list with a 20-patch series...

-Doug
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Re: [PATCH v3 5/5] regulator: tps65090: Make FETs more reliable by adding retries

[Doug Anderson]

Mark,

On Fri, Apr 18, 2014 at 10:43 AM, Mark Brown  wrote:
> On Wed, Apr 16, 2014 at 04:12:29PM -0700, Doug Anderson wrote:
>> An issue was discovered with tps65090 where sometimes the FETs
>> wouldn't actually turn on when requested (they would report
>> overcurrent).  The most problematic FET was the one used for the LCD
>
> This is basically fine but you said it depends on one of the previous
> patches which you didn't CC me on so I've no idea what's going on
> there?

Sorry about that.  :(

Lee has Acked the caching patch.  Lee: what's the best way for you and
Mark to coordinate there?  Should he apply the caching patch with your
Ack?

-Doug
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Re: [PATCH v3 5/5] regulator: tps65090: Make FETs more reliable by adding retries

[Mark Brown]

On Wed, Apr 16, 2014 at 04:12:29PM -0700, Doug Anderson wrote:
> An issue was discovered with tps65090 where sometimes the FETs
> wouldn't actually turn on when requested (they would report
> overcurrent).  The most problematic FET was the one used for the LCD

This is basically fine but you said it depends on one of the previous
patches which you didn't CC me on so I've no idea what's going on
there?


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Re: [PATCH 4/7] mfd: cros_ec: spi: Increase cros_ec_spi deadline from 5ms to 100ms

[Simon Glass]

Hi Doug,

On 17 April 2014 11:59, Doug Anderson  wrote:
> We're adding i2c tunneling to the list of things that goes over
> cros_ec.  i2c tunneling can be slooow, so increase our deadline to
> 100ms to account for that.
>
> Signed-off-by: Doug Anderson 

I believe the EC protocol should be changed on future platforms to
poll for completion of I2C, but in the meantime this patch prevents
failure.

Reviewed-by: Simon Glass 
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Re: [PATCH 5/7] mfd: cros_ec: Sync to the latest cros_ec_commands.h from EC sources

[Simon Glass]

On 17 April 2014 11:59, Doug Anderson  wrote:
> From: Bill Richardson 
>
> This just updates include/linux/mfd/cros_ec_commands.h to match the
> latest EC version (which is the One True Source for such things).  See
> 
>
> [dianders: took today's ToT version from the Chromium OS EC; deleted
> references to cros_ec_dev and cros_ec_lpc since those aren't upstream
> yet]
>
> Signed-off-by: Bill Richardson 
> Signed-off-by: Doug Anderson 

Reviewed-by: Simon Glass 
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Re: [PATCH 2/7] mfd: cros_ec: spi: Add mutex to cros_ec_spi

[Simon Glass]

Hi Doug,

On 17 April 2014 11:59, Doug Anderson  wrote:
> The main transfer function for cros_ec_spi can be called by more than
> one client at a time.  Make sure that those clients don't stomp on
> each other by locking the bus for the duration of the transfer
> function.

Is there no lock at the cros_ec layer?

Regards,
Simon
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Re: [PATCH 4/4] regulator: s5m8767: Use same binding for external control as in s2mps11

[Mark Brown]

On Tue, Apr 15, 2014 at 10:55:45AM +0200, Krzysztof Kozlowski wrote:

> Anyway more drivers seem to use this kind of binding (tps65090, max8952,
> da9055, arizona) so maybe there is a point in making this generic?

Yes.


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Re: [PATCH 1/7] mfd: cros_ec: spi: calculate delay between transfers correctly

[Simon Glass]

On 17 April 2014 11:59, Doug Anderson  wrote:
> From: David Hendricks 
>
> To avoid spamming the EC we calculate the time between the previous
> transfer and the current transfer and force a delay if the time delta
> is too small.
>
> However, a small miscalculation causes the delay period to be
> far too short. Most noticably this impacts commands with a long
> turnaround time such as EC firmware reads and writes.
>
> Signed-off-by: David Hendricks 
> Signed-off-by: Doug Anderson 

Reviewed-by: Simon Glass 
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Re: [PATCH 3/7] mfd: cros_ec: spi: Make the cros_ec_spi timeout more reliable

[Simon Glass]

On 17 April 2014 11:59, Doug Anderson  wrote:
> The cros_ec_spi transfer had two problems with its timeout code:
>
> 1. It looked at the timeout even in the case that it found valid data.
> 2. If the cros_ec_spi code got switched out for a while, it's possible
>it could get a timeout after a single loop.  Let's be paranoid and
>make sure we do one last transfer after the timeout expires.
>
> Signed-off-by: Doug Anderson 

Reviewed-by: Simon Glass 
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Re: [PATCH 1/2] dt-bindings: clock: Move at91.h to dt-bindigs/clock

[Nicolas Ferre]

On 06/03/2014 07:04, Tushar Behera :
> Most of the clock related dt-binding header files are located in
> dt-bindings/clock folder. It would be good to keep all the similar
> header files at a single location.
> 
> Signed-off-by: Tushar Behera 
> CC: Rob Landley 
> CC: Andrew Victor 
> CC: Jean-Christophe Plagniol-Villard 

I have just added at91sam9261 and at91sam9rl which appeared in 3.15
merge window and stacked this patch on top of at91-3.15-fixes.

I hope that it will be accepted for 3.15.

Bye,


> ---
>  .../devicetree/bindings/clock/at91-clock.txt   |2 +-
>  arch/arm/boot/dts/sama5d3.dtsi |2 +-
>  arch/arm/boot/dts/sama5d3_mci2.dtsi|2 +-
>  arch/arm/boot/dts/sama5d3_tcb1.dtsi|2 +-
>  arch/arm/boot/dts/sama5d3_uart.dtsi|2 +-
>  include/dt-bindings/{clk => clock}/at91.h  |0
>  6 files changed, 5 insertions(+), 5 deletions(-)
>  rename include/dt-bindings/{clk => clock}/at91.h (100%)
> 
> diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt 
> b/Documentation/devicetree/bindings/clock/at91-clock.txt
> index cd5e239..6794cdc 100644
> --- a/Documentation/devicetree/bindings/clock/at91-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
> @@ -62,7 +62,7 @@ Required properties for PMC node:
>  - interrupt-controller : tell that the PMC is an interrupt controller.
>  - #interrupt-cells : must be set to 1. The first cell encodes the interrupt 
> id,
>   and reflect the bit position in the PMC_ER/DR/SR registers.
> - You can use the dt macros defined in dt-bindings/clk/at91.h.
> + You can use the dt macros defined in dt-bindings/clock/at91.h.
>   0 (AT91_PMC_MOSCS) -> main oscillator ready
>   1 (AT91_PMC_LOCKA) -> PLL A ready
>   2 (AT91_PMC_LOCKB) -> PLL B ready
> diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
> index 3d5faf8..8c977b5 100644
> --- a/arch/arm/boot/dts/sama5d3.dtsi
> +++ b/arch/arm/boot/dts/sama5d3.dtsi
> @@ -13,7 +13,7 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
>  
>  / {
>   model = "Atmel SAMA5D3 family SoC";
> diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi 
> b/arch/arm/boot/dts/sama5d3_mci2.dtsi
> index b029fe7..1b02208 100644
> --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
> +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
> @@ -9,7 +9,7 @@
>  
>  #include 
>  #include 
> -#include 
> +#include 
>  
>  / {
>   ahb {
> diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi 
> b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
> index 382b044..0284845 100644
> --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
> +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
> @@ -9,7 +9,7 @@
>  
>  #include 
>  #include 
> -#include 
> +#include 
>  
>  / {
>   aliases {
> diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi 
> b/arch/arm/boot/dts/sama5d3_uart.dtsi
> index a9fa75e..7a8d4c6 100644
> --- a/arch/arm/boot/dts/sama5d3_uart.dtsi
> +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
> @@ -9,7 +9,7 @@
>  
>  #include 
>  #include 
> -#include 
> +#include 
>  
>  / {
>   aliases {
> diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clock/at91.h
> similarity index 100%
> rename from include/dt-bindings/clk/at91.h
> rename to include/dt-bindings/clock/at91.h
> 


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Re: [PATCH v3 4/5] regulator: tps65090: Allow setting the overcurrent wait time

[Mark Brown]

On Wed, Apr 16, 2014 at 04:12:28PM -0700, Doug Anderson wrote:
> The tps65090 regulator allows you to specify how long you want it to
> wait before detecting an overcurrent condition.  Allow specifying that
> through the device tree (or through platform data).

Applied, thanks.

> +- ti,overcurrent-wait: This is applicable to FET registers, which have a
> +  poorly defined "overcurrent wait" field.  If this property is present it
> +  should be between 0 - 3.  If this property isn't present we won't touch the
> +  "overcurrent wait" field and we'll leave it to the BIOS/EC to deal with.

What I was driving at by asking if this was the raw register value was
that the binding should make this clearer ideally.


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[PATCH 2/4] ARM: EXYNOS: Fix core ID used by platsmp and hotplug code

[Tomasz Figa]

When CPU topology is specified in device tree, cpu_logical_map() does
not return core ID anymore, but rather full MPIDR value. This breaks
existing calculation of PMU register offsets on Exynos SoCs.

This patch fixes the problem by adjusting the code to use only core ID
bits of the value returned by cpu_logical_map() to allow CPU topology to
be specified in device tree on Exynos SoCs.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-exynos/hotplug.c | 10 ++
 arch/arm/mach-exynos/platsmp.c | 31 ++-
 2 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 7e0f31a..8a5f07d 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -92,11 +92,13 @@ static inline void cpu_leave_lowpower(void)
 
 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
+   u32 mpidr = cpu_logical_map(cpu);
+   u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
for (;;) {
 
-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(1));
+   /* Turn the CPU off on next WFI instruction. */
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(core_id));
 
/*
 * here's the WFI
@@ -106,7 +108,7 @@ static inline void platform_do_lowpower(unsigned int cpu, 
int *spurious)
:
: "memory", "cc");
 
-   if (pen_release == cpu_logical_map(cpu)) {
+   if (pen_release == core_id) {
/*
 * OK, proper wakeup, we're done
 */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 7b7de4b..e08b2c5 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -89,7 +89,9 @@ static void exynos_secondary_init(unsigned int cpu)
 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
unsigned long timeout;
-   unsigned long phys_cpu = cpu_logical_map(cpu);
+   u32 mpidr = cpu_logical_map(cpu);
+   u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   u32 reg;
 
/*
 * Set synchronisation state between this boot processor
@@ -102,19 +104,20 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 * the holding pen - release it, then wait for it to flag
 * that it has been released by resetting pen_release.
 *
-* Note that "pen_release" is the hardware CPU ID, whereas
+* Note that "pen_release" is the hardware CPU core ID, whereas
 * "cpu" is Linux's internal ID.
 */
-   write_pen_release(phys_cpu);
+   write_pen_release(core_id);
 
-   if (!(__raw_readl(S5P_ARM_CORE_STATUS(1)) & S5P_CORE_LOCAL_PWR_EN)) {
+   reg = __raw_readl(S5P_ARM_CORE_STATUS(core_id));
+   if (!(reg & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE_CONFIGURATION(1));
+S5P_ARM_CORE_CONFIGURATION(core_id));
 
timeout = 10;
 
/* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE_STATUS(1))
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(core_id))
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -146,10 +149,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 * Try to set boot address using firmware first
 * and fall back to boot register if it fails.
 */
-   if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
-   __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+   if (call_firmware_op(set_cpu_boot_addr, core_id, boot_addr))
+   __raw_writel(boot_addr, cpu_boot_reg(core_id));
 
-   call_firmware_op(cpu_boot, phys_cpu);
+   call_firmware_op(cpu_boot, core_id);
 
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
@@ -215,14 +218,16 @@ static void __init exynos_smp_prepare_cpus(unsigned int 
max_cpus)
 * boot register if it fails.
 */
for (i = 1; i < max_cpus; ++i) {
-   unsigned long phys_cpu;
unsigned long boot_addr;
+   u32 mpidr;
+   u32 core_id;
 
-   phys_cpu = cpu_logical_map(i);
+   mpidr = cpu_logical_map(i);
+   core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
boot_addr = virt_to_phys(exynos4_secondary_startup);
 
-   if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
-   __raw_writel(boot_

[PATCH 0/4] Fixes for DT CPU topology specification on Exynos

[Tomasz Figa]

Due to some parts of Exynos SoC support designed originally in a non-scalable
way, relying on 1:1 mapping between value returned by cpu_logical_map() and
CPU IDs as seen by PMU and GIC, trying to specify CPU topology in device tree
caused various boot-up issues on Exynos SoCs, ranging from CPUs other than 0
failing to boot to crashes due to GIC driver accessing registers out of range.

This series attempts to fix aforementioned issues by removing incorrect
assumptions from Exynos SoC core code and GIC driver and then adding CPU
topology data to device tree sources of Exynos4.

[On Exynos4210-based TRATS and Exynos4412-based TRATS2 board]
Tested-by: Tomasz Figa 

Tomasz Figa (4):
  ARM: EXYNOS: Fix definitions of S5P_ARM_CORE_* registers
  ARM: EXYNOS: Fix core ID used by platsmp and hotplug code
  irqchip: gic: Add support for per CPU bank offset specification in DT
  ARM: dts: exynos4: Add CPU topology data

 Documentation/devicetree/bindings/arm/cpus.txt |  7 ++
 Documentation/devicetree/bindings/arm/gic.txt  | 34 +-
 arch/arm/boot/dts/exynos4210.dtsi  | 19 ++
 arch/arm/boot/dts/exynos4212.dtsi  | 19 ++
 arch/arm/boot/dts/exynos4412.dtsi  | 37 --
 arch/arm/mach-exynos/hotplug.c | 10 +--
 arch/arm/mach-exynos/platsmp.c | 31 +
 arch/arm/mach-exynos/regs-pmu.h|  4 +-
 drivers/irqchip/irq-gic.c  | 94 ++
 9 files changed, 202 insertions(+), 53 deletions(-)

-- 
1.9.2

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[PATCH 1/4] ARM: EXYNOS: Fix definitions of S5P_ARM_CORE_* registers

[Tomasz Figa]

On SoCs with more than 2 cores there are more than 2 S5P_ARM_CORE_*
registers that can be addressed with fixed stride of 0x80. This patch
renames the definitions of S5P_ARM_CORE1_* registers to be S5P_ARM_CORE_*
and make them take physical core ID as argument to calculate register
address.

Signed-off-by: Tomasz Figa 
---
 arch/arm/mach-exynos/hotplug.c  | 2 +-
 arch/arm/mach-exynos/platsmp.c  | 6 +++---
 arch/arm/mach-exynos/regs-pmu.h | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..7e0f31a 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -96,7 +96,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int 
*spurious)
 
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(1));
 
/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..7b7de4b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -107,14 +107,14 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);
 
-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(1)) & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(1));
 
timeout = 10;
 
/* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(1))
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..d94bbc8 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,8 @@
 #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR   S5P_PMUREG(0x13A0)
 
-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE_CONFIGURATION(n)  S5P_PMUREG(0x2000 + (n) * 0x80)
+#define S5P_ARM_CORE_STATUS(n) S5P_PMUREG(0x2004 + (n) * 0x80)
 
 #define S5P_PAD_RET_MAUDIO_OPTION  S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTIONS5P_PMUREG(0x3108)
-- 
1.9.2

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[PATCH 4/4] ARM: dts: exynos4: Add CPU topology data

[Tomasz Figa]

After fixing non-banked GIC support in GIC driver, CPU nodes can be
safely added to Exynos4 device tree sources, along with appropriate
gic-offset properties.

Signed-off-by: Tomasz Figa 
---
 arch/arm/boot/dts/exynos4210.dtsi | 19 +++
 arch/arm/boot/dts/exynos4212.dtsi | 19 +++
 arch/arm/boot/dts/exynos4412.dtsi | 37 +
 3 files changed, 71 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index cacf614..e463361 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -25,6 +25,25 @@
 / {
compatible = "samsung,exynos4210", "samsung,exynos4";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@900 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0x900>;
+   gic-offset = <0x>;
+   };
+
+   cpu@901 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0x901>;
+   gic-offset = <0x8000>;
+   };
+   };
+
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi 
b/arch/arm/boot/dts/exynos4212.dtsi
index 3c00e6e..211e129 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,6 +22,25 @@
 / {
compatible = "samsung,exynos4212", "samsung,exynos4";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@a00 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa00>;
+   gic-offset = <0x>;
+   };
+
+   cpu@a01 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa01>;
+   gic-offset = <0x8000>;
+   };
+   };
+
combiner: interrupt-controller@1044 {
samsung,combiner-nr = <18>;
};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
b/arch/arm/boot/dts/exynos4412.dtsi
index 15d3c0a..04530ef 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,11 +22,40 @@
 / {
compatible = "samsung,exynos4412", "samsung,exynos4";
 
-   combiner: interrupt-controller@1044 {
-   samsung,combiner-nr = <20>;
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@a00 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa00>;
+   gic-offset = <0x>;
+   };
+
+   cpu@a01 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa01>;
+   gic-offset = <0x4000>;
+   };
+
+   cpu@a02 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa02>;
+   gic-offset = <0x8000>;
+   };
+
+   cpu@a03 {
+   compatible = "arm,cortex-a9";
+   device_type = "cpu";
+   reg = <0xa03>;
+   gic-offset = <0xc000>;
+   };
};
 
-   gic: interrupt-controller@1049 {
-   cpu-offset = <0x4000>;
+   combiner: interrupt-controller@1044 {
+   samsung,combiner-nr = <20>;
};
 };
-- 
1.9.2

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[PATCH 3/4] irqchip: gic: Add support for per CPU bank offset specification in DT

[Tomasz Figa]

On most platforms GIC registers are banked, so each CPU can access its
registers at the same address. However there is a small number of SoCs
on which the banking is not implemented and each CPU has its GIC
register set at different offset from GIC base address.

Originally the driver used simple maths to calculate the address, i.e.
multiplying constant percpu_offset by cpu_logical_map(cpu). However this
assumed the namespace of cpu_logical_map() to be from 0 to num_cpus-1,
but if CPU topology is specified via DT, this changes to full ID in
the same format as MPIDR register and thus breaks the assumption.

This patch adds support for per CPU GIC bank offset specification
through device tree to separate SoC-internal core wiring from CPU
multi-processor IDs.

Signed-off-by: Tomasz Figa 
---
 Documentation/devicetree/bindings/arm/cpus.txt |  7 ++
 Documentation/devicetree/bindings/arm/gic.txt  | 34 +-
 drivers/irqchip/irq-gic.c  | 94 ++
 3 files changed, 105 insertions(+), 30 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 333f4ae..47654e6 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -209,6 +209,13 @@ nodes to be present and contain the properties described 
below.
Value type: 
Definition: Specifies the ACC[2] node associated with this CPU.
 
+   - gic-offset
+   Usage: required for systems that have non-banked GIC
+  implementation that requires each CPU to use different
+  offset to access its set of GIC registers
+   Value type: 
+   Definition: Specifies the offset of GIC registers specific to
+   this CPU.
 
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 
diff --git a/Documentation/devicetree/bindings/arm/gic.txt 
b/Documentation/devicetree/bindings/arm/gic.txt
index 5573c08..2bd03406 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -48,7 +48,7 @@ Optional
 
 - cpu-offset   : per-cpu offset within the distributor and cpu interface
   regions, used when the GIC doesn't have banked registers. The offset is
-  cpu-offset * cpu-nr.
+  cpu-offset * cpu-nr. (DEPRECATED, see per-CPU 'gic-offset' property.)
 
 - arm,routable-irqs : Total number of gic irq inputs which are not directly
  connected from the peripherals, but are routed dynamically
@@ -67,6 +67,38 @@ Example:
  <0xfff10100 0x100>;
};
 
+* Per-CPU register offset specification for non-banked GIC
+
+On most platforms GIC registers are banked, so each CPU can access its
+registers at the same address. However there is a small number of SoCs
+on which the banking is not implemented and each CPU has its GIC
+register set at different offset from GIC base address. These offsets
+need to be be provided from device tree, as described below.
+
+Optional properties in node of each CPU in the system:
+
+ - gic-offset : A single u32 value that needs to be added to GIC base
+   address to calculate address of GIC registers for that CPU.
+
+See [1] for more details about ARM CPU bindings.
+
+Example:
+
+   cpus {
+   /* ... */
+
+   cpu@a00 {
+   /* ... */
+   gic-offset = <0x>;
+   };
+
+   cpu@a01 {
+   /* ... */
+   gic-offset = <0x8000>;
+   };
+   };
+
+[1] Documentation/devicetree/bindings/arm/cpus.txt
 
 * GIC virtualization extensions (VGIC)
 
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4300b66..ad6f4fe 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -924,6 +924,69 @@ const struct irq_domain_ops 
gic_default_routable_irq_domain_ops = {
 const struct irq_domain_ops *gic_routable_irq_domain_ops =
&gic_default_routable_irq_domain_ops;
 
+static int gic_setup_bases(struct gic_chip_data *gic, void __iomem *dist_base,
+  void __iomem *cpu_base, u32 percpu_offset)
+{
+   bool use_cpu_nodes = true;
+   u32 offset;
+   unsigned int cpu;
+
+   for_each_possible_cpu(cpu) {
+   struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
+
+   if (!cpu_node
+   || of_property_read_u32(cpu_node, "gic-offset", &offset)) {
+   use_cpu_nodes = false;
+   break;
+   }
+   }
+
+   if (!(percpu_offset || use_cpu_nodes)
+   || !IS_ENABLED(CONFIG_GIC_NON_BANKED)) {
+   /* Normal, sane GIC... (or non-banked unsupported) */
+   WARN(percpu_offset || use_cpu_nodes,
+"GIC_NON_BANKED not enabled, ignoring

Re: [PATCH] arm: exynos: generalize power register address calculation

[Tomasz Figa]

Hi Chander,

On 15.04.2014 09:38, Chander Kashyap wrote:

Currently status/configuration power register values are hard-coded for cpu1.

Make it generic so that it is useful for SoC's with more than two cpus.

Signed-off-by: Chander Kashyap 
---
changes in v3:
1. Move cpunr calculation to a macro
2. Changed printk format specifier from unsigned hex to unsigned decimal
Changes in v2:
1. Used existing macros for clusterid and cpuid calculation

  arch/arm/mach-exynos/hotplug.c  |7 ---
  arch/arm/mach-exynos/platsmp.c  |   13 +++--
  arch/arm/mach-exynos/regs-pmu.h |   15 +--
  3 files changed, 24 insertions(+), 11 deletions(-)



Now as I think of it, the code that is touched by this patch is not 
supposed to be used on multi-cluster systems. Instead a separate MCPM 
driver should. As far as I know, somebody is said to be already working 
on this.


This means that we don't need to consider multi-cluster support in this 
patch and simplify any calculations to just account for core ID. This 
would also eliminate any need to handle non-zero cluster ID on 
single-cluster SoCs.


Please correct me if I'm wrong.


diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead53..9f74be2 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -92,11 +92,12 @@ static inline void cpu_leave_lowpower(void)

  static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
  {
+   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
for (;;) {

-   /* make cpu1 to be turned off at next WFI command */
-   if (cpu == 1)
-   __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+   /* make cpu to be turned off at next WFI command */
+   if (cpu)


As I mentioned in my previous reply, I don't see what could go wrong if 
this check is omitted. What happens if CPU0 is being hot-unplugged?


If hardware doesn't support this (but I don't see any mention about this 
in the documentation), such hotplug attempt should either simply fail on 
.cpu_kill() operation for CPU0 or even have CPU0 marked as non-hotpluggable.



+   __raw_writel(0, S5P_ARM_CORE_CONFIGURATION(cpunr));

/*
 * here's the WFI
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f..d9c182f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -90,7 +90,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
  {
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
-
+   unsigned int cpunr = ENYNOS_PMU_CPUNR(cpu_logical_map(cpu));
/*
 * Set synchronisation state between this boot processor
 * and the secondary one
@@ -107,14 +107,15 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
 */
write_pen_release(phys_cpu);

-   if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+   if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
+   & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
-S5P_ARM_CORE1_CONFIGURATION);
+S5P_ARM_CORE_CONFIGURATION(cpunr));

timeout = 10;

-   /* wait max 10 ms until cpu1 is on */
-   while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+   /* wait max 10 ms until secondary cpu is on */
+   while ((__raw_readl(S5P_ARM_CORE_STATUS(cpunr))
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -123,7 +124,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct 
task_struct *idle)
}

if (timeout == 0) {
-   printk(KERN_ERR "cpu1 power enable failed");
+   pr_err("cpu%u power enable failed", cpu);
spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..0de6df4 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -105,8 +105,13 @@
  #define S5P_GPS_LOWPWRS5P_PMUREG(0x139C)
  #define S5P_GPS_ALIVE_LOWPWR  S5P_PMUREG(0x13A0)

-#define S5P_ARM_CORE1_CONFIGURATIONS5P_PMUREG(0x2080)
-#define S5P_ARM_CORE1_STATUS   S5P_PMUREG(0x2084)
+#define S5P_ARM_CORE0_CONFIGURATIONS5P_PMUREG(0x2000)
+#define S5P_ARM_CORE0_STATUS   S5P_PMUREG(0x2004)
+
+#define S5P_ARM_CORE_CONFIGURATION(_cpunr) \
+   (S5P_ARM_CORE0_CONFIGURATION + 0x80 * (_cpunr))
+#define S5P_ARM_CORE_STATUS(_cpu

[PATCH] ARM: dts: disable MDMA1 node for smdk5420 board

[Seungwon Jeon]

This change is similar to commit 3da355c(ARM: dts: Disable MDMA1 node
for arndale-octa board). If MDMA1 region is configured with secure mode,
it makes the boot failure with the following.

Unhandled fault: imprecise external abort (0x1406) at 0x

Signed-off-by: Seungwon Jeon 
---
 arch/arm/boot/dts/exynos5420-smdk5420.dts |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6910485..9a48e3f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -373,4 +373,10 @@
};
};
};
+
+   amba {
+   mdma1: mdma@11C1 {
+   status = "disabled";
+   };
+   };
 };
-- 
1.7.0.4


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[PATCH v2 1/6] mfd/rtc: sec/s5m: Rename SEC* symbols to S5M

[Krzysztof Kozlowski]

This patch prepares for adding support for S2MPS14 RTC device to the
rtc-s5m driver:
1. Renames SEC* symbols to S5M.
2. Adds S5M prefix to some of defines which are different between S5M876X
and S2MPS14.

This is only a rename-like patch, new code is not added.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
Acked-by: Lee Jones 
---
 drivers/rtc/rtc-s5m.c   | 66 +--
 include/linux/mfd/samsung/rtc.h | 76 -
 2 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 8ec2d6a1dbe1..b37df8c790f2 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -30,10 +30,10 @@
 
 /*
  * Maximum number of retries for checking changes in UDR field
- * of SEC_RTC_UDR_CON register (to limit possible endless loop).
+ * of S5M_RTC_UDR_CON register (to limit possible endless loop).
  *
  * After writing to RTC registers (setting time or alarm) read the UDR field
- * in SEC_RTC_UDR_CON register. UDR is auto-cleared when data have
+ * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
  * been transferred.
  */
 #define UDR_READ_RETRY_CNT 5
@@ -54,7 +54,7 @@ static const struct regmap_config s5m_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
 
-   .max_register = SEC_RTC_REG_MAX,
+   .max_register = S5M_RTC_REG_MAX,
 };
 
 static const struct regmap_config s2mps14_rtc_regmap_config = {
@@ -119,8 +119,8 @@ static inline int s5m8767_wait_for_udr_update(struct 
s5m_rtc_info *info)
unsigned int data;
 
do {
-   ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data);
-   } while (--retry && (data & RTC_UDR_MASK) && !ret);
+   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
+   } while (--retry && (data & S5M_RTC_UDR_MASK) && !ret);
 
if (!retry)
dev_err(info->dev, "waiting for UDR update, reached max number 
of retries\n");
@@ -133,16 +133,16 @@ static inline int s5m8767_rtc_set_time_reg(struct 
s5m_rtc_info *info)
int ret;
unsigned int data;
 
-   ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data);
+   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
if (ret < 0) {
dev_err(info->dev, "failed to read update reg(%d)\n", ret);
return ret;
}
 
-   data |= RTC_TIME_EN_MASK;
-   data |= RTC_UDR_MASK;
+   data |= S5M_RTC_TIME_EN_MASK;
+   data |= S5M_RTC_UDR_MASK;
 
-   ret = regmap_write(info->regmap, SEC_RTC_UDR_CON, data);
+   ret = regmap_write(info->regmap, S5M_RTC_UDR_CON, data);
if (ret < 0) {
dev_err(info->dev, "failed to write update reg(%d)\n", ret);
return ret;
@@ -158,17 +158,17 @@ static inline int s5m8767_rtc_set_alarm_reg(struct 
s5m_rtc_info *info)
int ret;
unsigned int data;
 
-   ret = regmap_read(info->regmap, SEC_RTC_UDR_CON, &data);
+   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read update reg(%d)\n",
__func__, ret);
return ret;
}
 
-   data &= ~RTC_TIME_EN_MASK;
-   data |= RTC_UDR_MASK;
+   data &= ~S5M_RTC_TIME_EN_MASK;
+   data |= S5M_RTC_UDR_MASK;
 
-   ret = regmap_write(info->regmap, SEC_RTC_UDR_CON, data);
+   ret = regmap_write(info->regmap, S5M_RTC_UDR_CON, data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write update reg(%d)\n",
__func__, ret);
@@ -218,7 +218,7 @@ static int s5m_rtc_read_time(struct device *dev, struct 
rtc_time *tm)
u8 data[8];
int ret;
 
-   ret = regmap_bulk_read(info->regmap, SEC_RTC_SEC, data, 8);
+   ret = regmap_bulk_read(info->regmap, S5M_RTC_SEC, data, 8);
if (ret < 0)
return ret;
 
@@ -266,7 +266,7 @@ static int s5m_rtc_set_time(struct device *dev, struct 
rtc_time *tm)
1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday);
 
-   ret = regmap_raw_write(info->regmap, SEC_RTC_SEC, data, 8);
+   ret = regmap_raw_write(info->regmap, S5M_RTC_SEC, data, 8);
if (ret < 0)
return ret;
 
@@ -282,20 +282,20 @@ static int s5m_rtc_read_alarm(struct device *dev, struct 
rtc_wkalrm *alrm)
unsigned int val;
int ret, i;
 
-   ret = regmap_bulk_read(info->regmap, SEC_ALARM0_SEC, data, 8);
+   ret = regmap_bulk_read(info->regmap, S5M_ALARM0_SEC, data, 8);
if (ret < 0)
return ret;
 
switch (info->device_type) {
case S5M8763X:
s5m8763_data_to_tm(data, &alrm->time);
-   ret = regmap_read(info->regmap, SEC_ALARM0_CONF, &val);
+   ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val);
 

[PATCH v2 0/6] rtc: s5m: Add support for S2MPS14

[Krzysztof Kozlowski]

Hi,


This is second version of patches for S5M RTC driver adding support
for S2MPS14 device.

The patchset is rebased against current Linus' tree 
(v3.15-rc1-136-gd3e74dc8280c)
and on my last patch for RTC regmap fixes:
 - mfd/rtc: s5m: Do not allocate RTC I2C dummy and regmap for unsupported 
chipsets
   https://lkml.org/lkml/2014/4/14/50

Changes since v1

1. Add patch 6/6 (rtc: s5m: Consolidate two device type switch statements)


Best regards,
Krzysztof


Krzysztof Kozlowski (6):
  mfd/rtc: sec/s5m: Rename SEC* symbols to S5M
  rtc: s5m: Remove undocumented time init on first boot
  rtc: s5m: Use shorter time of register update
  rtc: s5m: Support different register layout
  rtc: s5m: Add support for S2MPS14 RTC
  rtc: s5m: Consolidate two device type switch statements

 drivers/rtc/Kconfig |   4 +-
 drivers/rtc/rtc-s5m.c   | 310 ++--
 include/linux/mfd/samsung/rtc.h |  86 ++-
 3 files changed, 252 insertions(+), 148 deletions(-)

-- 
1.8.3.2

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[PATCH v2 5/6] rtc: s5m: Add support for S2MPS14 RTC

[Krzysztof Kozlowski]

Add support for S2MPS14 to the rtc-s5m driver. Differences in S2MPS14
(in comparison to S5M8767):
 - Layout of registers;
 - Lack of century support for time and alarms (7 registers used for
   storing time/alarm);
 - Two buffer control registers: WUDR and RUDR;
 - No register for enabling writing time;
 - RTC interrupts are reported in main PMIC I2C device;

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
---
 drivers/rtc/Kconfig   |   4 +-
 drivers/rtc/rtc-s5m.c | 101 +-
 2 files changed, 86 insertions(+), 19 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 2e565f8e5165..d52fa23281f9 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -530,11 +530,11 @@ config RTC_DRV_RV3029C2
  will be called rtc-rv3029c2.
 
 config RTC_DRV_S5M
-   tristate "Samsung S5M series"
+   tristate "Samsung S2M/S5M series"
depends on MFD_SEC_CORE
help
  If you say yes here you will get support for the
- RTC of Samsung S5M PMIC series.
+ RTC of Samsung S2MPS14 and S5M PMIC series.
 
  This driver can also be built as a module. If so, the module
  will be called rtc-s5m.
diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 59860128a221..76287ebd0e35 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -17,16 +17,14 @@
 
 #include 
 #include 
-#include 
 #include 
-#include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 /*
  * Maximum number of retries for checking changes in UDR field
@@ -74,6 +72,21 @@ static const struct s5m_rtc_reg_config s5m_rtc_regs = {
.rtc_udr_mask   = S5M_RTC_UDR_MASK,
 };
 
+/*
+ * Register map for S2MPS14.
+ * It may be also suitable for S2MPS11 but this was not tested.
+ */
+static const struct s5m_rtc_reg_config s2mps_rtc_regs = {
+   .regs_count = 7,
+   .time   = S2MPS_RTC_SEC,
+   .ctrl   = S2MPS_RTC_CTRL,
+   .alarm0 = S2MPS_ALARM0_SEC,
+   .alarm1 = S2MPS_ALARM1_SEC,
+   .smpl_wtsr  = S2MPS_WTSR_SMPL_CNTL,
+   .rtc_udr_update = S2MPS_RTC_UDR_CON,
+   .rtc_udr_mask   = S2MPS_RTC_WUDR_MASK,
+};
+
 struct s5m_rtc_info {
struct device *dev;
struct i2c_client *i2c;
@@ -178,6 +191,11 @@ static inline int s5m_check_peding_alarm_interrupt(struct 
s5m_rtc_info *info,
ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
val &= S5M_ALARM0_STATUS;
break;
+   case S2MPS14X:
+   ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
+   &val);
+   val &= S2MPS_ALARM0_STATUS;
+   break;
default:
return -EINVAL;
}
@@ -203,8 +221,9 @@ static inline int s5m8767_rtc_set_time_reg(struct 
s5m_rtc_info *info)
return ret;
}
 
-   data |= S5M_RTC_TIME_EN_MASK;
data |= info->regs->rtc_udr_mask;
+   if (info->device_type == S5M8763X || info->device_type == S5M8767X)
+   data |= S5M_RTC_TIME_EN_MASK;
 
ret = regmap_write(info->regmap, info->regs->rtc_udr_update, data);
if (ret < 0) {
@@ -229,8 +248,18 @@ static inline int s5m8767_rtc_set_alarm_reg(struct 
s5m_rtc_info *info)
return ret;
}
 
-   data &= ~S5M_RTC_TIME_EN_MASK;
data |= info->regs->rtc_udr_mask;
+   switch (info->device_type) {
+   case S5M8763X:
+   case S5M8767X:
+   data &= ~S5M_RTC_TIME_EN_MASK;
+   break;
+   case S2MPS14X:
+   data |= S2MPS_RTC_RUDR_MASK;
+   break;
+   default:
+   return -EINVAL;
+   }
 
ret = regmap_write(info->regmap, info->regs->rtc_udr_update, data);
if (ret < 0) {
@@ -282,6 +311,17 @@ static int s5m_rtc_read_time(struct device *dev, struct 
rtc_time *tm)
u8 data[info->regs->regs_count];
int ret;
 
+   if (info->device_type == S2MPS14X) {
+   ret = regmap_update_bits(info->regmap,
+   info->regs->rtc_udr_update,
+   S2MPS_RTC_RUDR_MASK, S2MPS_RTC_RUDR_MASK);
+   if (ret) {
+   dev_err(dev,
+   "Failed to prepare registers for time reading: 
%d\n",
+   ret);
+   return ret;
+   }
+   }
ret = regmap_bulk_read(info->regmap, info->regs->time, data,
info->regs->regs_count);
if (ret < 0)
@@ -293,6 +333,7 @@ static int s5m_rtc_read_time(struct device *dev, struct 
rtc_time *tm)
break;
 
case S5M8767X:
+   case S2MPS14X:
s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
break;
 
@@ -3

[PATCH v2 3/6] rtc: s5m: Use shorter time of register update

[Krzysztof Kozlowski]

Set the time needed for updating alarm and time registers to 0.45 ms.
The default is 7.32 ms which is too long and leads to warnings when
setting alarm or time:
s5m-rtc: waiting for UDR update, reached max number of retries

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
---
 drivers/rtc/rtc-s5m.c   |  7 +++
 include/linux/mfd/samsung/rtc.h | 10 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 22137d4dbadf..3751ef90f93c 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -519,6 +519,13 @@ static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
u8 data[2];
int ret;
 
+   /* UDR update time. Default of 7.32 ms is too long. */
+   ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
+   S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
+   if (ret < 0)
+   dev_err(info->dev, "%s: fail to change UDR time: %d\n",
+   __func__, ret);
+
/* Set RTC control register : Binary mode, 24hour mode */
data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
diff --git a/include/linux/mfd/samsung/rtc.h b/include/linux/mfd/samsung/rtc.h
index 207fcfbde82e..b6401e7661c7 100644
--- a/include/linux/mfd/samsung/rtc.h
+++ b/include/linux/mfd/samsung/rtc.h
@@ -111,6 +111,16 @@ enum s2mps_rtc_reg {
 #define RTC_TCON_MASK  (1 << RTC_TCON_SHIFT)
 #define S5M_RTC_TIME_EN_SHIFT  3
 #define S5M_RTC_TIME_EN_MASK   (1 << S5M_RTC_TIME_EN_SHIFT)
+/*
+ * UDR_T field in S5M_RTC_UDR_CON register determines the time needed
+ * for updating alarm and time registers. Default is 7.32 ms.
+ */
+#define S5M_RTC_UDR_T_SHIFT6
+#define S5M_RTC_UDR_T_MASK (0x3 << S5M_RTC_UDR_T_SHIFT)
+#define S5M_RTC_UDR_T_7320_US  (0x0 << S5M_RTC_UDR_T_SHIFT)
+#define S5M_RTC_UDR_T_1830_US  (0x1 << S5M_RTC_UDR_T_SHIFT)
+#define S5M_RTC_UDR_T_3660_US  (0x2 << S5M_RTC_UDR_T_SHIFT)
+#define S5M_RTC_UDR_T_450_US   (0x3 << S5M_RTC_UDR_T_SHIFT)
 
 /* RTC Hour register */
 #define HOUR_PM_SHIFT  6
-- 
1.8.3.2

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[PATCH v2 4/6] rtc: s5m: Support different register layout

[Krzysztof Kozlowski]

This patch prepares for adding support for S2MPS14 RTC device to the
rtc-s5m driver:
1. Adds a map of registers used by the driver which differ between
the chipsets (S5M876X and S2MPS14).
2. Moves code of checking for alarm pending to separate function.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
---
 drivers/rtc/rtc-s5m.c | 157 +++---
 1 file changed, 109 insertions(+), 48 deletions(-)

diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 3751ef90f93c..59860128a221 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 Samsung Electronics Co., Ltd
+ * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
  * http://www.samsung.com
  *
  *  Copyright (C) 2013 Google, Inc
@@ -38,6 +38,42 @@
  */
 #define UDR_READ_RETRY_CNT 5
 
+/* Registers used by the driver which are different between chipsets. */
+struct s5m_rtc_reg_config {
+   /* Number of registers used for setting time/alarm0/alarm1 */
+   unsigned int regs_count;
+   /* First register for time, seconds */
+   unsigned int time;
+   /* RTC control register */
+   unsigned int ctrl;
+   /* First register for alarm 0, seconds */
+   unsigned int alarm0;
+   /* First register for alarm 1, seconds */
+   unsigned int alarm1;
+   /* SMPL/WTSR register */
+   unsigned int smpl_wtsr;
+   /*
+* Register for update flag (UDR). Typically setting UDR field to 1
+* will enable update of time or alarm register. Then it will be
+* auto-cleared after successful update.
+*/
+   unsigned int rtc_udr_update;
+   /* Mask for UDR field in 'rtc_udr_update' register */
+   unsigned int rtc_udr_mask;
+};
+
+/* Register map for S5M8763 and S5M8767 */
+static const struct s5m_rtc_reg_config s5m_rtc_regs = {
+   .regs_count = 8,
+   .time   = S5M_RTC_SEC,
+   .ctrl   = S5M_ALARM1_CONF,
+   .alarm0 = S5M_ALARM0_SEC,
+   .alarm1 = S5M_ALARM1_SEC,
+   .smpl_wtsr  = S5M_WTSR_SMPL_CNTL,
+   .rtc_udr_update = S5M_RTC_UDR_CON,
+   .rtc_udr_mask   = S5M_RTC_UDR_MASK,
+};
+
 struct s5m_rtc_info {
struct device *dev;
struct i2c_client *i2c;
@@ -48,6 +84,7 @@ struct s5m_rtc_info {
int device_type;
int rtc_24hr_mode;
bool wtsr_smpl;
+   const struct s5m_rtc_reg_config *regs;
 };
 
 static const struct regmap_config s5m_rtc_regmap_config = {
@@ -119,8 +156,9 @@ static inline int s5m8767_wait_for_udr_update(struct 
s5m_rtc_info *info)
unsigned int data;
 
do {
-   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
-   } while (--retry && (data & S5M_RTC_UDR_MASK) && !ret);
+   ret = regmap_read(info->regmap, info->regs->rtc_udr_update,
+   &data);
+   } while (--retry && (data & info->regs->rtc_udr_mask) && !ret);
 
if (!retry)
dev_err(info->dev, "waiting for UDR update, reached max number 
of retries\n");
@@ -128,21 +166,47 @@ static inline int s5m8767_wait_for_udr_update(struct 
s5m_rtc_info *info)
return ret;
 }
 
+static inline int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info,
+   struct rtc_wkalrm *alarm)
+{
+   int ret;
+   unsigned int val;
+
+   switch (info->device_type) {
+   case S5M8767X:
+   case S5M8763X:
+   ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
+   val &= S5M_ALARM0_STATUS;
+   break;
+   default:
+   return -EINVAL;
+   }
+   if (ret < 0)
+   return ret;
+
+   if (val)
+   alarm->pending = 1;
+   else
+   alarm->pending = 0;
+
+   return 0;
+}
+
 static inline int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
 {
int ret;
unsigned int data;
 
-   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
+   ret = regmap_read(info->regmap, info->regs->rtc_udr_update, &data);
if (ret < 0) {
dev_err(info->dev, "failed to read update reg(%d)\n", ret);
return ret;
}
 
data |= S5M_RTC_TIME_EN_MASK;
-   data |= S5M_RTC_UDR_MASK;
+   data |= info->regs->rtc_udr_mask;
 
-   ret = regmap_write(info->regmap, S5M_RTC_UDR_CON, data);
+   ret = regmap_write(info->regmap, info->regs->rtc_udr_update, data);
if (ret < 0) {
dev_err(info->dev, "failed to write update reg(%d)\n", ret);
return ret;
@@ -158,7 +222,7 @@ static inline int s5m8767_rtc_set_alarm_reg(struct 
s5m_rtc_info *info)
int ret;
unsigned int data;
 
-   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &data);
+   ret = regmap_read(info->regmap, info->regs->rtc_udr_update, &data);
if

[PATCH v2 2/6] rtc: s5m: Remove undocumented time init on first boot

[Krzysztof Kozlowski]

This patch removes the code for initializing time if this is first boot.

The code for detecting first boot uses undocumented field RTC_TCON in
RTC_UDR_CON register. According to S5M8767's datasheet this field is
reserved. On S2MPS14 it is not documented at all. On device first boot
the registers will be initialized with reset value (2000-01-01
00:00:00).

The code might work on S5M8763 but still this does not look like a task
for RTC driver.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
---
 drivers/rtc/rtc-s5m.c | 30 --
 1 file changed, 30 deletions(-)

diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index b37df8c790f2..22137d4dbadf 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -517,16 +517,7 @@ static void s5m_rtc_enable_smpl(struct s5m_rtc_info *info, 
bool enable)
 static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
 {
u8 data[2];
-   unsigned int tp_read;
int ret;
-   struct rtc_time tm;
-
-   ret = regmap_read(info->regmap, S5M_RTC_UDR_CON, &tp_read);
-   if (ret < 0) {
-   dev_err(info->dev, "%s: fail to read control reg(%d)\n",
-   __func__, ret);
-   return ret;
-   }
 
/* Set RTC control register : Binary mode, 24hour mode */
data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
@@ -540,27 +531,6 @@ static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
return ret;
}
 
-   /* In first boot time, Set rtc time to 1/1/2012 00:00:00(SUN) */
-   if ((tp_read & RTC_TCON_MASK) == 0) {
-   dev_dbg(info->dev, "rtc init\n");
-   tm.tm_sec = 0;
-   tm.tm_min = 0;
-   tm.tm_hour = 0;
-   tm.tm_wday = 0;
-   tm.tm_mday = 1;
-   tm.tm_mon = 0;
-   tm.tm_year = 112;
-   tm.tm_yday = 0;
-   tm.tm_isdst = 0;
-   ret = s5m_rtc_set_time(info->dev, &tm);
-   }
-
-   ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
-RTC_TCON_MASK, tp_read | RTC_TCON_MASK);
-   if (ret < 0)
-   dev_err(info->dev, "%s: fail to update TCON reg(%d)\n",
-   __func__, ret);
-
return ret;
 }
 
-- 
1.8.3.2

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[PATCH v2 6/6] rtc: s5m: Consolidate two device type switch statements

[Krzysztof Kozlowski]

In probe the configuration of driver for different chipsets was done in
two switch (pdata->device_type) statements. Consolidate them into one
switch statement to increase code readability.

Additionally check the return value of regmap_irq_get_virq and exit
probe on error.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kyungmin Park 
---
 drivers/rtc/rtc-s5m.c | 27 ---
 1 file changed, 8 insertions(+), 19 deletions(-)

diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c
index 76287ebd0e35..8f06250a0389 100644
--- a/drivers/rtc/rtc-s5m.c
+++ b/drivers/rtc/rtc-s5m.c
@@ -666,7 +666,7 @@ static int s5m_rtc_probe(struct platform_device *pdev)
struct sec_platform_data *pdata = s5m87xx->pdata;
struct s5m_rtc_info *info;
const struct regmap_config *regmap_cfg;
-   int ret;
+   int ret, alarm_irq;
 
if (!pdata) {
dev_err(pdev->dev.parent, "Platform data not supplied\n");
@@ -681,14 +681,17 @@ static int s5m_rtc_probe(struct platform_device *pdev)
case S2MPS14X:
regmap_cfg = &s2mps14_rtc_regmap_config;
info->regs = &s2mps_rtc_regs;
+   alarm_irq = S2MPS14_IRQ_RTCA0;
break;
case S5M8763X:
regmap_cfg = &s5m_rtc_regmap_config;
info->regs = &s5m_rtc_regs;
+   alarm_irq = S5M8763_IRQ_ALARM0;
break;
case S5M8767X:
regmap_cfg = &s5m_rtc_regmap_config;
info->regs = &s5m_rtc_regs;
+   alarm_irq = S5M8767_IRQ_RTCA1;
break;
default:
dev_err(&pdev->dev, "Device type is not supported by RTC 
driver\n");
@@ -714,25 +717,11 @@ static int s5m_rtc_probe(struct platform_device *pdev)
info->device_type = s5m87xx->device_type;
info->wtsr_smpl = s5m87xx->wtsr_smpl;
 
-   switch (pdata->device_type) {
-   case S2MPS14X:
-   info->irq = regmap_irq_get_virq(s5m87xx->irq_data,
-   S2MPS14_IRQ_RTCA0);
-   break;
-
-   case S5M8763X:
-   info->irq = regmap_irq_get_virq(s5m87xx->irq_data,
-   S5M8763_IRQ_ALARM0);
-   break;
-
-   case S5M8767X:
-   info->irq = regmap_irq_get_virq(s5m87xx->irq_data,
-   S5M8767_IRQ_RTCA1);
-   break;
-
-   default:
+   info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
+   if (info->irq <= 0) {
ret = -EINVAL;
-   dev_err(&pdev->dev, "Unsupported device type: %d\n", ret);
+   dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n",
+   alarm_irq);
goto err;
}
 
-- 
1.8.3.2

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Re: [PATCH RFC 3/3] drm/exynos: use pending_components for components tracking

[Russell King - ARM Linux]

On Fri, Apr 18, 2014 at 02:02:37PM +0200, Andrzej Hajda wrote:
> Separation of the interfaces exposed by the device from the device itself
> seems to me a good thing. I would even consider it as a biggest
> advantage of this solution :)
> 
> The problem of re-initialization does not seems to be relevant here, it
> is classic
> problem of coding correctness nothing more, it can appear here and in
> many different
> places.

It may be a problem of coding correctless, but it's also a maintainability
problem too - it makes it _much_ more difficult to ensure that everything
is correct.

> Anyway it seems we have different point of view on the problem, your say
> about devices with two stage initialization. I see it more as devices
> registering interfaces and superdevice using it.

Right, so please make this exynos-specific, because from what I can see it
has no reason to pretend to be generic.  As I've already pointed out, it
can't be used in the general case because it ties sub-components directly
to their main driver, which is absolutely absurd.  Please keep this
absurdness in exynos and don't spread it around.  Thanks.

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Re: [PATCH RFC 3/3] drm/exynos: use pending_components for components tracking

[Russell King - ARM Linux]

On Fri, Apr 18, 2014 at 01:27:53PM +0200, Andrzej Hajda wrote:
> Hi Russel,
> 
> Thanks for comments.
> 
> On 04/17/2014 11:47 PM, Russell King - ARM Linux wrote:
> > On Thu, Apr 17, 2014 at 01:28:50PM +0200, Andrzej Hajda wrote:
> >> +out:
> >> +  if (ret != -EPROBE_DEFER)
> >> +  exynos_drm_dev_ready(&pdev->dev);
> > So we end up with everyone needing a "ready" call in each sub-driver
> > back into the main driver... this makes it impossible to write a
> > generic subcomponent driver which is not tied in any way to the
> > main driver.
> >
> > That is quite some restriction, and would prevent, for example, the
> > TDA998x driver being used both with Armada DRM, tilcdc and any other
> > driver.
> 
> As I see in armada driver drm is deferred in case tda998x is not yet
> available. The same solution can be still used with pending_devices
> approach - the main driver will not report its readiness until tda998x
> is present.
> 
> Anyway it still seems to be better than componentize every driver which can
> probably become a part of some superdevice.
> 
> If you want to get rid of deferred probe one can make global list of
> 'ready' devices with notifications systems for master devices.
> 
> Maybe it would be good to consider notification system for devices probe
> result,
> it will require that driver register all its interfaces in probe, ie its
> readiness cannot
> be reported later but will not require to add new framework. I hope just
> extending current
> notification system should be enough.

You aren't addressing my point.  If I were to convert tda998x to use
your infrastructure, then I would have to add in ifdefs to tie it into
armada DRM _and_ a different set of ifdefs to tie it into tilcdc.  Then
when someone else wanted to use it in their driver, they'd have to add
yet more ifdefs into it to tie it into their driver.

This does not scale.

So, please address my point: in your system, how can a single component
be shared between multiple different master drivers?

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Re: [RFC PATCH v2 05/14] ARM: dts: samsung-fimd: add I80 specific properties

[Andrzej Hajda]

Hi again,

On 04/17/2014 01:53 PM, YoungJun Cho wrote:
> In case of using CPU interface panel, the relevant registers should be set.
> So this patch adds relevant dt bindings.
>
> Changelog v2:
> - Changes "samsung,sysreg-phandle" to "samsung,sysreg"
>
> Signed-off-by: YoungJun Cho 
> Signed-off-by: Inki Dae 
> Signed-off-by: Kyungmin Park 
> ---
>  .../devicetree/bindings/video/samsung-fimd.txt |9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
> b/Documentation/devicetree/bindings/video/samsung-fimd.txt
> index 2dad41b..6ea1adc 100644
> --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
> +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
> @@ -44,6 +44,15 @@ Optional Properties:
>  - display-timings: timing settings for FIMD, as described in document [1].
>   Can be used in case timings cannot be provided otherwise
>   or to override timings provided by the panel.
> +- samsung,sysreg: handle to syscon used to control the system registers
> +- vidout-i80-ldi: boolean to support i80 interface instead of rgb one
> +- cs-setup: clock cycles for the active period of address signal enable until
> + chip select is enable in i80 interface
> +- wr-setup: clock cycles for the active period of CS signal enable until
> + write signal is enable in i80 interface
> +- wr-act: clock cycles for the active period of CS enable in i80 interface
> +- wr-hold: clock cycles for the active period of CS disable until write 
> signal
> + is disable in i80 interface

As Laurent wrote earlier it would be good to consider providing these
properties
by panel. Panel can pass it to DSI probably via mipi_dsi_device
structure. DSI to FIMD
can use exynos drm_framework probably.
Anyway if you add optional properties please add info about default
value, ie when property
is not present.

Regards
Andrzej

>  
>  The device node can contain 'port' child nodes according to the bindings 
> defined
>  in [2]. The following are properties specific to those nodes:

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Re: [RFC PATCH 02/14] drm/exynos: dsi: delay setting clocks after reset

[Andrzej Hajda]

Hi YoungJun,

Thanks for the whole patchset.

On 04/15/2014 07:47 AM, YoungJun Cho wrote:
> Some phy control registers are not kept after software reset.
> So this patch makes the clocks containing phy control to be set
> after software reset.
>
> Signed-off-by: YoungJun Cho 
> Signed-off-by: Inki Dae 
> Signed-off-by: Kyungmin Park 
> ---
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index 956e5f3..2cf1f0b 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -946,10 +946,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
>  
>  static int exynos_dsi_init(struct exynos_dsi *dsi)
>  {
> - exynos_dsi_enable_clock(dsi);
>   exynos_dsi_reset(dsi);
>   enable_irq(dsi->irq);
>   exynos_dsi_wait_for_reset(dsi);
> + exynos_dsi_enable_clock(dsi);
>   exynos_dsi_init_link(dsi);
>  
>   return 0;
Are you sure this sequence is OK? I have observed that sequence:

dsi power off
dsi power on
dsi_reset

on 4210 or 4412 resulted in lack of irq after reset, only enabling
clocks helped.
And according to documentation reset do not touch registers set by
exynos_dsi_enable_clock,
so the current solution should work.

Regards
Andrzej
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Re: [PATCH RFC 3/3] drm/exynos: use pending_components for components tracking

[Andrzej Hajda]

On 04/18/2014 12:04 AM, Russell King - ARM Linux wrote:
> On Thu, Apr 17, 2014 at 01:28:50PM +0200, Andrzej Hajda wrote:
>> +static int exynos_drm_add_blocker(struct device *dev, void *data)
>> +{
>> +struct device_driver *drv = data;
>> +
>> +if (!platform_bus_type.match(dev, drv))
>> +return 0;
>> +
>> +device_lock(dev);
>> +if (!dev->driver)
>> +exynos_drm_dev_busy(dev);
>> +device_unlock(dev);
>> +
>> +return 0;
>> +}
>> +
>> +static void exynos_drm_init_blockers(struct device_driver *drv)
>> +{
>> +bus_for_each_dev(&platform_bus_type, NULL, drv, exynos_drm_add_blocker);
>> +}
> This feels very wrong to be dumping the above code into every driver which
> wants to make use of some kind of componentised support.
>
> You also appear to need to know the struct device_driver's for every
> component.  While that may work for exynos, it doesn't work elsewhere
> where the various components of the system are very real separate
> kernel modules - for example, a separate I2C driver such as the TDA998x
> case I mentioned in my first reply.
>
> I can't see how your solution would be usable in that circumstance.

It is up to the master driver how it want to create list of required
devices,
this is why I put it into exynos_drm and not into the framework.
You can use superdevice DT node for it, fixed list whatever you want.
It is not a part of the framework, it is just part of exynos_drm specific
implementation.
Component framework also does not provide mechanism for it.

Regarding TDA998x I have replied in the previous e-mail.

>
> The third issue I have is that you're still needing to have internal
> exynos sub-device management - you're having to add the individual
> devices to some kind of list, array or static data, and during DRM
> probe you're having to then walk these lists/arrays/static data to
> locate these sub-devices and finish each of their individual
> initialisations.  So you're ending up with a two-tier initialisation.
>
> That's not particularly good because it means you're exposed to
> problems where the state is different between two initialisations -
> when the device is recreated, your component attempts to re-finalise
> the initialisation a second time.  It wouldn't take much for a field
> to be assumed to be zero at init time somewhere for a bug to creep
> in.
>

Separation of the interfaces exposed by the device from the device itself
seems to me a good thing. I would even consider it as a biggest
advantage of this solution :)

The problem of re-initialization does not seems to be relevant here, it
is classic
problem of coding correctness nothing more, it can appear here and in
many different
places.

Anyway it seems we have different point of view on the problem, your say
about
devices with two stage initialization. I see it more as devices
registering interfaces and superdevice
using it.

Regards
Andrzej





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[PATCH] net: sxgbe: Added phy_found error path

[Byungho An]

This patch adds phy_found error path when there is no phy device 
and changes bus_name.

Signed-off-by: Byungho An 
---
 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c |   14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c 
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
index 01af2cb..7dcaf1a 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
@@ -27,7 +27,7 @@
 #define SXGBE_SMA_PREAD_CMD0x02 /* post read  increament address */
 #define SXGBE_SMA_READ_CMD 0x03 /* read command */
 #define SXGBE_SMA_SKIP_ADDRFRM 0x0004 /* skip the address frame */
-#define SXGBE_MII_BUSY 0x0080 /* mii busy */
+#define SXGBE_MII_BUSY 0x0040 /* mii busy */
 
 static int sxgbe_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_data)
 {
@@ -147,6 +147,7 @@ int sxgbe_mdio_register(struct net_device *ndev)
struct sxgbe_mdio_bus_data *mdio_data = priv->plat->mdio_bus_data;
int err, phy_addr;
int *irqlist;
+   bool phy_found = false;
bool act;
 
/* allocate the new mdio bus */
@@ -162,7 +163,7 @@ int sxgbe_mdio_register(struct net_device *ndev)
irqlist = priv->mii_irq;
 
/* assign mii bus fields */
-   mdio_bus->name = "samsxgbe";
+   mdio_bus->name = "sxgbe";
mdio_bus->read = &sxgbe_mdio_read;
mdio_bus->write = &sxgbe_mdio_write;
snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%x",
@@ -216,13 +217,22 @@ int sxgbe_mdio_register(struct net_device *ndev)
netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
phy->phy_id, phy_addr, irq_str,
dev_name(&phy->dev), act ? " active" : "");
+   phy_found = true;
}
}
 
+   if (!phy_found) {
+   netdev_err(ndev, "PHY not found\n");
+   goto phyfound_err;
+   }
+
priv->mii = mdio_bus;
 
return 0;
 
+phyfound_err:
+   err = -ENODEV;
+   mdiobus_unregister(mdio_bus);
 mdiobus_err:
mdiobus_free(mdio_bus);
return err;
-- 
1.7.10.4


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[PATCH] net: sxgbe: rearrange dma descriptor

[Byungho An]

This patch moves cksum_ctl to tx_rd_des23 from cksum_pktlen for correct 
checksum 
offloading and modifies size for Tx/Rx descriptor.

Signed-off-by: Byungho An 
---
 drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.c |4 +--
 drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h |   39 ++-
 2 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.c 
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.c
index e896dbb..d71691b 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.c
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.c
@@ -45,10 +45,10 @@ static void sxgbe_prepare_tx_desc(struct sxgbe_tx_norm_desc 
*p, u8 is_fd,
p->tdes23.tx_rd_des23.first_desc = is_fd;
p->tdes23.tx_rd_des23.buf1_size = buf1_len;
 
-   p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.total_pkt_len = pkt_len;
+   p->tdes23.tx_rd_des23.tx_pkt_len.pkt_len.total_pkt_len = pkt_len;
 
if (cksum)
-   p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.cksum_ctl = 
cic_full;
+   p->tdes23.tx_rd_des23.cksum_ctl = cic_full;
 }
 
 /* Set VLAN control information */
diff --git a/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h 
b/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h
index 838cb9f..0226300 100644
--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h
+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_desc.h
@@ -39,22 +39,22 @@ struct sxgbe_tx_norm_desc {
u32 int_on_com:1;
/* TDES3 */
union {
-   u32 tcp_payload_len:18;
+   u16 tcp_payload_len;
struct {
u32 total_pkt_len:15;
u32 reserved1:1;
-   u32 cksum_ctl:2;
-   } cksum_pktlen;
+   } pkt_len;
} tx_pkt_len;
 
-   u32 tse_bit:1;
-   u32 tcp_hdr_len:4;
-   u32 sa_insert_ctl:3;
-   u32 crc_pad_ctl:2;
-   u32 last_desc:1;
-   u32 first_desc:1;
-   u32 ctxt_bit:1;
-   u32 own_bit:1;
+   u16 cksum_ctl:2;
+   u16 tse_bit:1;
+   u16 tcp_hdr_len:4;
+   u16 sa_insert_ctl:3;
+   u16 crc_pad_ctl:2;
+   u16 last_desc:1;
+   u16 first_desc:1;
+   u16 ctxt_bit:1;
+   u16 own_bit:1;
} tx_rd_des23;
 
/* tx write back Desc 2,3 */
@@ -70,25 +70,20 @@ struct sxgbe_tx_norm_desc {
 
 struct sxgbe_rx_norm_desc {
union {
-   u32 rdes0; /* buf1 address */
-   struct {
+   u64 rdes01; /* buf1 address */
+   union {
u32 out_vlan_tag:16;
u32 in_vlan_tag:16;
-   } wb_rx_des0;
-   } rd_wb_des0;
-
-   union {
-   u32 rdes1;  /* buf2 address or buf1[63:32] */
-   u32 rss_hash;   /* Write-back RX */
-   } rd_wb_des1;
+   u32 rss_hash;
+   } rx_wb_des01;
+   } rdes01;
 
union {
/* RX Read format Desc 2,3 */
struct{
/* RDES2 */
-   u32 buf2_addr;
+   u64 buf2_addr:62;
/* RDES3 */
-   u32 buf2_hi_addr:30;
u32 int_on_com:1;
u32 own_bit:1;
} rx_rd_des23;
-- 
1.7.10.4


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Re: [PATCH RFC 3/3] drm/exynos: use pending_components for components tracking

[Andrzej Hajda]

Hi Russel,

Thanks for comments.

On 04/17/2014 11:47 PM, Russell King - ARM Linux wrote:
> On Thu, Apr 17, 2014 at 01:28:50PM +0200, Andrzej Hajda wrote:
>> +out:
>> +if (ret != -EPROBE_DEFER)
>> +exynos_drm_dev_ready(&pdev->dev);
> So we end up with everyone needing a "ready" call in each sub-driver
> back into the main driver... this makes it impossible to write a
> generic subcomponent driver which is not tied in any way to the
> main driver.
>
> That is quite some restriction, and would prevent, for example, the
> TDA998x driver being used both with Armada DRM, tilcdc and any other
> driver.

As I see in armada driver drm is deferred in case tda998x is not yet
available. The same solution can be still used with pending_devices
approach - the main driver will not report its readiness until tda998x
is present.

Anyway it still seems to be better than componentize every driver which can
probably become a part of some superdevice.

If you want to get rid of deferred probe one can make global list of
'ready' devices with notifications systems for master devices.

Maybe it would be good to consider notification system for devices probe
result,
it will require that driver register all its interfaces in probe, ie its
readiness cannot
be reported later but will not require to add new framework. I hope just
extending current
notification system should be enough.

Regards
Andrzej

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Re: [PATCH 7/7] drm/bridge: ptn3460: add drm_panel controls

[Jingoo Han]

On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
> 
> attach ptn3460 connector to drm_panel and support drm_panel routines,
> if a valid drm_panel object is passed to ptn3460_init.
> 
> Signed-off-by: Ajay Kumar 
> ---
>  drivers/gpu/drm/bridge/Kconfig  |  1 +
>  drivers/gpu/drm/bridge/ptn3460.c| 17 -
>  drivers/gpu/drm/exynos/exynos_dp_core.c | 15 +++
>  include/drm/bridge/ptn3460.h|  6 --
>  4 files changed, 32 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 884923f..3bc6845 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -2,4 +2,5 @@ config DRM_PTN3460
>   tristate "PTN3460 DP/LVDS bridge"
>   depends on DRM
>   select DRM_KMS_HELPER
> + select DRM_PANEL
>   ---help---
> diff --git a/drivers/gpu/drm/bridge/ptn3460.c 
> b/drivers/gpu/drm/bridge/ptn3460.c
> index f1d2afc..736c7a8 100644
> --- a/drivers/gpu/drm/bridge/ptn3460.c
> +++ b/drivers/gpu/drm/bridge/ptn3460.c
> @@ -24,6 +24,7 @@
>  #include "drm_edid.h"
>  #include "drm_crtc.h"
>  #include "drm_crtc_helper.h"
> +#include 

Move '' as below.

#include 
#include 
+#include 

#include "drmP.h"


> 
>  #include "bridge/ptn3460.h"
> 
> @@ -38,6 +39,7 @@ struct ptn3460_bridge {
>   struct i2c_client *client;
>   struct drm_encoder *encoder;
>   struct drm_bridge *bridge;
> + struct drm_panel *panel;
>   struct edid *edid;
>   int gpio_pd_n;
>   int gpio_rst_n;
> @@ -126,6 +128,8 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
>   gpio_set_value(ptn_bridge->gpio_rst_n, 1);
>   }
> 
> + drm_panel_pre_enable(ptn_bridge->panel);
> +
>   /*
>* There's a bug in the PTN chip where it falsely asserts hotplug before
>* it is fully functional. We're forced to wait for the maximum start up
> @@ -142,6 +146,9 @@ static void ptn3460_pre_enable(struct drm_bridge *bridge)
> 
>  static void ptn3460_enable(struct drm_bridge *bridge)
>  {
> + struct ptn3460_bridge *ptn_bridge = bridge->driver_private;
> +
> + drm_panel_enable(ptn_bridge->panel);
>  }
> 
>  static void ptn3460_disable(struct drm_bridge *bridge)
> @@ -153,6 +160,8 @@ static void ptn3460_disable(struct drm_bridge *bridge)
> 
>   ptn_bridge->enabled = false;
> 
> + drm_panel_disable(ptn_bridge->panel);
> +
>   if (gpio_is_valid(ptn_bridge->gpio_rst_n))
>   gpio_set_value(ptn_bridge->gpio_rst_n, 1);
> 
> @@ -265,7 +274,8 @@ struct drm_connector_funcs ptn3460_connector_funcs = {
>  };
> 
>  int ptn3460_init(struct drm_device *dev, struct drm_encoder *encoder,
> - struct i2c_client *client, struct device_node *node)
> + struct i2c_client *client, struct device_node *node,
> + struct drm_panel *panel)
>  {
>   int ret;
>   struct drm_bridge *bridge;
> @@ -324,6 +334,11 @@ int ptn3460_init(struct drm_device *dev, struct 
> drm_encoder *encoder,
>   goto err;
>   }
> 
> + if (panel) {
> + ptn_bridge->panel = panel;
> + drm_panel_attach(ptn_bridge->panel, &ptn_bridge->connector);
> + }
> +
>   bridge->driver_private = ptn_bridge;
>   encoder->bridge = bridge;
>   ptn_bridge->connector.polled = DRM_CONNECTOR_POLL_HPD;
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
> b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index 6beeab6..7f550b6 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -989,13 +989,14 @@ static bool find_bridge(const char *compat, struct 
> bridge_init *bridge)
> 
>  /* returns the number of bridges attached */
>  static int exynos_drm_attach_lcd_bridge(struct drm_device *dev,
> - struct drm_encoder *encoder)
> + struct drm_encoder *encoder, struct drm_panel *panel)
>  {
>   struct bridge_init bridge;
>   int ret;
> 
>   if (find_bridge("nxp,ptn3460", &bridge)) {
> - ret = ptn3460_init(dev, encoder, bridge.client, bridge.node);
> + ret = ptn3460_init(dev, encoder, bridge.client, bridge.node,
> + panel);

'panel' is too far. Please fix it as below.

if (find_bridge("nxp,ptn3460", &bridge)) {
ret = ptn3460_init(dev, encoder, bridge.client, bridge.node,
   panel);


>   if (!ret)
>   return 1;
>   }
> @@ -1012,9 +1013,15 @@ static int exynos_dp_create_connector(struct 
> exynos_drm_display *display,
>   dp->encoder = encoder;
> 
>   /* Pre-empt DP connector creation if there's a bridge */
> - ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder);
> - if (ret)
> + ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder, dp->drm_panel);
> + if (ret) {
> + /* Also set "dp->drm_pa

RE: [PATCH 5/7] drm/exynos: dp: modify driver to support drm_panel

[Jingoo Han]

On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
> 
> This patch attaches the dp connector to exynos_dp_panel, and adds
> calls to drm_panel functions to control panel power sequence.
> 
> Signed-off-by: Ajay Kumar 
> ---
>  drivers/gpu/drm/exynos/Kconfig  |  1 +
>  drivers/gpu/drm/exynos/exynos_dp_core.c | 19 +++
>  drivers/gpu/drm/exynos/exynos_dp_core.h |  1 +
>  3 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
> index 5bf5bca..56af433 100644
> --- a/drivers/gpu/drm/exynos/Kconfig
> +++ b/drivers/gpu/drm/exynos/Kconfig
> @@ -52,6 +52,7 @@ config DRM_EXYNOS_DP
>   bool "EXYNOS DRM DP driver support"
>   depends on DRM_EXYNOS && ARCH_EXYNOS
>   default DRM_EXYNOS
> + select DRM_PANEL
>   help
> This enables support for DP device.
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c 
> b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index 18fd9c5..6beeab6 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -28,6 +28,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
> 
>  #include "exynos_drm_drv.h"
> @@ -1028,6 +1029,9 @@ static int exynos_dp_create_connector(struct 
> exynos_drm_display *display,
>   drm_sysfs_connector_add(connector);
>   drm_mode_connector_attach_encoder(connector, encoder);
> 
> + if (dp->drm_panel)
> + drm_panel_attach(dp->drm_panel, &dp->connector);
> +
>   return 0;
>  }
> 
> @@ -1062,10 +1066,12 @@ static void exynos_dp_poweron(struct exynos_dp_device 
> *dp)
>   if (dp->dpms_mode == DRM_MODE_DPMS_ON)
>   return;
> 
> + drm_panel_pre_enable(dp->drm_panel);
>   clk_prepare_enable(dp->clock);
>   exynos_dp_phy_init(dp);
>   exynos_dp_init_dp(dp);
>   enable_irq(dp->irq);
> + drm_panel_enable(dp->drm_panel);
>  }
> 
>  static void exynos_dp_poweroff(struct exynos_dp_device *dp)
> @@ -1073,6 +1079,7 @@ static void exynos_dp_poweroff(struct exynos_dp_device 
> *dp)
>   if (dp->dpms_mode != DRM_MODE_DPMS_ON)
>   return;
> 
> + drm_panel_disable(dp->drm_panel);
>   disable_irq(dp->irq);
>   flush_work(&dp->hotplug_work);
>   exynos_dp_phy_exit(dp);
> @@ -1225,6 +1232,7 @@ static int exynos_dp_dt_parse_panel(struct 
> exynos_dp_device *dp)
>  static int exynos_dp_bind(struct device *dev, struct device *master, void 
> *data)
>  {
>   struct platform_device *pdev = to_platform_device(dev);
> + struct device_node *panel_node;
>   struct drm_device *drm_dev = data;
>   struct resource *res;
>   struct exynos_dp_device *dp;
> @@ -1299,6 +1307,17 @@ static int exynos_dp_bind(struct device *dev, struct 
> device *master, void *data)
> 
>   INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
> 
> + panel_node = of_find_compatible_node(NULL, NULL,
> + "samsung,exynos-dp-panel");
> + if (panel_node) {
> + dp->drm_panel = of_drm_find_panel(panel_node);
> + if (!dp->drm_panel) {
> + of_node_put(panel_node);
> + return -ENODEV;
> + }
> + of_node_put(panel_node);
> + }

The following is simpler.

+   if (panel_node) {
+   dp->drm_panel = of_drm_find_panel(panel_node);
+   of_node_put(panel_node);
+   if (!dp->drm_panel)
+   return -ENODEV;
+   }

Best regards,
Jingoo Han

> +
>   exynos_dp_phy_init(dp);
> 
>   exynos_dp_init_dp(dp);
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h 
> b/drivers/gpu/drm/exynos/exynos_dp_core.h
> index 56fa43e..9dc7991 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
> @@ -148,6 +148,7 @@ struct exynos_dp_device {
>   struct drm_device   *drm_dev;
>   struct drm_connectorconnector;
>   struct drm_encoder  *encoder;
> + struct drm_panel*drm_panel;
>   struct clk  *clock;
>   unsigned intirq;
>   void __iomem*reg_base;
> --
> 1.8.1.2

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Re: [PATCH 4/7] drm/exynos: add exynos_dp_panel driver registration to drm driver

[Jingoo Han]

On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
> 
> Register exynos_dp_panel before the list of exynos crtcs and
> connectors are probed.
> 
> This is needed because exynos_dp_panel should be registered to
> the drm_panel list via panel-exynos-dp probe, i.e much before
> exynos_dp_bind calls of_drm_find_panel().
> 
> Signed-off-by: Ajay Kumar 
> ---
>  drivers/gpu/drm/exynos/exynos_drm_drv.c | 11 +++
>  drivers/gpu/drm/exynos/exynos_drm_drv.h |  1 +
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c 
> b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> index 1d1c604..47266e7 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
> @@ -560,12 +560,23 @@ static int exynos_drm_platform_probe(struct 
> platform_device *pdev)
>   goto err_unregister_ipp;
>  #endif
> 
> +#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
> + ret = platform_driver_register(&exynos_dp_panel_driver);
> + if (ret < 0)
> + goto err_unregister_dp_panel;
> +#endif
> +
>   ret = component_master_add(&pdev->dev, &exynos_drm_ops);
>   if (ret < 0)
>   DRM_DEBUG_KMS("re-tried by last sub driver probed later.\n");
> 
>   return 0;
> 
> +#ifdef CONFIG_DRM_PANEL_EXYNOS_DP
> + platform_driver_unregister(&exynos_dp_panel_driver);
> +err_unregister_dp_panel:
> +#endif

Please add platform_driver_unregister() to exynos_drm_platform_remove(),
as well as exynos_drm_platform_probe().

Best regards,
Jingoo Han

> +
>  #ifdef CONFIG_DRM_EXYNOS_IPP
>   exynos_platform_device_ipp_unregister();
>  err_unregister_ipp:
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
> b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> index 257ce09..f606290 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> @@ -368,4 +368,5 @@ extern struct platform_driver fimc_driver;
>  extern struct platform_driver rotator_driver;
>  extern struct platform_driver gsc_driver;
>  extern struct platform_driver ipp_driver;
> +extern struct platform_driver exynos_dp_panel_driver;
>  #endif
> --
> 1.8.1.2

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Re: [PATCH 3/7] drm/panel: Add driver for exynos_dp based panels

[Jingoo Han]

On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
> 
> This patch adds a simple driver to handle all the LCD and LED
> powerup/down routines needed to support eDP/eDP-LVDS panels
> supported on exynos boards.
> 
> Most of the eDP/LVDS panels need this sequence for powerup:
>   -- LCD unit powerup/LCD_EN
>   -- video data on
>   -- LED unit powerup/BL_EN
> 
> The LCD and LED units are usually powered up via regulators,
> and almost on all boards, we will have a BL_EN pin to enable/
> disable the backlight. Sometimes, we can have LCD_EN switches
> as well. The routines in this driver can be used to control
> panel power sequence on such boards.
> 
> Signed-off-by: Ajay Kumar 
> ---
>  .../devicetree/bindings/panel/exynos-dp-panel.txt  |  32 
>  drivers/gpu/drm/panel/Kconfig  |   9 +
>  drivers/gpu/drm/panel/Makefile |   1 +
>  drivers/gpu/drm/panel/panel-exynos-dp.c| 213 
> +
>  4 files changed, 255 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
>  create mode 100644 drivers/gpu/drm/panel/panel-exynos-dp.c
> 
> diff --git a/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
> b/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
> new file mode 100644
> index 000..a1428d2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/panel/exynos-dp-panel.txt
> @@ -0,0 +1,32 @@
> +exynos_DP_panel/DP_to_LVDS_panel

Please remove unnecessary under lines as below.

Exynos DP panel/DP to LVDS panel

> +==
> +
> +Required properties:
> +  - compatible: "samsung,exynos-dp-panel"
> +
> +Optional properties:
> + -samsung,lcd-en-gpio:
> + eDP panel LCD poweron GPIO.
> + Indicates which GPIO needs to be powered up as output
> + to powerup/enable the switch to the LCD panel.
> + -samsung,led-en-gpio:
> + eDP panel LED enable GPIO.
> + Indicates which GPIO needs to be powered up as output
> + to enable the backlight.
> + -samsung,power-up-delay:
> + eDP panel powerup delay value in ms.
> + Delay in ms needed for the eDP panel to properly
> + powerup after giving powerup signals to the panel.
> + -samsung,power-down-delay:
> + eDP panel powerdown delay value in ms.
> + Delay in ms needed for the eDP panel to properly
> + powerdown after giving powerdown signals to the panel.
> +
> +Example:
> +
> + dp-panel {
> + compatible = "samsung,exynos-dp-panel";
> + samsung,led-en-gpio = <&gpx3 0 1>;
> + samsung,power-up-delay = <40>;
> + samsung,power-down-delay = <50>;
> + };
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index 4ec874d..ea9d5ac 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -30,4 +30,13 @@ config DRM_PANEL_S6E8AA0
>   select DRM_MIPI_DSI
>   select VIDEOMODE_HELPERS
> 
> +config DRM_PANEL_EXYNOS_DP
> + tristate "support for DP panels"
> + depends on OF && DRM_PANEL && DRM_EXYNOS_DP
> + help
> +   DRM panel driver for DP panels and LVDS connected via DP bridges
> +   that need at most a regulator for LCD unit, a regulator for LED unit
> +   and/or enable GPIOs for LCD or LED units. Delay values can also be
> +   specified to support powerup and powerdown process.
> +
>  endmenu
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index 8b92921..30311a4 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -1,3 +1,4 @@
>  obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
>  obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
>  obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
> +obj-$(CONFIG_DRM_PANEL_EXYNOS_DP) += panel-exynos-dp.o
> diff --git a/drivers/gpu/drm/panel/panel-exynos-dp.c 
> b/drivers/gpu/drm/panel/panel-exynos-dp.c
> new file mode 100644
> index 000..e85a7b2
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-exynos-dp.c
> @@ -0,0 +1,213 @@
> +/*
> + * Exynos DP panel driver
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd
> + *
> + * Ajay Kumar 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +struct panel_exynos_dp {
> + struct drm_panelbase;
> + struct regulator*bck_fet;
> + struct regulator*lcd_fet;

'bck' means 'backlight'? Then, just use 'backlight_fet'.
Also, I cannot understand the meaning of 'fet'.
What's t

Re: [PATCH 1/7] drm/exynos: dp: support hotplug detection via GPIO

[Jingoo Han]

On Wednesday, April 16, 2014 11:33 PM, Ajay Kumar wrote:
> 
> From: Andrew Bresticker 
> 
> Certain bridge chips use a GPIO to indicate the cable status instead
> of the I_DP_HPD pin.  This adds an optional device-tree property,
> "samsung,hpd-gpio", to the exynos-dp controller which indicates that
> the specified GPIO should be used for hotplug detection.
> The GPIO is then set up as an edge-triggered interrupt where the
> rising edge indicates hotplug-in and the falling edge indicates hotplug-out.
> 
> Signed-off-by: Andrew Bresticker 
> Signed-off-by: Rahul Sharma 
> Signed-off-by: Ajay Kumar 
> ---
>  .../devicetree/bindings/video/exynos_dp.txt|  4 +++
>  drivers/gpu/drm/exynos/exynos_dp_core.c| 32 
> --
>  drivers/gpu/drm/exynos/exynos_dp_core.h|  1 +
>  drivers/gpu/drm/exynos/exynos_dp_reg.c | 26 --
>  4 files changed, 57 insertions(+), 6 deletions(-)
> 

[.]

> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> @@ -13,6 +13,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #include "exynos_dp_core.h"
>  #include "exynos_dp_reg.h"
> @@ -326,6 +327,9 @@ void exynos_dp_clear_hotplug_interrupts(struct 
> exynos_dp_device *dp)
>  {
>   u32 reg;
> 
> + if (gpio_is_valid(dp->hpd_gpio))
> + return;
> +
>   reg = HOTPLUG_CHG | HPD_LOST | PLUG;
>   writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> 
> @@ -337,6 +341,9 @@ void exynos_dp_init_hpd(struct exynos_dp_device *dp)
>  {
>   u32 reg;
> 
> + if (gpio_is_valid(dp->hpd_gpio))
> + return;
> +
>   exynos_dp_clear_hotplug_interrupts(dp);
> 
>   reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> @@ -348,6 +355,14 @@ enum dp_irq_type exynos_dp_get_irq_type(struct 
> exynos_dp_device *dp)
>  {
>   u32 reg;
> 
> + if (gpio_is_valid(dp->hpd_gpio)) {
> + reg = gpio_get_value(dp->hpd_gpio);
> + if (reg)
> + return DP_IRQ_TYPE_HP_CABLE_IN;
> + else
> + return DP_IRQ_TYPE_HP_CABLE_OUT;
> + }
> +

Please keep the style. It enhances the readability.

if (gpio_is_valid(dp->hpd_gpio)) {
...
} else {
...
}

Then, it can be as bellows.

+   if (gpio_is_valid(dp->hpd_gpio)) {
+   reg = gpio_get_value(dp->hpd_gpio);
+   if (reg)
+   return DP_IRQ_TYPE_HP_CABLE_IN;
+   else
+   return DP_IRQ_TYPE_HP_CABLE_OUT;
+   } else {
+   /* Parse hotplug interrupt status register */
+   reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+
+   if (reg & PLUG)
+   return DP_IRQ_TYPE_HP_CABLE_IN;
+
+   if (reg & HPD_LOST)
+   return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+   if (reg & HOTPLUG_CHG)
+   return DP_IRQ_TYPE_HP_CHANGE;
+   }

return DP_IRQ_TYPE_UNKNOWN;
}

Best regards,
Jingoo Han

>   /* Parse hotplug interrupt status register */
>   reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> 
> @@ -402,9 +417,14 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device 
> *dp)
>  {
>   u32 reg;
> 
> - reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> - if (reg & HPD_STATUS)
> - return 0;
> + if (gpio_is_valid(dp->hpd_gpio)) {
> + if (gpio_get_value(dp->hpd_gpio))
> + return 0;
> + } else {
> + reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> + if (reg & HPD_STATUS)
> + return 0;
> + }
> 
>   return -EINVAL;
>  }
> --
> 1.8.1.2

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Re: [PATCH 0/2] Support cpufreq driver for Exynos3250

[Sachin Kamat]

Hi Chanwoo,

On 18 April 2014 07:50, Chanwoo Choi  wrote:
> This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
> dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
> instead of pr_err/info function.

Per SoC cpufreq driver which does not use CCF is no more encouraged for new
Exynos platforms. Thomas has already posted patches to make use of
generic cpu freq driver
on Exynos platforms. Please refer to [1] and try to utilize it for
this platform as well.

[1] http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/26886

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[PATCH v3 0/7] Support 4 levels of translation tables for ARM64

[Jungseok Lee]

Hi All,

This the 3rd patchset supports 4 levels of tranlsation tables for ARM64.

Firstly, The patchset decouples page size from level of translation tables
as taking account into the comment from Catalin Marinas:
http://www.spinics.net/linux/lists/arm-kernel/msg319552.html

Then, it implements 4 levels of translation tables for native, HYP
and stage2 sides.

All ARMv8 and ARMv7 related changes are validated with FastModels+kvmtool
and A15+QEMU, respectively.

Changes since v1:
- fixed unmatched data types as per Steve's comment
- removed unnecessary #ifdef in arch/arm64/mm/* as per Steve's comment
- revised create_pgd_entry to deal with PUD entry as per Steve's comment
- introduced a macro for initial memblock limit as per Steve's comment
- dropped "Fix line length exceeding 80 characters" patch as per Marc's comment
- removed unnecessary #ifdef in arch/arm/kvm/mmu.c as per Marc's comment
- added a macro for a number of objects of as per Marc's comment

Changes since v2:
- revised some macros in a generic way as per Marc's comment
- added a 2 level option for kvm mmu cache allocation as per Marc's comment

Jungseok Lee (7):
  arm64: Use pr_* instead of printk
  arm64: Decouple page size from level of translation tables
  arm64: Introduce a kernel configuration option for VA_BITS
  arm64: Add a description on 48-bit address space with 4KB pages
  arm64: Add 4 levels of page tables definition with 4KB pages
  arm64: mm: Implement 4 levels of translation tables
  arm64: KVM: Implement 4 levels of translation tables for HYP and stage2

 Documentation/arm64/memory.txt|   59 +--
 arch/arm/include/asm/kvm_mmu.h|   10 ++
 arch/arm/kvm/mmu.c|   88 ++---
 arch/arm64/Kconfig|   51 +-
 arch/arm64/include/asm/kvm_arm.h  |   34 +--
 arch/arm64/include/asm/kvm_mmu.h  |   12 +++
 arch/arm64/include/asm/memblock.h |6 ++
 arch/arm64/include/asm/memory.h   |6 +-
 arch/arm64/include/asm/page.h |6 +-
 arch/arm64/include/asm/pgalloc.h  |   24 -
 arch/arm64/include/asm/pgtable-4level-hwdef.h |   50 ++
 arch/arm64/include/asm/pgtable-4level-types.h |   71 +
 arch/arm64/include/asm/pgtable-hwdef.h|8 +-
 arch/arm64/include/asm/pgtable.h  |   52 --
 arch/arm64/include/asm/tlb.h  |   10 +-
 arch/arm64/kernel/head.S  |   40 +---
 arch/arm64/kernel/traps.c |   19 ++--
 arch/arm64/mm/fault.c |1 +
 arch/arm64/mm/mmu.c   |   16 ++-
 19 files changed, 495 insertions(+), 68 deletions(-)

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[PATCH v3 4/7] arm64: Add a description on 48-bit address space with 4KB pages

[Jungseok Lee]

This patch adds memory layout and translation lookup information
about 48-bit address space with 4K pages. The description is based
on 4 levels of translation tables.

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 Documentation/arm64/memory.txt |   59 ++--
 1 file changed, 51 insertions(+), 8 deletions(-)

diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index d50fa61..8142709 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -8,10 +8,11 @@ This document describes the virtual memory layout used by the 
AArch64
 Linux kernel. The architecture allows up to 4 levels of translation
 tables with a 4KB page size and up to 3 levels with a 64KB page size.
 
-AArch64 Linux uses 3 levels of translation tables with the 4KB page
-configuration, allowing 39-bit (512GB) virtual addresses for both user
-and kernel. With 64KB pages, only 2 levels of translation tables are
-used but the memory layout is the same.
+AArch64 Linux uses 3 levels and 4 levels of translation tables with
+the 4KB page configuration, allowing 39-bit (512GB) and 48-bit (256TB)
+virtual addresses, respectively, for both user and kernel. With 64KB
+pages, only 2 levels of translation tables are used but the memory layout
+is the same.
 
 User addresses have bits 63:39 set to 0 while the kernel addresses have
 the same bits set to 1. TTBRx selection is given by bit 63 of the
@@ -21,7 +22,7 @@ The swapper_pgd_dir address is written to TTBR1 and never 
written to
 TTBR0.
 
 
-AArch64 Linux memory layout with 4KB pages:
+AArch64 Linux memory layout with 4KB pages + 3 levels:
 
 Start  End SizeUse
 ---
@@ -48,7 +49,34 @@ ffbffc00 ffbf  64MB  
modules
 ffc0    256GB  kernel logical 
memory map
 
 
-AArch64 Linux memory layout with 64KB pages:
+AArch64 Linux memory layout with 4KB pages + 4 levels:
+
+Start  End SizeUse
+---
+    256TB  user
+
+   7bfe~124TB  vmalloc
+
+7bff   7bff  64KB  [guard page]
+
+7c00   7dff   2TB  vmemmap
+
+7e00   7bbf  ~2TB  [guard, future 
vmmemap]
+
+7a00   7aff  16MB  PCI I/O space
+
+7b00   7bbf  12MB  [guard]
+
+7bc0   7bdf   2MB  earlyprintk 
device
+
+7be0   7bff   2MB  [guard]
+
+7c00   7fff  64MB  modules
+
+8000    128TB  kernel logical 
memory map
+
+
+AArch64 Linux memory layout with 64KB pages + 2 levels:
 
 Start  End SizeUse
 ---
@@ -75,7 +103,7 @@ fdfffc00 fdff  64MB  
modules
 fe00      2TB  kernel logical 
memory map
 
 
-Translation table lookup with 4KB pages:
+Translation table lookup with 4KB pages + 3 levels:
 
 +++++++++
 |6356|5548|4740|3932|3124|2316|15 8|7  0|
@@ -90,7 +118,22 @@ Translation table lookup with 4KB pages:
  +-> [63] TTBR0/1
 
 
-Translation table lookup with 64KB pages:
+Translation table lookup with 4KB pages + 4 levels:
+
++++++++++
+|6356|5548|4740|3932|3124|2316|15 8|7  0|
++++++++++
+ | | | | | |
+ | | | | | v
+ | | | | |   [11:0]  in-page offset
+ | | | | +-> [20:12] L3 index
+ | | | +---> [29:21] L2 index
+ | | +-> [38:30] L1 index
+ | +---> [47:39] L0 index
+ +-> [63] TTBR0/1
+
+
+Translation table lookup with 64KB pages + 2 levels:
 
 +++++++++
 |6356|5548|4740|3932|3124|2316|15 8|7  0|
-- 
1.7.10.4


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[PATCH v3 3/7] arm64: Introduce a kernel configuration option for VA_BITS

[Jungseok Lee]

This patch adds a kernel configuration for VA_BITS.

It helps to prevent unnecessary #ifdef statements insertions
for VA_BITS when implementing different page sizes and level of
translation tables.

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm64/Kconfig  |8 
 arch/arm64/include/asm/memory.h |6 +-
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1a2faf9..431acbc 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -186,6 +186,14 @@ config ARM64_3_LEVELS
 
 endchoice
 
+config ARM64_VA_BITS
+   int "Virtual address space size"
+   range 39 39 if ARM64_4K_PAGES && ARM64_3_LEVELS
+   range 42 42 if ARM64_64K_PAGES && ARM64_2_LEVELS
+   help
+ This feature is determined by a combination of page size and
+ level of translation tables.
+
 config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
help
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index e94f945..f6e7480 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -41,11 +41,7 @@
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 128MB of the kernel text.
  */
-#ifdef CONFIG_ARM64_64K_PAGES
-#define VA_BITS(42)
-#else
-#define VA_BITS(39)
-#endif
+#define VA_BITS(CONFIG_ARM64_VA_BITS)
 #define PAGE_OFFSET(UL(0x) << (VA_BITS - 1))
 #define MODULES_END(PAGE_OFFSET)
 #define MODULES_VADDR  (MODULES_END - SZ_64M)
-- 
1.7.10.4


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[PATCH v3 1/7] arm64: Use pr_* instead of printk

[Jungseok Lee]

This patch fixed the following checkpatch complaint as using pr_*
instead of printk.

WARNING: printk() should include KERN_ facility level

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm64/kernel/traps.c |   14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 7ffaddd..0484e81 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -65,7 +65,7 @@ static void dump_mem(const char *lvl, const char *str, 
unsigned long bottom,
fs = get_fs();
set_fs(KERNEL_DS);
 
-   printk("%s%s(0x%016lx to 0x%016lx)\n", lvl, str, bottom, top);
+   pr_emerg("%s%s(0x%016lx to 0x%016lx)\n", lvl, str, bottom, top);
 
for (first = bottom & ~31; first < top; first += 32) {
unsigned long p;
@@ -83,7 +83,7 @@ static void dump_mem(const char *lvl, const char *str, 
unsigned long bottom,
sprintf(str + i * 9, " ");
}
}
-   printk("%s%04lx:%s\n", lvl, first & 0x, str);
+   pr_emerg("%s%04lx:%s\n", lvl, first & 0x, str);
}
 
set_fs(fs);
@@ -124,7 +124,7 @@ static void dump_instr(const char *lvl, struct pt_regs 
*regs)
break;
}
}
-   printk("%sCode: %s\n", lvl, str);
+   pr_emerg("%sCode: %s\n", lvl, str);
 
set_fs(fs);
 }
@@ -156,7 +156,7 @@ static void dump_backtrace(struct pt_regs *regs, struct 
task_struct *tsk)
frame.pc = thread_saved_pc(tsk);
}
 
-   printk("Call trace:\n");
+   pr_emerg("Call trace:\n");
while (1) {
unsigned long where = frame.pc;
int ret;
@@ -328,17 +328,17 @@ asmlinkage void bad_mode(struct pt_regs *regs, int 
reason, unsigned int esr)
 
 void __pte_error(const char *file, int line, unsigned long val)
 {
-   printk("%s:%d: bad pte %016lx.\n", file, line, val);
+   pr_crit("%s:%d: bad pte %016lx.\n", file, line, val);
 }
 
 void __pmd_error(const char *file, int line, unsigned long val)
 {
-   printk("%s:%d: bad pmd %016lx.\n", file, line, val);
+   pr_crit("%s:%d: bad pmd %016lx.\n", file, line, val);
 }
 
 void __pgd_error(const char *file, int line, unsigned long val)
 {
-   printk("%s:%d: bad pgd %016lx.\n", file, line, val);
+   pr_crit("%s:%d: bad pgd %016lx.\n", file, line, val);
 }
 
 void __init trap_init(void)
-- 
1.7.10.4


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[PATCH v3 6/7] arm64: mm: Implement 4 levels of translation tables

[Jungseok Lee]

This patch implements 4 levels of translation tables since 3 levels
of page tables with 4KB pages cannot support 40-bit physical address
space described in [1] due to the following issue.

It is a restriction that kernel logical memory map with 4KB + 3 levels
(0xffc0-0x) cannot cover RAM region from
544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create
mapping for this region in map_mem function since __phys_to_virt for
this region reaches to address overflow.

If SoC design follows the document, [1], over 32GB RAM would be placed
from 544GB. Even 64GB system is supposed to use the region from 544GB
to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels
of page tables to avoid hacking __virt_to_phys and __phys_to_virt.

However, it is recommended 4 levels of page table should be only enabled
if memory map is too sparse or there is about 512GB RAM.

References
--
[1]: Principles of ARM Memory Maps, White Paper, Issue C

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm64/Kconfig |7 +
 arch/arm64/include/asm/memblock.h  |6 +
 arch/arm64/include/asm/page.h  |4 ++-
 arch/arm64/include/asm/pgalloc.h   |   20 +++
 arch/arm64/include/asm/pgtable-hwdef.h |6 +++--
 arch/arm64/include/asm/pgtable.h   |   44 ++--
 arch/arm64/include/asm/tlb.h   |8 ++
 arch/arm64/kernel/head.S   |   40 -
 arch/arm64/kernel/traps.c  |5 
 arch/arm64/mm/fault.c  |1 +
 arch/arm64/mm/mmu.c|   16 +---
 11 files changed, 136 insertions(+), 21 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 431acbc..7f5270b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -184,12 +184,19 @@ config ARM64_3_LEVELS
help
  This feature enables 3 levels of translation tables.
 
+config ARM64_4_LEVELS
+   bool "4 level"
+   depends on ARM64_4K_PAGES
+   help
+ This feature enables 4 levels of translation tables.
+
 endchoice
 
 config ARM64_VA_BITS
int "Virtual address space size"
range 39 39 if ARM64_4K_PAGES && ARM64_3_LEVELS
range 42 42 if ARM64_64K_PAGES && ARM64_2_LEVELS
+   range 48 48 if ARM64_4K_PAGES && ARM64_4_LEVELS
help
  This feature is determined by a combination of page size and
  level of translation tables.
diff --git a/arch/arm64/include/asm/memblock.h 
b/arch/arm64/include/asm/memblock.h
index 6afeed2..e4ac8bf 100644
--- a/arch/arm64/include/asm/memblock.h
+++ b/arch/arm64/include/asm/memblock.h
@@ -16,6 +16,12 @@
 #ifndef __ASM_MEMBLOCK_H
 #define __ASM_MEMBLOCK_H
 
+#ifndef CONFIG_ARM64_4_LEVELS
+#define MEMBLOCK_INITIAL_LIMIT PGDIR_SIZE
+#else
+#define MEMBLOCK_INITIAL_LIMIT PUD_SIZE
+#endif
+
 extern void arm64_memblock_init(void);
 
 #endif
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 268e53d..83b5289 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -35,8 +35,10 @@
 
 #ifdef CONFIG_ARM64_2_LEVELS
 #include 
-#else
+#elif defined(CONFIG_ARM64_3_LEVELS)
 #include 
+#else
+#include 
 #endif
 
 extern void __cpu_clear_user_page(void *p, unsigned long user);
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index 4829837..8d745fa 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -26,6 +26,26 @@
 
 #define check_pgt_cache()  do { } while (0)
 
+#ifdef CONFIG_ARM64_4_LEVELS
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+   return (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+}
+
+static inline void pud_free(struct mm_struct *mm, pud_t *pud)
+{
+   BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
+   free_page((unsigned long)pud);
+}
+
+static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
+{
+   set_pgd(pgd, __pgd(__pa(pud) | PUD_TYPE_TABLE));
+}
+
+#endif  /* CONFIG_ARM64_4_LEVELS */
+
 #ifndef CONFIG_ARM64_2_LEVELS
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h 
b/arch/arm64/include/asm/pgtable-hwdef.h
index 9cd86c6..ba30053 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -18,8 +18,10 @@
 
 #ifdef CONFIG_ARM64_2_LEVELS
 #include 
-#else
+#elif defined(CONFIG_ARM64_3_LEVELS)
 #include 
+#else
+#include 
 #endif
 
 /*
@@ -27,7 +29,7 @@
  *
  * Level 1 descriptor (PUD).
  */
-
+#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
 #define PUD_TABLE_BIT  (_AT(pgdval_t, 1) << 1)
 
 /*
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index a64ce5e..efc40d1 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/

[PATCH v3 5/7] arm64: Add 4 levels of page tables definition with 4KB pages

[Jungseok Lee]

This patch adds hardware definition and types for 4 levels of
translation tables with 4KB pages.

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm64/include/asm/pgtable-4level-hwdef.h |   50 +
 arch/arm64/include/asm/pgtable-4level-types.h |   71 +
 2 files changed, 121 insertions(+)
 create mode 100644 arch/arm64/include/asm/pgtable-4level-hwdef.h
 create mode 100644 arch/arm64/include/asm/pgtable-4level-types.h

diff --git a/arch/arm64/include/asm/pgtable-4level-hwdef.h 
b/arch/arm64/include/asm/pgtable-4level-hwdef.h
new file mode 100644
index 000..0ec84e2
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-4level-hwdef.h
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+#ifndef __ASM_PGTABLE_4LEVEL_HWDEF_H
+#define __ASM_PGTABLE_4LEVEL_HWDEF_H
+
+#define PTRS_PER_PTE   512
+#define PTRS_PER_PMD   512
+#define PTRS_PER_PUD   512
+#define PTRS_PER_PGD   512
+
+/*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map.
+ */
+#define PGDIR_SHIFT39
+#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+
+/*
+ * PUD_SHIFT determines the size the second level page table entry can map.
+ */
+#define PUD_SHIFT  30
+#define PUD_SIZE   (_AC(1, UL) << PUD_SHIFT)
+#define PUD_MASK   (~(PUD_SIZE-1))
+
+/*
+ * PMD_SHIFT determines the size the third level page table entry can map.
+ */
+#define PMD_SHIFT  21
+#define PMD_SIZE   (_AC(1, UL) << PMD_SHIFT)
+#define PMD_MASK   (~(PMD_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT  21
+#define SECTION_SIZE   (_AC(1, UL) << SECTION_SHIFT)
+#define SECTION_MASK   (~(SECTION_SIZE-1))
+
+#endif
diff --git a/arch/arm64/include/asm/pgtable-4level-types.h 
b/arch/arm64/include/asm/pgtable-4level-types.h
new file mode 100644
index 000..7ad8dd2
--- /dev/null
+++ b/arch/arm64/include/asm/pgtable-4level-types.h
@@ -0,0 +1,71 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+#ifndef __ASM_PGTABLE_4LEVEL_TYPES_H
+#define __ASM_PGTABLE_4LEVEL_TYPES_H
+
+#include 
+
+typedef u64 pteval_t;
+typedef u64 pmdval_t;
+typedef u64 pudval_t;
+typedef u64 pgdval_t;
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pteval_t pte; } pte_t;
+typedef struct { pmdval_t pmd; } pmd_t;
+typedef struct { pudval_t pud; } pud_t;
+typedef struct { pgdval_t pgd; } pgd_t;
+typedef struct { pteval_t pgprot; } pgprot_t;
+
+#define pte_val(x) ((x).pte)
+#define pmd_val(x) ((x).pmd)
+#define pud_val(x) ((x).pud)
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x)  ((x).pgprot)
+
+#define __pte(x)   ((pte_t) { (x) } )
+#define __pmd(x)   ((pmd_t) { (x) } )
+#define __pud(x)   ((pud_t) { (x) } )
+#define __pgd(x)   ((pgd_t) { (x) } )
+#define __pgprot(x)((pgprot_t) { (x) } )
+
+#else  /* !STRICT_MM_TYPECHECKS */
+
+typedef pteval_t pte_t;
+typedef pmdval_t pmd_t;
+typedef pudval_t pud_t;
+typedef pgdval_t pgd_t;
+typedef pteval_t pgprot_t;
+
+#define pte_val(x) (x)
+#define pmd_val(x) (x)
+#define pud_val(x) (x)
+#define pgd_val(x) (x)
+#define pgprot_val(x)  (x)
+
+#define __pte(x)   (x)
+#define __pmd(x)   (x)
+#define __pud(x)   (x)
+#define __pgd(x)   (x)
+#define __pgprot(x)(x)
+
+#endif /* STRICT_MM_TYPECHECKS */
+
+#endif /* __ASM_PGTABLE_4LEVEL_TYPES_H */
-- 
1.7.10.4


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[PATCH v3 7/7] arm64: KVM: Implement 4 levels of translation tables for HYP and stage2

[Jungseok Lee]

This patch adds 4 levels of translation tables implementation for both
HYP and stage2.

Both symmetric and asymmetric configurations for page size and translation
levels are are validated on Fast Models:

 1) 4KB  + 3 levels guest on 4KB  + 3 levels host

 2) 4KB  + 4 levels guest on 4KB  + 3 levels host

 3) 64KB + 2 levels guest on 4KB  + 3 levels host

 4) 4KB  + 3 levels guest on 4KB  + 4 levels host

 5) 4KB  + 4 levels guest on 4KB  + 4 levels host

 6) 64KB + 2 levels guest on 4KB  + 4 levels host

 7) 4KB  + 3 levels guest on 64KB + 2 levels host

 8) 4KB  + 4 levels guest on 64KB + 2 levels host

 9) 64KB + 2 levels guest on 64KB + 2 levels host

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm/include/asm/kvm_mmu.h   |   10 +
 arch/arm/kvm/mmu.c   |   88 +-
 arch/arm64/include/asm/kvm_arm.h |   34 ---
 arch/arm64/include/asm/kvm_mmu.h |   12 ++
 4 files changed, 127 insertions(+), 17 deletions(-)

diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 5c7aa3c..cf934f1 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -37,6 +37,11 @@
  */
 #define TRAMPOLINE_VA  UL(CONFIG_VECTORS_BASE)
 
+/*
+ * MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels.
+ */
+#define MMU_CACHE_MIN_PAGES2
+
 #ifndef __ASSEMBLY__
 
 #include 
@@ -94,6 +99,11 @@ static inline void kvm_clean_pgd(pgd_t *pgd)
clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
 }
 
+static inline void kvm_clean_pmd(pmd_t *pmd)
+{
+   clean_dcache_area(pmd, PTRS_PER_PMD * sizeof(pmd_t));
+}
+
 static inline void kvm_clean_pmd_entry(pmd_t *pmd)
 {
clean_pmd_entry(pmd);
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 80bb1e6..3ffbdfb 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -388,13 +388,44 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned 
long start,
return 0;
 }
 
+static int create_hyp_pud_mappings(pgd_t *pgd, unsigned long start,
+  unsigned long end, unsigned long pfn,
+  pgprot_t prot)
+{
+   pud_t *pud;
+   pmd_t *pmd;
+   unsigned long addr, next;
+
+   addr = start;
+   do {
+   pud = pud_offset(pgd, addr);
+
+   if (pud_none_or_clear_bad(pud)) {
+   pmd = pmd_alloc_one(NULL, addr);
+   if (!pmd) {
+   kvm_err("Cannot allocate Hyp pmd\n");
+   return -ENOMEM;
+   }
+   pud_populate(NULL, pud, pmd);
+   get_page(virt_to_page(pud));
+   kvm_flush_dcache_to_poc(pud, sizeof(*pud));
+   }
+
+   next = pud_addr_end(addr, end);
+
+   create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
+   pfn += (next - addr) >> PAGE_SHIFT;
+   } while (addr = next, addr != end);
+
+   return 0;
+}
+
 static int __create_hyp_mappings(pgd_t *pgdp,
 unsigned long start, unsigned long end,
 unsigned long pfn, pgprot_t prot)
 {
pgd_t *pgd;
pud_t *pud;
-   pmd_t *pmd;
unsigned long addr, next;
int err = 0;
 
@@ -403,22 +434,23 @@ static int __create_hyp_mappings(pgd_t *pgdp,
end = PAGE_ALIGN(end);
do {
pgd = pgdp + pgd_index(addr);
-   pud = pud_offset(pgd, addr);
 
-   if (pud_none_or_clear_bad(pud)) {
-   pmd = pmd_alloc_one(NULL, addr);
-   if (!pmd) {
-   kvm_err("Cannot allocate Hyp pmd\n");
+   if (pgd_none(*pgd)) {
+   pud = pud_alloc_one(NULL, addr);
+   if (!pud) {
+   kvm_err("Cannot allocate Hyp pud\n");
err = -ENOMEM;
goto out;
}
-   pud_populate(NULL, pud, pmd);
-   get_page(virt_to_page(pud));
-   kvm_flush_dcache_to_poc(pud, sizeof(*pud));
+   pgd_populate(NULL, pgd, pud);
+   get_page(virt_to_page(pgd));
+   kvm_flush_dcache_to_poc(pgd, sizeof(*pgd));
}
 
next = pgd_addr_end(addr, end);
-   err = create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
+
+   err = create_hyp_pud_mappings(pgd, addr, next, pfn, prot);
+
if (err)
goto out;
pfn += (next - addr) >> PAGE_SHIFT;
@@ -563,6 +595,24 @@ void kvm_free_stage2_pgd(struct kvm *kvm)
kvm->arch.pgd = NULL;
 }
 
+static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache 
*cache,
+ 

[PATCH v3 2/7] arm64: Decouple page size from level of translation tables

[Jungseok Lee]

This patch separates page size from level of translation tables in
configuration. It facilitates introduction of different options,
such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily.

Signed-off-by: Jungseok Lee 
Reviewed-by: Sungjinn Chung 
---
 arch/arm64/Kconfig |   36 +++-
 arch/arm64/include/asm/page.h  |2 +-
 arch/arm64/include/asm/pgalloc.h   |4 ++--
 arch/arm64/include/asm/pgtable-hwdef.h |2 +-
 arch/arm64/include/asm/pgtable.h   |8 +++
 arch/arm64/include/asm/tlb.h   |2 +-
 6 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e6e4d37..1a2faf9 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -144,14 +144,48 @@ endmenu
 
 menu "Kernel Features"
 
+choice
+   prompt "Page size"
+   default ARM64_4K_PAGES
+   help
+ Allows page size.
+
+config ARM64_4K_PAGES
+   bool "4KB"
+   help
+ This feature enables 4KB pages support.
+
 config ARM64_64K_PAGES
-   bool "Enable 64KB pages support"
+   bool "64KB"
help
  This feature enables 64KB pages support (4KB by default)
  allowing only two levels of page tables and faster TLB
  look-up. AArch32 emulation is not available when this feature
  is enabled.
 
+endchoice
+
+choice
+   prompt "Level of translation tables"
+   default ARM64_3_LEVELS if ARM64_4K_PAGES
+   default ARM64_2_LEVELS if ARM64_64K_PAGES
+   help
+ Allows level of translation tables.
+
+config ARM64_2_LEVELS
+   bool "2 level"
+   depends on ARM64_64K_PAGES
+   help
+ This feature enables 2 levels of translation tables.
+
+config ARM64_3_LEVELS
+   bool "3 level"
+   depends on ARM64_4K_PAGES
+   help
+ This feature enables 3 levels of translation tables.
+
+endchoice
+
 config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
help
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 46bf666..268e53d 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -33,7 +33,7 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include 
 #else
 #include 
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index 9bea6e7..4829837 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -26,7 +26,7 @@
 
 #define check_pgt_cache()  do { } while (0)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
@@ -44,7 +44,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t 
*pud, pmd_t *pmd)
set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
 }
 
-#endif /* CONFIG_ARM64_64K_PAGES */
+#endif /* CONFIG_ARM64_2_LEVELS */
 
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h 
b/arch/arm64/include/asm/pgtable-hwdef.h
index 5fc8a66..9cd86c6 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -16,7 +16,7 @@
 #ifndef __ASM_PGTABLE_HWDEF_H
 #define __ASM_PGTABLE_HWDEF_H
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include 
 #else
 #include 
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 90c811f..a64ce5e 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -47,7 +47,7 @@ extern void __pmd_error(const char *file, int line, unsigned 
long val);
 extern void __pgd_error(const char *file, int line, unsigned long val);
 
 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
 #endif
 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
@@ -320,7 +320,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
  */
 #define mk_pte(page,prot)  pfn_pte(page_to_pfn(page),prot)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 #define pud_none(pud)  (!pud_val(pud))
 #define pud_bad(pud)   (!(pud_val(pud) & 2))
@@ -342,7 +342,7 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
 }
 
-#endif /* CONFIG_ARM64_64K_PAGES */
+#endif /* CONFIG_ARM64_2_LEVELS */
 
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)(((addr) >> PGDIR_SHIFT) & 
(PTRS_PER_PGD - 1))
@@ -353,7 +353,7 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
 
 /* Find an entry in the second-level page table.. */
-#ifndef CONFIG_ARM64_64K_PAGES
+#i