Re: [PATCH v2 1/2] ARM: EXYNOS: Map SYSRAM through generic SRAM bindings
Hi Tomasz,
On 2 May 2014 23:24, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Sachin,
The whole series looks quite good,
Thanks :)
but I have one concern about support for
Universal C210 board. Please see my comment inline.
On 02.05.2014 07:06, Sachin Kamat wrote:
Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic SRAM bindings are used
for achieving this.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Heiko Stuebner he...@sntech.de
---
This patch is based on linux next (next-20140501) on top of
my Kconfig consolidation patch
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/28642
Changes since v1:
Type and presence of sram nodes is SoC/board dependent. V1 mandated the
presence of both the nodes and used to return an error if one of the
nodes was absent and thus fail the boot altogether. Removed this
dependency.
Tested on 4210/4412 Origen, 5250/5420 Arndale and SMDK5420 boards.
---
arch/arm/Kconfig|1 +
arch/arm/boot/dts/exynos4210-universal_c210.dts | 17 ++
arch/arm/boot/dts/exynos4210.dtsi | 18 +++
arch/arm/boot/dts/exynos4x12.dtsi | 18 +++
arch/arm/boot/dts/exynos5250.dtsi | 18 +++
arch/arm/boot/dts/exynos5420.dtsi | 18 +++
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/exynos.c | 64
---
arch/arm/mach-exynos/firmware.c |8 ++-
arch/arm/mach-exynos/include/mach/map.h |7 ---
arch/arm/mach-exynos/platsmp.c | 33 ++--
11 files changed, 128 insertions(+), 75 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a6d19b1a..f66ea9453df9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -855,6 +855,7 @@ config ARCH_EXYNOS
select S5P_DEV_MFC
select SAMSUNG_DMADEV
select SPARSE_IRQ
+ select SRAM
select USE_OF
help
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 63e34b24b04f..8d4de5c0d0c7 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,23 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5
rw rootwait earlyprintk panic=5 maxcpus=1;
};
+ sram@0202 {
+ status = disabled;
Here you just disable just the top level node of non-secure SYSRAM, but the
sub-nodes are still present and enabled.
I was under the impression that disabling parent node would also
disable the sub-nodes.
I will disable all of them in this case.
+ };
+
+ sram@02025000 {
+ compatible = mmio-sram;
+ reg = 0x02025000 0x1000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0x02025000 0x1000;
+
+ smp-sram@0 {
+ compatible = samsung,exynos4210-sram;
+ reg = 0x0 0x1000;
+ };
+ };
+
mct@1005 {
compatible = none;
};
[snip]
diff --git a/arch/arm/mach-exynos/platsmp.c
b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f94705..0aac03204f9f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,6 +20,7 @@
#include linux/jiffies.h
#include linux/smp.h
#include linux/io.h
+#include linux/of_address.h
#include asm/cacheflush.h
#include asm/smp_plat.h
@@ -33,11 +34,33 @@
extern void exynos4_secondary_startup(void);
+static void __iomem *sram_base_addr;
+void __iomem *sram_ns_base_addr;
+
+static void __init exynos_smp_prepare_sram(void)
+{
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL,
samsung,exynos4210-sram);
Now here you don't check whether the node is okay, so on Universal C210 it
will pick just the first node with this compatible string,
Right. Missed that one.
I think you should be using for_each_compatible_node() here, then check if
the node is okay using of_devicE_is_available() and only then use this
node to map the SYSRAM.
OK.
+ if (node) {
+ sram_base_addr = of_iomap(node, 0);
+ if (!sram_base_addr)
+ pr_err(Secondary CPU boot address not found\n);
+ }
+
+ node = of_find_compatible_node(NULL, NULL,
samsung,exynos4210-sram-ns);
Same here.
OK.
+ if (node) {
+ sram_ns_base_addr = of_iomap(node, 0);
+ if (!sram_ns_base_addr)
+ pr_err(Secondary CPU boot address not
[PATCH 0/4] drm/exynos/mixer: small cleanups
I don't actually have a way of testing the video processor changes, but they seem correct from looking at the code. Hopefully someone has a way of testing them. Daniel Kurtz (4): drm/exynos/mixer: move format definitions to regs-mixer drm/exynos/mixer: use MXR_GRP_SXY_SY drm/exynos/mixer: planes are not disabled by setting dma_addr to zero drm/exynos/mixer: add support for NV21 drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 + drivers/gpu/drm/exynos/exynos_mixer.c | 54 +++ drivers/gpu/drm/exynos/regs-mixer.h | 4 +++ 3 files changed, 23 insertions(+), 36 deletions(-) -- 1.9.1.423.g4596e3a -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] drm/exynos/mixer: planes are not disabled by setting dma_addr to zero
Planes are disabled by calling the win_mode_disable() callback, not by
calling win_mode_commit()[-vp_video_buffer] with dma_addr set to zero.
Thus, the comment in the pixel_format switch default clause is obsolete,
we should always check if the pixel_format is supported, and therefore,
since the driver does not actually supported single-buffer formats,
buf_num will always be 2, and we drop the broken 1-buffer case.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/exynos/exynos_mixer.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 40cf39b..b252ec7 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -382,7 +382,6 @@ static void vp_video_buffer(struct mixer_context *ctx, int
win)
unsigned long flags;
struct hdmi_win_data *win_data;
unsigned int x_ratio, y_ratio;
- unsigned int buf_num = 1;
dma_addr_t luma_addr[2], chroma_addr[2];
bool tiled_mode = false;
bool crcb_mode = false;
@@ -393,16 +392,12 @@ static void vp_video_buffer(struct mixer_context *ctx,
int win)
switch (win_data-pixel_format) {
case DRM_FORMAT_NV12MT:
tiled_mode = true;
+ /* fall through */
case DRM_FORMAT_NV12:
crcb_mode = false;
- buf_num = 2;
break;
/* TODO: single buffer format NV12, NV21 */
default:
- /* ignore pixel format at disable time */
- if (!win_data-dma_addr)
- break;
-
DRM_ERROR(pixel format for vp is wrong [%d].\n,
win_data-pixel_format);
return;
@@ -412,14 +407,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int
win)
x_ratio = (win_data-src_width 16) / win_data-crtc_width;
y_ratio = (win_data-src_height 16) / win_data-crtc_height;
- if (buf_num == 2) {
- luma_addr[0] = win_data-dma_addr;
- chroma_addr[0] = win_data-chroma_dma_addr;
- } else {
- luma_addr[0] = win_data-dma_addr;
- chroma_addr[0] = win_data-dma_addr
- + (win_data-fb_width * win_data-fb_height);
- }
+ luma_addr[0] = win_data-dma_addr;
+ chroma_addr[0] = win_data-chroma_dma_addr;
if (win_data-scan_flags DRM_MODE_FLAG_INTERLACE) {
ctx-interlace = true;
--
1.9.1.423.g4596e3a
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[PATCH 4/4] drm/exynos/mixer: add support for NV21
AFAICT, the only difference between NV12 and NV21 is Cr:Cb vs Cb:Cr.
Since the video processor can handle either order, it should be able to
handle both formats.
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/exynos/exynos_drm_plane.c | 1 +
drivers/gpu/drm/exynos/exynos_mixer.c | 12 +---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c
b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index 8371cbd..bf2be7a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -31,6 +31,7 @@ static const uint32_t formats[] = {
DRM_FORMAT_ARGB,
DRM_FORMAT_NV12,
DRM_FORMAT_NV12MT,
+ DRM_FORMAT_NV21,
};
/*
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index b252ec7..52a94d9 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -383,8 +383,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int
win)
struct hdmi_win_data *win_data;
unsigned int x_ratio, y_ratio;
dma_addr_t luma_addr[2], chroma_addr[2];
- bool tiled_mode = false;
- bool crcb_mode = false;
+ bool tiled_mode;
+ bool crcb_mode;
u32 val;
win_data = ctx-win_data[win];
@@ -392,10 +392,16 @@ static void vp_video_buffer(struct mixer_context *ctx,
int win)
switch (win_data-pixel_format) {
case DRM_FORMAT_NV12MT:
tiled_mode = true;
- /* fall through */
+ crcb_mode = false;
+ break;
case DRM_FORMAT_NV12:
+ tiled_mode = false;
crcb_mode = false;
break;
+ case DRM_FORMAT_NV21:
+ tiled_mode = false;
+ crcb_mode = true;
+ break;
/* TODO: single buffer format NV12, NV21 */
default:
DRM_ERROR(pixel format for vp is wrong [%d].\n,
--
1.9.1.423.g4596e3a
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[PATCH 2/4] drm/exynos/mixer: use MXR_GRP_SXY_SY
Mixer hardware supports offsetting dma from start of source buffer using the MXR_GRP_SXY register. Signed-off-by: Daniel Kurtz djku...@chromium.org --- drivers/gpu/drm/exynos/exynos_mixer.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 475eb49..40cf39b 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -529,13 +529,11 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) dst_x_offset = win_data-crtc_x; dst_y_offset = win_data-crtc_y; + src_x_offset = win_data-fb_x; + src_y_offset = win_data-fb_y; /* converting dma address base and source offset */ - dma_addr = win_data-dma_addr - + (win_data-fb_x * win_data-bpp 3) - + (win_data-fb_y * win_data-fb_width * win_data-bpp 3); - src_x_offset = 0; - src_y_offset = 0; + dma_addr = win_data-dma_addr; if (win_data-scan_flags DRM_MODE_FLAG_INTERLACE) ctx-interlace = true; -- 1.9.1.423.g4596e3a -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] drm/exynos/mixer: move format definitions to regs-mixer
These constants directly define register values, so move them to the
register definition header.
Also, the logic used for setting fmt from bpp is either/or, so just use
if/else.
** No functional change
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm/exynos/exynos_mixer.c | 19 ---
drivers/gpu/drm/exynos/regs-mixer.h | 4
2 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index ce28881..475eb49 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -518,21 +518,10 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
int win)
win_data = ctx-win_data[win];
- #define RGB565 4
- #define ARGB1555 5
- #define ARGB 6
- #define ARGB 7
-
- switch (win_data-bpp) {
- case 16:
- fmt = ARGB;
- break;
- case 32:
- fmt = ARGB;
- break;
- default:
- fmt = ARGB;
- }
+ if (win_data-bpp == 16)
+ fmt = MXR_GRP_CFG_FORMAT_ARGB;
+ else
+ fmt = MXR_GRP_CFG_FORMAT_ARGB;
/* 2x scaling feature */
x_ratio = 0;
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h
b/drivers/gpu/drm/exynos/regs-mixer.h
index 4537026..785a97a 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -114,6 +114,10 @@
#define MXR_GRP_CFG_PIXEL_BLEND_EN (1 16)
#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8)
#define MXR_GRP_CFG_FORMAT_MASKMXR_GRP_CFG_FORMAT_VAL(~0)
+#define MXR_GRP_CFG_FORMAT_RGB565 4
+#define MXR_GRP_CFG_FORMAT_ARGB15555
+#define MXR_GRP_CFG_FORMAT_ARGB6
+#define MXR_GRP_CFG_FORMAT_ARGB7
#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)
/* bits for MXR_GRAPHICn_WH */
--
1.9.1.423.g4596e3a
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Re: [PATCH 1/1] ARM: dts: Keep LDO4 always ON on Arndale board
On 21 April 2014 10:33, Sachin Kamat sachin.ka...@linaro.org wrote: LDO4 regulator was getting disabled preventing the system from going into low power states. Keep it always on to fix it. Signed-off-by: Sachin Kamat sachin.ka...@linaro.org --- arch/arm/boot/dts/exynos5250-arndale.dts |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 090f983..cde19c8 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -107,6 +107,7 @@ regulator-name = VDD_IOPERI_1.8V; regulator-min-microvolt = 180; regulator-max-microvolt = 180; + regulator-always-on; op_mode = 1; }; Ping Kukjin. This is actually a fix patch and should go into rc. -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 0/6] Further cleanup and enable multiplat build
On 16 April 2014 19:21, Tomasz Figa t.f...@samsung.com wrote: Hi Sachin, On 15.04.2014 11:28, Sachin Kamat wrote: This series is based on latest linux-next and depends on the following patch: ARM: EXYNOS: Consolidate Kconfig entries http://article.gmane.org/gmane.linux.kernel.samsung-soc/28642 Changes since v2: Replaced patch 2, ARM: EXYNOS: Staticize exynos_subsys with ARM: EXYNOS: Remove exynos_subsys registration as that code is no more used. Tested on Exynos4210, 4412, 5250 and 5420 based boards. Arnd Bergmann (1): ARM: EXYNOS: Enable multi-platform build support Sachin Kamat (5): ARM: EXYNOS: Remove duplicate lines in Makefile ARM: EXYNOS: Remove exynos_subsys registration ARM: EXYNOS: Migrate Exynos specific macros from plat to mach ARM: EXYNOS: Remove unnecessary inclusion of cpu.h ARM: multi_v7_defconfig: Enable Exynos platform arch/arm/Kconfig | 27 ++- arch/arm/configs/exynos_defconfig|2 +- arch/arm/configs/multi_v7_defconfig | 10 + arch/arm/mach-exynos/Kconfig | 27 +++ arch/arm/mach-exynos/Makefile|9 ++-- arch/arm/mach-exynos/common.h| 72 ++ arch/arm/mach-exynos/cpuidle.c |1 - arch/arm/mach-exynos/exynos.c| 13 -- arch/arm/mach-exynos/hotplug.c |2 - arch/arm/mach-exynos/platsmp.c |2 - arch/arm/mach-exynos/pm.c|1 - arch/arm/mach-exynos/pmu.c |2 - arch/arm/plat-samsung/Makefile |3 ++ arch/arm/plat-samsung/include/plat/cpu.h | 61 - 14 files changed, 119 insertions(+), 113 deletions(-) For the whole series: Reviewed-by: Tomasz Figa t.f...@samsung.com Kukjin, Can you please apply the first 4 patches in this series for now? -- With warm regards, Sachin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] ARM: dts: Fix SPI interrupt numbers for Exynos5420
On 10 April 2014 18:28, Sachin Kamat sachin.ka...@linaro.org wrote:
Updated as per the user manual.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5420.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..6f662b5cc90d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -385,7 +385,7 @@
spi_0: spi@12d2 {
compatible = samsung,exynos4210-spi;
reg = 0x12d2 0x100;
- interrupts = 0 66 0;
+ interrupts = 0 68 0;
dmas = pdma0 5
pdma0 4;
dma-names = tx, rx;
@@ -401,7 +401,7 @@
spi_1: spi@12d3 {
compatible = samsung,exynos4210-spi;
reg = 0x12d3 0x100;
- interrupts = 0 67 0;
+ interrupts = 0 69 0;
dmas = pdma1 5
pdma1 4;
dma-names = tx, rx;
@@ -417,7 +417,7 @@
spi_2: spi@12d4 {
compatible = samsung,exynos4210-spi;
reg = 0x12d4 0x100;
- interrupts = 0 68 0;
+ interrupts = 0 70 0;
dmas = pdma0 7
pdma0 6;
dma-names = tx, rx;
--
Ping Kukjin. This is also a fix patch and should go in rc.
--
With warm regards,
Sachin
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Re: [PATCH 1/1] ARM: dts: Add MFC memory banks to Exynos5420 boards
On 17 March 2014 11:41, Sachin Kamat sachin.ka...@linaro.org wrote:
Add MFC memory banks to Exynos5420 based SMDK and Arndale-octa boards.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts |5 +
arch/arm/boot/dts/exynos5420-smdk5420.dts |5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index f509e8fc290f..051bde7c3665 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -37,6 +37,11 @@
status = okay;
};
+ codec@1100 {
+ samsung,mfc-r = 0x4300 0x80;
+ samsung,mfc-l = 0x5100 0x80;
+ };
+
mmc@1220 {
status = okay;
broken-cd;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ae1ee0470fca..6a9b4553d802 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,6 +68,11 @@
status = okay;
};
+ codec@1100 {
+ samsung,mfc-r = 0x4300 0x80;
+ samsung,mfc-l = 0x5100 0x80;
+ };
+
mmc@1220 {
status = okay;
broken-cd;
--
1.7.9.5
Ping Kukjin.
--
With warm regards,
Sachin
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Re: [PATCH v3 02/16] clk: exynos5420: add clocks for ISP block
Hi Tomasz,
Thanks for the review comments.
On Fri, May 2, 2014 at 2:55 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 01.05.2014 23:09, Tomasz Figa wrote:
Hi Shaik,
On 24.04.2014 15:03, Shaik Ameer Basha wrote:
This patch adds missing clocks for ISP block
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 80
++
1 file changed, 80 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389d4b1..972da5d 100755
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -57,6 +57,7 @@
#define SRC_FSYS0x10244
#define SRC_PERIC00x10250
#define SRC_PERIC10x10254
+#define SRC_ISP0x10270
#define SRC_TOP100x10280
#define SRC_TOP110x10284
#define SRC_TOP120x10288
@@ -77,12 +78,15 @@
#define DIV_PERIC20x10560
#define DIV_PERIC30x10564
#define DIV_PERIC40x10568
+#define SCLK_DIV_ISP00x10580
+#define SCLK_DIV_ISP10x10584
#define GATE_BUS_TOP0x10700
#define GATE_BUS_FSYS00x10740
#define GATE_BUS_PERIC0x10750
#define GATE_BUS_PERIC10x10754
#define GATE_BUS_PERIS00x10760
#define GATE_BUS_PERIS10x10764
+#define GATE_TOP_SCLK_ISP0x10870
#define GATE_IP_GSCL00x10910
#define GATE_IP_GSCL10x10920
#define GATE_IP_MFC0x1092c
@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[]
__initdata = {
SRC_MASK_FSYS,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
+SRC_ISP,
DIV_TOP0,
DIV_TOP1,
DIV_TOP2,
@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[]
__initdata = {
DIV_PERIC2,
DIV_PERIC3,
DIV_PERIC4,
+SCLK_DIV_ISP0,
+SCLK_DIV_ISP1,
GATE_BUS_TOP,
GATE_BUS_FSYS0,
GATE_BUS_PERIC,
GATE_BUS_PERIC1,
GATE_BUS_PERIS0,
GATE_BUS_PERIS1,
+GATE_TOP_SCLK_ISP,
GATE_IP_GSCL0,
GATE_IP_GSCL1,
GATE_IP_MFC,
@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p)= {fin_pll,
mout_sw_aclk200_fsys};
PNAME(mout_sw_aclk200_fsys2_p) = {dout_aclk200_fsys2,
mout_sclk_spll};
PNAME(mout_user_aclk200_fsys2_p) = {fin_pll,
mout_sw_aclk200_fsys2};
+PNAME(mout_sw_aclk400_isp_p) = {dout_aclk400_isp, mout_sclk_spll};
+PNAME(mout_user_aclk400_isp_p) = {fin_pll, mout_sw_aclk400_isp};
+
+PNAME(mout_sw_aclk333_432_isp0_p) = {dout_aclk333_432_isp0,
+mout_sclk_spll};
+PNAME(mout_user_aclk333_432_isp0_p) = {fin_pll,
mout_sw_aclk333_432_isp0};
+
+PNAME(mout_sw_aclk333_432_isp_p) = {dout_aclk333_432_isp,
mout_sclk_spll};
+PNAME(mout_user_aclk333_432_isp_p) = {fin_pll,
mout_sw_aclk333_432_isp};
PNAME(mout_sw_aclk200_p) = {dout_aclk200, mout_sclk_spll};
PNAME(mout_aclk200_disp1_p) = {fin_pll, mout_sw_aclk200};
@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {fin_pll,
mout_sw_aclk166};
PNAME(mout_sw_aclk266_p) = {dout_aclk266, mout_sclk_spll};
PNAME(mout_user_aclk266_p) = {fin_pll, mout_sw_aclk266};
+PNAME(mout_user_aclk266_isp_p) = {fin_pll, mout_sw_aclk266};
PNAME(mout_sw_aclk333_432_gscl_p) = {dout_aclk333_432_gscl,
mout_sclk_spll};
PNAME(mout_user_aclk333_432_gscl_p) = {fin_pll,
mout_sw_aclk333_432_gscl};
@@ -448,6 +466,31 @@ static struct samsung_mux_clock
exynos5420_mux_clks[] __initdata = {
MUX(0, mout_spi0, mout_group2_p, SRC_PERIC1, 20, 3),
MUX(0, mout_spi1, mout_group2_p, SRC_PERIC1, 24, 3),
MUX(0, mout_spi2, mout_group2_p, SRC_PERIC1, 28, 3),
+MUX(0, mout_aclk400_isp, mout_group1_p, SRC_TOP0, 0, 2),
+MUX(0, mout_sw_aclk400_isp, mout_sw_aclk400_isp_p,
+SRC_TOP10, 0, 1),
+MUX(0, mout_user_aclk400_isp, mout_user_aclk400_isp_p,
+SRC_TOP3, 0, 1),
+MUX(0, mout_aclk333_432_isp0, mout_group4_p, SRC_TOP1, 12, 2),
+MUX(0, mout_sw_aclk333_432_isp0, mout_sw_aclk333_432_isp0_p,
+SRC_TOP11, 12, 1),
+MUX(0, mout_user_aclk333_432_isp0, mout_user_aclk333_432_isp0_p,
+SRC_TOP4, 12, 1),
+MUX(0, mout_aclk333_432_isp, mout_group4_p,
+SRC_TOP1, 4, 2),
+MUX(0, mout_sw_aclk333_432_isp, mout_sw_aclk333_432_isp_p,
+SRC_TOP11, 4, 1),
+MUX(0, mout_user_aclk333_432_isp, mout_user_aclk333_432_isp_p,
+SRC_TOP4, 4, 1),
+MUX(0, mout_user_aclk266_isp, mout_user_aclk266_isp_p,
+SRC_TOP4, 16, 1),
+
+/* ISP Block */
+MUX(0, mout_pwm_isp, mout_group2_p, SRC_ISP, 24, 3),
+MUX(0, mout_uart_isp, mout_group2_p, SRC_ISP, 20, 3),
+MUX(0, mout_spi0_isp, mout_group2_p, SRC_ISP, 12, 3),
+MUX(0, mout_spi1_isp, mout_group2_p, SRC_ISP, 16, 3),
+MUX(0, mout_isp_sensor, mout_group2_p, SRC_ISP, 28, 3),
};
static struct samsung_div_clock
Re: [PATCH] arm: exynos: add generic function to calculate cpu number
On 25 April 2014 11:14, Chander Kashyap chander.kash...@linaro.org wrote:
The address of cpu power registers in pmu is based on cpu number
offsets. This function calculate the same. This is essentially
required in case of multicluster SoC's e.g Exynos5420.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/regs-pmu.h |9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a256..217da2e 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -313,4 +313,13 @@
#define EXYNOS5_OPTION_USE_RETENTION (1 4)
+#include asm/cputype.h
+#define MAX_CPUS_IN_CLUSTER4
+
+static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
+{
+ return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
++ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
#endif /* __ASM_ARCH_REGS_PMU_H */
--
1.7.9.5
Kukjin, Can you please have a look.
--
with warm regards,
Chander Kashyap
--
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Re: Bare metal Code to test Big Little on Arndale Octa (5420)
Hi, No public code has been released to boot all 8 cores on the 5420. You can only see the A15s. You could however, if you are interested, get IKS[1] working by integrating the MCPM patches posted by Samsung and the IKS patches that are already in mainline. Regards, Amit [1] http://lwn.net/Articles/481055/ On Mon, Apr 28, 2014 at 11:21 AM, armdev armdev@gmail.com wrote: Hi, We are trying a write a bare metal test code for Switching tasks from A15 Core to A7 core. As of now we have this article to start with https://lwn.net/Articles/481055/. Can the list help us in a) Where (file/directory ) in Linux kernel code that does the switching code (arch specific) for 5420 ? b) Any test cases for big little on 5420 ? -Regards armdev team ___ linaro-kernel mailing list linaro-ker...@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 02/16] clk: exynos5420: add clocks for ISP block
Hi Tomasz,
On Fri, May 2, 2014 at 3:03 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 24.04.2014 15:03, Shaik Ameer Basha wrote:
This patch adds missing clocks for ISP block
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 80
++
1 file changed, 80 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389d4b1..972da5d 100755
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -57,6 +57,7 @@
#define SRC_FSYS 0x10244
#define SRC_PERIC00x10250
#define SRC_PERIC10x10254
+#define SRC_ISP0x10270
#define SRC_TOP10 0x10280
#define SRC_TOP11 0x10284
#define SRC_TOP12 0x10288
@@ -77,12 +78,15 @@
#define DIV_PERIC20x10560
#define DIV_PERIC30x10564
#define DIV_PERIC40x10568
+#define SCLK_DIV_ISP0 0x10580
+#define SCLK_DIV_ISP1 0x10584
#define GATE_BUS_TOP 0x10700
#define GATE_BUS_FSYS00x10740
#define GATE_BUS_PERIC0x10750
#define GATE_BUS_PERIC1 0x10754
#define GATE_BUS_PERIS0 0x10760
#define GATE_BUS_PERIS1 0x10764
+#define GATE_TOP_SCLK_ISP 0x10870
#define GATE_IP_GSCL0 0x10910
#define GATE_IP_GSCL1 0x10920
#define GATE_IP_MFC 0x1092c
@@ -145,6 +149,7 @@ static unsigned long exynos5420_clk_regs[] __initdata
= {
SRC_MASK_FSYS,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
+ SRC_ISP,
DIV_TOP0,
DIV_TOP1,
DIV_TOP2,
@@ -158,12 +163,15 @@ static unsigned long exynos5420_clk_regs[]
__initdata = {
DIV_PERIC2,
DIV_PERIC3,
DIV_PERIC4,
+ SCLK_DIV_ISP0,
+ SCLK_DIV_ISP1,
GATE_BUS_TOP,
GATE_BUS_FSYS0,
GATE_BUS_PERIC,
GATE_BUS_PERIC1,
GATE_BUS_PERIS0,
GATE_BUS_PERIS1,
+ GATE_TOP_SCLK_ISP,
GATE_IP_GSCL0,
GATE_IP_GSCL1,
GATE_IP_MFC,
@@ -250,6 +258,15 @@ PNAME(mout_user_aclk200_fsys_p)= {fin_pll,
mout_sw_aclk200_fsys};
PNAME(mout_sw_aclk200_fsys2_p) = {dout_aclk200_fsys2,
mout_sclk_spll};
PNAME(mout_user_aclk200_fsys2_p) = {fin_pll, mout_sw_aclk200_fsys2};
+PNAME(mout_sw_aclk400_isp_p) = {dout_aclk400_isp, mout_sclk_spll};
+PNAME(mout_user_aclk400_isp_p) = {fin_pll, mout_sw_aclk400_isp};
+
+PNAME(mout_sw_aclk333_432_isp0_p) = {dout_aclk333_432_isp0,
+ mout_sclk_spll};
+PNAME(mout_user_aclk333_432_isp0_p) = {fin_pll,
mout_sw_aclk333_432_isp0};
+
+PNAME(mout_sw_aclk333_432_isp_p) = {dout_aclk333_432_isp,
mout_sclk_spll};
+PNAME(mout_user_aclk333_432_isp_p) = {fin_pll,
mout_sw_aclk333_432_isp};
PNAME(mout_sw_aclk200_p) = {dout_aclk200, mout_sclk_spll};
PNAME(mout_aclk200_disp1_p) = {fin_pll, mout_sw_aclk200};
@@ -265,6 +282,7 @@ PNAME(mout_user_aclk166_p) = {fin_pll,
mout_sw_aclk166};
PNAME(mout_sw_aclk266_p) = {dout_aclk266, mout_sclk_spll};
PNAME(mout_user_aclk266_p) = {fin_pll, mout_sw_aclk266};
+PNAME(mout_user_aclk266_isp_p) = {fin_pll, mout_sw_aclk266};
PNAME(mout_sw_aclk333_432_gscl_p) = {dout_aclk333_432_gscl,
mout_sclk_spll};
PNAME(mout_user_aclk333_432_gscl_p) = {fin_pll,
mout_sw_aclk333_432_gscl};
@@ -448,6 +466,31 @@ static struct samsung_mux_clock exynos5420_mux_clks[]
__initdata = {
MUX(0, mout_spi0, mout_group2_p, SRC_PERIC1, 20, 3),
MUX(0, mout_spi1, mout_group2_p, SRC_PERIC1, 24, 3),
MUX(0, mout_spi2, mout_group2_p, SRC_PERIC1, 28, 3),
+ MUX(0, mout_aclk400_isp, mout_group1_p, SRC_TOP0, 0, 2),
+ MUX(0, mout_sw_aclk400_isp, mout_sw_aclk400_isp_p,
+ SRC_TOP10, 0, 1),
+ MUX(0, mout_user_aclk400_isp, mout_user_aclk400_isp_p,
+ SRC_TOP3, 0, 1),
+ MUX(0, mout_aclk333_432_isp0, mout_group4_p, SRC_TOP1, 12, 2),
+ MUX(0, mout_sw_aclk333_432_isp0, mout_sw_aclk333_432_isp0_p,
+ SRC_TOP11, 12, 1),
+ MUX(0, mout_user_aclk333_432_isp0, mout_user_aclk333_432_isp0_p,
+ SRC_TOP4, 12, 1),
+ MUX(0, mout_aclk333_432_isp, mout_group4_p,
+ SRC_TOP1, 4, 2),
+ MUX(0, mout_sw_aclk333_432_isp, mout_sw_aclk333_432_isp_p,
+ SRC_TOP11, 4, 1),
+ MUX(0, mout_user_aclk333_432_isp, mout_user_aclk333_432_isp_p,
+ SRC_TOP4, 4, 1),
+ MUX(0, mout_user_aclk266_isp, mout_user_aclk266_isp_p,
+ SRC_TOP4, 16, 1),
+
+ /* ISP Block */
+ MUX(0, mout_pwm_isp, mout_group2_p, SRC_ISP, 24, 3),
+ MUX(0, mout_uart_isp, mout_group2_p, SRC_ISP, 20, 3),
+ MUX(0, mout_spi0_isp, mout_group2_p,
Re: [PATCH v3 00/16] exynos5420: clock file cleanup
Hi Tomasz, On Fri, May 2, 2014 at 2:58 AM, Tomasz Figa tomasz.f...@gmail.com wrote: On 24.04.2014 15:03, Shaik Ameer Basha wrote: Many changes/fixes have been identified for clock file for exynos5420. These include correct parents, bit fields, new clocks etc. Existing files needs some correction in terms of names of the clock and indentation. These issues are addressed in this patch series. It also replaces the usage of enums with macro as clock ids. This patch series is rebased on, git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git:master This patch is also dependent on the following patch. ARM: dts: add dt node for sss module for exynos5250/5420 Also a general comment to all the patches. Please assign clock IDs for all the clocks being added. In general, all the defined clocks should have clock IDs defined to let them be accessed from Device Tree, for example in case of DT clock initialization that is being worked on right now. Ok. Will take care of this in next series. Regards, Shaik Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 4/4] usb: ehci-exynos: Change to use phy provided by the generic phy framework
From: Kamil Debski k.deb...@samsung.com
Add the phy provider, supplied by new Exynos-usb2phy using
Generic phy framework.
Keeping the support for older USB phy intact right now, in order
to prevent any functionality break in absence of relevant
device tree side change for ehci-exynos.
Once we move to new phy in the device nodes for ehci, we can
remove the support for older phys.
Signed-off-by: Kamil Debski k.deb...@samsung.com
[gautam.vi...@samsung.com: Addressed review comments from mailing list]
[gautam.vi...@samsung.com: Kept the code for old usb-phy, and just
added support for new exynos5-usb2phy in generic phy framework]
[gautam.vi...@samsung.com: Edited the commit message]
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
Acked-by: Alan Stern st...@rowland.harvard.edu
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes from v11:
- Removed setting phy explicitly to error pointer.
- Changed error check to '-ENOSYS' instead of '-ENXIO' in failure case of
devm_of_phy_get().
Changes from v10:
- Removed 'phy-names' property from the bindings since we don't need it.
- Restructured exynos_ehci_get_phy() function to handle error codes as
well as return relevant error codes effectively.
- Added IS_ERR() check for PHYs in exynos_ehci_phy_enable()/disable().
Changes from v9:
- Calling usb_phy_shutdown() when exynos_ehci_phy_enable() is failing.
- Made exynos_ehci_phy_disable() return void, since its return value
did not serve any purpose.
- Calling clk_disable_unprepare() in exynos_ehci_resume() when
exynos_ehci_phy_enable() is failed.
.../devicetree/bindings/usb/exynos-usb.txt | 15 +++
drivers/usb/host/ehci-exynos.c | 129 +---
2 files changed, 124 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 49a9c6f..a3b5990 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -12,6 +12,13 @@ Required properties:
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be usbhost.
+ - port: if in the SoC there are EHCI phys, they should be listed here.
+ One phy per port. Each port should have following entries:
+ - reg: port number on EHCI controller, e.g
+ On Exynos5250, port 0 is USB2.0 otg phy
+ port 1 is HSIC phy0
+ port 2 is HSIC phy1
+ - phys: from the *Generic PHY* bindings; specifying phy used by port.
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
@@ -27,6 +34,14 @@ Example:
clocks = clock 285;
clock-names = usbhost;
+
+ #address-cells = 1;
+ #size-cells = 0;
+ port@0 {
+ reg = 0;
+ phys = usb2phy 1;
+ status = disabled;
+ };
};
OHCI
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 4d763dc..c7081c7 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -19,6 +19,7 @@
#include linux/module.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/phy/phy.h
#include linux/platform_device.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
@@ -42,14 +43,104 @@
static const char hcd_name[] = ehci-exynos;
static struct hc_driver __read_mostly exynos_ehci_hc_driver;
+#define PHY_NUMBER 3
+
struct exynos_ehci_hcd {
struct clk *clk;
struct usb_phy *phy;
struct usb_otg *otg;
+ struct phy *phy_g[PHY_NUMBER];
};
#define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)-priv)
+static int exynos_ehci_get_phy(struct device *dev,
+ struct exynos_ehci_hcd *exynos_ehci)
+{
+ struct device_node *child;
+ struct phy *phy;
+ int phy_number;
+ int ret = 0;
+
+ exynos_ehci-phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(exynos_ehci-phy)) {
+ ret = PTR_ERR(exynos_ehci-phy);
+ if (ret != -ENXIO ret != -ENODEV) {
+ dev_err(dev, no usb2 phy configured\n);
+ return ret;
+ }
+ dev_dbg(dev, Failed to get usb2 phy\n);
+ } else {
+ exynos_ehci-otg = exynos_ehci-phy-otg;
+ }
+
+ for_each_available_child_of_node(dev-of_node, child) {
+ ret = of_property_read_u32(child, reg, phy_number);
+ if (ret) {
+ dev_err(dev, Failed to parse device tree\n);
+ of_node_put(child);
+ return ret;
+ }
+
+ if (phy_number = PHY_NUMBER)
[PATCH v6 3/4] usb: ohci-exynos: Add facility to use phy provided by the generic phy framework
Add support to consume phy provided by Generic phy framework.
Keeping the support for older usb-phy intact right now, in order
to prevent any functionality break in absence of relevant
device tree side change for ohci-exynos.
Once we move to new phy in the device nodes for ohci, we can
remove the support for older phys.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Cc: Jingoo Han jg1@samsung.com
Acked-by: Alan Stern st...@rowland.harvard.edu
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes from v5:
- Removed setting phy explicitly to error pointer.
- Changed error check to '-ENOSYS' instead of '-ENXIO' in failure case of
devm_of_phy_get().
Changes from v4:
- Removed 'phy-names' property from the bindings since we don't need it.
- Restructured exynos_ohci_get_phy() function to handle error codes as
well as return relevant error codes effectively.
- Added IS_ERR() check for PHYs in exynos_ohci_phy_enable()/disable().
Changes from v3:
- Calling usb_phy_shutdown() when exynos_ohci_phy_enable() is failing.
- Made exynos_ohci_phy_disable() return void, since its return value
did not serve any purpose.
- Calling clk_disable_unprepare() in exynos_ohci_resume() when
exynos_ohci_phy_enable() is failed.
.../devicetree/bindings/usb/exynos-usb.txt | 16 +++
drivers/usb/host/ohci-exynos.c | 118 +---
2 files changed, 118 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt
b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index d967ba1..49a9c6f 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -38,6 +38,13 @@ Required properties:
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be usbhost.
+ - port: if in the SoC there are OHCI phys, they should be listed here.
+ One phy per port. Each port should have following entries:
+ - reg: port number on OHCI controller, e.g
+ On Exynos5250, port 0 is USB2.0 otg phy
+ port 1 is HSIC phy0
+ port 2 is HSIC phy1
+ - phys: from the *Generic PHY* bindings, specifying phy used by port.
Example:
usb@1212 {
@@ -47,6 +54,15 @@ Example:
clocks = clock 285;
clock-names = usbhost;
+
+ #address-cells = 1;
+ #size-cells = 0;
+ port@0 {
+ reg = 0;
+ phys = usb2phy 1;
+ status = disabled;
+ };
+
};
DWC3
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 05f00e3..32f2ff1 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -18,6 +18,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/phy/phy.h
#include linux/usb/phy.h
#include linux/usb/samsung_usb_phy.h
#include linux/usb.h
@@ -33,28 +34,110 @@ static struct hc_driver __read_mostly
exynos_ohci_hc_driver;
#define to_exynos_ohci(hcd) (struct exynos_ohci_hcd *)(hcd_to_ohci(hcd)-priv)
+#define PHY_NUMBER 3
+
struct exynos_ohci_hcd {
struct clk *clk;
struct usb_phy *phy;
struct usb_otg *otg;
+ struct phy *phy_g[PHY_NUMBER];
};
-static void exynos_ohci_phy_enable(struct device *dev)
+static int exynos_ohci_get_phy(struct device *dev,
+ struct exynos_ohci_hcd *exynos_ohci)
+{
+ struct device_node *child;
+ struct phy *phy;
+ int phy_number;
+ int ret = 0;
+
+ exynos_ohci-phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(exynos_ohci-phy)) {
+ ret = PTR_ERR(exynos_ohci-phy);
+ if (ret != -ENXIO ret != -ENODEV) {
+ dev_err(dev, no usb2 phy configured\n);
+ return ret;
+ }
+ dev_dbg(dev, Failed to get usb2 phy\n);
+ } else {
+ exynos_ohci-otg = exynos_ohci-phy-otg;
+ }
+
+ /*
+* Getting generic phy:
+* We are keeping both types of phys as a part of transiting OHCI
+* to generic phy framework, so as to maintain backward compatibilty
+* with old DTB.
+* If there are existing devices using DTB files built from them,
+* to remove the support for old bindings in this driver,
+* we need to make sure that such devices have their DTBs
+* updated to ones built from new DTS.
+*/
+ for_each_available_child_of_node(dev-of_node, child) {
+ ret = of_property_read_u32(child, reg, phy_number);
+ if (ret) {
+ dev_err(dev, Failed to parse device tree\n);
+ of_node_put(child);
+
[PATCH v4 1/4] usb: ohci-exynos: Use struct device instead of platform_device
Change to use struct device instead of struct platform_device
for some static functions.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Acked-by: Alan Stern st...@rowland.harvard.edu
Acked-by: Jingoo Han jg1@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes since v1:
- none
drivers/usb/host/ohci-exynos.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 9cf80cb..05f00e3 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -39,18 +39,18 @@ struct exynos_ohci_hcd {
struct usb_otg *otg;
};
-static void exynos_ohci_phy_enable(struct platform_device *pdev)
+static void exynos_ohci_phy_enable(struct device *dev)
{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
if (exynos_ohci-phy)
usb_phy_init(exynos_ohci-phy);
}
-static void exynos_ohci_phy_disable(struct platform_device *pdev)
+static void exynos_ohci_phy_disable(struct device *dev)
{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
if (exynos_ohci-phy)
@@ -139,7 +139,7 @@ skip_phy:
platform_set_drvdata(pdev, hcd);
- exynos_ohci_phy_enable(pdev);
+ exynos_ohci_phy_enable(pdev-dev);
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (err) {
@@ -150,7 +150,7 @@ skip_phy:
return 0;
fail_add_hcd:
- exynos_ohci_phy_disable(pdev);
+ exynos_ohci_phy_disable(pdev-dev);
fail_io:
clk_disable_unprepare(exynos_ohci-clk);
fail_clk:
@@ -168,7 +168,7 @@ static int exynos_ohci_remove(struct platform_device *pdev)
if (exynos_ohci-otg)
exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
- exynos_ohci_phy_disable(pdev);
+ exynos_ohci_phy_disable(pdev-dev);
clk_disable_unprepare(exynos_ohci-clk);
@@ -190,7 +190,6 @@ static int exynos_ohci_suspend(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
- struct platform_device *pdev = to_platform_device(dev);
bool do_wakeup = device_may_wakeup(dev);
int rc = ohci_suspend(hcd, do_wakeup);
@@ -200,7 +199,7 @@ static int exynos_ohci_suspend(struct device *dev)
if (exynos_ohci-otg)
exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
- exynos_ohci_phy_disable(pdev);
+ exynos_ohci_phy_disable(dev);
clk_disable_unprepare(exynos_ohci-clk);
@@ -211,14 +210,13 @@ static int exynos_ohci_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
- struct platform_device *pdev= to_platform_device(dev);
clk_prepare_enable(exynos_ohci-clk);
if (exynos_ohci-otg)
exynos_ohci-otg-set_host(exynos_ohci-otg, hcd-self);
- exynos_ohci_phy_enable(pdev);
+ exynos_ohci_phy_enable(dev);
ohci_resume(hcd, false);
--
1.7.10.4
--
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[PATCH v4 2/4] usb: ehci-exynos: Use struct device instead of platform_device
Change to use struct device instead of struct platform_device
for some static functions.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Acked-by: Alan Stern st...@rowland.harvard.edu
Acked-by: Jingoo Han jg1@samsung.com
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes since v1:
- none
drivers/usb/host/ehci-exynos.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index 7f425ac..4d763dc 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -50,9 +50,8 @@ struct exynos_ehci_hcd {
#define to_exynos_ehci(hcd) (struct exynos_ehci_hcd *)(hcd_to_ehci(hcd)-priv)
-static void exynos_setup_vbus_gpio(struct platform_device *pdev)
+static void exynos_setup_vbus_gpio(struct device *dev)
{
- struct device *dev = pdev-dev;
int err;
int gpio;
@@ -88,7 +87,7 @@ static int exynos_ehci_probe(struct platform_device *pdev)
if (err)
return err;
- exynos_setup_vbus_gpio(pdev);
+ exynos_setup_vbus_gpio(pdev-dev);
hcd = usb_create_hcd(exynos_ehci_hc_driver,
pdev-dev, dev_name(pdev-dev));
--
1.7.10.4
--
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Re: [PATCH v3 01/16] clk: exynos5420: rename parent clocks
Hi Tomasz,
On Thu, May 1, 2014 at 11:09 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Shaik,
Thanks for splitting the series into reasonably-sized patches. It's much
more convenient to review them now.
On 24.04.2014 15:03, Shaik Ameer Basha wrote:
This patch modifies the defined parent clock names as per the
exynos5420 datasheet.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 359
++
1 file changed, 187 insertions(+), 172 deletions(-)
mode change 100644 = 100755 drivers/clk/samsung/clk-exynos5420.c
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
old mode 100644
new mode 100755
index 35311e1..389d4b1
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}
#endif
/* list of all parent clocks */
-PNAME(mspll_cpu_p) = { sclk_cpll, sclk_dpll,
- sclk_mpll, sclk_spll };
-PNAME(cpu_p) = { mout_apll , mout_mspll_cpu };
-PNAME(kfc_p) = { mout_kpll , mout_mspll_kfc };
-PNAME(apll_p) = { fin_pll, fout_apll, };
-PNAME(bpll_p) = { fin_pll, fout_bpll, };
-PNAME(cpll_p) = { fin_pll, fout_cpll, };
-PNAME(dpll_p) = { fin_pll, fout_dpll, };
-PNAME(epll_p) = { fin_pll, fout_epll, };
-PNAME(ipll_p) = { fin_pll, fout_ipll, };
-PNAME(kpll_p) = { fin_pll, fout_kpll, };
-PNAME(mpll_p) = { fin_pll, fout_mpll, };
-PNAME(rpll_p) = { fin_pll, fout_rpll, };
-PNAME(spll_p) = { fin_pll, fout_spll, };
-PNAME(vpll_p) = { fin_pll, fout_vpll, };
-
-PNAME(group1_p)= { sclk_cpll, sclk_dpll, sclk_mpll
};
-PNAME(group2_p)= { fin_pll, sclk_cpll, sclk_dpll,
sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll,
sclk_rpll };
-PNAME(group3_p)= { sclk_rpll, sclk_spll };
-PNAME(group4_p)= { sclk_ipll, sclk_dpll, sclk_mpll
};
-PNAME(group5_p)= { sclk_vpll, sclk_dpll };
-
-PNAME(sw_aclk66_p) = { dout_aclk66, sclk_spll };
-PNAME(aclk66_peric_p) = { fin_pll, mout_sw_aclk66 };
-
-PNAME(sw_aclk200_fsys_p) = { dout_aclk200_fsys, sclk_spll};
-PNAME(user_aclk200_fsys_p) = { fin_pll, mout_sw_aclk200_fsys };
-
-PNAME(sw_aclk200_fsys2_p) = { dout_aclk200_fsys2, sclk_spll};
-PNAME(user_aclk200_fsys2_p)= { fin_pll, mout_sw_aclk200_fsys2 };
-
-PNAME(sw_aclk200_p) = { dout_aclk200, sclk_spll};
-PNAME(aclk200_disp1_p) = { fin_pll, mout_sw_aclk200 };
-
-PNAME(sw_aclk400_mscl_p) = { dout_aclk400_mscl, sclk_spll};
-PNAME(user_aclk400_mscl_p) = { fin_pll, mout_sw_aclk400_mscl };
-
-PNAME(sw_aclk333_p) = { dout_aclk333, sclk_spll};
-PNAME(user_aclk333_p) = { fin_pll, mout_sw_aclk333 };
-
-PNAME(sw_aclk166_p) = { dout_aclk166, sclk_spll};
-PNAME(user_aclk166_p) = { fin_pll, mout_sw_aclk166 };
-
-PNAME(sw_aclk266_p) = { dout_aclk266, sclk_spll};
-PNAME(user_aclk266_p) = { fin_pll, mout_sw_aclk266 };
-
-PNAME(sw_aclk333_432_gscl_p) = { dout_aclk333_432_gscl, sclk_spll};
-PNAME(user_aclk333_432_gscl_p) = { fin_pll, mout_sw_aclk333_432_gscl
};
-
-PNAME(sw_aclk300_gscl_p) = { dout_aclk300_gscl, sclk_spll};
-PNAME(user_aclk300_gscl_p) = { fin_pll, mout_sw_aclk300_gscl };
-
-PNAME(sw_aclk300_disp1_p) = { dout_aclk300_disp1, sclk_spll};
-PNAME(user_aclk300_disp1_p)= { fin_pll, mout_sw_aclk300_disp1 };
-
-PNAME(sw_aclk300_jpeg_p) = { dout_aclk300_jpeg, sclk_spll};
-PNAME(user_aclk300_jpeg_p) = { fin_pll, mout_sw_aclk300_jpeg };
-
-PNAME(sw_aclk_g3d_p) = { dout_aclk_g3d, sclk_spll};
-PNAME(user_aclk_g3d_p) = { fin_pll, mout_sw_aclk_g3d };
-
-PNAME(sw_aclk266_g2d_p) = { dout_aclk266_g2d, sclk_spll};
-PNAME(user_aclk266_g2d_p) = { fin_pll, mout_sw_aclk266_g2d };
-
-PNAME(sw_aclk333_g2d_p) = { dout_aclk333_g2d, sclk_spll};
-PNAME(user_aclk333_g2d_p) = { fin_pll, mout_sw_aclk333_g2d };
-
-PNAME(audio0_p)= { fin_pll, cdclk0, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(audio1_p)= { fin_pll, cdclk1, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(audio2_p)= { fin_pll, cdclk2, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(spdif_p) = { fin_pll, dout_audio0, dout_audio1,
dout_audio2,
- spdif_extclk, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(hdmi_p) = { dout_hdmi_pixel, sclk_hdmiphy };
-PNAME(maudio0_p) = { fin_pll, maudio_clk, sclk_dpll,
sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll,
sclk_rpll };
+PNAME(mout_mspll_cpu_p) = {mout_sclk_cpll, mout_sclk_dpll,
+
Re: [PATCH v3 01/16] clk: exynos5420: rename parent clocks
On Mon, May 5, 2014 at 10:58 AM, Shaik Ameer Basha
shaik.sams...@gmail.com wrote:
Hi Tomasz,
On Thu, May 1, 2014 at 11:09 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Shaik,
Thanks for splitting the series into reasonably-sized patches. It's much
more convenient to review them now.
On 24.04.2014 15:03, Shaik Ameer Basha wrote:
This patch modifies the defined parent clock names as per the
exynos5420 datasheet.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 359
++
1 file changed, 187 insertions(+), 172 deletions(-)
mode change 100644 = 100755 drivers/clk/samsung/clk-exynos5420.c
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
old mode 100644
new mode 100755
index 35311e1..389d4b1
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -217,85 +217,92 @@ static void exynos5420_clk_sleep_init(void) {}
#endif
/* list of all parent clocks */
-PNAME(mspll_cpu_p) = { sclk_cpll, sclk_dpll,
- sclk_mpll, sclk_spll };
-PNAME(cpu_p) = { mout_apll , mout_mspll_cpu };
-PNAME(kfc_p) = { mout_kpll , mout_mspll_kfc };
-PNAME(apll_p) = { fin_pll, fout_apll, };
-PNAME(bpll_p) = { fin_pll, fout_bpll, };
-PNAME(cpll_p) = { fin_pll, fout_cpll, };
-PNAME(dpll_p) = { fin_pll, fout_dpll, };
-PNAME(epll_p) = { fin_pll, fout_epll, };
-PNAME(ipll_p) = { fin_pll, fout_ipll, };
-PNAME(kpll_p) = { fin_pll, fout_kpll, };
-PNAME(mpll_p) = { fin_pll, fout_mpll, };
-PNAME(rpll_p) = { fin_pll, fout_rpll, };
-PNAME(spll_p) = { fin_pll, fout_spll, };
-PNAME(vpll_p) = { fin_pll, fout_vpll, };
-
-PNAME(group1_p)= { sclk_cpll, sclk_dpll, sclk_mpll
};
-PNAME(group2_p)= { fin_pll, sclk_cpll, sclk_dpll,
sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll,
sclk_rpll };
-PNAME(group3_p)= { sclk_rpll, sclk_spll };
-PNAME(group4_p)= { sclk_ipll, sclk_dpll, sclk_mpll
};
-PNAME(group5_p)= { sclk_vpll, sclk_dpll };
-
-PNAME(sw_aclk66_p) = { dout_aclk66, sclk_spll };
-PNAME(aclk66_peric_p) = { fin_pll, mout_sw_aclk66 };
-
-PNAME(sw_aclk200_fsys_p) = { dout_aclk200_fsys, sclk_spll};
-PNAME(user_aclk200_fsys_p) = { fin_pll, mout_sw_aclk200_fsys };
-
-PNAME(sw_aclk200_fsys2_p) = { dout_aclk200_fsys2, sclk_spll};
-PNAME(user_aclk200_fsys2_p)= { fin_pll, mout_sw_aclk200_fsys2 };
-
-PNAME(sw_aclk200_p) = { dout_aclk200, sclk_spll};
-PNAME(aclk200_disp1_p) = { fin_pll, mout_sw_aclk200 };
-
-PNAME(sw_aclk400_mscl_p) = { dout_aclk400_mscl, sclk_spll};
-PNAME(user_aclk400_mscl_p) = { fin_pll, mout_sw_aclk400_mscl };
-
-PNAME(sw_aclk333_p) = { dout_aclk333, sclk_spll};
-PNAME(user_aclk333_p) = { fin_pll, mout_sw_aclk333 };
-
-PNAME(sw_aclk166_p) = { dout_aclk166, sclk_spll};
-PNAME(user_aclk166_p) = { fin_pll, mout_sw_aclk166 };
-
-PNAME(sw_aclk266_p) = { dout_aclk266, sclk_spll};
-PNAME(user_aclk266_p) = { fin_pll, mout_sw_aclk266 };
-
-PNAME(sw_aclk333_432_gscl_p) = { dout_aclk333_432_gscl, sclk_spll};
-PNAME(user_aclk333_432_gscl_p) = { fin_pll, mout_sw_aclk333_432_gscl
};
-
-PNAME(sw_aclk300_gscl_p) = { dout_aclk300_gscl, sclk_spll};
-PNAME(user_aclk300_gscl_p) = { fin_pll, mout_sw_aclk300_gscl };
-
-PNAME(sw_aclk300_disp1_p) = { dout_aclk300_disp1, sclk_spll};
-PNAME(user_aclk300_disp1_p)= { fin_pll, mout_sw_aclk300_disp1 };
-
-PNAME(sw_aclk300_jpeg_p) = { dout_aclk300_jpeg, sclk_spll};
-PNAME(user_aclk300_jpeg_p) = { fin_pll, mout_sw_aclk300_jpeg };
-
-PNAME(sw_aclk_g3d_p) = { dout_aclk_g3d, sclk_spll};
-PNAME(user_aclk_g3d_p) = { fin_pll, mout_sw_aclk_g3d };
-
-PNAME(sw_aclk266_g2d_p) = { dout_aclk266_g2d, sclk_spll};
-PNAME(user_aclk266_g2d_p) = { fin_pll, mout_sw_aclk266_g2d };
-
-PNAME(sw_aclk333_g2d_p) = { dout_aclk333_g2d, sclk_spll};
-PNAME(user_aclk333_g2d_p) = { fin_pll, mout_sw_aclk333_g2d };
-
-PNAME(audio0_p)= { fin_pll, cdclk0, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(audio1_p)= { fin_pll, cdclk1, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(audio2_p)= { fin_pll, cdclk2, sclk_dpll, sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(spdif_p) = { fin_pll, dout_audio0, dout_audio1,
dout_audio2,
- spdif_extclk, sclk_ipll, sclk_epll, sclk_rpll };
-PNAME(hdmi_p) = { dout_hdmi_pixel, sclk_hdmiphy };
-PNAME(maudio0_p) = { fin_pll, maudio_clk, sclk_dpll,
sclk_mpll,
- sclk_spll, sclk_ipll, sclk_epll,
sclk_rpll };
