Re: [PATCH v4 7/8] ARM: Exynos: switch to using generic cpufreq-cpu0 driver
Hi Arnd/Rob/Mike et al,
We didn't conclude anything out of this thread and so kicking it
again as we need to close bindings to support cpufreq-cpu0
better for platforms not sharing clock lines across all CPUs.
https://lkml.org/lkml/2014/7/1/358
On 14 May 2014 20:03, Arnd Bergmann wrote:
> On Wednesday 14 May 2014 08:45:23 Rob Herring wrote:
>> We already have properties which indicate this driver can be used by a
>> platform: opp table and a clock for the cpu. If this information is
There can be platform drivers which also depend on these properties
and picking cpufreq-cpu0 on this basis doesn't look correct.
>> not sufficient to determine whether you can use this driver or not,
>> then you simply need to match against the platform. Perhaps the match
>> list should be a blacklist rather than a whitelist, so new platforms
>> work without a kernel change.
>
> We'd not only need a blacklist, but also a way to tell whether we
> want to use the cpu0 or the big/little implementation, which currently
> have indistinguishable bindings.
Correct and there can be other platform drivers which cannot use
cpufreq-cpu0 (though I am trying to force people to use cpufreq-cpu0
instead of a new driver).
Is something terribly wrong with having a property at 'cpus' node
which can point to the driver we want to use? Like:
cpus {
#address-cells = <1>;
#size-cells = <0>;
scaling-method = "cpufreq-cpu0"
cpu@0 {
};
};
Or if we can reuse compatibility string some way.
[Copying mail from Mike]
On 15 May 2014 02:46, Mike Turquette wrote:
> The hardware property that matters for cpufreq-cpu0 users is that a
> multi-core CPU uses a single clock input to scale frequency across all
> of the cores in that cluster. So an accurate description is:
>
> scaling-method = "clock-ganged"; //hardware-people-speak
>
> Or,
>
> scaling-method = "clock-shared"; //software-people-speak
>
> Versus independently scalable CPUs in an SMP cluster:
>
> scaling-method = "independent"; //x86, Krait, etc.
>
> Or perhaps instead of "independent" at the parent "cpus" node we would
> put the following in each cpu@N node:
>
> scaling-method = "clock";
>
> Or "psci" or "acpi" or whatever.
>
> Thought exercise: for Hyperthreaded(tm) CPUs with 2 virtual cores for
> every hard CPU (and multiple CPUs in a cluster):
>
> scaling-method = "paired";
>
> Or more simply, "hyperthreaded".
Probably we have mixed both the problems. We have two problems to
solve:
- Identifying which driver to probe for a platform, earlier explanation
I tried to gave were around that..
- Identifying if clocks are shared between CPUs? If yes which ones?
Probably Mike's suggestions were around this second problem, but
I still couldn't make out which CPUs share clock line from his
examples.
Please see if we can close this thread soon... Few platforms are waiting
to reuse cpufreq-cpu0 :)
--
viresh
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCHv2 0/3] Power-domain clk handling
This patch series for clock handling in power domain is re-send for merging after rebasing onto latest linux-samsung.git, for-next branch. Original series and discussion can be found here: https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31550.html Arun Kumar K (2): clk: exynos5420: Add IDs for clocks used in PD mfc ARM: dts: Add clock property for mfc_pd in 5420 Prathyush K (1): ARM: EXYNOS: Add support for clock handling in power domain .../bindings/arm/exynos/power_domain.txt | 20 +++ arch/arm/boot/dts/exynos5420.dtsi |3 + arch/arm/mach-exynos/pm_domains.c | 61 +++- drivers/clk/samsung/clk-exynos5420.c |6 +- include/dt-bindings/clock/exynos5420.h |2 + 5 files changed, 89 insertions(+), 3 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCHv2 1/3] ARM: EXYNOS: Add support for clock handling in power domain
From: Prathyush K
While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk333) gets modified to oscclk
= 0x1, no change in clocks.
The recommended value of SYSCLK_SYS_PWR_REG before power gating any
domain is 0x0. So we must also restore the clocks while powering on a
domain everytime.
This patch adds the framework for getting the required mux and parent clocks
through a power domain device node. With this patch, while powering off
a domain, parent is set to oscclk and while powering back on, its re-set
to the correct parent which is as per the recommended pd on/off
sequence.
Signed-off-by: Prathyush K
Signed-off-by: Andrew Bresticker
Signed-off-by: Arun Kumar K
Signed-off-by: Shaik Ameer Basha
Reviewed-by: Tomasz Figa
---
.../bindings/arm/exynos/power_domain.txt | 20 +++
arch/arm/mach-exynos/pm_domains.c | 61 +++-
2 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..8b4f7b7f 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
- reg: physical base address of the controller and length of memory mapped
region.
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+ devices in this power domain are set to oscclk before power gating
+ and restored back after powering on a domain. This is required for
+ all domains which are powered on and off and not required for unused
+ domains.
+- clock-names: The following clocks can be specified:
+ - oscclk: Oscillator clock.
+ - pclkN, clkN: Pairs of parent of input clock and input clock to the
+ devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+ are supported currently.
+
Node of a device using power domains must have a samsung,power-domain property
defined with a phandle to respective power domain.
@@ -19,6 +31,14 @@ Example:
reg = <0x10023C00 0x10>;
};
+ mfc_pd: power-domain@10044060 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x10044060 0x20>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+ <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "pclk0", "clk0";
+ };
+
Example of the node using power domain:
node {
diff --git a/arch/arm/mach-exynos/pm_domains.c
b/arch/arm/mach-exynos/pm_domains.c
index bcd8dcf..41f064b 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -24,6 +25,8 @@
#define INT_LOCAL_PWR_EN 0x7
+#define MAX_CLK_PER_DOMAIN 4
+
/*
* Exynos specific wrapper around the generic power domain
*/
@@ -32,6 +35,9 @@ struct exynos_pm_domain {
char const *name;
bool is_off;
struct generic_pm_domain pd;
+ struct clk *oscclk;
+ struct clk *clk[MAX_CLK_PER_DOMAIN];
+ struct clk *pclk[MAX_CLK_PER_DOMAIN];
};
static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
@@ -44,6 +50,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain,
bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd->base;
+ /* Set oscclk before powering off a domain*/
+ if (!power_on) {
+ int i;
+
+ for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+ if (IS_ERR(pd->clk[i]))
+ break;
+ if (clk_set_parent(pd->clk[i], pd->oscclk))
+ pr_err("%s: error setting oscclk as parent to
clock %d\n",
+ pd->name, i);
+ }
+ }
+
pwr = power_on ? INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
@@ -60,6 +79,20 @@ static int exynos_pd_power(struct generic_pm_domain *domain,
bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+ /* Restore clocks after powering on a domain*/
+ if (power_on) {
+ int i;
+
+ for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
+ if (IS_ERR(pd->clk[i]))
+ break;
+ if (clk_set_parent(pd->clk[i], pd->pclk[i]))
+ pr_err("%s: error setting paren
[RESEND PATCHv2 2/3] clk: exynos5420: Add IDs for clocks used in PD mfc
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K
Signed-off-by: Shaik Ameer Basha
Acked-by: Tomasz Figa
---
drivers/clk/samsung/clk-exynos5420.c |6 --
include/dt-bindings/clock/exynos5420.h |2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7ee..f74f882f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
- MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+ MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+ SRC_TOP4, 28, 1),
MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP11, 12, 1),
MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
- MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+ SRC_TOP11, 28, 1),
MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
SRC_TOP12, 4, 1),
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 97dcb89..3fc08ff 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -203,6 +203,8 @@
#define CLK_MOUT_G3D 641
#define CLK_MOUT_VPLL 642
#define CLK_MOUT_MAUDIO0 643
+#define CLK_MOUT_USER_ACLK333 644
+#define CLK_MOUT_SW_ACLK333645
/* divider clocks */
#define CLK_DOUT_PIXEL 768
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCHv2 3/3] ARM: dts: Add clock property for mfc_pd in 5420
Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K
Signed-off-by: Shaik Ameer Basha
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/exynos5420.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 79e9119..1595722 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -260,6 +260,9 @@
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+ <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "pclk0", "clk0";
};
disp_pd: power-domain@100440C0 {
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 3/3] clk: samsung: exynos5420: Setup clocks before system suspend
Hi Kukjin, On Mon, Jun 30, 2014 at 11:28 PM, Tomasz Figa wrote: > Hi Vikas, Abhilash, > > On 26.06.2014 13:12, Vikas Sajjan wrote: >> Prior to suspending the system, we need to ensure that certain >> clock source and gate registers are unmasked. >> >> while at it, add these clks to save/restore list also. >> >> Signed-off-by: Vikas Sajjan >> Signed-off-by: Abhilash Kesavan >> --- >> drivers/clk/samsung/clk-exynos5420.c | 29 + >> 1 file changed, 29 insertions(+) > > Looks good. Will apply. > Can you apply this patch. > Best regards, > Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
On Mon, Jul 7, 2014 at 10:53 AM, Seungwon Jeon wrote:
> On Fri, July 04, 2014, Seungwon Jeon wrote:
>> On Tue, July 01, 2014. Yuvaraj Kumar wrote:
>> > On Fri, Jun 27, 2014 at 4:48 PM, Seungwon Jeon
>> > wrote:
>> > > Hi Yuvaraj,
>> > >
>> > > On Fri, June 27, 2014, Yuvaraj Kumar wrote:
>> > >> On Thu, Jun 26, 2014 at 10:20 PM, Doug Anderson
>> > >> wrote:
>> > >> > Seungwon,
>> > >> >
>> > >> > On Thu, Jun 26, 2014 at 3:41 AM, Seungwon Jeon
>> > >> > wrote:
>> > >> >> On Thu, June 26, 2014, Doug Anderson wrote:
>> > >> >>> Seungwon,
>> > >> >>>
>> > >> >>> On Wed, Jun 25, 2014 at 6:08 AM, Seungwon Jeon
>> > >> >>> wrote:
>> > >> >>> > On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
>> > >> >>> >> Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
>> > >> >>> >>
>> > >> >>> >> From: Doug Anderson
>> > >> >>> >>
>> > >> >>> >> For UHS cards we need the ability to switch voltages from 3.3V to
>> > >> >>> >> 1.8V. Add support to the dw_mmc driver to handle this. Note
>> > >> >>> >> that
>> > >> >>> >> dw_mmc needs a little bit of extra code since the interface
>> > >> >>> >> needs a
>> > >> >>> >> special bit programmed to the CMD register while CMD11 is
>> > >> >>> >> progressing.
>> > >> >>> >> This means adding a few extra states to the state machine to
>> > >> >>> >> track.
>> > >> >>> >
>> > >> >>> > Overall new additional states makes it complicated.
>> > >> >>> > Can we do that in other way?
>> > >> >>>
>> > >> >>> That was the best I was able to figure out when I thought this
>> > >> >>> through. If you have ideas for doing it another way I'd imagine
>> > >> >>> that
>> > >> >>> Yuvaraj would be happy to take your feedback.
>> > >> >> Let's clean up SDMMC_CMD_VOLT_SWITCH.
>> > >> >> In turn, we may remove state-handling simply.
>> > >> >>
>> > >> >>>
>> > >> >>>
>> > >> >>> >> Signed-off-by: Doug Anderson
>> > >> >>> >> Signed-off-by: Yuvaraj Kumar C D
>> > >> >>> >>
>> > >> >>> >> ---
>> > >> >>> >> drivers/mmc/host/dw_mmc.c | 145
>> > >> >>> >> +---
>> > >> >>> >> drivers/mmc/host/dw_mmc.h |5 +-
>> > >> >>> >> include/linux/mmc/dw_mmc.h |2 +
>> > >> >>> >> 3 files changed, 142 insertions(+), 10 deletions(-)
>> > >> >>> >>
>> > >> >>> >> diff --git a/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> b/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> index e034bce..38eb548 100644
>> > >> >>> >> --- a/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> +++ b/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> @@ -29,6 +29,7 @@
>> > >> >>> >> #include
>> > >> >>> >> #include
>> > >> >>> >> #include
>> > >> >>> >> +#include
>> > >> >>> >> #include
>> > >> >>> >> #include
>> > >> >>> >> #include
>> > >> >>> >> @@ -235,10 +236,13 @@ err:
>> > >> >>> >> }
>> > >> >>> >> #endif /* defined(CONFIG_DEBUG_FS) */
>> > >> >>> >>
>> > >> >>> >> +static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32
>> > >> >>> >> arg);
>> > >> >>> >> +
>> > >> >>> >> static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct
>> > >> >>> >> mmc_command *cmd)
>> > >> >>> >> {
>> > >> >>> >> struct mmc_data *data;
>> > >> >>> >> struct dw_mci_slot *slot = mmc_priv(mmc);
>> > >> >>> >> + struct dw_mci *host = slot->host;
>> > >> >>> >> const struct dw_mci_drv_data *drv_data =
>> > >> >>> >> slot->host->drv_data;
>> > >> >>> >> u32 cmdr;
>> > >> >>> >> cmd->error = -EINPROGRESS;
>> > >> >>> >> @@ -254,6 +258,32 @@ static u32 dw_mci_prepare_command(struct
>> > >> >>> >> mmc_host *mmc, struct
>> > mmc_command
>> > >> >>> *cmd)
>> > >> >>> >> else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
>> > >> >>> >> cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
>> > >> >>> >>
>> > >> >>> >> + if (cmd->opcode == SD_SWITCH_VOLTAGE) {
>> > >> >>> >> + u32 clk_en_a;
>> > >> >>> >> +
>> > >> >>> >> + /* Special bit makes CMD11 not die */
>> > >> >>> >> + cmdr |= SDMMC_CMD_VOLT_SWITCH;
>> > >> >>> >> +
>> > >> >>> >> + /* Change state to continue to handle CMD11
>> > >> >>> >> weirdness */
>> > >> >>> >> + WARN_ON(slot->host->state != STATE_SENDING_CMD);
>> > >> >>> >> + slot->host->state = STATE_SENDING_CMD11;
>> > >> >>> >> +
>> > >> >>> >> + /*
>> > >> >>> >> + * We need to disable clock stop while doing
>> > >> >>> >> voltage switch
>> > >> >>> >> + * according to 7.4.1.2 Voltage Switch Normal
>> > >> >>> >> Scenario.
>> > >> >>> >> + *
>> > >> >>> >> + * It's assumed that by the next time the CLKENA
>> > >> >>> >> is updated
>> > >> >>> >> + * (when we set the clock next) that the voltage
>> > >> >>> >> change will
>> > >> >>> >> + * be over, so we don't bother setting any bits to
>> > >> >>> >> synchronize
>> > >> >>> >> + * with dw_mci_setup_bus().
>> > >> >>> >> + */
>> > >> >>> >> + clk_en_a = mci_readl(host, CLKENA);
Re: [GIT PULL] Samsung fixes-2 for v3.16
On Mon, Jul 7, 2014 at 4:11 PM, Kukjin Kim wrote: > The following changes since commit 4c834452aad01531db949414f94f817a86348d59: > > Linux 3.16-rc3 (2014-06-29 14:11:36 -0700) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git > tags/samsung-fixes-2 > > for you to fetch changes up to 35e75645f16c86918f26df1bfc2c24ad8ebb5a17: > > ARM: EXYNOS: Update secondary boot addr for secure mode (2014-07-08 > 08:03:49 +0900) Merged. -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] phy: Kconfig: Re-organize Exynos USB 2.0 PHY configs
On Mon, Jun 30, 2014 at 2:26 PM, Sachin Kamat wrote: > Since the USB 2.0 PHYs are required only with EHCI/OHCI USB drivers, > make it depend on them and default to ARCH_EXYNOS as they are meant > for Exynos platforms. Also, make the sub-drivers silent options enabling > them based on the SoC platforms that they are meant to work with. This > will make life easier for end users who do not have any way knowing the > dependencies. > > Signed-off-by: Sachin Kamat > --- > drivers/phy/Kconfig | 35 +++ > 1 file changed, 11 insertions(+), 24 deletions(-) > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 16a2f067c242..9aab5dfb0adf 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -122,43 +122,30 @@ config PHY_SUN4I_USB > > config PHY_SAMSUNG_USB2 > tristate "Samsung USB 2.0 PHY driver" > + depends on USB_EHCI_EXYNOS || USB_OHCI_EXYNOS > select GENERIC_PHY > select MFD_SYSCON > + default ARCH_EXYNOS > help > Enable this to support the Samsung USB 2.0 PHY driver for Samsung > - SoCs. This driver provides the interface for USB 2.0 PHY. Support > for > - particular SoCs has to be enabled in addition to this driver. Number > - and type of supported phys depends on the SoC. > + SoCs. This driver provides the interface for USB 2.0 PHY. Support > + for particular PHYs will be enabled based on the SoC type in > addition > + to this driver. > > config PHY_EXYNOS4210_USB2 > - bool "Support for Exynos 4210" > + bool > depends on PHY_SAMSUNG_USB2 > - depends on CPU_EXYNOS4210 > - help > - Enable USB PHY support for Exynos 4210. This option requires that > - Samsung USB 2.0 PHY driver is enabled and means that support for > this > - particular SoC is compiled in the driver. In case of Exynos 4210 > four > - phys are available - device, host, HSIC0 and HSIC1. > + default CPU_EXYNOS4210 > > config PHY_EXYNOS4X12_USB2 > - bool "Support for Exynos 4x12" > + bool > depends on PHY_SAMSUNG_USB2 > - depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) > - help > - Enable USB PHY support for Exynos 4x12. This option requires that > - Samsung USB 2.0 PHY driver is enabled and means that support for > this > - particular SoC is compiled in the driver. In case of Exynos 4x12 > four > - phys are available - device, host, HSIC0 and HSIC1. > + default SOC_EXYNOS4212 || SOC_EXYNOS4412 > > config PHY_EXYNOS5250_USB2 > - bool "Support for Exynos 5250" > + bool > depends on PHY_SAMSUNG_USB2 > - depends on SOC_EXYNOS5250 > - help > - Enable USB PHY support for Exynos 5250. This option requires that > - Samsung USB 2.0 PHY driver is enabled and means that support for > this > - particular SoC is compiled in the driver. In case of Exynos 5250 > four > - phys are available - device, host, HSIC0 and HSIC. > + default SOC_EXYNOS5250 || SOC_EXYNOS5420 > > config PHY_EXYNOS5_USBDRD > tristate "Exynos5 SoC series USB DRD PHY driver" > -- > 1.7.9.5 Kishon, Any comments on these patches? -- Regards, Sachin. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 07/08/2014 05:04 AM, Kukjin Kim wrote: > On 07/01/14 20:59, Tushar Behera wrote: >> On 06/27/2014 08:18 PM, Kevin Hilman wrote: >>> On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilman >>> wrote: On Thu, Jun 26, 2014 at 8:38 PM, Tushar Behera wrote: > Would you please provide me the environment setting of your u-boot? > U-boot environment on my board has been over-written, I would like to > set it same as yours and try to reproduce the issue at my end. With > only > 'sound init', I don't seem to hit this issue anymore. Attached is a full boot log using v3.16-rc2 with my patch adding CLK_IGNORE_UNUSED to mau_epll and Doug's aclk66_peric patch. In the boot log, you'll see the output of 'printenv' inside u-boot where the environment is dumped. >>> >>> Oops, I sent you a boot log for the octa board. Here's the one for >>> peach-pi with the same kernel (built with upstream exynos_defconfig) >>> >>> Kevin >>> >> >> The u-boot version is a little different on my Peach-Pi as compared to >> the market release version. Not sure if that is making any difference. >> >> Peach # version >> >> U-Boot 2013.04 (Feb 13 2014 - 16:35:03) for Peach >> armv7a-cros-linux-gnueabi-gcc.real (4.8.1_cos_gg_feea904_4.8.1-r66) >> 4.8.x-google 20130905 (prerelease) >> GNU ld (binutils-2.22_cos_gg_2) 2.22 >> > > Note that I've applied this only from this series so I'm not sure how > much the problem can be solved...any updates for 1/3 and 3/3? > > - Kukjin Thanks for applying 2/3. I am working on 1/3 to see if we are following the right approach to fix Kevin's issue (unfortunately, I am not hitting the bug on my board ATM). 3/3 has already been merged through a different patchset. -- Tushar Behera -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 1/3] of: Split early_init_dt_scan into two parts
On 7/1/2014 7:03 PM, Laura Abbott wrote: > Currently, early_init_dt_scan validates the header, sets the > boot params, and scans for chosen/memory all in one function. > Split this up into two separate functions (validation/setting > boot params in one, scanning in another) to allow for > additional setup between boot params and scanning the memory. > > Signed-off-by: Laura Abbott I haven't heard anything more on this series but the holiday weekend in the US probably affected that. Grant/Rob are you okay with taking this through the devicetree tree if this gets a few more acks or would you rather this go through an ARM tree? Thanks, Laura -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 14/14] ARM: dts: exynos5420: add dsi node
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = <1>;
};
+ dsi@1450 {
+ compatible = "samsung,exynos5410-mipi-dsi";
+ reg = <0x1450 0x1>;
+ interrupts = <0 82 0>;
+ samsung,power-domain = <&disp_pd>;
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+ clock-names = "bus_clk", "pll_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
fimd: fimd@1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 12/14] ARM: dts: exynos5: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- arch/arm/boot/dts/exynos5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608..fdead12 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -87,6 +87,7 @@ reg = <0x1440 0x4>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = <18 4>, <18 5>, <18 6>; + samsung,sysreg = <&sysreg_system_controller>; status = "disabled"; }; -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
include/drm/drm_mipi_dsi.h | 7 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
#include
#include
+#include "exynos_drm_crtc.h"
#include "exynos_drm_drv.h"
/* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct
mipi_dsi_host *host,
return (ret < 0) ? ret : xfer.rx_done;
}
+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+ struct exynos_dsi *dsi = host_to_dsi(host);
+ struct drm_encoder *encoder = dsi->encoder;
+
+ if (dsi->state & DSIM_STATE_ENABLED)
+ exynos_drm_crtc_te_handler(encoder->crtc);
+}
+
static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+ .pass_te = exynos_dsi_host_pass_te,
};
static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal between
+ * MCU and FB to display video images. And the display controller
+ * should trigger to transfer video image at this signal. So the panel
+ * receives the TE IRQ, then calls this function to notify it to the
+ * display controller.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+ void (*pass_te)(struct mipi_dsi_host *host);
};
/**
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 10/14] drm/panel: add S6E3FA0 driver
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/panel/Kconfig | 7 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 ++
3 files changed, 577 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E3FA0
+ tristate "S6E3FA0 DSI command mode panel"
+ depends on DRM && DRM_PANEL
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..66058a7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,569 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER 0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT 0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL 0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM 0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1 0xf0
+#define MCS_GAMMA_UPDATE 0xf7
+#define MCS_KEY_LEV2 0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL 0x15
+
+struct s6e3fa0 {
+ struct device *dev;
+ struct drm_panelpanel;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc*reset_gpio;
+ struct gpio_desc*det_gpio;
+ struct gpio_desc*te_gpio;
+ struct videomodevm;
+
+ unsigned intpower_on_delay;
+ unsigned intreset_delay;
+ unsigned intinit_delay;
+ unsigned intwidth_mm;
+ unsigned intheight_mm;
+
+ unsigned char id;
+ unsigned char vddm;
+ unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+ {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+ {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+ {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+ {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+ {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+ {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+ {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+ {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+ {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+ {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+ {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+ {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+ {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+ {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+ {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x
[PATCH v5 06/14] drm/exynos: fimd: support LCD I80 interface
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
flip request, and implements TE handler to call trigger function.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/Kconfig | 1 +
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
include/video/samsung_fimd.h | 3 +-
3 files changed, 235 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+ select MFD_SYSCON
help
Choose this option if you want to use Exynos FIMD for DRM.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..207872d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -61,6 +63,24 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x) ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
/* FIMD has totally five hardware windows. */
#define WINDOWS_NR 5
@@ -68,10 +88,14 @@
struct fimd_driver_data {
unsigned int timing_base;
+ unsigned int lcdblk_offset;
+ unsigned int lcdblk_vt_shift;
+ unsigned int lcdblk_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+ unsigned int has_vidoutcon:1;
};
static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {
static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+ .lcdblk_offset = 0x210,
+ .lcdblk_vt_shift = 10,
+ .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
};
static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+ .lcdblk_offset = 0x214,
+ .lcdblk_vt_shift = 24,
+ .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+ .has_vidoutcon = 1,
};
struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem*regs;
+ struct regmap *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long irq_flags;
+ u32 vidcon0;
u32 vidcon1;
+ u32 vidout_con;
+ u32 i80ifcon;
+ booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
+ atomic_twin_updated;
+ atomic_ttriggering;
struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
u32 clkdiv;
+ if (ctx->i80_if) {
+ /*
+* The frame done interrupt sho
[PATCH v5 07/14] ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
This patch adds relevant to exynos5410 compatible for exynos5410 / 5420 / 5440 SoCs support. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 33b5730..31036c6 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -1,7 +1,9 @@ Exynos MIPI DSI Master Required properties: - - compatible: "samsung,exynos4210-mipi-dsi" + - compatible: value should be one of the following + "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ + "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.
In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
1 file changed, 135 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 76e34ca..162f74d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
#include
@@ -55,9 +56,12 @@
/* FIFO memory AC characteristic register */
#define DSIM_PLLCTRL_REG 0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
#define DSIM_PHYACCHR_REG 0x54/* D-PHY AC characteristic register */
#define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG 0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c
/* DSIM_STATUS */
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -201,6 +205,24 @@
#define DSIM_PLL_M(x) ((x) << 4)
#define DSIM_PLL_S(x) ((x) << 1)
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
#define DSI_MAX_BUS_WIDTH 4
#define DSI_NUM_VIRTUAL_CHANNELS 4
#define DSI_TX_FIFO_SIZE 2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_INITIALIZED BIT(1)
#define DSIM_STATE_CMD_LPM BIT(2)
+struct exynos_dsi_driver_data {
+ unsigned int plltmr_reg;
+
+ unsigned int has_freqband:1;
+};
+
struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {
spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+ struct exynos_dsi_driver_data *driver_data;
};
#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+ .plltmr_reg = 0x50,
+ .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+ .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+ { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+ { .compatible = "samsung,exynos5410-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+ { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+ return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
{
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct
exynos_dsi *dsi,
static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
{
- static const unsigned long freq_bands[] = {
- 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
- 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
- 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
- 770 * MHZ, 870 * MHZ, 950 * MHZ,
- };
+ struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
- int timeout, band;
+ int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
"failed to find PLL PMS for requested frequency\n");
return -EFAULT;
}
+ dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p,
[PATCH v5 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties
In case of using MIPI DSI based I80 interface panel, the relevant registers should be set. So this patch adds relevant DT bindings. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- .../devicetree/bindings/video/samsung-fimd.txt | 28 ++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index 2dad41b..59ff61e 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -44,6 +44,34 @@ Optional Properties: - display-timings: timing settings for FIMD, as described in document [1]. Can be used in case timings cannot be provided otherwise or to override timings provided by the panel. +- samsung,sysreg: handle to syscon used to control the system registers +- i80-if-timings: timing configuration for lcd i80 interface support. + - cs-setup: clock cycles for the active period of address signal is enabled + until chip select is enabled. + If not specified, the default value(0) will be used. + - wr-setup: clock cycles for the active period of CS signal is enabled until + write signal is enabled. + If not specified, the default value(0) will be used. + - wr-active: clock cycles for the active period of CS is enabled. + If not specified, the default value(1) will be used. + - wr-hold: clock cycles for the active period of CS is disabled until write + signal is disabled. + If not specified, the default value(0) will be used. + + The parameters are defined as: + +VCLK(internal) __|¯¯|_|¯¯|_|¯¯|_|¯¯|_|¯¯ + ::::: +Address Output --:|::: +Chip Select ¯¯¯|::|¯¯ + | wr-setup+1 || wr-hold+1 | + |<-->||<-->| +Write Enable||¯¯¯ +| wr-active+1| +|<-->| +Video Data -- The device node can contain 'port' child nodes according to the bindings defined in [2]. The following are properties specific to those nodes: -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 00/14] drm/exynos: support LCD I80 interface display
Hi, This series adds LCD I80 interface display support for Exynos DRM driver. The FIMD(display controller) specification describes it as "LCD I80 interface" and the DSI specification describes it as "Command mode interface". This is based on exynos-drm-next branch. The previous patches, RFC: http://www.spinics.net/lists/dri-devel/msg58898.html V1: http://www.spinics.net/lists/dri-devel/msg59291.html V2: http://www.spinics.net/lists/dri-devel/msg59867.html V3: http://www.spinics.net/lists/dri-devel/msg60708.html V4: http://www.spinics.net/lists/dri-devel/msg60943.html Changelog v2: - Fixes typo and removes unnecessary error log (commented by Andrzej Hazda) - Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz) Changelog v3: - Removes generic command mode and command mode display timing interface. - Moves I80 interface timings from panel DT to the FIMD(display controller) DT. Changelog v4: - Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because it was already updated by linux-samsung-soc (commented by Vivek Gautam) Changelog v5: - Fixes FIMD vidcon0 register relevant code - Fixes panel gamma table, disable sequence - Slitely updates for code cleanup Patches 1 and 2 fix trivial bugs. Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface. The MIPI DSI command mode based panel generates Tearing Effect synchronization signal between MCU and FB to display video image, and FIMD should trigger to transfer video image at this signal. So the panel should receive the TE IRQ and call TE handler chains to notify it to the FIMD. Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver which is different from previous Exynos4 SoCs for some registers control. Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED 5.7" LCD drm panel driver. The ohters add DT property nodes to support MIPI DSI command mode. I welcome any comments. Thank you. Best regards YJ YoungJun Cho (14): drm/exynos: dsi: move the EoT packets configuration point drm/exynos: use wait_event_timeout() for safety usage ARM: dts: samsung-fimd: add LCD I80 interface specific properties drm/exynos: add TE handler to support LCD I80 interface drm/exynos: dsi: add pass TE host ops to support LCD I80 interface drm/exynos: fimd: support LCD I80 interface ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs ARM: dts: s6e3fa0: add DT bindings drm/panel: add S6E3FA0 driver ARM: dts: exynos4: add system register property ARM: dts: exynos5: add system register property ARM: dts: exynos5420: add mipi-phy node ARM: dts: exynos5420: add dsi node .../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++ .../devicetree/bindings/video/exynos_dsim.txt | 4 +- .../devicetree/bindings/video/samsung-fimd.txt | 28 + arch/arm/boot/dts/exynos4.dtsi | 1 + arch/arm/boot/dts/exynos5.dtsi | 1 + arch/arm/boot/dts/exynos5420.dtsi | 20 + drivers/gpu/drm/exynos/Kconfig | 1 + drivers/gpu/drm/exynos/exynos_drm_crtc.c | 15 +- drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 + drivers/gpu/drm/exynos/exynos_drm_drv.h| 3 + drivers/gpu/drm/exynos/exynos_drm_dsi.c| 181 ++- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 -- drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 + include/drm/drm_mipi_dsi.h | 7 + include/video/samsung_fimd.h | 3 +- 17 files changed, 1098 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 11/14] ARM: dts: exynos4: add system register property
This patch adds sysreg property to fimd device node which is required to use I80 interface. Signed-off-by: YoungJun Cho Acked-by: Inki Dae Acked-by: Kyungmin Park --- arch/arm/boot/dts/exynos4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index b8ece4b..92ee786 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -608,6 +608,7 @@ clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; samsung,power-domain = <&pd_lcd0>; + samsung,sysreg = <&sys_reg>; status = "disabled"; }; }; -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 09/14] ARM: dts: s6e3fa0: add DT bindings
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+ - compatible: "samsung,s6e3fa0"
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: core voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin
+ - det-gpios: a GPIO spec for the OLED detection pin
+ - te-gpios: a GPIO spec for the TE pin
+ - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+ panel@0 {
+ compatible = "samsung,s6e3fa0";
+ reg = <0>;
+ vdd3-supply = <&vcclcd_reg>;
+ vci-supply = <&vlcd_reg>;
+ reset-gpios = <&gpy7 4 0>;
+ det-gpios = <&gpg0 6 0>;
+ te-gpios = <&gpd1 7 0>;
+
+ display-timings {
+ timings0 {
+ clock-frequency = <0>;
+ hactive = <1080>;
+ vactive = <1920>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <1>;
+ vfront-porch = <1>;
+ vback-porch = <4>;
+ vsync-len = <1>;
+ };
+ };
+ };
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 04/14] drm/exynos: add TE handler to support LCD I80 interface
To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8
drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
drivers/gpu/drm/exynos/exynos_drm_drv.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device
*drm_dev,
return -EPERM;
}
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+ struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
+
+ if (manager->ops->te_handler)
+ manager->ops->te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc,
int zpos);
int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);
+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 06cde45..d4e0726 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -188,6 +188,8 @@ struct exynos_drm_display {
* @win_commit: apply hardware specific overlay data to registers.
* @win_enable: enable hardware specific overlay.
* @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
*/
struct exynos_drm_manager;
struct exynos_drm_manager_ops {
@@ -206,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+ void (*te_handler)(struct exynos_drm_manager *mgr);
};
/*
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 13/14] ARM: dts: exynos5420: add mipi-phy node
This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..0b9d15d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -517,6 +517,12 @@
phy-names = "dp";
};
+ mipi_phy: video-phy@10040714 {
+ compatible = "samsung,s5pv210-mipi-video-phy";
+ reg = <0x10040714 12>;
+ #phy-cells = <1>;
+ };
+
fimd: fimd@1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 01/14] drm/exynos: dsi: move the EoT packets configuration point
This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6302aa6..dad543a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,19 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;
+ /* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;
+ /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
- if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
- reg |= DSIM_EOT_DISABLE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +497,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}
+ if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+ reg |= DSIM_EOT_DISABLE;
+
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 02/14] drm/exynos: use wait_event_timeout() for safety usage
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_crtc.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
if (mode > DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
- wait_event(exynos_crtc->pending_flip_queue,
- atomic_read(&exynos_crtc->pending_flip) == 0);
+ if (!wait_event_timeout(exynos_crtc->pending_flip_queue,
+ !atomic_read(&exynos_crtc->pending_flip),
+ HZ/20))
+ atomic_set(&exynos_crtc->pending_flip, 0);
drm_vblank_off(crtc->dev, exynos_crtc->pipe);
}
@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(&dev->event_lock);
drm_vblank_put(dev, exynos_crtc->pipe);
list_del(&event->base.link);
+ atomic_set(&exynos_crtc->pending_flip, 0);
spin_unlock_irq(&dev->event_lock);
goto out;
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Using s5p-sss hw crypto causes ipsec to break
On Wed, Jun 25, 2014 at 11:35 PM, Herbert Xu wrote: > Sonny Rao wrote: >> Hi, I've been investigating an issue relating to hardware crypto which >> is that when I enable the s5p-sss module for hardware cryptographic >> acceleration on Samsung Exynos SoCs the in-kernel IPSec seems to >> break, although cryptographic operations on filesystems/block devices >> using this driver seem to work fine. >> >> Originally we were looking at an older kernel (3.8 with patches), but >> I've now verified on linux-next from 20140612 (after 3.15) with a few >> additional patches (to enable both s5p-sss and Exynos5420) that this >> is still the case. >> >> It looks like what is happening in the kernel is that IPsec ends up >> with this callstack >> >> esp_output()-> crypto_aead_givencrypt()-> >> crypto_authenc_givencrypt()-> eseqiv_givencrypt() -> >> crypto_ablkcipher_encrypt() >> >> >> which calls into the s5p-sss driver and that is returning -EINPROGRESS >> (or possibly -EBUSY), and that is passed all the way back up the call >> stack and that seems to be treated as an error condition by the ipsec >> stack. >> >> For example esp_output does this: >> >> err = crypto_aead_givencrypt(req); >>if (err == -EINPROGRESS) >>goto error; >> >>if (err == -EBUSY) >>err = NET_XMIT_DROP; >> >> So, I'm not sure how this is supposed to work, or if s5p-sss is doing >> something wrong. > > Something else must be happening because EINPROGRESS is meant to > be handled by xfrm_output_resume (which gets called on the normal > path as well as on the actual resume path). > > So I don't think this is your problem. > > Cheers, Hi Herbert, thanks for the reply. Sorry for the delay in my response, I just got a chance to look at this again with the information you provided. It looks like the driver is rejecting the encryption request, and is calling xfrm_output_resume with -22 (-EINVAL) because in s5p_set_indata() this driver is calling sg_dma_len() on the sg lists from the crypto request and getting back something that isn't a multiple of AES_BLOCK_SIZE, and thus decides that this isn't a valid request. In my particular test, It looks like it's getting a dma size of either 92 or 124 bytes while AES_BLOCK_SIZE is 16 bytes, and neither of those are multiples of 16. I looked into why this was happening and it looks like in eseqiv_givencrypt() we're calling ablkcipher_request_set_crypt() with a value of either 80 or 112 (which is a multiple of AES_BLOCK_SIZE) while reqctx->src->length is 96 or 124. I think this is happening because the sg list associated with the request has been set up for a network transfer, which is of a larger size than what needs to be encrypted due to additional network headers. So, I'm wondering, is it correct for the HW crypto driver to be using this sg list, which is part of the request , or should it somehow be using different sg lists with the proper length for it's DMA operations, or should that be happening somewhere else in the network stack? > -- > Email: Herbert Xu > Home Page: http://gondor.apana.org.au/~herbert/ > PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] ARM: dts: Update the parent for Audss clocks in Exynos5420
On 07/01/14 20:59, Tushar Behera wrote: On 06/27/2014 08:18 PM, Kevin Hilman wrote: On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilman wrote: On Thu, Jun 26, 2014 at 8:38 PM, Tushar Behera wrote: Would you please provide me the environment setting of your u-boot? U-boot environment on my board has been over-written, I would like to set it same as yours and try to reproduce the issue at my end. With only 'sound init', I don't seem to hit this issue anymore. Attached is a full boot log using v3.16-rc2 with my patch adding CLK_IGNORE_UNUSED to mau_epll and Doug's aclk66_peric patch. In the boot log, you'll see the output of 'printenv' inside u-boot where the environment is dumped. Oops, I sent you a boot log for the octa board. Here's the one for peach-pi with the same kernel (built with upstream exynos_defconfig) Kevin The u-boot version is a little different on my Peach-Pi as compared to the market release version. Not sure if that is making any difference. Peach # version U-Boot 2013.04 (Feb 13 2014 - 16:35:03) for Peach armv7a-cros-linux-gnueabi-gcc.real (4.8.1_cos_gg_feea904_4.8.1-r66) 4.8.x-google 20130905 (prerelease) GNU ld (binutils-2.22_cos_gg_2) 2.22 Note that I've applied this only from this series so I'm not sure how much the problem can be solved...any updates for 1/3 and 3/3? - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/6] Various Samsung fixes for v3.16-rc3
On 07/01/14 22:54, Tomasz Figa wrote: Hi, On 24.06.2014 15:57, Tomasz Figa wrote: This series inteds to fix various issues spotted while testing v3.16-rc2. The patches should be reasonably independent from each other and so could be picked to respective trees. See descriptions of individual patches for more information. Tested on Exynos4412-based Trats2 and Exynos4210-based Trats boards. AFAIK there is no need to backport those fixes to stable. Tomasz Figa (6): mmc: sdhci-s3c: Fix local I/O clock gating ARM: EXYNOS: Fix core ID used by platsmp and hotplug code clk: samsung: exynos4: Remove SRC_MASK_ISP gates ARM: SAMSUNG: Restore Samsung PM Debug functionality ARM: EXYNOS: Fix suspend/resume sequencies ARM: EXYNOS: Register cpuidle device only on Exynos4210 and 5250 arch/arm/mach-exynos/exynos.c | 6 ++ arch/arm/mach-exynos/hotplug.c| 10 ++ arch/arm/mach-exynos/platsmp.c| 34 +++--- arch/arm/mach-exynos/pm.c | 20 arch/arm/plat-samsung/Kconfig | 8 +++- arch/arm/plat-samsung/pm-debug.c | 1 + drivers/clk/samsung/clk-exynos4.c | 16 drivers/mmc/host/sdhci-s3c.c | 17 ++--- 8 files changed, 53 insertions(+), 59 deletions(-) Gentle ping. Oops, I missed this fixes from 2nd samsung fixes for 3.16...let me have a look this series today then will send again soon... Thanks, Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: Add sound-card name for Snow/Peach-Pit/Peach-Pi
On 07/05/14 04:31, Mark Brown wrote: On Fri, Jul 04, 2014 at 02:50:52PM +0530, Tushar Behera wrote: Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards. Acked-by: Mark Brown Thanks, applied. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung fixes-2 for v3.16
The following changes since commit 4c834452aad01531db949414f94f817a86348d59: Linux 3.16-rc3 (2014-06-29 14:11:36 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/samsung-fixes-2 for you to fetch changes up to 35e75645f16c86918f26df1bfc2c24ad8ebb5a17: ARM: EXYNOS: Update secondary boot addr for secure mode (2014-07-08 08:03:49 +0900) Samsung fixes-2 for v3.16 - fix the check for SMP configuration with using CONFIG_SMP not just SMP - fix the number of pwm-cells for exynos4 pwm - fix ftrace for exynos_mct - register exynos_mct for stable udely - fix secondary boot addr for secure mode for exynos SoCs Abhilash Kesavan (1): ARM: EXYNOS: Fix the check for non-smp configuration Amit Daniel Kachhap (1): clocksource: exynos_mct: Register the timer for stable udelay Doug Anderson (1): clocksource: exynos_mct: Fix ftrace Jaewon Kim (1): ARM: dts: fix pwm-cells in pwm node for exynos4 Sachin Kamat (1): ARM: EXYNOS: Update secondary boot addr for secure mode arch/arm/boot/dts/exynos4.dtsi | 2 +- arch/arm/mach-exynos/exynos.c| 2 +- arch/arm/mach-exynos/firmware.c | 9 +++-- drivers/clocksource/exynos_mct.c | 20 ++-- 4 files changed, 27 insertions(+), 6 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] Samsung cleanup for S5P SoCs for 3.17
The following changes since commit a497c3ba1d97fc69c1e78e7b96435ba8c2cb42ee: Linux 3.16-rc2 (2014-06-21 19:02:54 -1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/s5p-cleanup for you to fetch changes up to 58595ebd9306691441ccf88973b97d4f8eaa8279: ASoC: Samsung: remove s5pc100 related codes (2014-07-08 07:29:05 +0900) Cleanup S5P SoCs for 3.17 - removing s5p64x0 SoCs and s5pc100 SoC in mainline because no more user and if it is required next time, it will be supported with DT. Kukjin Kim (13): ARM: S5P64X0: no more support S5P6440 and S5P6450 SoCs gpio: samsung: remove s5p64x0 related gpio codes spi: s3c64xx: remove s5p64x0 related spi codes ASoC: samsung: no more support for S5P6440 and S5P6450 SoCs video: fbdev: s3c-fb: remove s5p64x0 related fimd codes serial: samsung: no more support for S5P6440 and S5P6450 SoCs ARM: S5PC100: no more support S5PC100 SoC gpio: samsung: remov s5pc100 related gpio codes spi: s3c64xx: remove s5pc100 related spi codes serial: samsung: no more support for S5PC100 SoC mtd: onenand: remove s5pc100 related onenand codes video: fbdev: s3c-fb: remove s5pc100 related fimd and fb codes ASoC: Samsung: remove s5pc100 related codes Documentation/arm/Samsung/Overview.txt | 11 - .../arm/Samsung/clksrc-change-registers.awk|1 - .../devicetree/bindings/spi/spi-samsung.txt|1 - .../devicetree/bindings/video/samsung-fimd.txt |2 - arch/arm/Kconfig | 43 +- arch/arm/Makefile |2 - arch/arm/configs/s5p64x0_defconfig | 68 - arch/arm/configs/s5pc100_defconfig | 49 - arch/arm/mach-s5p64x0/Kconfig | 102 -- arch/arm/mach-s5p64x0/Makefile | 36 - arch/arm/mach-s5p64x0/Makefile.boot|2 - arch/arm/mach-s5p64x0/clock-s5p6440.c | 632 - arch/arm/mach-s5p64x0/clock-s5p6450.c | 701 -- arch/arm/mach-s5p64x0/clock.c | 236 arch/arm/mach-s5p64x0/clock.h | 38 - arch/arm/mach-s5p64x0/common.c | 490 --- arch/arm/mach-s5p64x0/common.h | 56 - arch/arm/mach-s5p64x0/dev-audio.c | 176 --- arch/arm/mach-s5p64x0/dma.c| 128 -- arch/arm/mach-s5p64x0/i2c.h| 16 - arch/arm/mach-s5p64x0/include/mach/debug-macro.S | 32 - arch/arm/mach-s5p64x0/include/mach/dma.h | 26 - arch/arm/mach-s5p64x0/include/mach/gpio.h | 132 -- arch/arm/mach-s5p64x0/include/mach/hardware.h | 18 - arch/arm/mach-s5p64x0/include/mach/irqs.h | 148 --- arch/arm/mach-s5p64x0/include/mach/map.h | 96 -- arch/arm/mach-s5p64x0/include/mach/pm-core.h | 119 -- arch/arm/mach-s5p64x0/include/mach/regs-clock.h| 98 -- arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | 68 - arch/arm/mach-s5p64x0/include/mach/regs-irq.h | 18 - arch/arm/mach-s5p64x0/irq-pm.c | 98 -- arch/arm/mach-s5p64x0/mach-smdk6440.c | 280 arch/arm/mach-s5p64x0/mach-smdk6450.c | 299 - arch/arm/mach-s5p64x0/pm.c | 202 --- arch/arm/mach-s5p64x0/setup-fb-24bpp.c | 29 - arch/arm/mach-s5p64x0/setup-i2c0.c | 38 - arch/arm/mach-s5p64x0/setup-i2c1.c | 38 - arch/arm/mach-s5p64x0/setup-sdhci-gpio.c | 104 -- arch/arm/mach-s5p64x0/setup-spi.c | 38 - arch/arm/mach-s5pc100/Kconfig | 81 -- arch/arm/mach-s5pc100/Makefile | 32 - arch/arm/mach-s5pc100/Makefile.boot|2 - arch/arm/mach-s5pc100/clock.c | 1361 arch/arm/mach-s5pc100/common.c | 255 arch/arm/mach-s5pc100/common.h | 30 - arch/arm/mach-s5pc100/dev-audio.c | 239 arch/arm/mach-s5pc100/dma.c| 130 -- arch/arm/mach-s5pc100/include/mach/debug-macro.S | 39 - arch/arm/mach-s5pc100/include/mach/dma.h | 26 - arch/arm/mach-s5pc100/include/mach/entry-macro.S | 19 - arch/arm/mach-s5pc100/include/mach/gpio.h | 144 --- arch/arm/mach-s5pc100/include/mach/hardware.h | 14 - arch/arm/mach-s5pc100/include/mach/irqs.h | 115 -- arch/arm/mach-s5pc100/include/mach/map.h | 137 -- arch/arm/mach-s5pc100/include/mach/regs-clock.h| 80 -- arch/arm/mach-s5pc100/include/mach/regs-gpio.h | 38 - arch/arm/mach-s5pc100/inclu
Re: [PATCH v6 2/6] ARM: EXYNOS: Move cpufreq and cpuidle device registration to init_machine
On 07/07/14 12:50, Pankaj Dubey wrote:
As exynos_cpuidle_init and exynos_cpufreq_init function have just one lines
of code for registering platform devices. We can move these lines to
exynos_dt_machine_init and delete exynos_cpuidle_init and exynos_cpufreq_init
function. This will help in reducing lines of code in exynos.c, making it
more cleaner.
Suggested-by: Tomasz Figa
Signed-off-by: Pankaj Dubey
Reviewed-by: Tomasz Figa
---
arch/arm/mach-exynos/exynos.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index ff60b4c..47170eb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -171,19 +171,6 @@ static struct platform_device exynos_cpuidle = {
.id= -1,
};
-void __init exynos_cpuidle_init(void)
-{
- if (soc_is_exynos5440())
- return;
-
- platform_device_register(&exynos_cpuidle);
-}
-
-void __init exynos_cpufreq_init(void)
-{
- platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
-}
-
void __iomem *sysram_base_addr;
void __iomem *sysram_ns_base_addr;
@@ -300,10 +287,11 @@ static void __init exynos_dt_machine_init(void)
if (!IS_ENABLED(CONFIG_SMP))
exynos_sysram_init();
- if (!of_machine_is_compatible("samsung,exynos5420"))
- exynos_cpuidle_init();
+ if (!of_machine_is_compatible("samsung,exynos5420") ||
+ !of_machine_is_compatible("samsung,exynos5440"))
+ platform_device_register(&exynos_cpuidle);
- exynos_cpufreq_init();
+ platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
This cannot be applied in my tree now
- Kukjin
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 0/6] Cleanup patches for mach-exynos
On 07/07/14 12:50, Pankaj Dubey wrote: This series is doing code cleanup under arch/arm/mach-exynos. These patches have been separated from main exynos pmu v4 patch posted here [1]. [1]: https://lkml.org/lkml/2014/5/10/29 Changes Since v5: - Rebased on latest for-next of Kukjin Kim's tree. - Using of_machine_is_compatible instead of soc_is_exynos in patch 2. Changes Since v4: - Rebased on latest for-next of Kukjin Kim's tree. - Removing file path comment from mach-exynos/headsmp.S also. - Removed signed-off-by of Young-Gun Jang, as this id is no more valid. Taking ownership of all his patches. - Separated these patches from main exynos pmu v4 patch series as suggested by Tomasz Figa. Changes Since v3: - Addressed build fail issue in exynos.c as reported by Sachin Kamat. - Rebased on top of Sysram patches by Sachin Kamat. Changes Since v2: - Rebased on top of Daniel Lezcano's Exynos cpuidle refactor patches. - Removed exynos_cpuidle_init and exynos_cpufreq_init code as suggested by Tomasz Figa. Changes Since v1: - Rebased on latest for-next of Kukjin Kim's tree. - Added patch: "Make exynos machine_ops as static". For making more cleanup in "mach-exynos/common.h" as suggested by Tomasz Figa. - Addressed comments of Tomasz Figa for cleaning "mach-exynos/common.h". - Updated patch: Remove file path from comment section As suggested by Michel Simek, instead of updating file path lets remove them from each file under "mach-exynos". Even though Kukjin pointed out that there is similar patch pending from Sachin/Tushar but since I could not find I have included this here. If I have missed something please point to any existing such patch. - Added patch: Remove "linux/bug.h" from pmu.c. - Added patch: Move "mach/map.h" inclusion from regs-pmu.h to platsmp.c Pankaj Dubey (6): ARM: EXYNOS: Make exynos machine_ops as static ARM: EXYNOS: Move cpufreq and cpuidle device registration to init_machine ARM: EXYNOS: Move SYSREG definition into sys-reg specific file ARM: EXYNOS: Remove file path from comment section ARM: EXYNOS: Remove regs-pmu.h header dependency from pm_domain ARM: EXYNOS: Remove "linux/bug.h" from pmu.c arch/arm/mach-exynos/common.h |8 arch/arm/mach-exynos/exynos.c | 27 --- arch/arm/mach-exynos/headsmp.S |1 - arch/arm/mach-exynos/hotplug.c |3 +-- arch/arm/mach-exynos/include/mach/map.h|3 +-- arch/arm/mach-exynos/include/mach/memory.h |3 +-- arch/arm/mach-exynos/platsmp.c |3 +-- arch/arm/mach-exynos/pm.c |1 + arch/arm/mach-exynos/pm_domains.c |8 arch/arm/mach-exynos/pmu.c |1 - arch/arm/mach-exynos/regs-pmu.h|4 arch/arm/mach-exynos/regs-sys.h| 22 ++ 12 files changed, 39 insertions(+), 45 deletions(-) create mode 100644 arch/arm/mach-exynos/regs-sys.h OK, looks good to me, I think we don't need 4/6 patch though :-) I've applied this whole series, thanks. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/17] pwm: samsung: remove s5p64x0 related pwm codes
On 07/04/14 17:10, Tomasz Figa wrote:
Hi Kukjin,
Tomasz,
On 30.06.2014 23:32, Kukjin Kim wrote:
This patch removes supporting s5p64x0 related pwm codes because of
no more support for S5P6440 and S5P6450 SoCs. And this patch changes
the name of s5p6440-pwm to exynos-pwm instead.
Signed-off-by: Kukjin Kim
Cc: Thierry Reding
---
Documentation/devicetree/bindings/pwm/pwm-samsung.txt |1 -
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
drivers/clocksource/samsung_pwm_timer.c | 13 -
drivers/pwm/pwm-samsung.c |5 ++---
4 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
index 5538de9..43925d3 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
@@ -11,7 +11,6 @@ Required properties:
- compatible : should be one of following:
samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs
samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs
-samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs
samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210,
Exynos4210 rev0 SoCs
samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210,
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..0ca26e0 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -461,7 +461,7 @@
};
pwm@139D {
- compatible = "samsung,s5p6440-pwm";
+ compatible = "samsung,exynos4210-pwm";
There is a reason to use a different compatible string for Exynos4210
rev0. The PWM block is used as a timer there, while on newer revs MCT is
used. Sorry, but I have to NAK this patch.
I remember why exynos4210-universal_c210 uses PWM...OK.
As I explained in my reply to patch 11/17, I'd suggest keeping the PWM
drivers as is, because there is no need to remove support for DT
compatible strings.
OK, let me remove pwm related patches in this series but I think need to
update the compatible strings, at least remove non-support SoC in doc?...
Thanks,
Kukjin
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 00/10] drm: exynos: few patches to enhance bridge chip support
Hi, On Wed, Jul 2, 2014 at 10:19 PM, Andreas Färber wrote: > With these 10 patches applied on top of my dt on top of kgene's tree, > the last U-Boot screen stays visible for ~50 seconds, then the screen > goes blank, and I can ssh in some time later. > If I comment out the dp-controller node again, it takes long for the > kernel boot to graphically proceed but works okay then. > In both cases there's a gap of ~2900 seconds visible in dmesg. I would have imagined that this was fixed by (1d80415 clocksource: exynos_mct: Don't reset the counter during boot and resume). ...that should also fix a long delay at bootup (delay was based on how much time you spent in U-Boot). -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 00/10] drm: exynos: few patches to enhance bridge chip support
Andreas, On Fri, Jul 4, 2014 at 6:06 AM, Andreas Färber wrote: >> Doug can help you in adding changes required for tps65090. > > Hm, Doug had pointed out an issue with tps65090 in my v1, so I dropped > it: https://patchwork.kernel.org/patch/4397321/ tps65090 on Spring is nowhere near obvious due to the EC commands that were available during the Spring timeframe. See http://crbug.com/391797 for some details. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] phy: phy-samsung-usb2: Change phy power on/power off sequence
On Tue, Jul 1, 2014 at 4:15 PM, Kamil Debski wrote: > The Exynos4412 USB 2.0 PHY hardware differs from the description provided > in the documentation. Some register bits have different function. This > patch fixes the defines of register bits and changes the way how phys are > powered on and off. > > Signed-off-by: Kamil Debski Tested on ODROID-U2 with the internal LAN (which is a USB device), and an external USB mouse connected via the internal USB hub. Tested-by: Daniel Drake -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/9] s5p-jpeg: add chroma subsampling adjustment for Exynos3250
Take into account limitations specific to the Exynos3250 SoC,
regarding setting chroma subsampling control value.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 59 +--
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 1ef004b..283249d 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -1603,36 +1603,53 @@ static int s5p_jpeg_g_volatile_ctrl(struct v4l2_ctrl
*ctrl)
return 0;
}
-static int s5p_jpeg_try_ctrl(struct v4l2_ctrl *ctrl)
+static int s5p_jpeg_adjust_subs_ctrl(struct s5p_jpeg_ctx *ctx, int *ctrl_val)
{
- struct s5p_jpeg_ctx *ctx = ctrl_to_ctx(ctrl);
- unsigned long flags;
- int ret = 0;
-
- spin_lock_irqsave(&ctx->jpeg->slock, flags);
-
- if (ctrl->id == V4L2_CID_JPEG_CHROMA_SUBSAMPLING) {
- if (ctx->jpeg->variant->version == SJPEG_S5P)
- goto error_free;
+ switch (ctx->jpeg->variant->version) {
+ case SJPEG_S5P:
+ return 0;
+ case SJPEG_EXYNOS3250:
+ /*
+* The exynos3250 device can produce JPEG image only
+* of 4:4:4 subsampling when given RGB32 source image.
+*/
+ if (ctx->out_q.fmt->fourcc == V4L2_PIX_FMT_RGB32)
+ *ctrl_val = 0;
+ break;
+ case SJPEG_EXYNOS4:
/*
* The exynos4x12 device requires input raw image fourcc
* to be V4L2_PIX_FMT_GREY if gray jpeg format
* is to be set.
*/
if (ctx->out_q.fmt->fourcc != V4L2_PIX_FMT_GREY &&
- ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY) {
- ret = -EINVAL;
- goto error_free;
- }
- /*
-* The exynos4x12 device requires resulting jpeg subsampling
-* not to be lower than the input raw image subsampling.
-*/
- if (ctx->out_q.fmt->subsampling > ctrl->val)
- ctrl->val = ctx->out_q.fmt->subsampling;
+ *ctrl_val == V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY)
+ return -EINVAL;
+ break;
}
-error_free:
+ /*
+* The exynos4x12 and exynos3250 devices require resulting
+* jpeg subsampling not to be lower than the input raw image
+* subsampling.
+*/
+ if (ctx->out_q.fmt->subsampling > *ctrl_val)
+ *ctrl_val = ctx->out_q.fmt->subsampling;
+
+ return 0;
+}
+
+static int s5p_jpeg_try_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct s5p_jpeg_ctx *ctx = ctrl_to_ctx(ctrl);
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctx->jpeg->slock, flags);
+
+ if (ctrl->id == V4L2_CID_JPEG_CHROMA_SUBSAMPLING)
+ ret = s5p_jpeg_adjust_subs_ctrl(ctx, &ctrl->val);
+
spin_unlock_irqrestore(&ctx->jpeg->slock, flags);
return ret;
}
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/9] Documentation: devicetree: Document sclk-jpeg clock for exynos3250 SoC
JPEG IP on Exynos3250 SoC requires enabling two clock gates for its operation. This patch documents this requirement. Signed-off-by: Jacek Anaszewski Signed-off-by: Kyungmin Park Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: devicet...@vger.kernel.org --- .../bindings/media/exynos-jpeg-codec.txt |9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt index 937b755..20cd150 100644 --- a/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt +++ b/Documentation/devicetree/bindings/media/exynos-jpeg-codec.txt @@ -3,9 +3,12 @@ Samsung S5P/EXYNOS SoC series JPEG codec Required properties: - compatible : should be one of: - "samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg"; + "samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg", + "samsung,exynos3250-jpeg"; - reg : address and length of the JPEG codec IP register set; - interrupts : specifies the JPEG codec IP interrupt; - clocks : should contain the JPEG codec IP gate clock specifier, from the - common clock bindings; -- clock-names : should contain "jpeg" entry. + common clock bindings; for Exynos3250 SoC special clock gate + should be defined as the second element of the clocks array +- clock-names : should contain "jpeg" entry and additionally "sclk-jpeg" entry + for Exynos3250 SoC -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 9/9] ARM: dts: exynos3250: add JPEG codec device node
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..351871a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -206,6 +206,18 @@
interrupts = <0 240 0>;
};
+ jpeg-codec@1183 {
+ compatible = "samsung,exynos3250-jpeg";
+ reg = <0x1183 0x1000>;
+ interrupts = <0 171 0>;
+ clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
+ clock-names = "jpeg", "sclk-jpeg";
+ samsung,power-domain = <&pd_cam>;
+ assigned-clock-parents = <&cmu CLK_MOUT_CAM_BLK &cmu
CLK_DIV_MPLL_PRE>,
+<&cmu CLK_SCLK_JPEG &cmu>;
+ assigned-clock-rates = <&cmu CLK_SCLK_JPEG 15000>;
+ };
+
mshc_0: mshc@1251 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x1251 0x1000>;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/9] s5p-jpeg: Prevent erroneous downscaling for Exynos3250 SoC
JPEG codec on Exynos3250 SoC produces broken raw image if
a JPEG is decoded to YUV420 format and downscaling by
more then 2 is applied. Prevent this by asserting downscale
ratio to 2.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 2491ef8..1ef004b 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -1317,12 +1317,16 @@ static int exynos4_jpeg_get_output_buffer_size(struct
s5p_jpeg_ctx *ctx,
return w * h * fmt_depth >> 3;
}
+static int exynos3250_jpeg_try_downscale(struct s5p_jpeg_ctx *ctx,
+ struct v4l2_rect *r);
+
static int s5p_jpeg_s_fmt(struct s5p_jpeg_ctx *ct, struct v4l2_format *f)
{
struct vb2_queue *vq;
struct s5p_jpeg_q_data *q_data = NULL;
struct v4l2_pix_format *pix = &f->fmt.pix;
struct v4l2_ctrl *ctrl_subs;
+ struct v4l2_rect scale_rect;
unsigned int f_type;
vq = v4l2_m2m_get_vq(ct->fh.m2m_ctx, f->type);
@@ -1382,6 +1386,20 @@ static int s5p_jpeg_s_fmt(struct s5p_jpeg_ctx *ct,
struct v4l2_format *f)
ct->crop_rect.width = pix->width;
ct->crop_rect.height = pix->height;
}
+
+ /*
+* Prevent downscaling to YUV420 format by more than 2
+* for Exynos3250 SoC as it produces broken raw image
+* in such cases.
+*/
+ if (ct->mode == S5P_JPEG_DECODE &&
+ f_type == FMT_TYPE_CAPTURE &&
+ ct->jpeg->variant->version == SJPEG_EXYNOS3250 &&
+ pix->pixelformat == V4L2_PIX_FMT_YUV420 &&
+ ct->scale_factor > 2) {
+ scale_rect.width = ct->out_q.w / 2;
+ scale_rect.height = ct->out_q.h / 2;
+ exynos3250_jpeg_try_downscale(ct, &scale_rect);
}
return 0;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/9] s5p-jpeg: fix g_selection op
V4L2_SEL_TGT_COMPOSE_DEFAULT switch case should select whole available area of the image and V4L2_SEL_TGT_COMPOSE should apply user settings. Signed-off-by: Jacek Anaszewski Signed-off-by: Kyungmin Park --- drivers/media/platform/s5p-jpeg/jpeg-core.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c index 0854f37..09b59d3 100644 --- a/drivers/media/platform/s5p-jpeg/jpeg-core.c +++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c @@ -1505,21 +1505,23 @@ static int s5p_jpeg_g_selection(struct file *file, void *priv, case V4L2_SEL_TGT_CROP: case V4L2_SEL_TGT_CROP_BOUNDS: case V4L2_SEL_TGT_CROP_DEFAULT: - case V4L2_SEL_TGT_COMPOSE: case V4L2_SEL_TGT_COMPOSE_DEFAULT: s->r.width = ctx->out_q.w; s->r.height = ctx->out_q.h; + s->r.left = 0; + s->r.top = 0; break; + case V4L2_SEL_TGT_COMPOSE: case V4L2_SEL_TGT_COMPOSE_BOUNDS: case V4L2_SEL_TGT_COMPOSE_PADDED: - s->r.width = ctx->cap_q.w; - s->r.height = ctx->cap_q.h; + s->r.width = ctx->crop_rect.width; + s->r.height = ctx->crop_rect.height; + s->r.left = ctx->crop_rect.left; + s->r.top = ctx->crop_rect.top; break; default: return -EINVAL; } - s->r.left = 0; - s->r.top = 0; return 0; } -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/9] s5p-jpeg: Assure proper crop rectangle initialization
Assure proper crop_rect initialization in case
the user space doesn't call S_SELECTION ioctl.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 09b59d3..2491ef8 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -1367,6 +1367,21 @@ static int s5p_jpeg_s_fmt(struct s5p_jpeg_ctx *ct,
struct v4l2_format *f)
V4L2_CID_JPEG_CHROMA_SUBSAMPLING);
if (ctrl_subs)
v4l2_ctrl_s_ctrl(ctrl_subs, q_data->fmt->subsampling);
+ ct->crop_altered = false;
+ }
+
+ /*
+* For decoding init crop_rect with capture buffer dimmensions which
+* contain aligned dimensions of the input JPEG image and do it only
+* if crop rectangle hasn't been altered by the user space e.g. with
+* S_SELECTION ioctl. For encoding assign output buffer dimensions.
+*/
+ if (!ct->crop_altered &&
+ ((ct->mode == S5P_JPEG_DECODE && f_type == FMT_TYPE_CAPTURE) ||
+(ct->mode == S5P_JPEG_ENCODE && f_type == FMT_TYPE_OUTPUT))) {
+ ct->crop_rect.width = pix->width;
+ ct->crop_rect.height = pix->height;
+ }
}
return 0;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/9] s5p-jpeg: return error immediately after get_byte fails
When parsing JPEG header s5p_jpeg_parse_hdr function
should return immediately in case there was an error
while reading a byte.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/jpeg-core.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 7d604f2..df3aaa9 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -906,14 +906,14 @@ static bool s5p_jpeg_parse_hdr(struct s5p_jpeg_q_data
*result,
while (notfound) {
c = get_byte(&jpeg_buffer);
if (c == -1)
- break;
+ return false;
if (c != 0xff)
continue;
do
c = get_byte(&jpeg_buffer);
while (c == 0xff);
if (c == -1)
- break;
+ return false;
if (c == 0)
continue;
length = 0;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/9] s5p-jpeg: Add support for Exynos3250 SoC
This patch adds support for jpeg codec on Exynos3250 SoC to
the s5p-jpeg driver. Supported raw formats are: YUYV, YVYU, UYVY,
VYUY, RGB565, RGB565X, RGB32, NV12, NV21. The support includes
also scaling and cropping features.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/Makefile |2 +-
drivers/media/platform/s5p-jpeg/jpeg-core.c| 533 +++-
drivers/media/platform/s5p-jpeg/jpeg-core.h| 33 +-
.../media/platform/s5p-jpeg/jpeg-hw-exynos3250.c | 486 ++
.../media/platform/s5p-jpeg/jpeg-hw-exynos3250.h | 60 +++
drivers/media/platform/s5p-jpeg/jpeg-regs.h| 247 -
6 files changed, 1341 insertions(+), 20 deletions(-)
create mode 100644 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c
create mode 100644 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.h
diff --git a/drivers/media/platform/s5p-jpeg/Makefile
b/drivers/media/platform/s5p-jpeg/Makefile
index a1a9169..9e5f214 100644
--- a/drivers/media/platform/s5p-jpeg/Makefile
+++ b/drivers/media/platform/s5p-jpeg/Makefile
@@ -1,2 +1,2 @@
-s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
+s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o
jpeg-hw-s5p.o
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 0dcb796..7d604f2 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -1,6 +1,6 @@
/* linux/drivers/media/platform/s5p-jpeg/jpeg-core.c
*
- * Copyright (c) 2011-2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Author: Andrzej Pietrasiewicz
@@ -32,6 +32,7 @@
#include "jpeg-core.h"
#include "jpeg-hw-s5p.h"
#include "jpeg-hw-exynos4.h"
+#include "jpeg-hw-exynos3250.h"
#include "jpeg-regs.h"
static struct s5p_jpeg_fmt sjpeg_formats[] = {
@@ -41,6 +42,7 @@ static struct s5p_jpeg_fmt sjpeg_formats[] = {
.flags = SJPEG_FMT_FLAG_ENC_CAPTURE |
SJPEG_FMT_FLAG_DEC_OUTPUT |
SJPEG_FMT_FLAG_S5P |
+ SJPEG_FMT_FLAG_EXYNOS3250 |
SJPEG_FMT_FLAG_EXYNOS4,
},
{
@@ -70,6 +72,19 @@ static struct s5p_jpeg_fmt sjpeg_formats[] = {
.subsampling= V4L2_JPEG_CHROMA_SUBSAMPLING_422,
},
{
+ .name = "YUV 4:2:2 packed, YCbYCr",
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .depth = 16,
+ .colplanes = 1,
+ .h_align= 2,
+ .v_align= 0,
+ .flags = SJPEG_FMT_FLAG_ENC_OUTPUT |
+ SJPEG_FMT_FLAG_DEC_CAPTURE |
+ SJPEG_FMT_FLAG_EXYNOS3250 |
+ SJPEG_FMT_NON_RGB,
+ .subsampling= V4L2_JPEG_CHROMA_SUBSAMPLING_422,
+ },
+ {
.name = "YUV 4:2:2 packed, YCrYCb",
.fourcc = V4L2_PIX_FMT_YVYU,
.depth = 16,
@@ -83,6 +98,45 @@ static struct s5p_jpeg_fmt sjpeg_formats[] = {
.subsampling= V4L2_JPEG_CHROMA_SUBSAMPLING_422,
},
{
+ .name = "YUV 4:2:2 packed, YCrYCb",
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .depth = 16,
+ .colplanes = 1,
+ .h_align= 2,
+ .v_align= 0,
+ .flags = SJPEG_FMT_FLAG_ENC_OUTPUT |
+ SJPEG_FMT_FLAG_DEC_CAPTURE |
+ SJPEG_FMT_FLAG_EXYNOS3250 |
+ SJPEG_FMT_NON_RGB,
+ .subsampling= V4L2_JPEG_CHROMA_SUBSAMPLING_422,
+ },
+ {
+ .name = "YUV 4:2:2 packed, YCrYCb",
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .depth = 16,
+ .colplanes = 1,
+ .h_align= 2,
+ .v_align= 0,
+ .flags = SJPEG_FMT_FLAG_ENC_OUTPUT |
+ SJPEG_FMT_FLAG_DEC_CAPTURE |
+ SJPEG_FMT_FLAG_EXYNOS3250 |
+ SJPEG_FMT_NON_RGB,
+ .subsampling= V4L2_JPEG_CHROMA_SUBSAMPLING_422,
+ },
+ {
+ .name = "YUV 4:2:2 packed, YCrYCb",
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .depth = 16,
+ .colplanes = 1,
+ .h_align= 2,
+ .v_align= 0,
+ .flags = SJPEG_FMT_FLAG_ENC_OUT
[PATCH 3/9] s5p-jpeg: Adjust jpeg_bound_align_image to Exynos3250 needs
The jpeg_bound_align_image function needs to know the context
in which it is called, as it needs to align image dimensions in
a slight different manner for Exynos3250, which crops pixels for
specific values in case the format is RGB.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
---
drivers/media/platform/s5p-jpeg/jpeg-core.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c
b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index df3aaa9..0854f37 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -1133,7 +1133,8 @@ static struct s5p_jpeg_fmt *s5p_jpeg_find_format(struct
s5p_jpeg_ctx *ctx,
return NULL;
}
-static void jpeg_bound_align_image(u32 *w, unsigned int wmin, unsigned int
wmax,
+static void jpeg_bound_align_image(struct s5p_jpeg_ctx *ctx,
+ u32 *w, unsigned int wmin, unsigned int wmax,
unsigned int walign,
u32 *h, unsigned int hmin, unsigned int hmax,
unsigned int halign)
@@ -1145,13 +1146,27 @@ static void jpeg_bound_align_image(u32 *w, unsigned int
wmin, unsigned int wmax,
w_step = 1 << walign;
h_step = 1 << halign;
+
+ if (ctx->jpeg->variant->version == SJPEG_EXYNOS3250) {
+ /*
+* Rightmost and bottommost pixels are cropped by the
+* Exynos3250 JPEG IP for RGB formats, for the specific
+* width and height values respectively. This assignment
+* will result in v4l_bound_align_image returning dimensions
+* reduced by 1 for the aforementioned cases.
+*/
+ if (w_step == 4 && ((width & 3) == 1)) {
+ wmax = width;
+ hmax = height;
+ }
+ }
+
v4l_bound_align_image(w, wmin, wmax, walign, h, hmin, hmax, halign, 0);
if (*w < width && (*w + w_step) < wmax)
*w += w_step;
if (*h < height && (*h + h_step) < hmax)
*h += h_step;
-
}
static int vidioc_try_fmt(struct v4l2_format *f, struct s5p_jpeg_fmt *fmt,
@@ -1167,12 +1182,12 @@ static int vidioc_try_fmt(struct v4l2_format *f, struct
s5p_jpeg_fmt *fmt,
/* V4L2 specification suggests the driver corrects the format struct
* if any of the dimensions is unsupported */
if (q_type == FMT_TYPE_OUTPUT)
- jpeg_bound_align_image(&pix->width, S5P_JPEG_MIN_WIDTH,
+ jpeg_bound_align_image(ctx, &pix->width, S5P_JPEG_MIN_WIDTH,
S5P_JPEG_MAX_WIDTH, 0,
&pix->height, S5P_JPEG_MIN_HEIGHT,
S5P_JPEG_MAX_HEIGHT, 0);
else
- jpeg_bound_align_image(&pix->width, S5P_JPEG_MIN_WIDTH,
+ jpeg_bound_align_image(ctx, &pix->width, S5P_JPEG_MIN_WIDTH,
S5P_JPEG_MAX_WIDTH, fmt->h_align,
&pix->height, S5P_JPEG_MIN_HEIGHT,
S5P_JPEG_MAX_HEIGHT, fmt->v_align);
@@ -1294,7 +1309,7 @@ static int exynos4_jpeg_get_output_buffer_size(struct
s5p_jpeg_ctx *ctx,
else
wh_align = 1;
- jpeg_bound_align_image(&w, S5P_JPEG_MIN_WIDTH,
+ jpeg_bound_align_image(ctx, &w, S5P_JPEG_MIN_WIDTH,
S5P_JPEG_MAX_WIDTH, wh_align,
&h, S5P_JPEG_MIN_HEIGHT,
S5P_JPEG_MAX_HEIGHT, wh_align);
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/9] Add support for Exynos3250 SoC to the s5p-jpeg driver
This patch series adds support for jpeg codec on Exynos3250 SoC to the s5p-jpeg driver. Supported raw formats are: YUYV, YVYU, UYVY, VYUY, RGB565, RGB565X, RGB32, NV12, NV21. The support includes also scaling and cropping features. Thanks, Jacek Anaszewski Jacek Anaszewski (9): s5p-jpeg: Add support for Exynos3250 SoC s5p-jpeg: return error immediately after get_byte fails s5p-jpeg: Adjust jpeg_bound_align_image to Exynos3250 needs s5p-jpeg: fix g_selection op s5p-jpeg: Assure proper crop rectangle initialization s5p-jpeg: Prevent erroneous downscaling for Exynos3250 SoC s5p-jpeg: add chroma subsampling adjustment for Exynos3250 Documentation: devicetree: Document sclk-jpeg clock for exynos3250 SoC ARM: dts: exynos3250: add JPEG codec device node .../bindings/media/exynos-jpeg-codec.txt |9 +- arch/arm/boot/dts/exynos3250.dtsi | 12 + drivers/media/platform/s5p-jpeg/Makefile |2 +- drivers/media/platform/s5p-jpeg/jpeg-core.c| 666 ++-- drivers/media/platform/s5p-jpeg/jpeg-core.h| 33 +- .../media/platform/s5p-jpeg/jpeg-hw-exynos3250.c | 486 ++ .../media/platform/s5p-jpeg/jpeg-hw-exynos3250.h | 60 ++ drivers/media/platform/s5p-jpeg/jpeg-regs.h| 247 +++- 8 files changed, 1459 insertions(+), 56 deletions(-) create mode 100644 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c create mode 100644 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/17] gpio: samsung: remov s5pc100 related gpio codes
On Mon, Jun 30, 2014 at 11:32 PM, Kukjin Kim wrote: > This patch removes gpio codes for s5pc100 SoC. > > Signed-off-by: Kukjin Kim > Cc: Linus Walleij Acked-by: Linus Walleij Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/17] gpio: samsung: remove s5p64x0 related gpio codes
On Mon, Jun 30, 2014 at 11:32 PM, Kukjin Kim wrote: > This patch removes gpio codes for s5p6440 and s5p6450 SoCs. > > Signed-off-by: Kukjin Kim > Cc: Linus Walleij Acked-by: Linus Walleij Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: add EXYNOS3250 PMU support
Hi,
On Mon, Jun 2, 2014 at 10:24 PM, Bartlomiej Zolnierkiewicz
wrote:
>
> This is needed for suspend/resume and cpuidle AFTR mode support.
>
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Bartlomiej Zolnierkiewicz
> ---
> against next-20140602
>
> arch/arm/mach-exynos/pmu.c | 163
> +++-
> arch/arm/mach-exynos/regs-pmu.h | 128 +++
> 2 files changed, 290 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
> index fb0deda..9e9bad5 100644
> --- a/arch/arm/mach-exynos/pmu.c
> +++ b/arch/arm/mach-exynos/pmu.c
> @@ -18,6 +18,98 @@
>
> static const struct exynos_pmu_conf *exynos_pmu_config;
>
> +static struct exynos_pmu_conf exynos3250_pmu_config[] = {
> + /* { .reg = address, .val = { AFTR, W-AFTR, SLEEP } */
> + { EXYNOS3_ARM_CORE0_SYS_PWR_REG,{ 0x0, 0x0, 0x2} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 0x0} },
> + { EXYNOS3_ARM_CORE1_SYS_PWR_REG,{ 0x0, 0x0, 0x2} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 0x0} },
> + { EXYNOS3_ARM_CORE2_SYS_PWR_REG,{ 0x0, 0x0, 0x2} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 0x0} },
> + { EXYNOS3_ARM_CORE3_SYS_PWR_REG,{ 0x0, 0x0, 0x2} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 0x0} },
> + { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,{ 0x0, 0x0, 0x0} },
> + { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
> + { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
> + { EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} },
> + { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
> + { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
> + { EXYNOS3_CMU_RESET_SYS_PWR_REG,{ 0x1, 0x1, 0x0} },
> + { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
> + { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG,{ 0x1, 0x1, 0x1} },
> + { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
> + { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG,{ 0x1, 0x1, 0x0} },
> + { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
> + { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
> + { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG,{ 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG,{ 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG,{ 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG,{ 0x1, 0x0, 0x0} },
> + { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
> + { EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
> + { EXYNOS3_TOP_RETENTION_SYS_PWR_REG,{ 0x1, 0x1, 0x1} },
> + { EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
> + { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
> + { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG,{ 0x1, 0x1, 0x1} },
> + { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
> + { EXYNOS
Re: [PATCH] ARM: EXYNOS: add EXYNOS3250 PMU support
Hi Kukjin, On Monday, June 02, 2014 06:54:07 PM Bartlomiej Zolnierkiewicz wrote: > > This is needed for suspend/resume and cpuidle AFTR mode support. > > Signed-off-by: Chanwoo Choi > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > against next-20140602 Could this patch be applied for v3.17 please? [ It still applies fine to next-20140707. ] Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] phy: core: the node pointer of PHY need not be the same as that of PHY provider
On Mon, 07 Jul 2014, Kishon Vijay Abraham I wrote: > Hi, > > On Monday 07 July 2014 06:42 PM, Lee Jones wrote: > > On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote: > > > >> In case of multi-phy PHY providers, each PHY should be modeled as a sub > >> node of the PHY provider. Then each PHY will have a different node pointer > >> (node pointer of sub node) than that of PHY provider. Added this provision > >> in the PHY core. > >> Also fixed all drivers to use the updated API. > >> > >> Signed-off-by: Kishon Vijay Abraham I > >> --- > >> Documentation/phy.txt | 10 ++ > >> drivers/phy/phy-bcm-kona-usb2.c |2 +- > >> drivers/phy/phy-core.c | 25 ++--- > >> drivers/phy/phy-exynos-dp-video.c |2 +- > >> drivers/phy/phy-exynos-mipi-video.c |2 +- > >> drivers/phy/phy-exynos5-usbdrd.c|3 ++- > >> drivers/phy/phy-exynos5250-sata.c |2 +- > >> drivers/phy/phy-mvebu-sata.c|2 +- > >> drivers/phy/phy-omap-usb2.c |2 +- > >> drivers/phy/phy-samsung-usb2.c |3 ++- > >> drivers/phy/phy-sun4i-usb.c |2 +- > >> drivers/phy/phy-ti-pipe3.c |2 +- > >> drivers/phy/phy-twl4030-usb.c |2 +- > >> drivers/phy/phy-xgene.c |2 +- > >> include/linux/phy/phy.h | 15 ++- > >> 15 files changed, 48 insertions(+), 28 deletions(-) > > > > I wrote a very similar patch already. I knew I should have sent it on > > Friday. :( > > No problem! you can send your patch along with the MiPHY series. That's okay. It's silly for us both to submit the same patch and yours hit the MLs first & looks good so, the honour is yours. > > Patch looks good, just a real minor point. > > > >>phy->dev.class = phy_class; > >>phy->dev.parent = dev; > >> - phy->dev.of_node = dev->of_node; > >> + phy->dev.of_node = node?node:dev->of_node; > > > > There should be spaces either side of the '?' and ':', or you can do > > this more succinctly by: > > > > phy->dev.of_node = node ?: dev->of_node; > > > > Once fixed, feel free to add my: > > > > Acked-by: Lee Jones > > -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] phy: core: the node pointer of PHY need not be the same as that of PHY provider
Hi, On Monday 07 July 2014 06:42 PM, Lee Jones wrote: > On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote: > >> In case of multi-phy PHY providers, each PHY should be modeled as a sub >> node of the PHY provider. Then each PHY will have a different node pointer >> (node pointer of sub node) than that of PHY provider. Added this provision >> in the PHY core. >> Also fixed all drivers to use the updated API. >> >> Signed-off-by: Kishon Vijay Abraham I >> --- >> Documentation/phy.txt | 10 ++ >> drivers/phy/phy-bcm-kona-usb2.c |2 +- >> drivers/phy/phy-core.c | 25 ++--- >> drivers/phy/phy-exynos-dp-video.c |2 +- >> drivers/phy/phy-exynos-mipi-video.c |2 +- >> drivers/phy/phy-exynos5-usbdrd.c|3 ++- >> drivers/phy/phy-exynos5250-sata.c |2 +- >> drivers/phy/phy-mvebu-sata.c|2 +- >> drivers/phy/phy-omap-usb2.c |2 +- >> drivers/phy/phy-samsung-usb2.c |3 ++- >> drivers/phy/phy-sun4i-usb.c |2 +- >> drivers/phy/phy-ti-pipe3.c |2 +- >> drivers/phy/phy-twl4030-usb.c |2 +- >> drivers/phy/phy-xgene.c |2 +- >> include/linux/phy/phy.h | 15 ++- >> 15 files changed, 48 insertions(+), 28 deletions(-) > > I wrote a very similar patch already. I knew I should have sent it on > Friday. :( No problem! you can send your patch along with the MiPHY series. Cheers Kishon > > Patch looks good, just a real minor point. > >> phy->dev.class = phy_class; >> phy->dev.parent = dev; >> -phy->dev.of_node = dev->of_node; >> +phy->dev.of_node = node?node:dev->of_node; > > There should be spaces either side of the '?' and ':', or you can do > this more succinctly by: > > phy->dev.of_node = node ?: dev->of_node; > > Once fixed, feel free to add my: > > Acked-by: Lee Jones > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 1/2] phy: core: Fix of_phy_provider_lookup to return PHY provider for sub node
On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote:
> Fixed of_phy_provider_lookup to return 'phy_provider' if _of_phy_get
> passes the node pointer of the sub-node of phy provider node. This is
> needed when phy provider implements multiple PHYs and each PHY is
> modelled as the sub-node of PHY provider device node.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/phy/phy-core.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index c64a2f3..a4a1f783 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -86,10 +86,18 @@ static struct phy *phy_lookup(struct device *device,
> const char *port)
> static struct phy_provider *of_phy_provider_lookup(struct device_node *node)
> {
> struct phy_provider *phy_provider;
> + struct device_node *child;
>
> list_for_each_entry(phy_provider, &phy_provider_list, list) {
> - if (phy_provider->dev->of_node == node)
> + if (phy_provider->dev->of_node != node) {
> + for_each_child_of_node(phy_provider->dev->of_node,
> + child) {
> + if (child == node)
> + return phy_provider;
> + }
> + } else {
> return phy_provider;
> + }
> }
>
> return ERR_PTR(-EPROBE_DEFER);
How about this instead:
> list_for_each_entry(phy_provider, &phy_provider_list, list) {
> if (phy_provider->dev->of_node == node)
> return phy_provider;
> +
> + for_each_child_of_node(phy_provider->dev->of_node, child)
> + if (child == node)
> + return phy_provider;
> }
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: remove display power domain for exynos5420
Hi Andrej, Inki,
On 18 June 2014 12:06, Rahul Sharma wrote:
> Hi Andrej,
>
> On 18 June 2014 11:46, Andrzej Hajda wrote:
>> On 06/17/2014 07:49 AM, Rahul Sharma wrote:
>>> Hi All,
>>>
>>> Please review this patch.
>>>
>>> Regards,
>>> Rahul Sharma
>>>
>>> On 9 June 2014 16:58, Rahul Sharma wrote:
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the pm_genpd_poweroff_unused which
powers off the unused power domains. This call hits before
the trigger to deferred probes.
DRM DP Panel defers the probe due to supply get failure. By the
time, deferred probe is scheduled again, Display Power Domain is
powered off by pm_genpd_poweroff_unused.
FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power
Domain Disable fail notification. Increasing the Timeout also
didn't help.
>>
>> As I understand the problem is that fimd and dp drivers access hw
>> registers without enabling power domain. So the proper solution is to
>> fix these drivers.
>
> That is also a problem but I fixed those accesses in my local kernel before
> hitting this issue. If we do register accesses in FIMD/DP probe/bind we
> observes "Prefetch abort" exception. But here the problem is that 'DP
> domain disable' starts failing if we enable/disable multiple times.
>
>>
>> Btw. there are already patches removing hw access from probe/bind of
>> fimd. I guess removing also hw access from dp probe/bind could be a good
>> solution.
>
> Please let me know the links for posted patches. I will test with those
> patches.
Is there any update on this? Please share the patches which fixes the
above issue or avoid the above scenario of multiple PM Domain enable/disable.
I will test them for exynos5 based boards. Otherwise we should get this change
merged else display will remain broken for exynos5 based boards.
Regards,
Rahul Sharma.
>
> Regards,
> Rahul Sharma
>
>>
>> Regards
>> Andrzej
>>
Signed-off-by: Rahul Sharma
---
based on Kukjin's for-next branch.
arch/arm/boot/dts/exynos5420.dtsi |6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..3d528cf 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -262,11 +262,6 @@
reg = <0x10044060 0x20>;
};
- disp_pd: power-domain@100440C0 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x100440C0 0x20>;
- };
-
msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
@@ -518,7 +513,6 @@
};
fimd: fimd@1440 {
- samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
clock-names = "sclk_fimd", "fimd";
};
--
1.7.9.5
>>
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] phy: core: the node pointer of PHY need not be the same as that of PHY provider
On Fri, 04 Jul 2014, Kishon Vijay Abraham I wrote: > In case of multi-phy PHY providers, each PHY should be modeled as a sub > node of the PHY provider. Then each PHY will have a different node pointer > (node pointer of sub node) than that of PHY provider. Added this provision > in the PHY core. > Also fixed all drivers to use the updated API. > > Signed-off-by: Kishon Vijay Abraham I > --- > Documentation/phy.txt | 10 ++ > drivers/phy/phy-bcm-kona-usb2.c |2 +- > drivers/phy/phy-core.c | 25 ++--- > drivers/phy/phy-exynos-dp-video.c |2 +- > drivers/phy/phy-exynos-mipi-video.c |2 +- > drivers/phy/phy-exynos5-usbdrd.c|3 ++- > drivers/phy/phy-exynos5250-sata.c |2 +- > drivers/phy/phy-mvebu-sata.c|2 +- > drivers/phy/phy-omap-usb2.c |2 +- > drivers/phy/phy-samsung-usb2.c |3 ++- > drivers/phy/phy-sun4i-usb.c |2 +- > drivers/phy/phy-ti-pipe3.c |2 +- > drivers/phy/phy-twl4030-usb.c |2 +- > drivers/phy/phy-xgene.c |2 +- > include/linux/phy/phy.h | 15 ++- > 15 files changed, 48 insertions(+), 28 deletions(-) I wrote a very similar patch already. I knew I should have sent it on Friday. :( Patch looks good, just a real minor point. > phy->dev.class = phy_class; > phy->dev.parent = dev; > - phy->dev.of_node = dev->of_node; > + phy->dev.of_node = node?node:dev->of_node; There should be spaces either side of the '?' and ':', or you can do this more succinctly by: phy->dev.of_node = node ?: dev->of_node; Once fixed, feel free to add my: Acked-by: Lee Jones -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 4/4] clk: samsung: exynos5420: Setup clocks before system suspend
Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.
while at it, add these clks to save/restore list also.
Signed-off-by: Vikas Sajjan
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos5420.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7ee..7e87d7c 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -28,6 +28,7 @@
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
#define CLKOUT_CMU_CPU 0xa00
+#define SRC_MASK_CPERI 0x4300
#define GATE_IP_G2D0x8800
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
@@ -70,6 +71,8 @@
#define SRC_TOP11 0x10284
#define SRC_TOP12 0x10288
#define SRC_TOP13 0x1028c /* 5800 specific */
+#define SRC_MASK_TOP0 0x10300
+#define SRC_MASK_TOP1 0x10304
#define SRC_MASK_TOP2 0x10308
#define SRC_MASK_TOP7 0x1031c
#define SRC_MASK_DISP100x1032c
@@ -77,6 +80,7 @@
#define SRC_MASK_FSYS 0x10340
#define SRC_MASK_PERIC00x10350
#define SRC_MASK_PERIC10x10354
+#define SRC_MASK_ISP 0x10370
#define DIV_TOP0 0x10500
#define DIV_TOP1 0x10504
#define DIV_TOP2 0x10508
@@ -98,6 +102,7 @@
#define DIV2_RATIO00x10590
#define DIV4_RATIO 0x105a0
#define GATE_BUS_TOP 0x10700
+#define GATE_BUS_DISP1 0x10728
#define GATE_BUS_GEN 0x1073c
#define GATE_BUS_FSYS0 0x10740
#define GATE_BUS_FSYS2 0x10748
@@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
SRC_MASK_FSYS,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
+ SRC_MASK_TOP0,
+ SRC_MASK_TOP1,
+ SRC_MASK_MAU,
+ SRC_MASK_ISP,
SRC_ISP,
DIV_TOP0,
DIV_TOP1,
@@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
SCLK_DIV_ISP1,
DIV2_RATIO0,
DIV4_RATIO,
+ GATE_BUS_DISP1,
GATE_BUS_TOP,
GATE_BUS_GEN,
GATE_BUS_FSYS0,
@@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = {
GATE_IP_CAM,
};
+static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
+ { .offset = SRC_MASK_CPERI, .value = 0x, },
+ { .offset = SRC_MASK_TOP0, .value = 0x, },
+ { .offset = SRC_MASK_TOP1, .value = 0x1110, },
+ { .offset = SRC_MASK_TOP2, .value = 0x1110, },
+ { .offset = SRC_MASK_TOP7, .value = 0x0000, },
+ { .offset = SRC_MASK_DISP10,.value = 0x1110, },
+ { .offset = SRC_MASK_MAU, .value = 0x1000, },
+ { .offset = SRC_MASK_FSYS, .value = 0x1110, },
+ { .offset = SRC_MASK_PERIC0,.value = 0x1110, },
+ { .offset = SRC_MASK_PERIC1,.value = 0x1100, },
+ { .offset = SRC_MASK_ISP, .value = 0x1000, },
+ { .offset = GATE_BUS_DISP1, .value = 0x, },
+ { .offset = GATE_IP_PERIC, .value = 0x, },
+};
+
static int exynos5420_clk_suspend(void)
{
samsung_clk_save(reg_base, exynos5x_save,
@@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void)
samsung_clk_save(reg_base, exynos5800_save,
ARRAY_SIZE(exynos5800_clk_regs));
+ samsung_clk_restore(reg_base, exynos5420_set_clksrc,
+ ARRAY_SIZE(exynos5420_set_clksrc));
+
return 0;
}
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 3/4] arm: exynos5: Add Suspend-to-RAM support for 5420
From: Abhilash Kesavan
Adds Suspend-to-RAM support for EXYNOS5420
Signed-off-by: Vikas Sajjan
Signed-off-by: Abhilash Kesavan
---
arch/arm/mach-exynos/pm.c | 146 +
1 file changed, 146 insertions(+)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index c0dae28..7edc3d0 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -40,6 +40,8 @@
#define REG_TABLE_END (-1U)
+#define EXYNOS5420_CPU_STATE 0x28
+
/**
* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
* @hwirq: Hardware IRQ signal of the GIC
@@ -76,6 +78,9 @@ struct exynos_pm_data {
struct exynos_pm_data *pm_data;
+static int exynos5420_cpu_state;
+static unsigned int exynos_pmu_spare3;
+
/*
* GIC wake-up support
*/
@@ -115,6 +120,23 @@ unsigned int exynos_release_ret_regs[] = {
REG_TABLE_END,
};
+unsigned int exynos5420_release_ret_regs[] = {
+ EXYNOS_PAD_RET_DRAM_OPTION,
+ EXYNOS_PAD_RET_MAUDIO_OPTION,
+ EXYNOS_PAD_RET_JTAG_OPTION,
+ EXYNOS5420_PAD_RET_GPIO_OPTION,
+ EXYNOS5420_PAD_RET_UART_OPTION,
+ EXYNOS5420_PAD_RET_MMCA_OPTION,
+ EXYNOS5420_PAD_RET_MMCB_OPTION,
+ EXYNOS5420_PAD_RET_MMCC_OPTION,
+ EXYNOS5420_PAD_RET_HSI_OPTION,
+ EXYNOS_PAD_RET_EBIA_OPTION,
+ EXYNOS_PAD_RET_EBIB_OPTION,
+ EXYNOS5420_PAD_RET_SPI_OPTION,
+ EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
+ REG_TABLE_END,
+};
+
static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
const struct exynos_wkup_irq *wkup_irq;
@@ -312,6 +334,17 @@ static int exynos5250_cpu_suspend(unsigned long arg)
return exynos_cpu_do_idle();
}
+static int exynos5420_cpu_suspend(unsigned long arg)
+{
+#ifdef CONFIG_CACHE_L2X0
+ outer_flush_all();
+#endif
+ __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+ flush_cache_all();
+ return exynos_cpu_do_idle();
+}
+
static void exynos_pm_set_wakeup_mask(void)
{
/* Set wake-up mask registers */
@@ -329,6 +362,49 @@ static void exynos_pm_enter_sleep_mode(void)
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
+static void exynos5420_pm_prepare(void)
+{
+ unsigned int tmp;
+
+ /* Set wake-up mask registers */
+ exynos_pm_set_wakeup_mask();
+
+ s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+
+ exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
+ /*
+* The cpu state needs to be saved and restored so that the
+* secondary CPUs will enter low power start. Though the U-Boot
+* is setting the cpu state with low power flag, the kernel
+* needs to restore it back in case, the primary cpu fails to
+* suspend for any reason.
+*/
+ exynos5420_cpu_state = __raw_readl(sysram_base_addr +
+ EXYNOS5420_CPU_STATE);
+
+ exynos_pm_enter_sleep_mode();
+
+ tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
+ tmp &= ~EXYNOS5_USE_RETENTION;
+ pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+
+ tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+ tmp |= EXYNOS5420_UFS;
+ pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+
+ tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+ tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
+ pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
+
+ tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
+ tmp |= EXYNOS5420_EMULATION;
+ pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+
+ tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
+ tmp |= EXYNOS5420_EMULATION;
+ pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+}
+
static void exynos5250_pm_prepare(void)
{
unsigned int tmp;
@@ -403,6 +479,24 @@ static int exynos5250_pm_suspend(void)
return 0;
}
+static int exynos5420_pm_suspend(void)
+{
+ u32 this_cluster;
+
+ exynos_pm_central_suspend();
+
+ /* Setting SEQ_OPTION register */
+
+ this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+ if (!this_cluster)
+ pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
+ S5P_CENTRAL_SEQ_OPTION);
+ else
+ pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
+ S5P_CENTRAL_SEQ_OPTION);
+ return 0;
+}
+
static int exynos_pm_central_resume(void)
{
unsigned long tmp;
@@ -479,6 +573,45 @@ early_wakeup:
pmu_raw_writel(0x0, S5P_INFORM1);
}
+static void exynos5420_pm_resume(void)
+{
+ unsigned long tmp;
+
+ /* Restore the sysram cpu state register */
+ __raw_writel(exynos5420_cpu_state,
+ sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+ pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
+ S5P_CENTRAL_SEQ_OPTION);
+
+ if (exynos_pm_central_resume())
+ goto early_wakeup;
+
[PATCH v6 2/4] ARM: EXYNOS: Refactor the code to use DT based lookup
Refactoring the pm.c to avoid using "soc_is_exynos" checks,
instead use the DT based lookup.
While at it, consolidate the common code across SoCs
and create a static helper functions.
Signed-off-by: Vikas Sajjan
---
arch/arm/mach-exynos/pm.c | 232 +++
arch/arm/mach-exynos/regs-pmu.h |1 +
2 files changed, 189 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index ba75171..c0dae28 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,6 +38,8 @@
#include "regs-pmu.h"
#include "regs-sys.h"
+#define REG_TABLE_END (-1U)
+
/**
* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
* @hwirq: Hardware IRQ signal of the GIC
@@ -61,6 +63,19 @@ static struct sleep_save exynos_core_save[] = {
SAVE_ITEM(S5P_SROM_BC3),
};
+struct exynos_pm_data {
+ const struct exynos_wkup_irq *wkup_irq;
+ unsigned int wake_disable_mask;
+ unsigned int *release_ret_regs;
+
+ void (*pm_prepare)(void);
+ void (*pm_resume)(void);
+ int (*pm_suspend)(void);
+ int (*cpu_suspend)(unsigned long);
+};
+
+struct exynos_pm_data *pm_data;
+
/*
* GIC wake-up support
*/
@@ -89,14 +104,21 @@ static inline u32 pmu_raw_readl(u32 offset)
return __raw_readl(pmu_base_addr + offset);
}
+unsigned int exynos_release_ret_regs[] = {
+ S5P_PAD_RET_MAUDIO_OPTION,
+ S5P_PAD_RET_GPIO_OPTION,
+ S5P_PAD_RET_UART_OPTION,
+ S5P_PAD_RET_MMCA_OPTION,
+ S5P_PAD_RET_MMCB_OPTION,
+ S5P_PAD_RET_EBIA_OPTION,
+ S5P_PAD_RET_EBIB_OPTION,
+ REG_TABLE_END,
+};
+
static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
const struct exynos_wkup_irq *wkup_irq;
-
- if (soc_is_exynos5250())
- wkup_irq = exynos5250_wkup_irq;
- else
- wkup_irq = exynos4_wkup_irq;
+ wkup_irq = pm_data->wkup_irq;
while (wkup_irq->mask) {
if (wkup_irq->hwirq == data->hwirq) {
@@ -253,13 +275,13 @@ static void exynos_cpu_restore_register(void)
static int exynos_cpu_suspend(unsigned long arg)
{
-#ifdef CONFIG_CACHE_L2X0
- outer_flush_all();
-#endif
-
- if (soc_is_exynos5250())
- flush_cache_all();
+ if (pm_data->cpu_suspend)
+ return pm_data->cpu_suspend(arg);
+ return -1;
+}
+static int exynos_cpu_do_idle(void)
+{
/* issue the standby signal into the pm unit. */
cpu_do_idle();
@@ -269,32 +291,73 @@ static int exynos_cpu_suspend(unsigned long arg)
static void exynos_pm_prepare(void)
{
- unsigned int tmp;
+ if (pm_data->pm_prepare)
+ pm_data->pm_prepare();
+}
+
+static int exynos4_cpu_suspend(unsigned long arg)
+{
+#ifdef CONFIG_CACHE_L2X0
+ outer_flush_all();
+#endif
+ return exynos_cpu_do_idle();
+}
+
+static int exynos5250_cpu_suspend(unsigned long arg)
+{
+#ifdef CONFIG_CACHE_L2X0
+ outer_flush_all();
+#endif
+ flush_cache_all();
+ return exynos_cpu_do_idle();
+}
+static void exynos_pm_set_wakeup_mask(void)
+{
/* Set wake-up mask registers */
pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+}
- s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-
- if (soc_is_exynos5250()) {
- s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
- /* Disable USE_RETENTION of JPEG_MEM_OPTION */
- tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
- tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
- pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
- }
-
+static void exynos_pm_enter_sleep_mode(void)
+{
/* Set value of power down register for sleep mode */
-
exynos_sys_powerdown_conf(SYS_SLEEP);
pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
-
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
+static void exynos5250_pm_prepare(void)
+{
+ unsigned int tmp;
+
+ /* Set wake-up mask registers */
+ exynos_pm_set_wakeup_mask();
+
+ s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+
+ s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
+
+ /* Disable USE_RETENTION of JPEG_MEM_OPTION */
+ tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+ tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
+ pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+
+ exynos_pm_enter_sleep_mode();
+}
+
+static void exynos4_pm_prepare(void)
+{
+ /* Set wake-up mask registers */
+ exynos_pm_set_wakeup_mask();
+
+ s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+
+ exynos_pm_enter_sleep_mode();
+}
+
static void exynos_pm_central_suspend(void)
{
unsig
[PATCH v6 1/4] arm: exynos5: Add PMU support for 5420
From: Abhilash Kesavan
Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham
Signed-off-by: Abhilash Kesavan
Signed-off-by: Vikas Sajjan
---
arch/arm/mach-exynos/pmu.c | 288 +++
arch/arm/mach-exynos/regs-pmu.h | 229 +++
2 files changed, 517 insertions(+)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index a4ede73..c962c66 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,6 +14,9 @@
#include
#include
#include
+#include
+
+#include
#include "exynos-pmu.h"
#include "regs-pmu.h"
@@ -349,6 +352,151 @@ static const struct exynos_pmu_conf
exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
+static struct exynos_pmu_conf exynos5420_pmu_config[] = {
+ /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
+ { EXYNOS5_ARM_CORE0_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_ARM_CORE1_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,{ 0x1, 0x0,
0x0} },
+ { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0,
0x0} },
+ { EXYNOS5420_KFC_L2_SYS_PWR_REG,{ 0x0, 0x0,
0x0} },
+ { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { EXYNOS5_CMU_RESET_SYS_PWR_REG,{ 0x1, 0x1,
0x0} },
+ { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1,
0x0} },
+ { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,{ 0x1, 0x1,
0x1} },
+ { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0,
0x1} },
+ { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1,
0x0} },
+ { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0,
0x0} },
+ { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG, {
[PATCH v6 0/4] Adds PMU and S2R support for exynos5420
Rebased on 1] Kukjin Kim's tree, for-next branch https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next 2] Pankaj Dubey's v6 PMU patchset http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg33660.html changes since v5: - Refactored pm.c to use DT based lookup as suggested by Tomasz Figa. changes since v4: - Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset changes since v3: Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz, Tomasz Figa and Alim Akhtar: - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h. - Merged exynos5420_set_core_flag function into powerdown_conf. - Removed XXTI_DURATION3 register setting. - Updated the commit message and ordered the clock registers in clock patch. - Removed the code for SYS_DISP1_BLK_CFG handling. - Modified SoC checks to A9 specific checks in PM code. - Updated some comments in the code and added macros for register offsets. - Fixed code which was changing pad retention code for older SoCs. changes since v2: - Addressed comments from Tomasz figa - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612 - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420", will be sent separately. changes since v1: - Addressed comments from Tomasz figa. - restructured/consolidated as per Tomasz figa's PM consolidations for exynos Tested on Kukjin Kim's tree, for-next branch + 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html 2] http://www.spinics.net/lists/linux-samsung-soc/msg32923.html 3] https://www.mail-archive.com/linux-mmc@vger.kernel.org/msg26210.html (for eMMC S2R fail issue) on Exynos5420 based chromebook (peach-pit board) and Exynos5250 based chromebook (snow board). PS : Not tested on exynos4 based boards. Tested-by for exynos4 would be appreciated. Below procedures were followed to test S2R: Procedure A: 1. make multi_v7_defconfig 2 enable MCPM for 5420 3. enable S3C RTC 4. pass "no_console_suspend" in bootargs 5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state Procedure B: 1. make exynos_defconfig 2 enable MCPM for 5420 3 enable CONFIG_PL330_DMA 4. enable CONFIG_PM_RUNTIME 5. pass "no_console_suspend" in bootargs 6. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state Abhilash Kesavan (2): arm: exynos5: Add PMU support for 5420 arm: exynos5: Add Suspend-to-RAM support for 5420 Vikas Sajjan (2): ARM: EXYNOS: Refactor the code to use DT based lookup clk: samsung: exynos5420: Setup clocks before system suspend arch/arm/mach-exynos/pm.c| 376 ++ arch/arm/mach-exynos/pmu.c | 288 ++ arch/arm/mach-exynos/regs-pmu.h | 230 + drivers/clk/samsung/clk-exynos5420.c | 29 +++ 4 files changed, 880 insertions(+), 43 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v5] spi: s3c64xx: fix broken "cs_gpios" usage in the driver
Hello Naveen and Mark,
On Mon, Jul 7, 2014 at 10:31 AM, Naveen Krishna Ch
wrote:
> Hello Mark,
>
> On 7 July 2014 13:02, Mark Brown wrote:
>> On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote:
>>> On 2 July 2014 22:26, Mark Brown wrote:
>>> > On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
>>
>>> >> Hence, spi-s3c64xx.c is broken since "Jun 21 11:26:12 2013" and
>>> >> considering the time with no compliants about the breakage.
>>
>>> > I'm not clear what the breakage is? Some boards are broken but what's
>>> > the driver issue?
>>
>>> ToT was broken for few boards
>>> exynos4412-trats2.dts, exynos4210-smdkv310.dts and exynos5250-smdk5250.dts
>>
>>> With some DTS changes SPI works well, spi-s3c64xx.c driver had no issues.
>>
Correct me if I'm wrong but I think that the driver does have issues
since the commit mentioned (3146bee) broke DT backward compatibility.
>> No, you're not answering my question - to repeat, what is the breakage?
>
As far as I understand, the breakage is that any DTS that followed the
DT binding documented in
Documentation/devicetree/bindings/spi/spi-samsung.txt is not working
with the current driver. So is not that some boards are broken, is
that the driver is broken and it has been broken for more than a year
(the commit date is Jun 21 2013).
> The Documentation/devicetree/bindings/spi/spi-samsung.txt
> describes "cs-gpio" as a controller specific property.
>
> The dts entries for SPI in exynos4412-trats2.dts, exynos4210-smdkv310.dts
> and exynos5250-smdk5250.dts boards have the "cs-gpio" property defined
> under controller-data node, which is inside the SPI device node
> &spi_1 {
> controller-data {
> cs-gpio = <>;
> };
> };
>
> But, _probe() of spi-s3c64xx.c driver looks for "cs-gpio" in the SPI
> device node and
> sets a flag "sdd->cs_gpio = false" (If the property is not available)
> &spi_1 {
> cs-gpio = <>;
> };
>
> the sdd->cs_gpio flag is checked before actually getting the gpios
> from the controller-data node
>if (sdd->cs_gpio)
> cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
>
I think that if changing the binding is not possible, at least we
should document this new "cs-gpio" property that is looked in the top
level SPI node after commit 3146bee and also revert the default in
order to allow DTs using the old binding to keep working.
By default not having the "cs-gpio" property in the SPI dev node
should mean that the "cs-gpio" property in the controller-data node
should be used to signal the chip-select and having the "cs-gpio"
property in the SPI node should mean that the native chip select
should be used instead of a GPIO. That preserves the old DT binding
semantic while making the GPIO to be optional.
Of course in that case the property name does not make too much sense,
so probably should be changed to "cs-native" or something like that.
But I still don't understand why this is needed in the first place
since according to Documentation/devicetree/bindings/spi/spi-bus.txt
you can use the cs-gpios property to specify that a native chip-select
will be used instead of a GPIO by doing:
cs-gpios = <&gpio1 0 0> <0>
cs0 : &gpio1 0 0
cs1 : native
> Hence, SPI was failing on those boards.
>
> 1. As the SPI core and several drivers were changed to work with
> DT property "cs-gpios" (plural) defined under SPI node.
> 2. Since the commit 3146beec21b64f4551fcf0ac148381d54dc41b1b
> "spi: s3c64xx: Added provision for dedicated cs pin"
> Dated: Fri Jun 21 11:26:12 2013 +0530
>
> For the above 2 reasons, It was decided to drop the backward compatibility
> of using "cs-gpio"(singular) in controller-data.
> Instead, start supporting "cs-gpios"(plural) in the SPI node.
>
Right, since the DT binding has been broken for a year and because is
not consistent with the bindings used by all other SPI drivers, many
agreed that it was one of the exceptional cases where the DT binding
can be rethought and changed to use the generic "cs-gpios" property
already supported by SPI core. It breaks backward compatibility that's
true but the DT binding has been broken anyways and nobody noticed
before.
The other option is what I said above, fixing the DT binding
compatibility breakage while keeping the custom binding for this SPI
driver.
>>
>>> > Also I'd need to check but are you sure that GPIO 0 is not valid?
>>
>>> gpio_is_valid() returns true for
>>> "number >= 0 && number < ARCH_NR_GPIOS"
>>
>> Right, so this means that any board that is using the internal chip
>> select with zero as default in their platform data is broken by this
>> change.
>
I think this problem could be present in other SPI drivers as well? So
maybe the right fix for this is to convert the SPI core gpio handling
to use the new descriptor-based gpio API instead of the integer-base
one?
> using gpio_is_valid() to "sdd->cs_gpio" flag every where to check for the
> validity was a review comment.
> Which seems to fail for
Re: [PATCHv2 5/5] mmc: dw_mmc: replace "disable-wp" from slot's quirk to host's quirk
Hi, Seungwon.
On 07/07/2014 06:19 PM, Seungwon Jeon wrote:
> Sorry for late review.
Never mind. :)
> If you're in progress for next, please consider it.
>
> On Mon, June 30, 2014, Jaehoon Chung wrote:
>> Replaced the "disable-wp" into host's quirks.
>> (Because the slot-node is removed at dt-file.)
>>
>> Signed-off-by: Jaehoon Chung
>> ---
>> drivers/mmc/host/dw_mmc.c | 13 ++---
>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 1ac227c..6c5d696 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -994,10 +994,11 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
>> {
>> int read_only;
>> struct dw_mci_slot *slot = mmc_priv(mmc);
>> +struct dw_mci_board *brd = slot->host->pdata;
>> int gpio_ro = mmc_gpio_get_ro(mmc);
>>
>> /* Use platform get_ro function, else try on board write protect */
>> -if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
> It would be better to use host->quirks instead of brd->quirks
> It's finally updated with host->pdata->quirks on probing.
It's reasonable, i will fix it and resend.
Best Regards,
Jaehoon Chung
>
> Thanks,
> Seungwon Jeon
>
>
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] ARM: dts: exynos 3250: add hsotg and usb2phy device nodes
This patch adds device tree nodes required to enable support for USB
device controller.
Signed-off-by: Marek Szyprowski
---
Changelog:
v2:
- removed phandle to syscon, because mode switch register is not needed for
3250.
---
arch/arm/boot/dts/exynos3250.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index eb457620975b..64a0ef44325a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -309,6 +309,27 @@
status = "disabled";
};
+ hsotg: hsotg@1248 {
+ compatible = "samsung,s3c6400-hsotg";
+ reg = <0x1248 0x2>;
+ interrupts = <0 141 0>;
+ clocks = <&cmu CLK_USBOTG>;
+ clock-names = "otg";
+ phys = <&exynos_usbphy 0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ exynos_usbphy: exynos-usbphy@125B {
+ compatible = "samsung,exynos3250-usb2-phy";
+ reg = <0x125B 0x100>;
+ samsung,pmureg-phandle = <&pmu_system_controller>;
+ clocks = <&cmu CLK_USBOTG>, <&xusbxti>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
serial_0: serial@1380 {
compatible = "samsung,exynos4210-uart";
reg = <0x1380 0x100>;
--
1.9.2
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] drivers: phy: exynos-usb2: add support for Exynos 3250
This patch adds support for Exynos3250 SoC to Exynos2USB PHY driver.
Although Exynos3250 has only one device phy interface, the register
layout and all operations that are required to get it enabled are almost
same as on Exynos4x12. The only different is one more register
(REFCLKSEL) which need to be set and lack of MODE SWITCH register.
Signed-off-by: Marek Szyprowski
---
Changelog:
v2:
- added new binding documentation
- removed superfluous defines
- removed mode switch for 3250, because it is not really needed
---
Documentation/devicetree/bindings/phy/samsung-phy.txt | 2 ++
drivers/phy/Kconfig | 12 ++--
drivers/phy/phy-exynos4x12-usb2.c | 17 +++--
drivers/phy/phy-samsung-usb2.c| 6 ++
drivers/phy/phy-samsung-usb2.h| 2 ++
5 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 2049261d8c31..6099a5c94283 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -26,6 +26,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
Required properties:
- compatible : should be one of the listed compatibles:
+ - "samsung,exynos3250-usb2-phy"
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4x12-usb2-phy"
- "samsung,exynos5250-usb2-phy"
@@ -46,6 +47,7 @@ and Exynos 4212) it is as follows:
1 - USB host ("host"),
2 - HSIC0 ("hsic0"),
3 - HSIC1 ("hsic1"),
+Exynos3250 has only USB device phy available as phy 0.
Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
register is supplied.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f067c242..50bee8357a7f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -141,14 +141,14 @@ config PHY_EXYNOS4210_USB2
phys are available - device, host, HSIC0 and HSIC1.
config PHY_EXYNOS4X12_USB2
- bool "Support for Exynos 4x12"
+ bool "Support for Exynos 3250/4x12"
depends on PHY_SAMSUNG_USB2
- depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+ depends on (SOC_EXYNOS3250 || SOC_EXYNOS4212 || SOC_EXYNOS4412)
help
- Enable USB PHY support for Exynos 4x12. This option requires that
- Samsung USB 2.0 PHY driver is enabled and means that support for this
- particular SoC is compiled in the driver. In case of Exynos 4x12 four
- phys are available - device, host, HSIC0 and HSIC1.
+ Enable USB PHY support for Exynos 3250/4x12. This option requires
+ that Samsung USB 2.0 PHY driver is enabled and means that support for
+ this particular SoC is compiled in the driver. In case of Exynos 4x12
+ four phys are available - device, host, HSIC0 and HSIC1.
config PHY_EXYNOS5250_USB2
bool "Support for Exynos 5250"
diff --git a/drivers/phy/phy-exynos4x12-usb2.c
b/drivers/phy/phy-exynos4x12-usb2.c
index 59d8dd3ff390..f26ab22bc9c7 100644
--- a/drivers/phy/phy-exynos4x12-usb2.c
+++ b/drivers/phy/phy-exynos4x12-usb2.c
@@ -67,6 +67,8 @@
#define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
#define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
+#define EXYNOS_3250_UPHYCLK_REFCLKSEL (0x2 << 8)
+
#define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3)
#define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4)
#define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7)
@@ -197,6 +199,10 @@ static void exynos4x12_setup_clk(struct
samsung_usb2_phy_instance *inst)
clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK);
clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK;
+
+ if (drv->cfg->has_refclk_sel)
+ clk = EXYNOS_3250_UPHYCLK_REFCLKSEL;
+
clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET;
clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON;
writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
@@ -278,7 +284,7 @@ static int exynos4x12_power_on(struct
samsung_usb2_phy_instance *inst)
exynos4x12_power_on_internal(&drv->instances[EXYNOS4x12_DEVICE]);
}
- if (inst->cfg->id == EXYNOS4x12_DEVICE)
+ if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
EXYNOS_4x12_MODE_SWITCH_MASK,
EXYNOS_4x12_MODE_SWITCH_DEVICE);
@@ -310,7 +316,7 @@ static int exynos4x12_power_off(struct
samsung_usb2_phy_instance *inst)
if (inst->ext_cnt-- > 1)
return 0;
- if (inst->cfg->id == EXYNOS4x12_DEVICE)
+ if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
RE: [PATCHv2 5/5] mmc: dw_mmc: replace "disable-wp" from slot's quirk to host's quirk
Sorry for late review.
If you're in progress for next, please consider it.
On Mon, June 30, 2014, Jaehoon Chung wrote:
> Replaced the "disable-wp" into host's quirks.
> (Because the slot-node is removed at dt-file.)
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/mmc/host/dw_mmc.c | 13 ++---
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 1ac227c..6c5d696 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -994,10 +994,11 @@ static int dw_mci_get_ro(struct mmc_host *mmc)
> {
> int read_only;
> struct dw_mci_slot *slot = mmc_priv(mmc);
> + struct dw_mci_board *brd = slot->host->pdata;
> int gpio_ro = mmc_gpio_get_ro(mmc);
>
> /* Use platform get_ro function, else try on board write protect */
> - if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
It would be better to use host->quirks instead of brd->quirks
It's finally updated with host->pdata->quirks on probing.
Thanks,
Seungwon Jeon
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v5] spi: s3c64xx: fix broken "cs_gpios" usage in the driver
Hello Mark,
On 7 July 2014 13:02, Mark Brown wrote:
> On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote:
>> On 2 July 2014 22:26, Mark Brown wrote:
>> > On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
>
>> >> Hence, spi-s3c64xx.c is broken since "Jun 21 11:26:12 2013" and
>> >> considering the time with no compliants about the breakage.
>
>> > I'm not clear what the breakage is? Some boards are broken but what's
>> > the driver issue?
>
>> ToT was broken for few boards
>> exynos4412-trats2.dts, exynos4210-smdkv310.dts and exynos5250-smdk5250.dts
>
>> With some DTS changes SPI works well, spi-s3c64xx.c driver had no issues.
>
> No, you're not answering my question - to repeat, what is the breakage?
The Documentation/devicetree/bindings/spi/spi-samsung.txt
describes "cs-gpio" as a controller specific property.
The dts entries for SPI in exynos4412-trats2.dts, exynos4210-smdkv310.dts
and exynos5250-smdk5250.dts boards have the "cs-gpio" property defined
under controller-data node, which is inside the SPI device node
&spi_1 {
controller-data {
cs-gpio = <>;
};
};
But, _probe() of spi-s3c64xx.c driver looks for "cs-gpio" in the SPI
device node and
sets a flag "sdd->cs_gpio = false" (If the property is not available)
&spi_1 {
cs-gpio = <>;
};
the sdd->cs_gpio flag is checked before actually getting the gpios
from the controller-data node
if (sdd->cs_gpio)
cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
Hence, SPI was failing on those boards.
1. As the SPI core and several drivers were changed to work with
DT property "cs-gpios" (plural) defined under SPI node.
2. Since the commit 3146beec21b64f4551fcf0ac148381d54dc41b1b
"spi: s3c64xx: Added provision for dedicated cs pin"
Dated: Fri Jun 21 11:26:12 2013 +0530
For the above 2 reasons, It was decided to drop the backward compatibility
of using "cs-gpio"(singular) in controller-data.
Instead, start supporting "cs-gpios"(plural) in the SPI node.
>
>> > Also I'd need to check but are you sure that GPIO 0 is not valid?
>
>> gpio_is_valid() returns true for
>> "number >= 0 && number < ARCH_NR_GPIOS"
>
> Right, so this means that any board that is using the internal chip
> select with zero as default in their platform data is broken by this
> change.
using gpio_is_valid() to "sdd->cs_gpio" flag every where to check for the
validity was a review comment.
Which seems to fail for internal chip select with zero.
I can submit another version with"sdd->cs_gpio" flag for this purpose.
--
Thanks & Regards,
(: Nav :)
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3 v5] spi: s3c64xx: fix broken "cs_gpios" usage in the driver
On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote: > On 2 July 2014 22:26, Mark Brown wrote: > > On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote: > >> Hence, spi-s3c64xx.c is broken since "Jun 21 11:26:12 2013" and > >> considering the time with no compliants about the breakage. > > I'm not clear what the breakage is? Some boards are broken but what's > > the driver issue? > ToT was broken for few boards > exynos4412-trats2.dts, exynos4210-smdkv310.dts and exynos5250-smdk5250.dts > With some DTS changes SPI works well, spi-s3c64xx.c driver had no issues. No, you're not answering my question - to repeat, what is the breakage? > > Also I'd need to check but are you sure that GPIO 0 is not valid? > gpio_is_valid() returns true for > "number >= 0 && number < ARCH_NR_GPIOS" Right, so this means that any board that is using the internal chip select with zero as default in their platform data is broken by this change. signature.asc Description: Digital signature
Re: [PATCHv2 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc
Hi, Seungwon.
I will fix it, and add dt-file related with exynos3250.
Best Regards,
Jaehoon Chung
On 07/07/2014 04:29 PM, Seungwon Jeon wrote:
> Hi Jaehoon,
>
> Please check one thing below.
>
> On Mon, June 30, 2014, Jaehoon Chung wrote:
>> dw-mmc controller can support multiple slots.
>> But, there are no use-cases anywhere. So we don't need to support the
>> slot-node for dw-mmc controller.
>> And "supports-highspeed" property in dw-mmc is deprecated.
>> "supports-highspeed" property can be replaced to "cap-sd/mmc-highspeed".
>>
>> Signed-off-by: Jaehoon Chung
>> Reviewed-by: Tushar Behera
>> Reviewed-by: Ulf Hansson
>> ---
>
>> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
>> b/arch/arm/boot/dts/exynos5420-arndale-
>> octa.dts
>> index 434fd9d..5f37b81 100644
>> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
>> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
>> @@ -50,7 +50,6 @@
>> mmc@1220 {
>> status = "okay";
>> broken-cd;
>> -supports-highspeed;
>> card-detect-delay = <200>;
>> samsung,dw-mshc-ciu-div = <3>;
>> samsung,dw-mshc-sdr-timing = <0 4>;
>> @@ -58,16 +57,12 @@
>> pinctrl-names = "default";
>> pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
>> vmmc-supply = <&ldo10_reg>;
>> -
>> -slot@0 {
>> -reg = <0>;
>> -bus-width = <8>;
>> -};
>> +bus-width = <8>;
>> +cap-mmc-highspeed;
>> };
>>
>> mmc@1222 {
>> status = "okay";
>> -supports-highspeed;
>> card-detect-delay = <200>;
>> samsung,dw-mshc-ciu-div = <3>;
>> samsung,dw-mshc-sdr-timing = <2 3>;
>> @@ -75,11 +70,8 @@
>> pinctrl-names = "default";
>> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
>> vmmc-supply = <&ldo10_reg>;
>> -
>> -slot@0 {
>> -reg = <0>;
>> -bus-width = <4>;
>> -};
>> +bus-width = <8>;
> <4> is correct?
>
>> +cap-mmc-highspeed;
>
> Thanks,
> Seungwon Jeon
>
>
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHv2 2/5] ARM: dts: exynos: unuse the slot-node and deprecated the supports-highspeed for dw-mmc
Hi Jaehoon,
Please check one thing below.
On Mon, June 30, 2014, Jaehoon Chung wrote:
> dw-mmc controller can support multiple slots.
> But, there are no use-cases anywhere. So we don't need to support the
> slot-node for dw-mmc controller.
> And "supports-highspeed" property in dw-mmc is deprecated.
> "supports-highspeed" property can be replaced to "cap-sd/mmc-highspeed".
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Tushar Behera
> Reviewed-by: Ulf Hansson
> ---
> diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> b/arch/arm/boot/dts/exynos5420-arndale-
> octa.dts
> index 434fd9d..5f37b81 100644
> --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
> @@ -50,7 +50,6 @@
> mmc@1220 {
> status = "okay";
> broken-cd;
> - supports-highspeed;
> card-detect-delay = <200>;
> samsung,dw-mshc-ciu-div = <3>;
> samsung,dw-mshc-sdr-timing = <0 4>;
> @@ -58,16 +57,12 @@
> pinctrl-names = "default";
> pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
> vmmc-supply = <&ldo10_reg>;
> -
> - slot@0 {
> - reg = <0>;
> - bus-width = <8>;
> - };
> + bus-width = <8>;
> + cap-mmc-highspeed;
> };
>
> mmc@1222 {
> status = "okay";
> - supports-highspeed;
> card-detect-delay = <200>;
> samsung,dw-mshc-ciu-div = <3>;
> samsung,dw-mshc-sdr-timing = <2 3>;
> @@ -75,11 +70,8 @@
> pinctrl-names = "default";
> pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
> vmmc-supply = <&ldo10_reg>;
> -
> - slot@0 {
> - reg = <0>;
> - bus-width = <4>;
> - };
> + bus-width = <8>;
<4> is correct?
> + cap-mmc-highspeed;
Thanks,
Seungwon Jeon
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
