Re: [PATCH v3 3/5] pinctrl: exynos: add exynos5410 SoC specific data
Hi Andreas,
On 23.11.2014 07:26, Andreas Färber wrote:
From: Hakjoo Kim ruppi@hardkernel.com
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: Hakjoo Kim ruppi@hardkernel.com
[AF: Rebased onto Exynos5260 and irq_chip consolidation]
Signed-off-by: Andreas Färber afaer...@suse.de
---
v2 - v3:
* Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped)
v1 - v2:
* Filled in Sob from Hakjoo Kim
Any news on this patch? I'd like to ACK it, but apparently it is waiting
for a rebase.
Sorry for the delay, unfortunately things are a little bit busy on my
side nowadays.
Best regards,
Tomasz
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Re: [PATCH 01/19] pinctrl: exynos: Add support for Exynos5433
Hi Chanwoo,
On 27.11.2014 16:34, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 163 ++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 166 insertions(+)
Any plans for a respin? Apparently this patch needs a rebase. Also some
comments below.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 8e3e0c0..bd4c4ec 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1268,6 +1268,169 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos5433_pin_banks0[] = {
Maybe instead the structure could be named exynos5433_pin_bank_alive?
Similarly for remaining banks.
Also please, if not done already, please remember about documenting
alias IDs of particular controllers in DT binding documentation.
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static struct samsung_pin_bank exynos5433_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static struct samsung_pin_bank exynos5433_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(2, 0x000, gpv6, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static struct samsung_pin_bank exynos5433_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj2, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static struct samsung_pin_bank exynos5433_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpd5, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static struct samsung_pin_bank exynos5433_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gph1, 0x00),
+ EXYNOS_PIN_BANK_EINTG(7, 0x020, gpr4, 0x04),
+ EXYNOS_PIN_BANK_EINTG(5, 0x040, gpr0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpr2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpr3, 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static struct samsung_pin_bank exynos5433_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpf0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static struct samsung_pin_bank exynos5433_pin_banks7[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static struct samsung_pin_bank exynos5433_pin_banks8[] = {
+ EXYNOS_PIN_BANK_EINTG(6, 0x000, gpv7, 0x00),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x060, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x080, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0c0, gpg0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0e0, gpd0, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x100, gpd1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd2, 0x24),
+ EXYNOS_PIN_BANK_EINTG(5, 0x140, gpd4, 0x28),
+ EXYNOS_PIN_BANK_EINTG(2, 0x160, gpd8, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x180, gpd6, 0x30),
+ EXYNOS_PIN_BANK_EINTG(3, 0x1a0, gpd7, 0x34),
+ EXYNOS_PIN_BANK_EINTG(5, 0x1c0, gpg1, 0x38),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1e0, gpg2, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, gpg3, 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos5433_pin_banks9[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
Looks like four is a copy/paste error here.
Sorry for the delay. Unfortunately things are quite busy on my side
nowadays.
Best regards,
Tomasz
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Re: [PATCH V3 2/2] pinctrl: exynos: Add BUS1 pin controller for exynos7
On 10.12.2014 17:39, Vivek Gautam wrote: USB and Power regulator on Exynos7 require gpios available in BUS1 pin controller block. So adding the BUS1 pinctrl support. Signed-off-by: Naveen Krishna Ch naveenkrishna...@gmail.com Signed-off-by: Vivek Gautam gautam.vi...@samsung.com Cc: Tomasz Figa tomasz.f...@gmail.com Cc: Linus Walleij linus.wall...@linaro.org --- Changes since V2: - Added documentation on alias for BUS1 pin controller block. Changes since V1: - Added support for all pin banks which are part of BUS1 pin controller. .../devicetree/bindings/pinctrl/samsung-pinctrl.txt |1 + drivers/pinctrl/samsung/pinctrl-exynos.c| 19 +++ 2 files changed, 20 insertions(+) Acked-by: Tomasz Figa tomasz.f...@gmail.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] pinctrl: exynos: Add AUDIO pin controller for exynos7
On 19.12.2014 22:10, Padmavathi Venna wrote: Audio IPs on Exynos7 require gpios available in AUDIO pin controller block. So adding the AUDIO pinctrl support. Signed-off-by: Padmavathi Venna padm...@samsung.com --- .../bindings/pinctrl/samsung-pinctrl.txt |1 + drivers/pinctrl/samsung/pinctrl-exynos.c | 10 ++ 2 files changed, 11 insertions(+), 0 deletions(-) Acked-by: Tomasz Figa tomasz.f...@gmail.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 2/8] ARM: l2c: Refactor the driver to use commit-like interface
Nishanth, Tony, On 24.12.2014 02:13, Nishanth Menon wrote: On 12/23/2014 11:06 AM, Tony Lindgren wrote: * Marek Szyprowski m.szyprow...@samsung.com [141223 02:51]: From: Tomasz Figa t.f...@samsung.com Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes the .write_sec()-based interface insufficient and provoking ugly hacks. This patch is first step to make the driver not rely on availability of writes to individual registers. This is achieved by refactoring the driver to use a commit-like operation scheme: all register values are prepared first and stored in an instance of l2x0_regs struct and then a single callback is responsible to flush those values to the hardware. The first patch of the series applied things boot with no problem. But after applying this one I get the following on am437x: Unhandled fault: imprecise external abort (0xc06) at 0xb6f33884 Probably the same issue Nishanth mentioned. yep - just finished the bisect... came to the same conclusion.. c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f is the first bad commit commit c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f Author: Tomasz Figa t.f...@samsung.com Date: Tue Dec 23 11:48:30 2014 +0100 ARM: l2c: Refactor the driver to use commit-like interface Certain implementations of secure hypervisors (namely the one found on Samsung Exynos-based boards) do not provide access to individual L2C registers. This makes the .write_sec()-based interface insufficient and provoking ugly hacks. This patch is first step to make the driver not rely on availability of writes to individual registers. This is achieved by refactoring the driver to use a commit-like operation scheme: all register values are prepared first and stored in an instance of l2x0_regs struct and then a single callback is responsible to flush those values to the hardware. Signed-off-by: Tomasz Figa t.f...@samsung.com Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com :04 04 74c6c74a0dc0612d124cd759951adf2a1e4124ee 8082aabb474f8659231de744d87cd8dbd6dd79bb M arch $ git bisect log git bisect start # good: [97bf6af1f928216fd6c5a66e8a57bfa95a659672] Linux 3.19-rc1 git bisect good 97bf6af1f928216fd6c5a66e8a57bfa95a659672 # bad: [9afe195db6558621bd8bac379ed65ef121930684] ARM: dts: exynos4: Add nodes for L2 cache controller git bisect bad 9afe195db6558621bd8bac379ed65ef121930684 # bad: [0a89ef4dd870bbf692e30fef6c8182d7b8b42e17] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL git bisect bad 0a89ef4dd870bbf692e30fef6c8182d7b8b42e17 # bad: [c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f] ARM: l2c: Refactor the driver to use commit-like interface git bisect bad c8c3a07fa6a8e9b27a1658e0d305b6f7e0fa068f # good: [080ab387c653b8655dc1ee790658b618399db2aa] ARM: OMAP2+: use common l2cache initialization code git bisect good 080ab387c653b8655dc1ee790658b618399db2aa May I ask you (or anyone else working on OMAP) to try to figure out what the issue is? It is stopping L2 cache support for Exynos4 being merged and Exynos people don't have access to any of affected boards to do anything about it. After all, this is generic code, so I believe community should cooperate with pushing it forward. (Of course I understand it is a holiday season at the moment, so I don't expect any solution right at this moment :)) Apparently patch 1/8 solved problems with some of the boards. Could you check how those boards differ and look for potential causes? Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/19] pinctrl: exynos: Add support for Exynos5433
Hi Tomasz,
On 12/28/2014 08:21 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 27.11.2014 16:34, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228
multi-
functional input/output port pins and 135 memory port pins. There are 41
general
port groups and 2 memory port groups.
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Thomas Abraham thomas.abra...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
drivers/pinctrl/samsung/pinctrl-exynos.c | 163
++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 166 insertions(+)
Any plans for a respin? Apparently this patch needs a rebase. Also some
comments below.
I'll rebase it on latest kernel and re-send it on next time.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 8e3e0c0..bd4c4ec 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1268,6 +1268,169 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
},
};
+/* pin banks of exynos5433 pin-controller - ALIVE */
+static struct samsung_pin_bank exynos5433_pin_banks0[] = {
Maybe instead the structure could be named exynos5433_pin_bank_alive?
Similarly for remaining banks.
Also please, if not done already, please remember about documenting alias IDs
of particular controllers in DT binding documentation.
+EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos5433 pin-controller - AUD */
+static struct samsung_pin_bank exynos5433_pin_banks1[] = {
+EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos5433 pin-controller - CPIF */
+static struct samsung_pin_bank exynos5433_pin_banks2[] = {
+EXYNOS_PIN_BANK_EINTG(2, 0x000, gpv6, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - eSE */
+static struct samsung_pin_bank exynos5433_pin_banks3[] = {
+EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj2, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FINGER */
+static struct samsung_pin_bank exynos5433_pin_banks4[] = {
+EXYNOS_PIN_BANK_EINTG(4, 0x000, gpd5, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - FSYS */
+static struct samsung_pin_bank exynos5433_pin_banks5[] = {
+EXYNOS_PIN_BANK_EINTG(6, 0x000, gph1, 0x00),
+EXYNOS_PIN_BANK_EINTG(7, 0x020, gpr4, 0x04),
+EXYNOS_PIN_BANK_EINTG(5, 0x040, gpr0, 0x08),
+EXYNOS_PIN_BANK_EINTG(8, 0x060, gpr1, 0x0c),
+EXYNOS_PIN_BANK_EINTG(2, 0x080, gpr2, 0x10),
+EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpr3, 0x14),
+};
+
+/* pin banks of exynos5433 pin-controller - IMEM */
+static struct samsung_pin_bank exynos5433_pin_banks6[] = {
+EXYNOS_PIN_BANK_EINTG(8, 0x000, gpf0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - NFC */
+static struct samsung_pin_bank exynos5433_pin_banks7[] = {
+EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos5433 pin-controller - PERIC */
+static struct samsung_pin_bank exynos5433_pin_banks8[] = {
+EXYNOS_PIN_BANK_EINTG(6, 0x000, gpv7, 0x00),
+EXYNOS_PIN_BANK_EINTG(5, 0x020, gpb0, 0x04),
+EXYNOS_PIN_BANK_EINTG(8, 0x040, gpc0, 0x08),
+EXYNOS_PIN_BANK_EINTG(2, 0x060, gpc1, 0x0c),
+EXYNOS_PIN_BANK_EINTG(6, 0x080, gpc2, 0x10),
+EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpc3, 0x14),
+EXYNOS_PIN_BANK_EINTG(2, 0x0c0, gpg0, 0x18),
+EXYNOS_PIN_BANK_EINTG(4, 0x0e0, gpd0, 0x1c),
+EXYNOS_PIN_BANK_EINTG(6, 0x100, gpd1, 0x20),
+EXYNOS_PIN_BANK_EINTG(8, 0x120, gpd2, 0x24),
+EXYNOS_PIN_BANK_EINTG(5, 0x140, gpd4, 0x28),
+EXYNOS_PIN_BANK_EINTG(2, 0x160, gpd8, 0x2c),
+EXYNOS_PIN_BANK_EINTG(7, 0x180, gpd6, 0x30),
+EXYNOS_PIN_BANK_EINTG(3, 0x1a0, gpd7, 0x34),
+EXYNOS_PIN_BANK_EINTG(5, 0x1c0, gpg1, 0x38),
+EXYNOS_PIN_BANK_EINTG(2, 0x1e0, gpg2, 0x3c),
+EXYNOS_PIN_BANK_EINTG(8, 0x200, gpg3, 0x40),
+};
+
+/* pin banks of exynos5433 pin-controller - TOUCH */
+static struct samsung_pin_bank exynos5433_pin_banks9[] = {
+EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
Looks like four is a copy/paste error here.
Mistake. I'll fix it.
Best Regards,
Chanwoo Choi
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[PATCHv6 2/9] devfreq: event: Add the list of supported devfreq-event type
This patch adds the list of supported devfreq-event type as following.
Each devfreq-event device driver would support the various devfreq-event type
for devfreq governor at the same time.
- DEVFREQ_EVENT_TYPE_RAW_DATA
- DEVFREQ_EVENT_TYPE_UTILIZATION
- DEVFREQ_EVENT_TYPE_BANDWIDTH
- DEVFREQ_EVENT_TYPE_LATENCY
Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/devfreq/devfreq-event.c | 58 -
include/linux/devfreq-event.h | 25 +++---
2 files changed, 73 insertions(+), 10 deletions(-)
diff --git a/drivers/devfreq/devfreq-event.c b/drivers/devfreq/devfreq-event.c
index 81448ba..64c1764 100644
--- a/drivers/devfreq/devfreq-event.c
+++ b/drivers/devfreq/devfreq-event.c
@@ -20,6 +20,9 @@
#include linux/list.h
#include linux/of.h
+#define EVENT_TYPE_RAW_DATA_MAXULONG_MAX
+#define EVENT_TYPE_UTILIZATION_MAX 100
+
static struct class *devfreq_event_class;
/* The list of all devfreq event list */
@@ -132,7 +135,8 @@ EXPORT_SYMBOL_GPL(devfreq_event_is_enabled);
* Note that this function set the event to the devfreq-event device to start
* for getting the event data which could be various event type.
*/
-int devfreq_event_set_event(struct devfreq_event_dev *edev)
+int devfreq_event_set_event(struct devfreq_event_dev *edev,
+ enum devfreq_event_type type)
{
int ret;
@@ -146,7 +150,15 @@ int devfreq_event_set_event(struct devfreq_event_dev *edev)
return -EPERM;
mutex_lock(edev-lock);
- ret = edev-desc-ops-set_event(edev);
+
+ if ((edev-desc-type type) == 0) {
+ dev_err(edev-dev, unsupported devfreq-event type\n);
+ mutex_unlock(edev-lock);
+ return -EINVAL;
+ }
+
+ ret = edev-desc-ops-set_event(edev, type);
+
mutex_unlock(edev-lock);
return ret;
@@ -162,6 +174,7 @@ EXPORT_SYMBOL_GPL(devfreq_event_set_event);
* after stoping the progress of whole sequence of devfreq-event dev.
*/
int devfreq_event_get_event(struct devfreq_event_dev *edev,
+ enum devfreq_event_type type,
struct devfreq_event_data *edata)
{
int ret;
@@ -175,18 +188,49 @@ int devfreq_event_get_event(struct devfreq_event_dev
*edev,
if (!devfreq_event_is_enabled(edev))
return -EINVAL;
+ mutex_lock(edev-lock);
+
+ if ((edev-desc-type type) == 0) {
+ dev_err(edev-dev, unsupported devfreq-event type\n);
+ return -EINVAL;
+ }
+
edata-event = edata-total_event = 0;
+ ret = edev-desc-ops-get_event(edev, type, edata);
+ if (ret 0
+ || edata-total_event = 0
+ || edata-event edata-total_event) {
+ edata-event = edata-total_event = 0;
+ mutex_unlock(edev-lock);
+ return -EINVAL;
+ }
- mutex_lock(edev-lock);
- ret = edev-desc-ops-get_event(edev, edata);
- mutex_unlock(edev-lock);
+ switch (type) {
+ case DEVFREQ_EVENT_TYPE_RAW_DATA:
+ case DEVFREQ_EVENT_TYPE_BANDWIDTH:
+ case DEVFREQ_EVENT_TYPE_LATENCY:
+ if ((edata-event EVENT_TYPE_RAW_DATA_MAX) ||
+ (edata-total_event EVENT_TYPE_RAW_DATA_MAX)) {
+ edata-event = edata-total_event = 0;
+ ret = -EINVAL;
+ }
+ break;
+ case DEVFREQ_EVENT_TYPE_UTILIZATION:
+ edata-total_event = EVENT_TYPE_UTILIZATION_MAX;
- if ((edata-total_event = 0)
- || (edata-event edata-total_event)) {
+ if (edata-event EVENT_TYPE_UTILIZATION_MAX) {
+ edata-event = edata-total_event = 0;
+ ret = -EINVAL;
+ }
+ break;
+ default:
edata-event = edata-total_event = 0;
ret = -EINVAL;
+ break;
}
+ mutex_unlock(edev-lock);
+
return ret;
}
EXPORT_SYMBOL_GPL(devfreq_event_get_event);
diff --git a/include/linux/devfreq-event.h b/include/linux/devfreq-event.h
index 6023be8..6b86c1d 100644
--- a/include/linux/devfreq-event.h
+++ b/include/linux/devfreq-event.h
@@ -36,6 +36,14 @@ struct devfreq_event_dev {
const struct devfreq_event_desc *desc;
};
+/* The supported type by devfreq-event device */
+enum devfreq_event_type {
+ DEVFREQ_EVENT_TYPE_RAW_DATA = BIT(0),
+ DEVFREQ_EVENT_TYPE_UTILIZATION = BIT(1),
+ DEVFREQ_EVENT_TYPE_BANDWIDTH= BIT(2),
+ DEVFREQ_EVENT_TYPE_LATENCY = BIT(3),
+};
+
/**
* struct devfreq_event_data - the devfreq-event data
*
@@ -69,8 +77,10 @@ struct devfreq_event_ops {
int (*reset)(struct devfreq_event_dev *edev);
/* Mandatory functions */
-
[PATCHv6 0/9] devfreq: Add devfreq-event class to provide raw data for devfreq device
This patchset add new devfreq_event class to provide raw data to determine current utilization of device which is used for devfreq governor. [Description of devfreq-event class] This patchset add new devfreq_event class for devfreq_event device which provide raw data (e.g., memory bus utilization/GPU utilization). This raw data from devfreq_event data would be used for the governor of devfreq subsystem. - devfreq_event device : Provide raw data for governor of existing devfreq device - devfreq device : Monitor device state and change frequency/voltage of device using the raw data from devfreq_event device The devfreq subsystem support generic DVFS(Dynamic Voltage/Frequency Scaling) for Non-CPU Devices. The devfreq device would dertermine current device state using various governor (e.g., ondemand, performance, powersave). After completed determination of system state, devfreq device would change the frequency/voltage of devfreq device according to the result of governor. But, devfreq governor must need basic data which indicates current device state. Existing devfreq subsystem only consider devfreq device which check current system state and determine proper system state using basic data. There is no subsystem for device providing basic data to devfreq device. The devfreq subsystem must need devfreq_event device(data-provider device) for existing devfreq device. So, this patch add new devfreq_event class for devfreq_event device which read various basic data(e.g, memory bus utilization, GPU utilization) and provide measured data to existing devfreq device through standard APIs of devfreq_event class. The following description explains the feature of two kind of devfreq class: - devfreq class (existing) : devfreq consumer device use raw data from devfreq_event device for determining proper current system state and change voltage/frequency dynamically using various governors. - devfreq_event class (new) : Provide measured raw data to devfreq device for governor Also, the devfreq-event device would support various type event as following: : DEVFREQ_EVENT_TYPE_RAW_DATA : DEVFREQ_EVENT_TYPE_UTILIZATION : DEVFREQ_EVENT_TYPE_BANDWIDTH : DEVFREQ_EVENT_TYPE_LATENCY [For example] If board dts includes PPMU_DMC0/DMC1/LEFTBUS/RIGHTBUS event node, would show following sysfs entry. Also devfreq driver(e.g., exynos4_bus.c) can get the instance of devfreq-event device by using provided API and then get raw data which reflect the current state of device. -sh-3.2# cd /sys/class/devfreq-event/ -sh-3.2# ls -al total 0 drwxr-xr-x 2 root root 0 Jan 9 16:47 . drwxr-xr-x 37 root root 0 Jan 9 16:47 .. lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.0 - ../../devices/soc/106a.ppmu_dmc0/devfreq-event/event.0 lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.1 - ../../devices/soc/106b.ppmu_dmc1/devfreq-event/event.1 lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.2 - ../../devices/soc/112a.ppmu_rightbus/devfreq-event/event.2 lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.3 - ../../devices/soc/116a.ppmu_leftbus0/devfreq-event/event.3 Changes from v5: - Rebase these patch-set on v3.19-rc1 and Test it. 1. exynos-ppmu.c - Change the error value when of_iomap() fail to map the memory - Remove owner setting of platform_driver - Add exynos_ppmu_disable() function 2. exynos dts file - Add PPMU node to Exynos3250-based Monk board - Remove ppmu_cpu node on Exynos4412-based TRATS2 board and add ppmu_leftbus/rightbus node Changes from v4: 1. devfreq-event class driver - Add devfreq_event_get_edev_count() function - Modify the simple description of devfreq-event framework in devfreq-event.c - Minimize the usage range of global lock usage in devfreq_event_add_edev() - Remove '_is_enabled()' function pointer in devfreq_event_ops structure - Add separte CONFIG_PM_DEVFREQ_EVENT configuration - Add new devfreq-event.h header file including devfreq-event helper functions 2. exynos dts file - Add new patch to support PPMU with DEVFREQ-event on Exynos4412-based TRATS2 Changes from v3: 1. devfreq-event class driver - Fix return value of devfreq_event_get_event() - Add new structure devfreq_event_data for devfreq_event_get_event() - Modify the prototype of devfreq_event_get_event() function - Call of_node_put after calling of_parse_phandle() to decrement refcount 2. exynos-ppmu driver - Modify usage of devfreq_event_get_event() function according to new prototype of this funciton - Add the additional description to exynos-ppmu.txt how to add PPMU node in board dts file - Use 'PPMU_EVENT' macro to remove duplicate codes - Add the support of PPMU for Exynos5260 3. exynos dts file - Add missing PPMU_FSYS node to exynos3250.dtsi - Fix 'ppmu_mfc_l' node name as 'ppmu_mfc' because exynos3250 has only one MFC IP. - Add missing PPMU_ACP/G3D to exynos4.dtsi 4. etc - Fix wrong abbreviation of PPMU (PPMU :Platform Performance Monitoring Unit) - Add new patch to support the PPMU of Exynos5260
[PATCHv6 6/9] ARM: dts: Add PPMU dt node for Exynos4 SoCs
This patch add PPMU (Platform Performance Monitoring Unit) dt node for Exynos4
(Exynos4210/4212/4412) SoC. PPMU dt node is used to monitor the utilization of
each IP.
The Exynos4210/Exynos4212/Exynos4412 SoC includes following PPMUs:
- PPMU_DMC0 0x106A_
- PPMU_DMC1 0x106B_
- PPMU_CPU 0x106C_
- PPMU_ACP 0x10AE_
- PPMU_RIGHT_BUS 0x112A_
- PPMU_LEFT_BUS 0x116A_
- PPMU_FSYS 0x1263_
- PPMU_LCD0 0x11E4_
- PPMU_CAMIF 0x11AC_
- PPMU_IMAGE 0x12AA_
- PPMU_TV0x12E4_
- PPMU_3D0x1322_
- PPMU_MFC_LEFT 0x1366_
- PPMU_MFC_RIGHT 0x1367_
Additionally, the Exynos4210 SoC includes following PPMUs:
- PPMU_LCD1 0x1224_
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos4.dtsi| 108 ++
arch/arm/boot/dts/exynos4210.dtsi | 8 +++
2 files changed, 116 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8168f1..70064dc 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -645,4 +645,112 @@
samsung,sysreg = sys_reg;
status = disabled;
};
+
+ ppmu_dmc0: ppmu_dmc0@106a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106a 0x2000;
+ clocks = clock CLK_PPMUDMC0;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_dmc1: ppmu_dmc1@106b {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106b 0x2000;
+ clocks = clock CLK_PPMUDMC1;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_cpu: ppmu_cpu@106c {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106c 0x2000;
+ clocks = clock CLK_PPMUCPU;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_acp: ppmu_acp@10ae {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106e 0x2000;
+ status = disabled;
+ };
+
+ ppmu_rightbus: ppmu_rightbus@112a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x112a 0x2000;
+ clocks = clock CLK_PPMURIGHT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_leftbus: ppmu_leftbus0@116a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x116a 0x2000;
+ clocks = clock CLK_PPMULEFT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_camif: ppmu_camif@11ac {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x11ac 0x2000;
+ clocks = clock CLK_PPMUCAMIF;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_lcd0: ppmu_lcd0@11e4 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x11e4 0x2000;
+ clocks = clock CLK_PPMULCD0;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_fsys: ppmu_g3d@1263 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1263 0x2000;
+ status = disabled;
+ };
+
+ ppmu_image: ppmu_image@12aa {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x12aa 0x2000;
+ clocks = clock CLK_PPMUIMAGE;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_tv: ppmu_tv@12e4 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x12e4 0x2000;
+ clocks = clock CLK_PPMUTV;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_g3d: ppmu_g3d@1322 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1322 0x2000;
+ clocks = clock CLK_PPMUG3D;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_mfc_left: ppmu_mfc_left@1366 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1366 0x2000;
+ clocks = clock CLK_PPMUMFC_L;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_mfc_right: ppmu_mfc_right@1367 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1367 0x2000;
+ clocks = clock CLK_PPMUMFC_R;
+ clock-names = ppmu;
+ status = disabled;
+ };
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..b2598de 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -192,4 +192,12 @@
[PATCHv6 1/9] devfreq: event: Add new devfreq_event class to provide basic data for devfreq governor
This patch add new devfreq_event class for devfreq_event device which provide raw data (e.g., memory bus utilization/GPU utilization). This raw data from devfreq_event data would be used for the governor of devfreq subsystem. - devfreq_event device : Provide raw data for governor of existing devfreq device - devfreq device : Monitor device state and change frequency/voltage of device using the raw data from devfreq_event device The devfreq subsystem support generic DVFS(Dynamic Voltage/Frequency Scaling) for Non-CPU Devices. The devfreq device would dertermine current device state using various governor (e.g., ondemand, performance, powersave). After completed determination of system state, devfreq device would change the frequency/voltage of devfreq device according to the result of governor. But, devfreq governor must need basic data which indicates current device state. Existing devfreq subsystem only consider devfreq device which check current system state and determine proper system state using basic data. There is no subsystem for device providing basic data to devfreq device. The devfreq subsystem must need devfreq_event device(data-provider device) for existing devfreq device. So, this patch add new devfreq_event class for devfreq_event device which read various basic data(e.g, memory bus utilization, GPU utilization) and provide measured data to existing devfreq device through standard APIs of devfreq_event class. The following description explains the feature of two kind of devfreq class: - devfreq class (existing) : devfreq consumer device use raw data from devfreq_event device for determining proper current system state and change voltage/frequency dynamically using various governors. - devfreq_event class (new) : Provide measured raw data to devfreq device for governor Cc: MyungJoo Ham myungjoo@samsung.com Cc: Kyungmin Park kyungmin.p...@samsung.com Signed-off-by: Chanwoo Choi cw00.c...@samsung.com --- drivers/devfreq/Kconfig | 2 + drivers/devfreq/Makefile| 6 +- drivers/devfreq/devfreq-event.c | 466 drivers/devfreq/event/Kconfig | 16 ++ drivers/devfreq/event/Makefile | 1 + include/linux/devfreq-event.h | 170 +++ 6 files changed, 660 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/devfreq-event.c create mode 100644 drivers/devfreq/event/Kconfig create mode 100644 drivers/devfreq/event/Makefile create mode 100644 include/linux/devfreq-event.h diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index faf4e70..21f8f17 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -87,4 +87,6 @@ config ARM_EXYNOS5_BUS_DEVFREQ It reads PPMU counters of memory controllers and adjusts the operating frequencies and voltages with OPP support. +source drivers/devfreq/event/Kconfig + endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 16138c9..c449336 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -1,4 +1,5 @@ -obj-$(CONFIG_PM_DEVFREQ) += devfreq.o +obj-$(CONFIG_PM_DEVFREQ) += devfreq.o +obj-$(CONFIG_PM_DEVFREQ_EVENT) += devfreq-event.o obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) += governor_simpleondemand.o obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)+= governor_powersave.o @@ -7,3 +8,6 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ + +# DEVFREQ Event Drivers +obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/devfreq-event.c b/drivers/devfreq/devfreq-event.c new file mode 100644 index 000..81448ba --- /dev/null +++ b/drivers/devfreq/devfreq-event.c @@ -0,0 +1,466 @@ +/* + * devfreq-event: a framework to provide raw data and events of devfreq devices + * + * Copyright (C) 2014 Samsung Electronics + * Author: Chanwoo Choi cw00.c...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This driver is based on drivers/devfreq/devfreq.c. + */ + +#include linux/devfreq-event.h +#include linux/kernel.h +#include linux/err.h +#include linux/init.h +#include linux/module.h +#include linux/slab.h +#include linux/list.h +#include linux/of.h + +static struct class *devfreq_event_class; + +/* The list of all devfreq event list */ +static LIST_HEAD(devfreq_event_list); +static DEFINE_MUTEX(devfreq_event_list_lock); + +#define to_devfreq_event(DEV) container_of(DEV, struct devfreq_event_dev, dev) + +/** + * devfreq_event_enable_edev() - Enable the devfreq-event dev and increase + * the enable_count of
[PATCHv6 3/9] devfreq: event: Add exynos-ppmu devfreq-event driver
This patch adds exynos-ppmu devfreq-event driver to get performance data
of each IP for Samsung Exynos SoC. These event from Exynos PPMU provide
useful information about the behavior of the SoC that you can use when
analyzing system performance, and made visible and can be counted using
logic in each IP.
This patch is based on existing drivers/devfreq/exynos/exynos-ppmu.c
Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/devfreq/event/Kconfig | 9 +
drivers/devfreq/event/Makefile | 1 +
drivers/devfreq/event/exynos-ppmu.c | 410
3 files changed, 420 insertions(+)
create mode 100644 drivers/devfreq/event/exynos-ppmu.c
diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
index 1ced42c..a11720a 100644
--- a/drivers/devfreq/event/Kconfig
+++ b/drivers/devfreq/event/Kconfig
@@ -13,4 +13,13 @@ menuconfig PM_DEVFREQ_EVENT
if PM_DEVFREQ_EVENT
+config DEVFREQ_EVENT_EXYNOS_PPMU
+ bool EXYNOS PPMU (Platform Performance Monitoring Unit) DEVFREQ event
Driver
+ depends on ARCH_EXYNOS
+ select PM_OPP
+ help
+ This add the devfreq-event driver for Exynos SoC. It provides PPMU
+ (Platform Performance Monitoring Unit) counters to estimate the
+ utilization of each module.
+
endif # PM_DEVFREQ_EVENT
diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
index dc56005..be146ea 100644
--- a/drivers/devfreq/event/Makefile
+++ b/drivers/devfreq/event/Makefile
@@ -1 +1,2 @@
# Exynos DEVFREQ Event Drivers
+obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
diff --git a/drivers/devfreq/event/exynos-ppmu.c
b/drivers/devfreq/event/exynos-ppmu.c
new file mode 100644
index 000..2d417a1
--- /dev/null
+++ b/drivers/devfreq/event/exynos-ppmu.c
@@ -0,0 +1,410 @@
+/*
+ * exynos_ppmu.c - EXYNOS PPMU (Platform Performance Monitoring Unit) support
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author : Chanwoo Choi cw00.c...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver is based on drivers/devfreq/exynos/exynos_ppmu.c
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of_address.h
+#include linux/platform_device.h
+#include linux/suspend.h
+#include linux/devfreq-event.h
+
+#define PPMU_ENABLE BIT(0)
+#define PPMU_DISABLE0x0
+#define PPMU_CYCLE_RESETBIT(1)
+#define PPMU_COUNTER_RESET BIT(2)
+
+#define PPMU_ENABLE_COUNT0 BIT(0)
+#define PPMU_ENABLE_COUNT1 BIT(1)
+#define PPMU_ENABLE_COUNT2 BIT(2)
+#define PPMU_ENABLE_COUNT3 BIT(3)
+#define PPMU_ENABLE_CYCLE BIT(31)
+
+#define PPMU_CNTENS0x10
+#define PPMU_FLAG 0x50
+#define PPMU_CCNT_OVERFLOW BIT(31)
+#define PPMU_CCNT 0x100
+
+#define PPMU_PMCNT00x110
+#define PPMU_PMCNT_OFFSET 0x10
+#define PMCNT_OFFSET(x)(PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x))
+
+#define PPMU_BEVT0SEL 0x1000
+#define PPMU_BEVTSEL_OFFSET0x100
+#define PPMU_BEVTSEL(x)(PPMU_BEVT0SEL + (x *
PPMU_BEVTSEL_OFFSET))
+
+#define RD_DATA_COUNT 0x5
+#define WR_DATA_COUNT 0x6
+#define RDWR_DATA_COUNT0x7
+
+enum ppmu_counter {
+ PPMU_PMNCNT0 = 0,
+ PPMU_PMNCNT1,
+ PPMU_PMNCNT2,
+ PPMU_PMNCNT3,
+
+ PPMU_PMNCNT_MAX,
+};
+
+struct exynos_ppmu_data {
+ struct devfreq_event_dev **edev;
+ struct devfreq_event_desc *desc;
+ unsigned int num_events;
+
+ struct device *dev;
+ struct clk *clk_ppmu;
+ struct mutex lock;
+
+ struct __exynos_ppmu {
+ void __iomem *base;
+ unsigned int event[PPMU_PMNCNT_MAX];
+ unsigned int count[PPMU_PMNCNT_MAX];
+ bool ccnt_overflow;
+ bool count_overflow[PPMU_PMNCNT_MAX];
+ } ppmu;
+};
+
+#define PPMU_EVENT(name) \
+ { ppmu-event0-#name, PPMU_PMNCNT0 }, \
+ { ppmu-event1-#name, PPMU_PMNCNT1 }, \
+ { ppmu-event2-#name, PPMU_PMNCNT2 }, \
+ { ppmu-event3-#name, PPMU_PMNCNT3 }
+
+struct __exynos_ppmu_events {
+ char *name;
+ int id;
+} ppmu_events[] = {
+ /* For Exynos3250, Exynos4 and Exynos5260 */
+ PPMU_EVENT(g3d),
+ PPMU_EVENT(fsys),
+
+ /* For Exynos4 SoCs and Exynos3250 */
+ PPMU_EVENT(dmc0),
+ PPMU_EVENT(dmc1),
+ PPMU_EVENT(cpu),
+ PPMU_EVENT(rightbus),
+ PPMU_EVENT(leftbus),
+ PPMU_EVENT(lcd0),
+ PPMU_EVENT(camif),
+
+ /* Only for Exynos3250 and Exynos5260 */
+ PPMU_EVENT(mfc),
+
+ /*
[PATCHv6 9/9] ARM: dts: exynos: Add PPMU node for Exynos4412-based TRATS2 board
This patch add dt node for PPMU_{DMC0|DMC1|LEFTBUS|RIGHTBUS} for
exynos4412-trats2 board. Each PPMU dt node includes one event of 'PPMU Count3'.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos4412-trats2.dts | 40 +
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index c9b70b6..bee0eed 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -877,6 +877,46 @@
};
};
+ppmu_dmc0 {
+ status = okay;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = ppmu-event3-dmc0;
+ };
+ };
+};
+
+ppmu_dmc1 {
+ status = okay;
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = ppmu-event3-dmc1;
+ };
+ };
+};
+
+ppmu_leftbus {
+ status = okay;
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = ppmu-event3-leftbus;
+ };
+ };
+};
+
+ppmu_rightbus {
+ status = okay;
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = ppmu-event3-rightbus;
+ };
+ };
+};
+
pinctrl_0 {
pinctrl-names = default;
pinctrl-0 = sleep0;
--
1.8.5.5
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[PATCHv6 7/9] ARM: dts: Add PPMU dt node for Exynos5260 SoC
This patch adds PPMU (Performance Profiling Monitoring Unit) dt node
Exynos5260 SoC.
Exynos5260 SoC has following PPMU IPs:
- PPMU_DREX0_S0 0x10c6
- PPMU_DREX0_S1 0x10c7
- PPMU_DREX1_S0 0x10c8
- PPMU_DREX1_S1 0x10c9
- PPMU_EAGLE0x10cc
- PPMU_KFC 0x10cd
- PPMU_MFC 0x1104
- PPMU_G3D 0x1188
- PPMU_FSYS 0x1222
- PPMU_ISP 0x1337
- PPMU_FICM 0x13cb
- PPMU_GSCL 0x13e6
- PPMU_MSCL 0x13ee
- PPMU_FIMD0X 0x145b
- PPMU_FIMD1X 0x145c
The drivers/devfreq/exynos/exynos5_bus.c supports the memory bus frequency/
voltage scaling of Exynos5260 SoC with DEVFREQ framework.
Cc: Kukjin Kim kgene@samsung.com
Cc: Abhilash Kesavan a.kesa...@samsung.com
Cc: Jonghwan Choi jhbird.c...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
arch/arm/boot/dts/exynos5260.dtsi | 90 +++
1 file changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5260.dtsi
b/arch/arm/boot/dts/exynos5260.dtsi
index 36da38e..26f3074 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -307,6 +307,96 @@
fifo-depth = 64;
status = disabled;
};
+
+ ppmu_drex0_s0: ppmu_drex0_s0@10c6 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10c6 0x2000;
+ status = disabled;
+ };
+
+ ppmu_drex0_s1: ppmu_drex0_s1@10c7 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10c7 0x2000;
+ status = disabled;
+ };
+
+ ppmu_drex1_s0: ppmu_drex1_s0@10c8 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10c8 0x2000;
+ status = disabled;
+ };
+
+ ppmu_drex1_s1: ppmu_drex1_s1@10c9 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10c9 0x2000;
+ status = disabled;
+ };
+
+ ppmu_eagle: ppmu_eagle@10cc {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10cc 0x2000;
+ status = disabled;
+ };
+
+ ppmu_kfc: ppmu_kfc@10cd {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x10cd 0x2000;
+ status = disabled;
+ };
+
+ ppmu_mfc: ppmu_mfc@1104 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1104 0x2000;
+ status = disabled;
+ };
+
+ ppmu_g3d: ppmu_g3d@1188 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1188 0x2000;
+ status = disabled;
+ };
+
+ ppmu_fsys: ppmu_fsys@1222 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1222 0x2000;
+ status = disabled;
+ };
+
+ ppmu_isp: ppmu_isp@1337 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1337 0x2000;
+ status = disabled;
+ };
+
+ ppmu_fimc: ppmu_fimc@13cb {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x13cb 0x2000;
+ status = disabled;
+ };
+
+ ppmu_gscl: ppmu_gscl@13e6 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x13e6 0x2000;
+ status = disabled;
+ };
+
+ ppmu_mscl: ppmu_gscl@13ee {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x13ee 0x2000;
+ status = disabled;
+ };
+
+ ppmu_fimd0x: ppmu_fimd0x@145b {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x145b 0x2000;
+ status = disabled;
+ };
+
+ ppmu_fimd1x: ppmu_fimd1x@145c {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x145c 0x2000;
+ status = disabled;
+ };
};
};
--
1.8.5.5
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[PATCHv6 4/9] devfreq: event: Add documentation for exynos-ppmu devfreq-event driver
This patch adds the documentation for Exynos PPMU (Platform Performance
Monitoring Unit) devfreq-event driver.
Cc: MyungJoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
.../bindings/devfreq/event/exynos-ppmu.txt | 110 +
1 file changed, 110 insertions(+)
create mode 100644
Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
diff --git a/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
b/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
new file mode 100644
index 000..e665d30
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/exynos-ppmu.txt
@@ -0,0 +1,110 @@
+
+* Samsung Exynos PPMU (Performance Profiling Monitoring Unit) device
+
+The Samsung Exynos SoC have PPMU (Performance Profiling Monitoring Unit) for
+each IPs. PPMU provides the primitive values to get performance data. These
+events provide useful information about the behavior of the SoC that you can
+use when analyzing system performance, and made visible and can be counted
+using login in each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D,
+MFC). The Exynos PPMU driver use the devfreq-event class to provide event data
+to various devfreq device. The devfreq device would use the event data when
+derterming the current state of each IP.
+
+Required properties:
+- compatible: Should be samsung,exynos-ppmu.
+- reg: physical base address of each PPMU and length of memory mapped region.
+
+Optional properties:
+- clock-names : the name of clock used by the PPMU, ppmu
+- clocks : phandles for clock specified in clock-names property
+- #clock-cells: should be 1.
+
+Example1 : PPMU nodes in exynos3250.dtsi are listed below.
+
+ ppmu_dmc0: ppmu_dmc0@106a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106a 0x2000;
+ status = disabled;
+ };
+
+ ppmu_dmc1: ppmu_dmc1@106b {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106b 0x2000;
+ status = disabled;
+ };
+
+ ppmu_cpu: ppmu_cpu@106c {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106c 0x2000;
+ status = disabled;
+ };
+
+ ppmu_rightbus: ppmu_rightbus@112a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x112a 0x2000;
+ clocks = cmu CLK_PPMURIGHT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_leftbus: ppmu_leftbus0@116a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x116a 0x2000;
+ clocks = cmu CLK_PPMULEFT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
+
+ ppmu_dmc0 {
+ status = okay;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = ppmu-event3-dmc0;
+ };
+
+ ppmu_dmc0_2: ppmu-event2-dmc0 {
+ event-name = ppmu-event2-dmc0;
+ };
+
+ ppmu_dmc0_1: ppmu-event1-dmc0 {
+ event-name = ppmu-event1-dmc0;
+ };
+
+ ppmu_dmc0_0: ppmu-event0-dmc0 {
+ event-name = ppmu-event0-dmc0;
+ };
+ };
+ };
+
+ ppmu_dmc1 {
+ status = okay;
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = ppmu-event3-dmc1;
+ };
+ };
+ };
+
+ ppmu_leftbus {
+ status = okay;
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = ppmu-event3-leftbus;
+ };
+ };
+ };
+
+ ppmu_rightbus {
+ status = okay;
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = ppmu-event3-rightbus;
+ };
+ };
+ };
--
1.8.5.5
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[PATCHv6 8/9] ARM: dts: exynos: Add PPMU node to Exynos3250-based Rinato/Monk board
This patch add PPMU dt node to Exynos3250-base Rinato/Monk board. The PPMU node
is used to get the utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250-monk.dts | 40 +
arch/arm/boot/dts/exynos3250-rinato.dts | 40 +
2 files changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 24822aa..fcceb59 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -420,6 +420,46 @@
status = okay;
};
+ppmu_dmc0 {
+ status = okay;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = ppmu-event3-dmc0;
+ };
+ };
+};
+
+ppmu_dmc1 {
+ status = okay;
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = ppmu-event3-dmc1;
+ };
+ };
+};
+
+ppmu_leftbus {
+ status = okay;
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = ppmu-event3-leftbus;
+ };
+ };
+};
+
+ppmu_rightbus {
+ status = okay;
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = ppmu-event3-rightbus;
+ };
+ };
+};
+
xusbxti {
clock-frequency = 2400;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 6ac1e4e..60948ae 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -524,6 +524,46 @@
status = okay;
};
+ppmu_dmc0 {
+ status = okay;
+
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = ppmu-event3-dmc0;
+ };
+ };
+};
+
+ppmu_dmc1 {
+ status = okay;
+
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = ppmu-event3-dmc1;
+ };
+ };
+};
+
+ppmu_leftbus {
+ status = okay;
+
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = ppmu-event3-leftbus;
+ };
+ };
+};
+
+ppmu_rightbus {
+ status = okay;
+
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = ppmu-event3-rightbus;
+ };
+ };
+};
+
xusbxti {
clock-frequency = 2400;
};
--
1.8.5.5
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[PATCHv6 5/9] ARM: dts: Add PPMU dt node for Exynos3250 SoC
This patch add PPMU (Platform Performance Monitoring Unit) dt node
to estimate the utilization of each IP in Exynos SoC throught DEVFREQ Event
subsystem.
This patch adds following PPMU dt nodes:
- PPMU_DMC0 0x106a
- PPMU_DMC1 0x106b
- PPMU_RIGHTBUS 0x112A
- PPMU_LEFTBUS 0x116A
- PPMU_CAMIF0x11AC
- PPMU_LCD0 0x11E4
- PPMU_FSYS 0x1263
- PPMU_3D 0x1322
- PPMU_MFC 0x1366
- PPMU_CPU 0x106c
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 74 +++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 2246549..9ed1260 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -515,6 +515,80 @@
compatible = arm,cortex-a7-pmu;
interrupts = 0 18 0, 0 19 0;
};
+
+ ppmu_dmc0: ppmu_dmc0@106a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106a 0x2000;
+ status = disabled;
+ };
+
+ ppmu_dmc1: ppmu_dmc1@106b {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106b 0x2000;
+ status = disabled;
+ };
+
+ ppmu_cpu: ppmu_cpu@106c {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x106c 0x2000;
+ status = disabled;
+ };
+
+ ppmu_rightbus: ppmu_rightbus@112a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x112a 0x2000;
+ clocks = cmu CLK_PPMURIGHT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_leftbus: ppmu_leftbus0@116a {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x116a 0x2000;
+ clocks = cmu CLK_PPMULEFT;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_camif: ppmu_camif@11ac {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x11ac 0x2000;
+ clocks = cmu CLK_PPMUCAMIF;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_lcd0: ppmu_lcd0@11e4 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x11e4 0x2000;
+ clocks = cmu CLK_PPMULCD0;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_fsys: ppmu_fsys@1263 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1263 0x2000;
+ clocks = cmu CLK_PPMUFILE;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_g3d: ppmu_g3d@1322 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1322 0x2000;
+ clocks = cmu CLK_PPMUG3D;
+ clock-names = ppmu;
+ status = disabled;
+ };
+
+ ppmu_mfc: ppmu_mfc@1366 {
+ compatible = samsung,exynos-ppmu;
+ reg = 0x1366 0x2000;
+ clocks = cmu CLK_PPMUMFC_L;
+ clock-names = ppmu;
+ status = disabled;
+ };
};
};
--
1.8.5.5
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