[PATCH RESEND 1/2] ARM: dts: exynos3250: remove unecessary property of gpio-keys node
This patch remove unecessary property of gpio-keys node.
gpio-keys driver do not uses interrupts and interrupt-parent.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |2 --
arch/arm/boot/dts/exynos3250-rinato.dts |2 --
2 files changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 24822aa..2129ab98 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -37,8 +37,6 @@
compatible = "gpio-keys";
power_key {
- interrupt-parent = <&gpx2>;
- interrupts = <7 0>;
gpios = <&gpx2 7 1>;
linux,code = ;
label = "power key";
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index 80aa8b4..c186ac6 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -37,8 +37,6 @@
compatible = "gpio-keys";
power_key {
- interrupt-parent = <&gpx2>;
- interrupts = <7 0>;
gpios = <&gpx2 7 1>;
linux,code = ;
label = "power key";
--
1.7.9.5
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[PATCH RESEND 2/2] ARM: dts: exynos3250: replace number by macro in gpio keys
This patch replace number by macro in gpio keys for exynos 3250 boards.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |3 ++-
arch/arm/boot/dts/exynos3250-rinato.dts |3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250-monk.dts
index 2129ab98..792a2c7 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -15,6 +15,7 @@
/dts-v1/;
#include "exynos3250.dtsi"
#include
+#include
/ {
model = "Samsung Monk board";
@@ -37,7 +38,7 @@
compatible = "gpio-keys";
power_key {
- gpios = <&gpx2 7 1>;
+ gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
linux,code = ;
label = "power key";
debounce-interval = <10>;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos3250-rinato.dts
index c186ac6..3493bca 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -15,6 +15,7 @@
/dts-v1/;
#include "exynos3250.dtsi"
#include
+#include
/ {
model = "Samsung Rinato board";
@@ -37,7 +38,7 @@
compatible = "gpio-keys";
power_key {
- gpios = <&gpx2 7 1>;
+ gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
linux,code = ;
label = "power key";
debounce-interval = <10>;
--
1.7.9.5
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[PATCH RESEND 0/2] ARM: dts: exynos3250: revise property for gpio-keys node
This patch revises property of gpio-keys node. The first patch remove unecessary property. And then, replace by macro in gpio keys. Beomho Seo (2): ARM: dts: exynos3250: remove unecessary property of gpio-keys node ARM: dts: exynos3250: replace number by macro in gpio keys arch/arm/boot/dts/exynos3250-monk.dts |5 ++--- arch/arm/boot/dts/exynos3250-rinato.dts |5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv6 0/9] devfreq: Add devfreq-event class to provide raw data for devfreq device
Genlty Ping. Best Regards, Chanwoo Choi On 12/29/2014 09:04 AM, Chanwoo Choi wrote: > This patchset add new devfreq_event class to provide raw data to determine > current utilization of device which is used for devfreq governor. > > [Description of devfreq-event class] > This patchset add new devfreq_event class for devfreq_event device which > provide > raw data (e.g., memory bus utilization/GPU utilization). This raw data from > devfreq_event data would be used for the governor of devfreq subsystem. > - devfreq_event device : Provide raw data for governor of existing devfreq > device > - devfreq device : Monitor device state and change frequency/voltage of > device > using the raw data from devfreq_event device > > The devfreq subsystem support generic DVFS(Dynamic Voltage/Frequency Scaling) > for Non-CPU Devices. The devfreq device would dertermine current device state > using various governor (e.g., ondemand, performance, powersave). After > completed > determination of system state, devfreq device would change the > frequency/voltage > of devfreq device according to the result of governor. > > But, devfreq governor must need basic data which indicates current device > state. > Existing devfreq subsystem only consider devfreq device which check current > system > state and determine proper system state using basic data. There is no > subsystem > for device providing basic data to devfreq device. > > The devfreq subsystem must need devfreq_event device(data-provider device) for > existing devfreq device. So, this patch add new devfreq_event class for > devfreq_event device which read various basic data(e.g, memory bus > utilization, > GPU utilization) and provide measured data to existing devfreq device through > standard APIs of devfreq_event class. > > The following description explains the feature of two kind of devfreq class: > - devfreq class (existing) > : devfreq consumer device use raw data from devfreq_event device for >determining proper current system state and change voltage/frequency >dynamically using various governors. > - devfreq_event class (new) > : Provide measured raw data to devfreq device for governor > > Also, the devfreq-event device would support various type event as following: > : DEVFREQ_EVENT_TYPE_RAW_DATA > : DEVFREQ_EVENT_TYPE_UTILIZATION > : DEVFREQ_EVENT_TYPE_BANDWIDTH > : DEVFREQ_EVENT_TYPE_LATENCY > > [For example] > If board dts includes PPMU_DMC0/DMC1/LEFTBUS/RIGHTBUS event node, > would show following sysfs entry. Also devfreq driver(e.g., exynos4_bus.c) > can get the instance of devfreq-event device by using provided API and then > get raw data which reflect the current state of device. > > -sh-3.2# cd /sys/class/devfreq-event/ > -sh-3.2# ls -al > total 0 > drwxr-xr-x 2 root root 0 Jan 9 16:47 . > drwxr-xr-x 37 root root 0 Jan 9 16:47 .. > lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.0 -> > ../../devices/soc/106a.ppmu_dmc0/devfreq-event/event.0 > lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.1 -> > ../../devices/soc/106b.ppmu_dmc1/devfreq-event/event.1 > lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.2 -> > ../../devices/soc/112a.ppmu_rightbus/devfreq-event/event.2 > lrwxrwxrwx 1 root root 0 Jan 9 16:47 event.3 -> > ../../devices/soc/116a.ppmu_leftbus0/devfreq-event/event.3 > > Changes from v5: > - Rebase these patch-set on v3.19-rc1 and Test it. > 1. exynos-ppmu.c > - Change the error value when of_iomap() fail to map the memory > - Remove owner setting of platform_driver > - Add exynos_ppmu_disable() function > 2. exynos dts file > - Add PPMU node to Exynos3250-based Monk board > - Remove ppmu_cpu node on Exynos4412-based TRATS2 board and add > ppmu_leftbus/rightbus node > > Changes from v4: > 1. devfreq-event class driver > - Add devfreq_event_get_edev_count() function > - Modify the simple description of devfreq-event framework in devfreq-event.c > - Minimize the usage range of global lock usage in devfreq_event_add_edev() > - Remove '_is_enabled()' function pointer in devfreq_event_ops structure > - Add separte CONFIG_PM_DEVFREQ_EVENT configuration > - Add new devfreq-event.h header file including devfreq-event helper functions > 2. exynos dts file > - Add new patch to support PPMU with DEVFREQ-event on Exynos4412-based TRATS2 > > Changes from v3: > 1. devfreq-event class driver > - Fix return value of devfreq_event_get_event() > - Add new structure devfreq_event_data for devfreq_event_get_event() > - Modify the prototype of devfreq_event_get_event() function > - Call of_node_put after calling of_parse_phandle() to decrement refcount > 2. exynos-ppmu driver > - Modify usage of devfreq_event_get_event() function > according to new prototype of this funciton > - Add the additional description to exynos-ppmu.txt how to add PPMU node > in board dts file > - Use 'PPMU_EVENT' macro to remove duplicate codes > - Add the support of PPMU for Exynos5260 > 3. exynos dts file >
Re: [PATCHv3] clocksource: exynos_mct: Add the support for Exynos 64bit SoC
Gently Ping.
Best Regards,
Chanwoo Choi
On 12/17/2014 08:46 AM, Chanwoo Choi wrote:
> This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
> for Exynos 32bit SoC.
>
> Cc: Daniel Lezcano
> Cc: Thomas Gleixner
> Cc: Kukjin Kim
> Cc: Mark Rutland
> Signed-off-by: Chanwoo Choi
> ---
> This patch set is tested on 64-bit Exynos SoC. I send only this patch from
> following patchst[1].
> [1] https://lkml.org/lkml/2014/12/2/134
>
> Changes from v2:
> - None
> Changes from v1:
> - Use CONFIG_ARM instead of CONFIG_ARM64
>
> drivers/clocksource/Kconfig | 1 -
> drivers/clocksource/exynos_mct.c | 4
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 9042060..27ef3fa 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -134,7 +134,6 @@ config CLKSRC_METAG_GENERIC
>
> config CLKSRC_EXYNOS_MCT
> def_bool y if ARCH_EXYNOS
> - depends on !ARM64
> help
> Support for Multi Core Timer controller on Exynos SoCs.
>
> diff --git a/drivers/clocksource/exynos_mct.c
> b/drivers/clocksource/exynos_mct.c
> index 9403061..b840ea1 100644
> --- a/drivers/clocksource/exynos_mct.c
> +++ b/drivers/clocksource/exynos_mct.c
> @@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
> return exynos4_read_count_32();
> }
>
> +#if defined(CONFIG_ARM)
> static struct delay_timer exynos4_delay_timer;
>
> static cycles_t exynos4_read_current_timer(void)
> @@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
>"cycles_t needs to move to 32-bit for ARM64 usage");
> return exynos4_read_count_32();
> }
> +#endif
>
> static void __init exynos4_clocksource_init(void)
> {
> exynos4_mct_frc_start();
>
> +#if defined(CONFIG_ARM)
> exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
> exynos4_delay_timer.freq = clk_rate;
> register_current_timer_delay(&exynos4_delay_timer);
> +#endif
>
> if (clocksource_register_hz(&mct_frc, clk_rate))
> panic("%s: can't register clocksource\n", mct_frc.name);
>
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Re: [PATCH v3 1/4] mmc: dw_mmc: exynos: incorporate ciu_div into timing property
Alim, On Sun, Jan 4, 2015 at 2:43 PM, Alim Akhtar wrote: >> You are breaking backward compatibility here. If your change is >> merged then all old boards will instantly break. Since the "dts" and >> code changes will likely be merged through different trees you'll end >> up with a bunch of broken trees until everything is merged together. >> Even if you don't subscribe to the stable bindings theory this is not >> acceptable. >> > yes the major concern in this series is probably this, which breaks > things unless everything merge in one go and via one tree. Thats why I > re-based everything including dts change on mmc-tree for this case and > added device-tree mailing list for more opinion etc. Got it. I doubt that folks will like this, but I could be wrong. In order for this to work, you'd need all changes in the series to land in _both_ the ARMSoC tree and the MMC tree. That's not unheard of, but it doesn't seem ideal. You also break bisect-ability here since without the code the DTS change will break things and without the DTS change the code will break things. If you add all the above to the fact that bindings are supposed to be stable (ish) I'm not convinced this will land. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
Dear all, On Tue, 06 Jan 2015 00:21:22 +0900 Inki Dae wrote: > On 2015년 01월 05일 23:19, Thierry Reding wrote: > > On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote: > >> Hi Thierry, > >> > >> Ping~. > >> > >> Or is it ok to pick up this patch to my tree, exynos-drm-next? It > >> doesn't seem to care for a long time. > > > > I don't seem to have a copy of the v2 2/3 patch. All I found in my > > inbox is the v2 0/3 cover-letter. Please resend with me in Cc so > > that I can properly review (and apply) the patch. > > Please, refer to below link, > http://lists.freedesktop.org/archives/dri-devel/2014-December/073666.html > > We already sent it with you in Cc. Anyway, I will resend it. > Also you can find the whole patchset from [1/3] https://patchwork.kernel.org/patch/5461421/ [2/3] https://patchwork.kernel.org/patch/5461431/ [3/3] https://patchwork.kernel.org/patch/5461441/ > Thanks, > Inki Dae > > > > > Thierry > > > Best regards, Hyungwon Hwang -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/17] thermal: exynos: Thermal code rework to use device tree
Hi, On Sat, Jan 03, 2015 at 08:53:45PM +0100, Lukasz Majewski wrote: > > > > Apologize for late answer. > > I will be able to address your comments no sooner than next Monday. > Moreover I still believe that we will manage to add this code to your > -next branch :-) Good! Take your time. Cheers, Eduardo Valentin > > > > > Cheers, > > > > Eduardo Valentin. > > Best regards, > Lukasz Majewski signature.asc Description: Digital signature
Re: [PATCH v11 1/9] ARM: OMAP2+: use common l2cache initialization code
On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote: > DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") > + .l2c_aux_val= OMAP_L2C_AUX_CTRL, > + .l2c_aux_mask = 0xcf9f, > + .l2c_write_sec = omap4_l2c310_write_sec, > .reserve= omap_reserve, > .smp= smp_ops(omap4_smp_ops), > .map_io = omap4_map_io, > Could we also get those values into the dts files? Clearly we can't remove them here without breaking compatibility with old dtbs, but it would be nice to have all new dtbs do the right thing. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] usb: dwc2: add support for initial state for dual-role mode
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Wednesday, December 17, 2014 5:50 AM
>
> DWC2 module on Exynos SoCs is used only as peripheral controller (UDC),
> so add support for selecting default initial state for dual-role mode. The
> default init mode can be overridden by device tree 'dr_mode' property.
> This patch enables to use usb gadget on Exynos SoCs, when DWC2 driver has
> been compiled as 'dual-role driver'.
>
> Signed-off-by: Marek Szyprowski
Hi Marek,
Why can't you just set dr_mode=USB_DR_MODE_PERIPHERAL in your platform's
device tree data?
--
Paul
> ---
> drivers/usb/dwc2/core.h | 3 +++
> drivers/usb/dwc2/platform.c | 62
> ++---
> 2 files changed, 56 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
> index 7a70a13..b0fed4e 100644
> --- a/drivers/usb/dwc2/core.h
> +++ b/drivers/usb/dwc2/core.h
> @@ -354,6 +354,7 @@ struct dwc2_core_params {
> int reload_ctl;
> int ahbcfg;
> int uframe_sched;
> + int default_dr_mode;
> };
>
> /**
> @@ -570,6 +571,8 @@ struct dwc2_hsotg {
> struct dwc2_core_params *core_params;
> enum usb_otg_state op_state;
> enum usb_dr_mode dr_mode;
> + unsigned int hcd_enabled:1;
> + unsigned int gadget_enabled:1;
>
> struct phy *phy;
> struct usb_phy *uphy;
> diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
> index 6a795aa..8abf437 100644
> --- a/drivers/usb/dwc2/platform.c
> +++ b/drivers/usb/dwc2/platform.c
> @@ -76,6 +76,7 @@ static const struct dwc2_core_params params_bcm2835 = {
> .reload_ctl = 0,
> .ahbcfg = 0x10,
> .uframe_sched = 0,
> + .default_dr_mode= USB_DR_MODE_OTG,
> };
>
> static const struct dwc2_core_params params_rk3066 = {
> @@ -104,6 +105,36 @@ static const struct dwc2_core_params params_rk3066 = {
> .reload_ctl = -1,
> .ahbcfg = 0x7, /* INCR16 */
> .uframe_sched = -1,
> + .default_dr_mode= USB_DR_MODE_OTG,
> +};
> +
> +static const struct dwc2_core_params params_s3c_hsotg = {
> + .otg_cap= -1,
> + .otg_ver= -1,
> + .dma_enable = 0,
> + .dma_desc_enable= 0,
> + .speed = -1,
> + .enable_dynamic_fifo= -1,
> + .en_multiple_tx_fifo= -1,
> + .host_rx_fifo_size = -1,
> + .host_nperio_tx_fifo_size = -1,
> + .host_perio_tx_fifo_size= -1,
> + .max_transfer_size = -1,
> + .max_packet_count = -1,
> + .host_channels = -1,
> + .phy_type = -1,
> + .phy_utmi_width = -1,
> + .phy_ulpi_ddr = -1,
> + .phy_ulpi_ext_vbus = -1,
> + .i2c_enable = -1,
> + .ulpi_fs_ls = -1,
> + .host_support_fs_ls_low_power = -1,
> + .host_ls_low_power_phy_clk = -1,
> + .ts_dline = -1,
> + .reload_ctl = -1,
> + .ahbcfg = -1,
> + .uframe_sched = -1,
> + .default_dr_mode= USB_DR_MODE_PERIPHERAL,
> };
>
> /**
> @@ -121,8 +152,10 @@ static int dwc2_driver_remove(struct platform_device
> *dev)
> {
> struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
>
> - dwc2_hcd_remove(hsotg);
> - s3c_hsotg_remove(hsotg);
> + if (hsotg->hcd_enabled)
> + dwc2_hcd_remove(hsotg);
> + if (hsotg->gadget_enabled)
> + s3c_hsotg_remove(hsotg);
>
> return 0;
> }
> @@ -131,7 +164,7 @@ static const struct of_device_id dwc2_of_match_table[] = {
> { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
> { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
> { .compatible = "snps,dwc2", .data = NULL },
> - { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
> + { .compatible = "samsung,s3c6400-hsotg", .data = ¶ms_s3c_hsotg },
> {},
> };
> MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
> @@ -211,15 +244,26 @@ static int dwc2_driver_probe(struct platform_device
> *dev)
> (unsigned long)res->start, hsotg->regs);
>
> hsotg->dr_mode = of_usb_get_dr_mode(dev->dev.of_node);
> + if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN &&
> + params->default_dr_mode > USB_DR_MODE_UNKNOWN)
> + hsotg->dr_mode = params->default_dr_mode;
>
> spin_lock_init(&hsotg->lock);
> mutex_init(&hsotg->init_mutex);
> - retval = dwc2_gadget_init(hsotg, irq);
> - if (retval)
> - return retval;
> - retval = dwc2_hcd_init(hsotg, irq, params);
> - if (r
Re: [PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
On 13:19-20150105, Marek Szyprowski wrote:
> All four register for latency and filter settings cannot be written in
> non-secure mode and they should go through l2c_write_sec(). More on this
> can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
> Reference Manual, 3.2. Register summary, table 3.1. This have been checked
> the TRM for r3p3, but it should be uniform for all revisions.
>
> Reported-by: Nishanth Menon
> Suggested-by: Tomasz Figa
> Signed-off-by: Marek Szyprowski
> ---
> arch/arm/mm/cache-l2x0.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 5e65ca8dea62..0aeeaa95c42d 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -623,14 +623,14 @@ static void l2c310_resume(void)
> unsigned revision;
>
> /* restore pl310 setup */
> - writel_relaxed(l2x0_saved_regs.tag_latency,
> -base + L310_TAG_LATENCY_CTRL);
> - writel_relaxed(l2x0_saved_regs.data_latency,
> -base + L310_DATA_LATENCY_CTRL);
> - writel_relaxed(l2x0_saved_regs.filter_end,
> -base + L310_ADDR_FILTER_END);
> - writel_relaxed(l2x0_saved_regs.filter_start,
> -base + L310_ADDR_FILTER_START);
> + l2c_write_sec(l2x0_saved_regs.tag_latency, base,
> + L310_TAG_LATENCY_CTRL);
> + l2c_write_sec(l2x0_saved_regs.data_latency, base,
> + L310_DATA_LATENCY_CTRL);
> + l2c_write_sec(l2x0_saved_regs.filter_end, base,
> + L310_ADDR_FILTER_END);
> + l2c_write_sec(l2x0_saved_regs.filter_start, base,
> + L310_ADDR_FILTER_START);
>
> revision = readl_relaxed(base + L2X0_CACHE_ID) &
> L2X0_CACHE_ID_RTL_MASK;
Do you need the following as well at this point in the patch series?
Agreed that the writes will disappear later in the series.
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 0aeeaa9..7afab37 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1135,28 +1135,28 @@ static void __init l2c310_of_parse(const struct
device_node *np,
of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
if (tag[0] && tag[1] && tag[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(tag[0] - 1) |
L310_LATENCY_CTRL_WR(tag[1] - 1) |
L310_LATENCY_CTRL_SETUP(tag[2] - 1),
- l2x0_base + L310_TAG_LATENCY_CTRL);
+ l2x0_base, L310_TAG_LATENCY_CTRL);
of_property_read_u32_array(np, "arm,data-latency",
data, ARRAY_SIZE(data));
if (data[0] && data[1] && data[2])
- writel_relaxed(
+ l2c_write_sec(
L310_LATENCY_CTRL_RD(data[0] - 1) |
L310_LATENCY_CTRL_WR(data[1] - 1) |
L310_LATENCY_CTRL_SETUP(data[2] - 1),
- l2x0_base + L310_DATA_LATENCY_CTRL);
+ l2x0_base, L310_DATA_LATENCY_CTRL);
of_property_read_u32_array(np, "arm,filter-ranges",
filter, ARRAY_SIZE(filter));
if (filter[1]) {
- writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
- l2x0_base + L310_ADDR_FILTER_END);
- writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
- l2x0_base + L310_ADDR_FILTER_START);
+ l2c_write_sec(ALIGN(filter[0] + filter[1], SZ_1M),
+ l2x0_base, L310_ADDR_FILTER_END);
+ l2c_write_sec((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
+ l2x0_base, L310_ADDR_FILTER_START);
}
ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
--
Regards,
Nishanth Menon
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Re: [PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface
On 13:19-20150105, Marek Szyprowski wrote:
> From: Tomasz Figa
>
> Certain implementations of secure hypervisors (namely the one found on
> Samsung Exynos-based boards) do not provide access to individual L2C
> registers. This makes the .write_sec()-based interface insufficient and
> provoking ugly hacks.
>
> This patch is first step to make the driver not rely on availability of
> writes to individual registers. This is achieved by refactoring the
> driver to use a commit-like operation scheme: all register values are
> prepared first and stored in an instance of l2x0_regs struct and then a
> single callback is responsible to flush those values to the hardware.
>
> Signed-off-by: Tomasz Figa
> [mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring
> latency and filter regs' patch]
> Signed-off-by: Marek Szyprowski
> ---
> arch/arm/mm/cache-l2x0.c | 210
> ++-
> 1 file changed, 115 insertions(+), 95 deletions(-)
>
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 0aeeaa95c42d..f9013320c8ce 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -41,12 +41,14 @@ struct l2c_init_data {
> void (*enable)(void __iomem *, u32, unsigned);
> void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
> void (*save)(void __iomem *);
> + void (*configure)(void __iomem *);
> struct outer_cache_fns outer_cache;
> };
>
> #define CACHE_LINE_SIZE 32
>
> static void __iomem *l2x0_base;
> +static const struct l2c_init_data *l2x0_data;
> static DEFINE_RAW_SPINLOCK(l2x0_lock);
> static u32 l2x0_way_mask;/* Bitmask of active ways */
> static u32 l2x0_size;
> @@ -106,6 +108,14 @@ static inline void l2c_unlock(void __iomem *base,
> unsigned num)
> }
> }
>
> +static void l2c_configure(void __iomem *base)
> +{
> + if (l2x0_data->configure)
> + l2x0_data->configure(base);
> +
> + l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
> +}
> +
> /*
> * Enable the L2 cache controller. This function must only be
> * called when the cache controller is known to be disabled.
> @@ -114,7 +124,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
> unsigned num_lock)
> {
> unsigned long flags;
>
> - l2c_write_sec(aux, base, L2X0_AUX_CTRL);
> + /* Do not touch the controller if already enabled. */
> + if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
> + return;
> +
> + l2x0_saved_regs.aux_ctrl = aux;
> + l2c_configure(base);
>
> l2c_unlock(base, num_lock);
>
> @@ -208,6 +223,11 @@ static void l2c_save(void __iomem *base)
> l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
> }
>
> +static void l2c_resume(void)
> +{
> + l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
> +}
> +
> /*
> * L2C-210 specific code.
> *
> @@ -288,14 +308,6 @@ static void l2c210_sync(void)
> __l2c210_cache_sync(l2x0_base);
> }
>
> -static void l2c210_resume(void)
> -{
> - void __iomem *base = l2x0_base;
> -
> - if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
> - l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
> -}
> -
> static const struct l2c_init_data l2c210_data __initconst = {
> .type = "L2C-210",
> .way_size_0 = SZ_8K,
> @@ -309,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst
> = {
> .flush_all = l2c210_flush_all,
> .disable = l2c_disable,
> .sync = l2c210_sync,
> - .resume = l2c210_resume,
> + .resume = l2c_resume,
> },
> };
>
> @@ -466,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
> .flush_all = l2c220_flush_all,
> .disable = l2c_disable,
> .sync = l2c220_sync,
> - .resume = l2c210_resume,
> + .resume = l2c_resume,
> },
> };
>
> @@ -615,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
> L310_POWER_CTRL);
> }
>
> -static void l2c310_resume(void)
> +static void l2c310_configure(void __iomem *base)
> {
> - void __iomem *base = l2x0_base;
> + unsigned revision;
>
> - if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
> - unsigned revision;
> -
> - /* restore pl310 setup */
> - l2c_write_sec(l2x0_saved_regs.tag_latency, base,
> -
Re: [PATCH v11 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs
On 01/05/2015 06:18 AM, Marek Szyprowski wrote:
> This is an updated patchset, which intends to add support for L2 cache
> on Exynos4 SoCs on boards running under secure firmware, which requires
> certain initialization steps to be done with help of firmware, as
> selected registers are writable only from secure mode.
>
> First patch updates Omap2+ platforms by moving l2cache initialization to
> common code. This will resolve too early call to l2cache init, what might
> cause kmalloc failure in code added in next patches.
>
> Next patch fixes access method to latency and filter settings in l2cache
> driver.
>
> Next four patches extend existing support for secure write in L2C driver
> to account for design of secure firmware running on Exynos. Namely:
> 1) direct read access to certain registers is needed on Exynos, because
> secure firmware calls set several registers at once,
> 2) not all boards are running secure firmware, so .write_sec callback
> needs to be installed in Exynos firmware ops initialization code,
> 3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
> is not allowed and so must use l2c_write_sec as well,
> 4) on certain boards, default value of prefetch register is incorrect
> and must be overridden at L2C initialization.
> For boards running with firmware that provides access to individual
> L2C registers this series should introduce no functional changes. However
> since the driver is widely used on other platforms I'd like to kindly ask
> any interested people for testing.
>
> Further three patches add implementation of .write_sec and .configure
> callbacks for Exynos secure firmware and necessary DT nodes to enable
> L2 cache.
>
> Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
> boards (both with secure firmware). There should be no functional change
> for Exynos boards running without secure firmware. I do not have access
> to affected non-Exynos boards, so I could not test on them.
>
> Depends on:
> - v3.19-rc2
>
> Changelog:
>
> Changes since v10:
> (https://lkml.org/lkml/2014/12/23/151)
> - Added patch, which fixes access method to latency and filter settings
> in l2cache
>
> Changes since v9:
> (https://lkml.org/lkml/2014/11/17/217)
> - Rebased onto vanilla v3.19-rc1
> - Added patch for Omap2+ (move l2cache initialization to common code), what
> fixes too early initialization (kmalloc failure)
>
> Changes since v8:
> (http://lkml.org/lkml/2014/11/13/263)
> - Rebased onto vanilla v3.18-rc3 and added required includes, which were
> previously added by other patches
> - Added Acked-by tags for Exynos part
>
> Changes since v7:
> (https://lkml.org/lkml/2014/10/29/158)
> - rebased onto arm-soc/for-next kernel tree (depends on patches merged to
> v3.18-rc3 and arm-soc/samsung/pm2 branch)
> - removed 'ARM: l2c: unify L2C-310 OF initialization error messages' patch
> (no longer needed)
>
> Changes since v6:
> (https://lkml.org/lkml/2014/10/27/233)
> - changed PL310 to L2C-310 prefix in error messages
> - added patch shortening the error message about incorrect associativity
>
> Changes since v5:
> (https://lkml.org/lkml/2014/9/24/364)
> - rebased onto v3.18-rc2
> - added error message about missing properties values
>
> Changes since v4:
> (https://lkml.org/lkml/2014/8/26/461)
> - rewrote the code accessing l2x0_saved_regs from assembly code
> - added comment and reworked unconditional call to SMC_CMD_L2X0INVALL
>
>
> Patch summary:
>
> Marek Szyprowski (2):
> ARM: OMAP2+: use common l2cache initialization code
> ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
>
> Tomasz Figa (7):
> ARM: l2c: Refactor the driver to use commit-like interface
> ARM: l2c: Add interface to ask hypervisor to configure L2C
> ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
> not NULL
> ARM: l2c: Add support for overriding prefetch settings
> ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
> ARM: EXYNOS: Add support for non-secure L2X0 resume
> ARM: dts: exynos4: Add nodes for L2 cache controller
>
> Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
> arch/arm/boot/dts/exynos4210.dtsi | 9 +
> arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
> arch/arm/include/asm/outercache.h | 3 +
> arch/arm/kernel/irq.c | 3 +-
> arch/arm/mach-exynos/firmware.c| 50 +
> arch/arm/mach-exynos/sleep.S | 46 +
> arch/arm/mach-omap2/board-generic.c| 6 +
> arch/arm/mach-omap2/common.h | 7 +
> arch/arm/mach-omap2/omap4-common.c | 16 +-
> arch/arm/mm/cache-l2x0.c | 270
> -
> 11 files changed, 323 insertions(+), 111 deletions(-)
>
Applied all 9 patches and tested on as many boards as I could get my
hands on.. all boot fine, Thanks
1: am335x-evm: BO
Re: [PATCH v11 5/9] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Certain platforms (i.e. Exynos) might need to set .write_sec callback
> from firmware initialization which is happenning in .init_early callback
> of machine descriptor. However current code will overwrite the pointer
> with whatever is present in machine descriptor, even though it can be
> already set earlier. This patch fixes this by making the assignment
> conditional, depending on whether current .write_sec callback is NULL.
>
> Signed-off-by: Tomasz Figa
> Signed-off-by: Marek Szyprowski
Acked-by: Tony Lindgren
> ---
> arch/arm/kernel/irq.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
> index ad857bada96c..350f188c92d2 100644
> --- a/arch/arm/kernel/irq.c
> +++ b/arch/arm/kernel/irq.c
> @@ -109,7 +109,8 @@ void __init init_IRQ(void)
>
> if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
> (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
> - outer_cache.write_sec = machine_desc->l2c_write_sec;
> + if (!outer_cache.write_sec)
> + outer_cache.write_sec = machine_desc->l2c_write_sec;
> ret = l2x0_of_init(machine_desc->l2c_aux_val,
> machine_desc->l2c_aux_mask);
> if (ret)
> --
> 1.9.2
>
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Re: [PATCH v11 6/9] ARM: l2c: Add support for overriding prefetch settings
* Marek Szyprowski [150105 04:22]: > From: Tomasz Figa > > Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch > settings configured in registers leading to crashes if L2C is enabled > without overriding them. This patch introduces bindings to enable > prefetch settings to be specified from DT and necessary support in the > driver. > > Signed-off-by: Tomasz Figa > [mszyprow: rebased onto v3.18-rc1, added error message when prefetch related > dt property has been provided without any value] > Signed-off-by: Marek Szyprowski Acked-by: Tony Lindgren -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 4/9] ARM: l2c: Add interface to ask hypervisor to configure L2C
* Marek Szyprowski [150105 04:22]:
> From: Tomasz Figa
>
> Because certain secure hypervisor do not allow writes to individual L2C
> registers, but rather expect set of parameters to be passed as argument
> to secure monitor calls, there is a need to provide an interface for the
> L2C driver to ask the firmware to configure the hardware according to
> specified parameters. This patch adds such.
>
> Signed-off-by: Tomasz Figa
> Signed-off-by: Marek Szyprowski
Acked-by: Tony Lindgren
> ---
> arch/arm/include/asm/outercache.h | 3 +++
> arch/arm/mm/cache-l2x0.c | 6 ++
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/arm/include/asm/outercache.h
> b/arch/arm/include/asm/outercache.h
> index 891a56b35bcf..563b92fc2f41 100644
> --- a/arch/arm/include/asm/outercache.h
> +++ b/arch/arm/include/asm/outercache.h
> @@ -23,6 +23,8 @@
>
> #include
>
> +struct l2x0_regs;
> +
> struct outer_cache_fns {
> void (*inv_range)(unsigned long, unsigned long);
> void (*clean_range)(unsigned long, unsigned long);
> @@ -36,6 +38,7 @@ struct outer_cache_fns {
>
> /* This is an ARM L2C thing */
> void (*write_sec)(unsigned long, unsigned);
> + void (*configure)(const struct l2x0_regs *);
> };
>
> extern struct outer_cache_fns outer_cache;
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index f9013320c8ce..dcde6086a228 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -110,6 +110,11 @@ static inline void l2c_unlock(void __iomem *base,
> unsigned num)
>
> static void l2c_configure(void __iomem *base)
> {
> + if (outer_cache.configure) {
> + outer_cache.configure(&l2x0_saved_regs);
> + return;
> + }
> +
> if (l2x0_data->configure)
> l2x0_data->configure(base);
>
> @@ -910,6 +915,7 @@ static int __init __l2c_init(const struct l2c_init_data
> *data,
>
> fns = data->outer_cache;
> fns.write_sec = outer_cache.write_sec;
> + fns.configure = outer_cache.configure;
> if (data->fixup)
> data->fixup(l2x0_base, cache_id, &fns);
>
> --
> 1.9.2
>
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Re: [PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface
* Marek Szyprowski [150105 04:22]: > From: Tomasz Figa > > Certain implementations of secure hypervisors (namely the one found on > Samsung Exynos-based boards) do not provide access to individual L2C > registers. This makes the .write_sec()-based interface insufficient and > provoking ugly hacks. > > This patch is first step to make the driver not rely on availability of > writes to individual registers. This is achieved by refactoring the > driver to use a commit-like operation scheme: all register values are > prepared first and stored in an instance of l2x0_regs struct and then a > single callback is responsible to flush those values to the hardware. > > Signed-off-by: Tomasz Figa > [mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring > latency and filter regs' patch] > Signed-off-by: Marek Szyprowski This version seems to boot just fine on am437x here: Acked-by: Tony Lindgren -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
* Marek Szyprowski [150105 04:22]: > All four register for latency and filter settings cannot be written in > non-secure mode and they should go through l2c_write_sec(). More on this > can be found in CoreLink Level 2 Cache Controller L2C-310 Technical > Reference Manual, 3.2. Register summary, table 3.1. This have been checked > the TRM for r3p3, but it should be uniform for all revisions. > > Reported-by: Nishanth Menon > Suggested-by: Tomasz Figa > Signed-off-by: Marek Szyprowski Acked-by: Tony Lindgren > --- > arch/arm/mm/cache-l2x0.c | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c > index 5e65ca8dea62..0aeeaa95c42d 100644 > --- a/arch/arm/mm/cache-l2x0.c > +++ b/arch/arm/mm/cache-l2x0.c > @@ -623,14 +623,14 @@ static void l2c310_resume(void) > unsigned revision; > > /* restore pl310 setup */ > - writel_relaxed(l2x0_saved_regs.tag_latency, > -base + L310_TAG_LATENCY_CTRL); > - writel_relaxed(l2x0_saved_regs.data_latency, > -base + L310_DATA_LATENCY_CTRL); > - writel_relaxed(l2x0_saved_regs.filter_end, > -base + L310_ADDR_FILTER_END); > - writel_relaxed(l2x0_saved_regs.filter_start, > -base + L310_ADDR_FILTER_START); > + l2c_write_sec(l2x0_saved_regs.tag_latency, base, > + L310_TAG_LATENCY_CTRL); > + l2c_write_sec(l2x0_saved_regs.data_latency, base, > + L310_DATA_LATENCY_CTRL); > + l2c_write_sec(l2x0_saved_regs.filter_end, base, > + L310_ADDR_FILTER_END); > + l2c_write_sec(l2x0_saved_regs.filter_start, base, > + L310_ADDR_FILTER_START); > > revision = readl_relaxed(base + L2X0_CACHE_ID) & > L2X0_CACHE_ID_RTL_MASK; > -- > 1.9.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 1/9] ARM: OMAP2+: use common l2cache initialization code
* Marek Szyprowski [150105 04:22]: > This patch implements generic DT L2C initialisation (the one from > init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and > kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c. > > Signed-off-by: Marek Szyprowski Seems to work just fine for me: Acked-by: Tony Lindgren -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 2/3] ASoC: samsung: Document Trats2 audio subsystem bindings
On Mon, Jan 05, 2015 at 08:25:16PM +0900, Inha Song wrote: > + - clocks : Reference to the codec master clock > + - clock-names : The clock should be named "mclk" This should be done in the CODEC driver, not in the machine driver - the CODEC always needs the clock, it's not something specific to this machine. Even if we decide that for Linux the best thing to do is to manage the clock in the machine driver it should be described in the DT as being attached to the CODEC. signature.asc Description: Digital signature
[Resend][PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
Just resend it with Thierry's request.
Thanks,
Inki Dae
Original Message
Subject: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
Date: Tue, 09 Dec 2014 18:29:05 +0900
From: Hyungwon Hwang
To: dri-de...@lists.freedesktop.org
CC: airl...@linux.ie, devicet...@vger.kernel.org, robh...@kernel.org,
pawel.m...@arm.com, mark.rutl...@arm.com, ijc+devicet...@hellion.org.uk,
ga...@codeaurora.org, linux-samsung-soc@vger.kernel.org,
kyungmin.p...@samsung.com, inki@samsung.com, a.ha...@samsung.com,
kgene@samsung.com, thierry.red...@gmail.com, Hyungwon Hwang
From: Inki Dae
This patch adds MIPI-DSI based S6E63J0X03 AMOLED LCD panel driver
which uses mipi_dsi bus to communicate with panel. The panel has
320×320 resolution in 1.63-inch physical panel. This panel is used in
Samsung Galaxy Gear 2.
Signed-off-by: Inki Dae
Signed-off-by: Hyungwon Hwang
Acked-by: Kyungmin Park
---
Changes for v2:
- Change the gamma table to 2-dimensional array
- Change the way to make index for brightness
- Make command functions to an array so that it can be called simply
- Change command id for reading device ID
- Change the way to handle the error condition
- Remove power variable, and use the same name variable in bl_dev
- Add the state FB_BLANK_NORMAL to represent the state which the panel
is working but blanked
- Miscellaneous changes to increase the readability and follow the
coding-style standard
drivers/gpu/drm/panel/Kconfig| 6 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-s6e63j0x03.c | 549
+++
3 files changed, 556 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-s6e63j0x03.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index bee9f72..bc133e2 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -27,4 +27,10 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS
+config DRM_PANEL_S6E63J0X03
+ tristate "S6E63J0X03 DSI video mode panel"
+ depends on OF
+ select DRM_MIPI_DSI
+ select VIDEOMODE_HELPERS
+
endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..7f36dc2 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E63J0X03) += panel-s6e63j0x03.o
diff --git a/drivers/gpu/drm/panel/panel-s6e63j0x03.c
b/drivers/gpu/drm/panel/panel-s6e63j0x03.c
new file mode 100644
index 000..28e4a51
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e63j0x03.c
@@ -0,0 +1,549 @@
+/*
+ * MIPI-DSI based S6E63J0X03 AMOLED lcd 1.63 inch panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * Inki Dae,
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define READ_ID1 0xDA
+#define READ_ID2 0xDB
+#define READ_ID3 0xDC
+
+#define MCS_LEVEL2_KEY 0xf0
+#define MCS_MTP_KEY0xf1
+#define MCS_MTP_SET3 0xd4
+
+#define MIN_BRIGHTNESS 0
+#define MAX_BRIGHTNESS 100
+#define DEFAULT_BRIGHTNESS 80
+
+#define GAMMA_LEVEL_NUM30
+#define NUM_GAMMA_STEPS9
+#define GAMMA_CMD_CNT 28
+
+struct s6e63j0x03 {
+ struct device *dev;
+ struct drm_panel panel;
+ struct backlight_device *bl_dev;
+
+ struct regulator_bulk_data supplies[2];
+ struct gpio_desc *reset_gpio;
+ u32 power_on_delay;
+ u32 power_off_delay;
+ u32 reset_delay;
+ u32 init_delay;
+ bool flip_horizontal;
+ bool flip_vertical;
+ struct videomode vm;
+ unsigned int width_mm;
+ unsigned int height_mm;
+};
+
+static const unsigned char gamma_tbl[NUM_GAMMA_STEPS][GAMMA_CMD_CNT] = {
+ { /* Gamma 10 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x52, 0x6b, 0x6f, 0x26,
+ 0x28, 0x2d, 0x28, 0x26, 0x27, 0x33, 0x34, 0x32, 0x36, 0x36,
+ 0x35, 0x00, 0xab, 0x00, 0xae, 0x00, 0xbf
+ },
+ { /* gamma 30 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x70, 0x7f, 0x7f, 0x4e, 0x64, 0x69, 0x26,
+ 0x27, 0x2a, 0x28, 0x29, 0x27, 0x31, 0x32, 0x31, 0x35, 0x34,
+ 0x35, 0x00, 0xc4, 0x00, 0xca, 0x00, 0xdc
+ },
+ { /* gamma 60 */
+ MCS_MTP_SET3,
+ 0x00, 0x00, 0x00, 0x65, 0x7b, 0x7d, 0x5f, 0x67, 0x68, 0x2a,
+ 0x28, 0x29, 0x28, 0x2
Re: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
On 2015년 01월 05일 23:19, Thierry Reding wrote: > On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote: >> Hi Thierry, >> >> Ping~. >> >> Or is it ok to pick up this patch to my tree, exynos-drm-next? It >> doesn't seem to care for a long time. > > I don't seem to have a copy of the v2 2/3 patch. All I found in my inbox > is the v2 0/3 cover-letter. Please resend with me in Cc so that I can > properly review (and apply) the patch. Please, refer to below link, http://lists.freedesktop.org/archives/dri-devel/2014-December/073666.html We already sent it with you in Cc. Anyway, I will resend it. Thanks, Inki Dae > > Thierry > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board
On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> Hi Sjoerd,
>
> On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > same as the vendors naming, which means it's prefixed with exynos5422
> > instead of exynos5800 as the SoC name even though it includes the
> > exyno5800 dtsi.
> >
> > Signed-off-by: Sjoerd Simons
> > ---
> > Changes since v1:
> > * Add chosen/linux,stdout-path to point the serial console device
> > * Change memory start offset to 0x4000 to match the vendors DTS
> > (pointed
> > out by Heesub Shin)
> > * Declare base address & size for the memory banks to be used by the MFC
> >
> > Kevin, Tyler, even though the changes are small i didn't want to just stick
> > your Tested-By on. Could you both be so kind to retest this on your XU3's ?
> >
> > Heesub, I would still love to know the reason for having the memory start
> > address at 0x4000 for this board?
> >
> > arch/arm/boot/dts/Makefile | 1 +
> > arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332
> > +
> > 2 files changed, 333 insertions(+)
> > create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 38c89ca..0a898cc 100644
> > +
> > +&hdmi {
> > + status = "okay";
> > + hpd-gpio = <&gpx3 7 0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&hdmi_hpd_irq>;
> > +
> > + vdd_osc-supply = <&ldo10_reg>;
> > + vdd_pll-supply = <&ldo8_reg>;
> > + vdd-supply = <&ldo8_reg>;
>
> ldo10 and ldo8 are right? I think ldo7 and ldo6 are related with hdmi
> from schematic.
Nice catch. I followed hardkernels dts here, which refers to ldo10 &
ldo8, however double-checking the schematics indeed indicate that ldo7
and ldo6 are used the HDMI supplies.
I'll do some testing and follow-up
--
Sjoerd Simons
Collabora Ltd.
smime.p7s
Description: S/MIME cryptographic signature
Re: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote: > Hi Thierry, > > Ping~. > > Or is it ok to pick up this patch to my tree, exynos-drm-next? It > doesn't seem to care for a long time. I don't seem to have a copy of the v2 2/3 patch. All I found in my inbox is the v2 0/3 cover-letter. Please resend with me in Cc so that I can properly review (and apply) the patch. Thierry pgpFd56LSEeeQ.pgp Description: PGP signature
Re: [PATCH v4 2/3] pinctrl: exynos: Fix GPIO setup failure because domain clock being gated
On pon, 2015-01-05 at 15:05 +0100, Linus Walleij wrote: > On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski > wrote: > > > The audio subsystem on Exynos 5420 has separate clocks and GPIO. To > > operate properly on GPIOs the main block clock 'mau_epll' must be > > enabled. > > > > This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0) > > after introducing runtime PM to pl330 DMA driver. After that commit the > > 'mau_epll' was gated, because the "amba" clock was disabled and there > > were no more users of mau_epll. > > > > The system hang just before probing i2s0 because > > samsung_pinmux_setup() tried to access memory from audss block which was > > gated. > > > > Add a clock property to the pinctrl driver and enable the clock during > > GPIO setup. During normal GPIO operations (set, get, set_direction) the > > clock is not enabled. > > > > Signed-off-by: Krzysztof Kozlowski > > Tested-by: Javier Martinez Canillas > > Tomasz, is this OK and should I apply it for fixes or next? Ha! That is a good question. The issue is fixed for now by the workaround (merged) [1]. The workaround just enables the clock for entire runtime of Exynos 5420-like device. This has some energy impact - around 1.5% in idle [2]. So actually this is question which way we want to solve it: 1. Stick with the workaround (small piece of code, energy impact when not used). 2. Full clock enable on use (big chunk of code, no energy impact when not used). [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=f1e9203e2366164b832d8a6ce10134de8c575178 [2] http://www.spinics.net/lists/linux-samsung-soc/msg39827.html Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/3] pinctrl: exynos: Fix GPIO setup failure because domain clock being gated
On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski wrote: > The audio subsystem on Exynos 5420 has separate clocks and GPIO. To > operate properly on GPIOs the main block clock 'mau_epll' must be > enabled. > > This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0) > after introducing runtime PM to pl330 DMA driver. After that commit the > 'mau_epll' was gated, because the "amba" clock was disabled and there > were no more users of mau_epll. > > The system hang just before probing i2s0 because > samsung_pinmux_setup() tried to access memory from audss block which was > gated. > > Add a clock property to the pinctrl driver and enable the clock during > GPIO setup. During normal GPIO operations (set, get, set_direction) the > clock is not enabled. > > Signed-off-by: Krzysztof Kozlowski > Tested-by: Javier Martinez Canillas Tomasz, is this OK and should I apply it for fixes or next? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V8 00/14] drm/exynos: few patches to enhance bridge chip support
On Fri, Jan 02, 2015 at 01:10:14PM +, Daniel Stone wrote: > Hi Ajay, > > On 17 December 2014 at 09:31, Javier Martinez Canillas < > javier.marti...@collabora.co.uk> wrote: > > > On 12/16/2014 12:37 AM, Laurent Pinchart wrote: > > >> You asked Ajay to change his series to use the video port and enpoints > > DT > > >> bindings instead of phandles, could you please review his latest > > version? > > >> > > >> I guess is now too late for 3.19 since we are in the middle of the merge > > >> window but it would be great if this series can at least made it to > > 3.20. > > > > > > I don't have time to review the series in details right now, but I'm > > happy > > > with the DT bindings, and have no big issue with the rest of the > > patches. I > > > don't really like the of_drm_find_bridge() concept introduced in 03/14 > > but I > > > won't nack it given lack of time to implement an alternative proposal. > > It's an > > > internal API, it can always be reworked later anyway. > > > > Thanks a lot for taking the time to look at the DT bindings, then I guess > > that the series are finally ready to be merged? > > > > Ajay's series don't apply cleanly anymore because it has been a while since > > he posted it but he can rebase on top of 3.19-rc1 once it is released and > > re-resend. > > > > Do you have any plans to rebase this so it's ready for merging? > > Thierry, Daniel, Dave - whose tree would this be best to merge through? The plan is for me to take the bridge patches through the drm/panel tree. I'm going to look at these patches again later this week but from a very quick peek there don't seem to be any major issues left. Thierry pgpBXPr2gyzrt.pgp Description: PGP signature
Re: 3.19-rc1: peach*: display not working (missing patches)
Hello Kukjin, On Mon, Jan 5, 2015 at 2:20 PM, Kukjin Kim wrote: > Javier Martinez Canillas wrote: >> >> I hope he can merge those patches as 3.19 fixes during the -rc cycle >> to avoid having another kernel release with a non-working display on >> Exynos5 boards. >> > Hi, > > Hmm...Probably I've queued the patch into -fixes if I remember correctly but > unfortunately only in my local at that time because all of pull-requests for > 3.19 have been sent out before that. Then, maybe I've missed it :( > > Anyway, I'll take the patch for 3.19-rc. Thanks and sorry for that. > Great, thanks a lot for your help! > - Kukjin > Best regards, Javier -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RESEND] ARM: exynos_defconfig: Enable options for display panel support
Hello Kukjin, >> >> Hello Kukjin, >> > Hi Javier, > > Happy new year :) > Thanks, happy new year for you as well! >> You dropped this patch since exynos drm was causing boot hangs on some >> platforms but the fix for that issue is already in linux-next (commit: >> f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable >> failure due to domain being gated) so I think it makes sense to enable >> the display options again. >> >> NOTE: Display panel is still not working since patch "arm: dts: Exynos5: >> Use pmu_system_controller phandle for dp phy" is needed [0] but I think >> we should enable display options to catch the regressions easier. >> > Agreed with your suggestion and I'll pick this up into Samsung tree soon. > Perfect, I hope you can pick my peach pit/pi and snow DTS updates series as well since those patches have been in the list for some time. > Thanks, > Kukjin > Best regards, Javier -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: 3.19-rc1: peach*: display not working (missing patches)
Javier Martinez Canillas wrote: > > [adding Kukjin and Vivek as cc] > > Hello Paolo, > > On Tue, Dec 23, 2014 at 11:16 AM, Paolo Pisati wrote: > > Hi, > > > > 3.19-rc1 still misses these two patches: > > > > 156823e arm: dts: Exynos5: Use pmu_system_controller phandle for dp phy > > 03c16e7 ARM: exynos_defconfig: Enable options for display panel > > support156823e > > > > and without them, the display doesn't turn on on my peachpi: can we have > > them > > queued for rc2? > > Yes, Vivek re-posted his dp phy patch a couple of times and I pinged > Kukjin several times about this both during the 3.18 -rc cycle (since > this also affected 3.18 where display is not working) and during the > 3.19 merge window but unfortunately it was not picked yet... > > I hope he can merge those patches as 3.19 fixes during the -rc cycle > to avoid having another kernel release with a non-working display on > Exynos5 boards. > Hi, Hmm...Probably I've queued the patch into -fixes if I remember correctly but unfortunately only in my local at that time because all of pull-requests for 3.19 have been sent out before that. Then, maybe I've missed it :( Anyway, I'll take the patch for 3.19-rc. Thanks and sorry for that. - Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [RESEND PATCH v6] ARM: EXYNOS: Remove i2c sys configuration related code
Pankaj Dubey wrote:
>
> As all these code has been moved into i2c driver, now we can
> safely remove them from machine files.
>
> CC: Russell King
> Signed-off-by: Pankaj Dubey
> ---
> This patch is leftover patch from patch series [1], resending it after
> rebasing.
> It can be cleanly applied on kgene/for-next and linux-next/next-20150103.
>
> [1]: http://www.spinics.net/lists/linux-samsung-soc/msg39440.html
>
Hi Pankaj,
Happy new year and looks good to me. Nice cleanup ;)
Thanks for your gentle reminder and will apply.
- Kukjin
>
> arch/arm/mach-exynos/exynos.c | 39
> ++---
> arch/arm/mach-exynos/include/mach/map.h | 3 ---
> arch/arm/mach-exynos/pm.c | 3 ++-
> arch/arm/mach-exynos/regs-sys.h | 22 ---
> arch/arm/mach-exynos/suspend.c | 7 --
> 5 files changed, 4 insertions(+), 70 deletions(-)
> delete mode 100644 arch/arm/mach-exynos/regs-sys.h
>
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index c13d083..2c84439 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -27,20 +27,16 @@
> #include
> #include
>
> +#include
> +
> #include "common.h"
> #include "mfc.h"
> #include "regs-pmu.h"
> -#include "regs-sys.h"
>
> void __iomem *pmu_base_addr;
>
> static struct map_desc exynos4_iodesc[] __initdata = {
> {
> - .virtual= (unsigned long)S3C_VA_SYS,
> - .pfn= __phys_to_pfn(EXYNOS4_PA_SYSCON),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> - }, {
> .virtual= (unsigned long)S5P_VA_SROMC,
> .pfn= __phys_to_pfn(EXYNOS4_PA_SROMC),
> .length = SZ_4K,
> @@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
>
> static struct map_desc exynos5_iodesc[] __initdata = {
> {
> - .virtual= (unsigned long)S3C_VA_SYS,
> - .pfn= __phys_to_pfn(EXYNOS5_PA_SYSCON),
> - .length = SZ_64K,
> - .type = MT_DEVICE,
> - }, {
> .virtual= (unsigned long)S5P_VA_SROMC,
> .pfn= __phys_to_pfn(EXYNOS5_PA_SROMC),
> .length = SZ_4K,
> @@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)
>
> static void __init exynos_dt_machine_init(void)
> {
> - struct device_node *i2c_np;
> - const char *i2c_compat = "samsung,s3c2440-i2c";
> - unsigned int tmp;
> - int id;
> -
> - /*
> - * Exynos5's legacy i2c controller and new high speed i2c
> - * controller have muxed interrupt sources. By default the
> - * interrupts for 4-channel HS-I2C controller are enabled.
> - * If node for first four channels of legacy i2c controller
> - * are available then re-configure the interrupts via the
> - * system register.
> - */
> - if (soc_is_exynos5()) {
> - for_each_compatible_node(i2c_np, NULL, i2c_compat) {
> - if (of_device_is_available(i2c_np)) {
> - id = of_alias_get_id(i2c_np, "i2c");
> - if (id < 4) {
> - tmp = readl(EXYNOS5_SYS_I2C_CFG);
> - writel(tmp & ~(0x1 << id),
> - EXYNOS5_SYS_I2C_CFG);
> - }
> - }
> - }
> - }
> -
> /*
>* This is called from smp_prepare_cpus if we've built for SMP, but
>* we still need to set it up for PM and firmware ops if not.
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index 1ad3f49..de3ae59 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -24,9 +24,6 @@
>
> #define EXYNOS_PA_CHIPID 0x1000
>
> -#define EXYNOS4_PA_SYSCON0x1001
> -#define EXYNOS5_PA_SYSCON0x10050100
> -
> #define EXYNOS4_PA_CMU 0x1003
> #define EXYNOS5_PA_CMU 0x1001
>
> diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
> index 86f3ecd..dfc8594 100644
> --- a/arch/arm/mach-exynos/pm.c
> +++ b/arch/arm/mach-exynos/pm.c
> @@ -23,12 +23,13 @@
> #include
> #include
>
> +#include
> +
> #include
>
> #include "common.h"
> #include "exynos-pmu.h"
> #include "regs-pmu.h"
> -#include "regs-sys.h"
>
> static inline void __iomem *exynos_boot_vector_addr(void)
> {
> diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h
> deleted file mode 100644
> index 84332b0..000
> --- a/arch/arm/mach-exynos/regs-sys.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> - *
RE: [PATCH RESEND] ARM: exynos_defconfig: Enable options for display panel support
Javier Martinez Canillas wrote: > > Many Exynos devices have a display panel. Most of them just have > a simple panel while others have more complex configurations that > requires an embedded DisplayPort (eDP) to LVDS bridges. > > This patch enables the following features to be built in the kernel > image to support both setups: > > - Direct Rendering Manager (DRM) > - DRM bridge registration and lookup framework > - Parade ps8622/ps8625 eDP/LVDS bridge > - NXP ptn3460 eDP/LVDS bridge > - Exynos Fully Interactive Mobile Display controller (FIMD) > - Panel registration and lookup framework > - Simple panels > - Backlight & LCD device support > > Signed-off-by: Javier Martinez Canillas > Tested-by: Kevin Hilman > Signed-off-by: Kukjin Kim > --- > > Hello Kukjin, > Hi Javier, Happy new year :) > You dropped this patch since exynos drm was causing boot hangs on some > platforms but the fix for that issue is already in linux-next (commit: > f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable > failure due to domain being gated) so I think it makes sense to enable > the display options again. > > NOTE: Display panel is still not working since patch "arm: dts: Exynos5: > Use pmu_system_controller phandle for dp phy" is needed [0] but I think > we should enable display options to catch the regressions easier. > Agreed with your suggestion and I'll pick this up into Samsung tree soon. Thanks, Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 1/3] ASoC: samsung: Add machine driver for Trats2
Hi,
Thanks for your comments.
> Hi,
>
> A few small comments inline.
>
> On 01/05/2015 12:25 PM, Inha Song wrote:
> > --- /dev/null
> > +++ b/sound/soc/samsung/trats2_wm1811.c
> > @@ -0,0 +1,216 @@
> >[...]
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "i2s.h"
> > +#include "i2s-regs.h"
>
> You probably don't need i2s-regs.h
OK, I will remove.
>
> > +#include "../codecs/wm8994.h"
> > +
> > +struct trats2_machine_priv {
> > + struct clk *clk_mclk;
> > +};
> > +
> > +static struct trats2_machine_priv trats2_wm1811_priv;
> > +
> > +static const struct snd_kcontrol_new trats2_controls[] = {
> > + SOC_DAPM_PIN_SWITCH("SPK"),
> > +};
> > +
> > +const struct snd_soc_dapm_widget trats2_dapm_widgets[] = {
>
> static
Sorry for my mistake.
>
> > + SND_SOC_DAPM_SPK("SPK", NULL),
> > +};
> > +
> > +static int trats2_aif1_hw_params(struct snd_pcm_substream *substream,
> > +struct snd_pcm_hw_params *params)
> > +{
> > + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> > + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
> > + struct snd_soc_dai *codec_dai = rtd->codec_dai;
> > + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
> > + unsigned int sysclk_rate;
> > + unsigned int mclk_rate =
> > + (unsigned int)clk_get_rate(priv->clk_mclk);
> > + int ret;
> > +
> > + /* Set the codec DAI configuration to Master*/
> > + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
> > + | SND_SOC_DAIFMT_NB_NF
> > + | SND_SOC_DAIFMT_CBM_CFM);
> > + if (ret < 0) {
> > + dev_err(codec_dai->dev,
> > + "Failed to set codec dai format: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + /* Set the cpu DAI configuration to Slave */
> > + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
> > + | SND_SOC_DAIFMT_NB_NF
> > + | SND_SOC_DAIFMT_CBM_CFM);
> > + if (ret < 0) {
> > + dev_err(cpu_dai->dev,
> > + "Failed to set cpu dai format: %d\n", ret);
> > + return ret;
> > + }
>
>
> Use the dai_fmt field in the dai_link struct to setup the DAI link format.
> This will configure both the CPU and the CODEC DAI with the specified
> format, no need to do it manually.
Ok, move to dai_fmt.
>
> >[...]
> > +static struct snd_soc_ops trats2_aif1_ops = {
>
> const
I will fix this.
>
> > + .hw_params = trats2_aif1_hw_params,
> > +};
> > +
> > +static int trats2_init_paiftx(struct snd_soc_pcm_runtime *rtd)
> > +{
> > + struct snd_soc_codec *codec = rtd->codec;
> > + struct snd_soc_card *card = rtd->card;
> > + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(card);
> > + int ret;
> > +
> > + ret = clk_prepare_enable(priv->clk_mclk);
>
> Maybe just do this in the platform device probe handler and you should have
> a matching disable call somewhere.
Ok, I will move clk_prepare_enable call to snd_soc_ops->startup
and clk_disable_unprepare call to snd_soc_ops->shutdown.
Best Regards,
Inha Song.
>
> > + if (ret) {
> > + dev_err(codec->dev, "Failed to enable mclk: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> >[...]
> ___
> Alsa-devel mailing list
> alsa-de...@alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
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[PATCH v11 5/9] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL
From: Tomasz Figa
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa
Signed-off-by: Marek Szyprowski
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index ad857bada96c..350f188c92d2 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -109,7 +109,8 @@ void __init init_IRQ(void)
if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
(machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
- outer_cache.write_sec = machine_desc->l2c_write_sec;
+ if (!outer_cache.write_sec)
+ outer_cache.write_sec = machine_desc->l2c_write_sec;
ret = l2x0_of_init(machine_desc->l2c_aux_val,
machine_desc->l2c_aux_mask);
if (ret)
--
1.9.2
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[PATCH v11 4/9] ARM: l2c: Add interface to ask hypervisor to configure L2C
From: Tomasz Figa
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.
Signed-off-by: Tomasz Figa
Signed-off-by: Marek Szyprowski
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 891a56b35bcf..563b92fc2f41 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
#include
+struct l2x0_regs;
+
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
+ void (*configure)(const struct l2x0_regs *);
};
extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index f9013320c8ce..dcde6086a228 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -110,6 +110,11 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
static void l2c_configure(void __iomem *base)
{
+ if (outer_cache.configure) {
+ outer_cache.configure(&l2x0_saved_regs);
+ return;
+ }
+
if (l2x0_data->configure)
l2x0_data->configure(base);
@@ -910,6 +915,7 @@ static int __init __l2c_init(const struct l2c_init_data
*data,
fns = data->outer_cache;
fns.write_sec = outer_cache.write_sec;
+ fns.configure = outer_cache.configure;
if (data->fixup)
data->fixup(l2x0_base, cache_id, &fns);
--
1.9.2
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[PATCH v11 3/9] ARM: l2c: Refactor the driver to use commit-like interface
From: Tomasz Figa
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.
Signed-off-by: Tomasz Figa
[mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring
latency and filter regs' patch]
Signed-off-by: Marek Szyprowski
---
arch/arm/mm/cache-l2x0.c | 210 ++-
1 file changed, 115 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 0aeeaa95c42d..f9013320c8ce 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -41,12 +41,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+ void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
};
#define CACHE_LINE_SIZE32
static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
@@ -106,6 +108,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
}
}
+static void l2c_configure(void __iomem *base)
+{
+ if (l2x0_data->configure)
+ l2x0_data->configure(base);
+
+ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
/*
* Enable the L2 cache controller. This function must only be
* called when the cache controller is known to be disabled.
@@ -114,7 +124,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
unsigned num_lock)
{
unsigned long flags;
- l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+ /* Do not touch the controller if already enabled. */
+ if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)
+ return;
+
+ l2x0_saved_regs.aux_ctrl = aux;
+ l2c_configure(base);
l2c_unlock(base, num_lock);
@@ -208,6 +223,11 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
}
+static void l2c_resume(void)
+{
+ l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
+}
+
/*
* L2C-210 specific code.
*
@@ -288,14 +308,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
}
-static void l2c210_resume(void)
-{
- void __iomem *base = l2x0_base;
-
- if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
- l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
static const struct l2c_init_data l2c210_data __initconst = {
.type = "L2C-210",
.way_size_0 = SZ_8K,
@@ -309,7 +321,7 @@ static const struct l2c_init_data l2c210_data __initconst =
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -466,7 +478,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -615,39 +627,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
}
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
- unsigned revision;
-
- /* restore pl310 setup */
- l2c_write_sec(l2x0_saved_regs.tag_latency, base,
- L310_TAG_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.data_latency, base,
- L310_DATA_LATENCY_CTRL);
- l2c_write_sec(l2x0_saved_regs.filter_end, base,
- L310_ADDR_FILTER_END);
- l2c_write_sec(l2x0_saved_regs.filter_start, base,
- L310_ADDR_FILTER_START);
-
- revision = readl_relaxed(base + L2X0_CACHE_ID) &
- L2X0_CACHE_ID_RTL_MASK;
-
- if (revision >= L310_CACHE_ID_RTL_R2P0)
- l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
-
[PATCH v11 1/9] ARM: OMAP2+: use common l2cache initialization code
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski
---
arch/arm/mach-omap2/board-generic.c | 6 ++
arch/arm/mach-omap2/common.h| 7 +++
arch/arm/mach-omap2/omap4-common.c | 16 +---
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 608079a1aba6..c5c480b76da5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -171,6 +171,9 @@ static const char *const omap4_boards_compat[] __initconst
= {
};
DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.reserve= omap_reserve,
.smp= smp_ops(omap4_smp_ops),
.map_io = omap4_map_io,
@@ -214,6 +217,9 @@ static const char *const am43_boards_compat[] __initconst =
{
};
DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec = omap4_l2c310_write_sec,
.map_io = am33xx_map_io,
.init_early = am43xx_init_early,
.init_late = am43xx_init_late,
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 377eea849e7b..19c9144d8b38 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -35,6 +35,7 @@
#include
#include
+#include
#include "i2c.h"
#include "serial.h"
@@ -94,11 +95,17 @@ extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
+#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
+L310_AUX_CTRL_DATA_PREFETCH | \
+L310_AUX_CTRL_INSTR_PREFETCH)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg);
#else
static inline int omap_l2_cache_init(void)
{
return 0;
}
+#define OMAP_L2C_AUX_CTRL 0
+#define omap4_l2c310_write_sec NULL
#endif
extern void omap5_realtime_timer_init(void);
diff --git a/arch/arm/mach-omap2/omap4-common.c
b/arch/arm/mach-omap2/omap4-common.c
index b7cb44abe49b..fe99ceff2e2d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -166,7 +166,7 @@ void __iomem *omap4_get_l2cache_base(void)
return l2cache_base;
}
-static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
+void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
{
unsigned smc_op;
@@ -201,24 +201,10 @@ static void omap4_l2c310_write_sec(unsigned long val,
unsigned reg)
int __init omap_l2_cache_init(void)
{
- u32 aux_ctrl;
-
/* Static mapping, never released */
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
if (WARN_ON(!l2cache_base))
return -ENOMEM;
-
- /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
- aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
- L310_AUX_CTRL_DATA_PREFETCH |
- L310_AUX_CTRL_INSTR_PREFETCH;
-
- outer_cache.write_sec = omap4_l2c310_write_sec;
- if (of_have_populated_dt())
- l2x0_of_init(aux_ctrl, 0xcf9f);
- else
- l2x0_init(l2cache_base, aux_ctrl, 0xcf9f);
-
return 0;
}
#endif
--
1.9.2
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[PATCH v11 2/9] ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
All four register for latency and filter settings cannot be written in non-secure mode and they should go through l2c_write_sec(). More on this can be found in CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, 3.2. Register summary, table 3.1. This have been checked the TRM for r3p3, but it should be uniform for all revisions. Reported-by: Nishanth Menon Suggested-by: Tomasz Figa Signed-off-by: Marek Szyprowski --- arch/arm/mm/cache-l2x0.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 5e65ca8dea62..0aeeaa95c42d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -623,14 +623,14 @@ static void l2c310_resume(void) unsigned revision; /* restore pl310 setup */ - writel_relaxed(l2x0_saved_regs.tag_latency, - base + L310_TAG_LATENCY_CTRL); - writel_relaxed(l2x0_saved_regs.data_latency, - base + L310_DATA_LATENCY_CTRL); - writel_relaxed(l2x0_saved_regs.filter_end, - base + L310_ADDR_FILTER_END); - writel_relaxed(l2x0_saved_regs.filter_start, - base + L310_ADDR_FILTER_START); + l2c_write_sec(l2x0_saved_regs.tag_latency, base, + L310_TAG_LATENCY_CTRL); + l2c_write_sec(l2x0_saved_regs.data_latency, base, + L310_DATA_LATENCY_CTRL); + l2c_write_sec(l2x0_saved_regs.filter_end, base, + L310_ADDR_FILTER_END); + l2c_write_sec(l2x0_saved_regs.filter_start, base, + L310_ADDR_FILTER_START); revision = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; -- 1.9.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 7/9] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
From: Tomasz Figa
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa
[added comment and reworked unconditional call to SMC_CMD_L2X0INVALL]
Signed-off-by: Marek Szyprowski
Acked-by: Arnd Bergmann
Acked-by: Kukjin Kim
---
arch/arm/mach-exynos/firmware.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 766f57d2f029..dc5ae53aa317 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
@@ -136,6 +137,43 @@ static const struct firmware_ops exynos_firmware_ops = {
.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ?
exynos_resume : NULL,
};
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+ static int l2cache_enabled;
+
+ switch (reg) {
+ case L2X0_CTRL:
+ if (val & L2X0_CTRL_EN) {
+ /*
+* Before the cache can be enabled, due to firmware
+* design, SMC_CMD_L2X0INVALL must be called.
+*/
+ if (!l2cache_enabled) {
+ exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+ l2cache_enabled = 1;
+ }
+ } else {
+ l2cache_enabled = 0;
+ }
+ exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
+ break;
+
+ case L2X0_DEBUG_CTRL:
+ exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+ break;
+
+ default:
+ WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
+ }
+}
+
+static void exynos_l2_configure(const struct l2x0_regs *regs)
+{
+ exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
+ regs->prefetch_ctrl);
+ exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
+}
+
void __init exynos_firmware_init(void)
{
struct device_node *nd;
@@ -155,4 +193,16 @@ void __init exynos_firmware_init(void)
pr_info("Running under secure firmware.\n");
register_firmware_ops(&exynos_firmware_ops);
+
+ /*
+* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
+* running under secure firmware, require certain registers of L2
+* cache controller to be written in secure mode. Here .write_sec
+* callback is provided to perform necessary SMC calls.
+*/
+ if (IS_ENABLED(CONFIG_CACHE_L2X0)
+ && read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ outer_cache.write_sec = exynos_l2_write_sec;
+ outer_cache.configure = exynos_l2_configure;
+ }
}
--
1.9.2
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[PATCH v11 6/9] ARM: l2c: Add support for overriding prefetch settings
From: Tomasz Figa
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.
Signed-off-by: Tomasz Figa
[mszyprow: rebased onto v3.18-rc1, added error message when prefetch related
dt property has been provided without any value]
Signed-off-by: Marek Szyprowski
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/mm/cache-l2x0.c | 54 ++
2 files changed, 64 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation/devicetree/bindings/arm/l2cc.txt
index 292ef7ca3058..0dbabe9a6b0a 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -57,6 +57,16 @@ Optional properties:
- cache-id-part: cache id part number to be used if it is not present
on hardware
- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
Example:
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index dcde6086a228..e7f1bd90dde6 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1169,6 +1169,8 @@ static void __init l2c310_of_parse(const struct
device_node *np,
u32 tag[3] = { 0, 0, 0 };
u32 filter[2] = { 0, 0 };
u32 assoc;
+ u32 prefetch;
+ u32 val;
int ret;
of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
@@ -1214,6 +1216,58 @@ static void __init l2c310_of_parse(const struct
device_node *np,
assoc);
break;
}
+
+ prefetch = l2x0_saved_regs.prefetch_ctrl;
+
+ ret = of_property_read_u32(np, "arm,double-linefill", &val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
+ else
+ prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
+ } else if (ret != -EINVAL) {
+ pr_err("L2C-310 OF arm,double-linefill property value is
missing\n");
+ }
+
+ ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ else
+ prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ } else if (ret != -EINVAL) {
+ pr_err("L2C-310 OF arm,double-linefill-incr property value is
missing\n");
+ }
+
+ ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
+ if (ret == 0) {
+ if (!val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ else
+ prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ } else if (ret != -EINVAL) {
+ pr_err("L2C-310 OF arm,double-linefill-wrap property value is
missing\n");
+ }
+
+ ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
+ if (ret == 0) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
+ else
+ prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
+ } else if (ret != -EINVAL) {
+ pr_err("L2C-310 OF arm,prefetch-drop property value is
missing\n");
+ }
+
+ ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
+ if (ret == 0) {
+ prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
+ prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
+ } else if (ret != -EINVAL) {
+ pr_err("L2C-310 OF arm,prefetch-offset property value is
missing\n");
+ }
+
+ l2x0_saved_regs.prefetch_ctrl = prefetch;
}
static const struct l2c_init_data of_l2c310_data __initconst = {
--
1.9.2
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[PATCH v11 8/9] ARM: EXYNOS: Add support for non-secure L2X0 resume
From: Tomasz Figa On Exynos SoCs it is necessary to resume operation of L2C early in assembly code, because otherwise certain systems will crash. This patch adds necessary code to non-secure resume handler. Signed-off-by: Tomasz Figa [rewrote the code accessing l2x0_saved_regs] Sigend-off-by: Marek Szyprowski Acked-by: Arnd Bergmann Acked-by: Kukjin Kim --- arch/arm/mach-exynos/sleep.S | 46 1 file changed, 46 insertions(+) diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c373082bbe..31d25834b9c4 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -16,6 +16,8 @@ */ #include +#include +#include #include "smc.h" #define CPU_MASK 0xff00 @@ -74,6 +76,45 @@ ENTRY(exynos_cpu_resume_ns) mov r0, #SMC_CMD_C15RESUME dsb smc #0 +#ifdef CONFIG_CACHE_L2X0 + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + /* Check that the address has been initialised. */ + ldr r1, [r0, #L2X0_R_PHY_BASE] + teq r1, #0 + beq skip_l2x0 + + /* Check if controller has been enabled. */ + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne skip_l2x0 + + ldr r1, [r0, #L2X0_R_TAG_LATENCY] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] + mov r0, #SMC_CMD_L2X0SETUP1 + smc #0 + + /* Reload saved regs pointer because smc corrupts registers. */ + adr r0, 1f + ldr r2, [r0] + add r0, r2, r0 + + ldr r1, [r0, #L2X0_R_PWR_CTRL] + ldr r2, [r0, #L2X0_R_AUX_CTRL] + mov r0, #SMC_CMD_L2X0SETUP2 + smc #0 + + mov r0, #SMC_CMD_L2X0INVALL + smc #0 + + mov r1, #1 + mov r0, #SMC_CMD_L2X0CTRL + smc #0 +skip_l2x0: +#endif /* CONFIG_CACHE_L2X0 */ skip_cp15: b cpu_resume ENDPROC(exynos_cpu_resume_ns) @@ -83,3 +124,8 @@ cp15_save_diag: .globl cp15_save_power cp15_save_power: .long 0 @ cp15 power control + +#ifdef CONFIG_CACHE_L2X0 + .align +1: .long l2x0_saved_regs - . +#endif /* CONFIG_CACHE_L2X0 */ -- 1.9.2 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 9/9] ARM: dts: exynos4: Add nodes for L2 cache controller
From: Tomasz Figa
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa
Signed-off-by: Marek Szyprowski
Acked-by: Arnd Bergmann
Acked-by: Kukjin Kim
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63c8070..8e45ea44317e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
reg = <0x10023CA0 0x20>;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <2 2 1>;
+ };
+
gic: interrupt-controller@1049 {
cpu-offset = <0x8000>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b70402e943..8bc97c415c9a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
reg = <0x10023CA0 0x20>;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <3 2 1>;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <1>;
+ arm,prefetch-offset = <7>;
+ };
+
clock: clock-controller@1003 {
compatible = "samsung,exynos4412-clock";
reg = <0x1003 0x2>;
--
1.9.2
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[PATCH v11 0/9] Enable L2 cache support on Exynos4210/4x12 SoCs
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+ platforms by moving l2cache initialization to
common code. This will resolve too early call to l2cache init, what might
cause kmalloc failure in code added in next patches.
Next patch fixes access method to latency and filter settings in l2cache
driver.
Next four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.
Further three patches add implementation of .write_sec and .configure
callbacks for Exynos secure firmware and necessary DT nodes to enable
L2 cache.
Changes in this version tested on Exynos4412-based TRATS2 and OdroidU3+
boards (both with secure firmware). There should be no functional change
for Exynos boards running without secure firmware. I do not have access
to affected non-Exynos boards, so I could not test on them.
Depends on:
- v3.19-rc2
Changelog:
Changes since v10:
(https://lkml.org/lkml/2014/12/23/151)
- Added patch, which fixes access method to latency and filter settings
in l2cache
Changes since v9:
(https://lkml.org/lkml/2014/11/17/217)
- Rebased onto vanilla v3.19-rc1
- Added patch for Omap2+ (move l2cache initialization to common code), what
fixes too early initialization (kmalloc failure)
Changes since v8:
(http://lkml.org/lkml/2014/11/13/263)
- Rebased onto vanilla v3.18-rc3 and added required includes, which were
previously added by other patches
- Added Acked-by tags for Exynos part
Changes since v7:
(https://lkml.org/lkml/2014/10/29/158)
- rebased onto arm-soc/for-next kernel tree (depends on patches merged to
v3.18-rc3 and arm-soc/samsung/pm2 branch)
- removed 'ARM: l2c: unify L2C-310 OF initialization error messages' patch
(no longer needed)
Changes since v6:
(https://lkml.org/lkml/2014/10/27/233)
- changed PL310 to L2C-310 prefix in error messages
- added patch shortening the error message about incorrect associativity
Changes since v5:
(https://lkml.org/lkml/2014/9/24/364)
- rebased onto v3.18-rc2
- added error message about missing properties values
Changes since v4:
(https://lkml.org/lkml/2014/8/26/461)
- rewrote the code accessing l2x0_saved_regs from assembly code
- added comment and reworked unconditional call to SMC_CMD_L2X0INVALL
Patch summary:
Marek Szyprowski (2):
ARM: OMAP2+: use common l2cache initialization code
ARM: l2c: use l2c_write_sec() for restoring latency and filter regs
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
ARM: l2c: Add support for overriding prefetch settings
ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
ARM: EXYNOS: Add support for non-secure L2X0 resume
ARM: dts: exynos4: Add nodes for L2 cache controller
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
arch/arm/include/asm/outercache.h | 3 +
arch/arm/kernel/irq.c | 3 +-
arch/arm/mach-exynos/firmware.c| 50 +
arch/arm/mach-exynos/sleep.S | 46 +
arch/arm/mach-omap2/board-generic.c| 6 +
arch/arm/mach-omap2/common.h | 7 +
arch/arm/mach-omap2/omap4-common.c | 16 +-
arch/arm/mm/cache-l2x0.c | 270 -
11 files changed, 323 insertions(+), 111 deletions(-)
--
1.9.2
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Re: kernel panic when booting on exynos 5440
On 1/5/15, Kukjin Kim wrote: > Ming Lei wrote: >> >> Hi Guys, >> > Hi, > > Sorry for late response. > >> On Thu, Dec 25, 2014 at 6:32 PM, Pankaj Dubey >> wrote: >> > +CC: Thomas Abraham >> > >> > Hi Ming, >> > >> > On Thursday 25 December 2014 02:18 PM, Ming Lei wrote: >> >> >> >> Hi Pankaj, >> >> >> >> In your commit fce9e5bb2(ARM: EXYNOS: Add support for >> >> mapping PMU base address via DT), 'pmu_base_addr' is >> >> only parsed for very limited machines from the table of >> >> 'exynos_dt_pmu_match'. For other boards, 'pmu_base_addr' >> >> will keep its default value of null, then panic() is triggered. >> >> >> > >> > Yes, it will. >> > As exynos5440 DT does not have PMU device node, neither above mentioned >> > patch added corresponding matching device_id. >> > If I remember correctly, I might have missed this because exynos5440 DT >> > was >> > not having PMU node. >> > >> >> What do you think about the problem? >> > >> > >> > I missed this part, and I should have taken care of this in original >> > patch >> > itself. Well as of now I can think of only one solution that if we >> > really >> > want to keep support for exynos5440 in mainline kernel, to avoid above >> > issue >> > we should skip pmu mapping for exynos5440. In this case following patch >> > will >> > do this work. >> > >> > Also I will like to know from Kukjin that what best can be done now. >> > If he is OK with below solution I can post the same. >> > >> > --- >> > >> > Subject: [PATCH] ARM: EXYNOS: do not try to map PMU for exynos5440 >> > >> > Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care >> > of mapping of exynos5440 PMU register which will result in kernel >> > panic. >> > As of now let's avoid mapping of exynos5440 PMU. >> > >> > Signed-off-by: Pankaj Dubey >> >> Is there any opportunity to merge the fix? Or exynos5440 will not be >> supported in future? >> > Basically, I'm fine on the change like others for exynos5440 at this moment > and if any other comments, I'll let you know on the patch in mailing list. Great thanks for your response! Thanks, Ming Lei -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/5] regulator: Allow parsing custom DT properties with simplified DT parse
Hi, The patchset adds: 1. a way of parsing custom DT properties by the driver when simplified DT parsing method is used, 2. GPIO enable control to the max77686 driver. Rationale = After converting drivers to simplified DT parsing method, the parsing is done by regulator core. The driver cannot longer parse any custom properties from Device Tree. Example of such special property is GPIO for enable control. Driver may want to rely on regulator core to parse most of the bindings but still need to parse one custom stuff. Additionally driver may need to perform some special activities depending on Device Tree. This is solved by adding a callback called from the core when regulator is matched from DT. The max77686 driver uses it for: 1. parsing "maxim,ena-gpios" property from regulator OF node, 2. enabling GPIO control for such regulator. Changes since v4 1. Re-work idea. Give up generic ena-gpios binding and let driver parse any custom property. Changes since v3 1. Regulator cleanup patches were applied by Mark, drop them. 2. Re-work idea by adding generic ena-gpios binding. Changes since v2 Re-work the board file support removal after Javier's comments: use new DT style parsing. This imposes a lot of changes. 1. Add "of_compatible" for regulator drivers. 2. Provide backward compatibility if such "of_compatible" is not present. The driver will search for regulators node and use it as dev->of_node. Everything should be bisect-friendly. 3. New patches: 1, 2, 3, 5, 13 and 14. 4. Because of new style DT parsing it is much easier to put "gpio" properties in regulators top node (not in each regulator). This will be also new-gpio-lib friendly. Changes since v1 1. Add patch: 1/8 "regulator: max77686: Consistently index opmode array by rdev id". 2. Remove patch "regulator: max77686: Make regulator_desc array const" (applied). 3. Re-work patches removing from regulators board file support (2/8 and 3/8). Parse regulators with of_regulator_match() at once, remove num_regulators. 4. Patch 4/8: Add depends on OF to mfd/Kconfig. Add Javier's reviewed-by. 5. Patch 5/8: Add Javier's reviewed-by. 6. Patch 6/8: Add depends on GPIOLIB to regulator/Kconfig. Rename "external control" to "GPIO control" and "ext_control_gpios" to simpler "gpios". I tried to use new GPIO API but it ended with more problems https://lkml.org/lkml/2014/10/29/239 Best regards, Krzysztof Krzysztof Kozlowski (5): regulator: Copy config passed during registration regulator: Allow parsing custom properties when using simplified DT parsing regulator: max77686: Add GPIO control mfd/regulator: dt-bindings: max77686: Document gpio properties ARM: dts: exynos4412-trats: Switch max77686 regulators to GPIO control Documentation/devicetree/bindings/mfd/max77686.txt | 14 + arch/arm/boot/dts/exynos4412-trats2.dts| 25 ++-- drivers/regulator/core.c | 20 +-- drivers/regulator/internal.h | 2 + drivers/regulator/max77686.c | 70 -- drivers/regulator/of_regulator.c | 11 include/linux/regulator/driver.h | 13 7 files changed, 126 insertions(+), 29 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/5] regulator: max77686: Add GPIO control
Add enable control over GPIO for regulators supporting this: LDO20,
LDO21, LDO22, buck8 and buck9.
This is needed for proper (and full) configuration of the Maxim 77686
PMIC without creating redundant 'regulator-fixed' entries.
Signed-off-by: Krzysztof Kozlowski
---
drivers/regulator/max77686.c | 70
1 file changed, 65 insertions(+), 5 deletions(-)
diff --git a/drivers/regulator/max77686.c b/drivers/regulator/max77686.c
index 10d206266ac2..15fb1416bfbd 100644
--- a/drivers/regulator/max77686.c
+++ b/drivers/regulator/max77686.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -46,6 +47,11 @@
#define MAX77686_DVS_UVSTEP12500
/*
+ * Value for configuring buck[89] and LDO{20,21,22} as GPIO control.
+ * It is the same as 'off' for other regulators.
+ */
+#define MAX77686_GPIO_CONTROL 0x0
+/*
* Values used for configuring LDOs and bucks.
* Forcing low power mode: LDO1, 3-5, 9, 13, 17-26
*/
@@ -82,6 +88,8 @@ enum max77686_ramp_rate {
};
struct max77686_data {
+ u64 gpio_enabled:MAX77686_REGULATORS;
+
/* Array indexed by regulator id */
unsigned int opmode[MAX77686_REGULATORS];
};
@@ -100,6 +108,26 @@ static unsigned int max77686_get_opmode_shift(int id)
}
}
+/*
+ * When regulator is configured for GPIO control then it
+ * replaces "normal" mode. Any change from low power mode to normal
+ * should actually change to GPIO control.
+ * Map normal mode to proper value for such regulators.
+ */
+static unsigned int max77686_map_normal_mode(struct max77686_data *max77686,
+int id)
+{
+ switch (id) {
+ case MAX77686_BUCK8:
+ case MAX77686_BUCK9:
+ case MAX77686_LDO20 ... MAX77686_LDO22:
+ if (max77686->gpio_enabled & (1 << id))
+ return MAX77686_GPIO_CONTROL;
+ }
+
+ return MAX77686_NORMAL;
+}
+
/* Some BUCKs and LDOs supports Normal[ON/OFF] mode during suspend */
static int max77686_set_suspend_disable(struct regulator_dev *rdev)
{
@@ -136,7 +164,7 @@ static int max77686_set_suspend_mode(struct regulator_dev
*rdev,
val = MAX77686_LDO_LOWPOWER_PWRREQ;
break;
case REGULATOR_MODE_NORMAL: /* ON in Normal Mode */
- val = MAX77686_NORMAL;
+ val = max77686_map_normal_mode(max77686, id);
break;
default:
pr_warn("%s: regulator_suspend_mode : 0x%x not supported\n",
@@ -160,7 +188,7 @@ static int max77686_ldo_set_suspend_mode(struct
regulator_dev *rdev,
{
unsigned int val;
struct max77686_data *max77686 = rdev_get_drvdata(rdev);
- int ret;
+ int ret, id = rdev_get_id(rdev);
switch (mode) {
case REGULATOR_MODE_STANDBY:/* switch off */
@@ -170,7 +198,7 @@ static int max77686_ldo_set_suspend_mode(struct
regulator_dev *rdev,
val = MAX77686_LDO_LOWPOWER_PWRREQ;
break;
case REGULATOR_MODE_NORMAL: /* ON in Normal Mode */
- val = MAX77686_NORMAL;
+ val = max77686_map_normal_mode(max77686, id);
break;
default:
pr_warn("%s: regulator_suspend_mode : 0x%x not supported\n",
@@ -184,7 +212,7 @@ static int max77686_ldo_set_suspend_mode(struct
regulator_dev *rdev,
if (ret)
return ret;
- max77686->opmode[rdev_get_id(rdev)] = val;
+ max77686->opmode[id] = val;
return 0;
}
@@ -197,7 +225,7 @@ static int max77686_enable(struct regulator_dev *rdev)
shift = max77686_get_opmode_shift(id);
if (max77686->opmode[id] == MAX77686_OFF_PWRREQ)
- max77686->opmode[id] = MAX77686_NORMAL;
+ max77686->opmode[id] = max77686_map_normal_mode(max77686, id);
return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
rdev->desc->enable_mask,
@@ -229,6 +257,36 @@ static int max77686_set_ramp_delay(struct regulator_dev
*rdev, int ramp_delay)
MAX77686_RAMP_RATE_MASK, ramp_value << 6);
}
+static int max77686_of_parse_cb(struct device_node *np,
+ const struct regulator_desc *desc,
+ struct regulator_config *config)
+{
+ struct max77686_data *max77686 = config->driver_data;
+
+ switch (desc->id) {
+ case MAX77686_BUCK8:
+ case MAX77686_BUCK9:
+ case MAX77686_LDO20 ... MAX77686_LDO22:
+ config->ena_gpio = of_get_named_gpio(np,
+ "maxim,ena-gpios", 0);
+ config->ena_gpio_flags = GPIOF_OUT_INIT_HIGH;
+ config->ena_gpio_initialized = true;
+ break;
+ default:
+ return 0;
+ }
+
+ if (gpio_is_valid(config->ena_gpio)) {
+
[PATCH v5 1/5] regulator: Copy config passed during registration
Copy the 'regulator_config' structure passed to regulator_register()
function so the driver could safely modify it after parsing init data.
The driver may want to change the config as a result of specific init
data parsed by regulator core (e.g. when core handled parsing device
tree).
Signed-off-by: Krzysztof Kozlowski
---
drivers/regulator/core.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index e225711bb8bc..c13b557a560e 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -3581,20 +3581,21 @@ static void rdev_init_debugfs(struct regulator_dev
*rdev)
*/
struct regulator_dev *
regulator_register(const struct regulator_desc *regulator_desc,
- const struct regulator_config *config)
+ const struct regulator_config *cfg)
{
const struct regulation_constraints *constraints = NULL;
const struct regulator_init_data *init_data;
+ struct regulator_config *config = NULL;
static atomic_t regulator_no = ATOMIC_INIT(0);
struct regulator_dev *rdev;
struct device *dev;
int ret, i;
const char *supply = NULL;
- if (regulator_desc == NULL || config == NULL)
+ if (regulator_desc == NULL || cfg == NULL)
return ERR_PTR(-EINVAL);
- dev = config->dev;
+ dev = cfg->dev;
WARN_ON(!dev);
if (regulator_desc->name == NULL || regulator_desc->ops == NULL)
@@ -3624,6 +3625,16 @@ regulator_register(const struct regulator_desc
*regulator_desc,
if (rdev == NULL)
return ERR_PTR(-ENOMEM);
+ /*
+* Duplicate the config so the driver could override it after
+* parsing init data.
+*/
+ config = kmemdup(cfg, sizeof(*cfg), GFP_KERNEL);
+ if (config == NULL) {
+ kfree(rdev);
+ return ERR_PTR(-ENOMEM);
+ }
+
init_data = regulator_of_get_init_data(dev, regulator_desc,
&rdev->dev.of_node);
if (!init_data) {
@@ -3752,6 +3763,7 @@ add_dev:
rdev_init_debugfs(rdev);
out:
mutex_unlock(®ulator_list_mutex);
+ kfree(config);
return rdev;
unset_supplies:
--
1.9.1
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[PATCH v5 4/5] mfd/regulator: dt-bindings: max77686: Document gpio properties
Document usage of maxim,ena-gpios properties which turn on external/GPIO
control over regulator.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/mfd/max77686.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt
b/Documentation/devicetree/bindings/mfd/max77686.txt
index 75fdfaf41831..e39f0bc1f55e 100644
--- a/Documentation/devicetree/bindings/mfd/max77686.txt
+++ b/Documentation/devicetree/bindings/mfd/max77686.txt
@@ -39,6 +39,12 @@ to get matched with their hardware counterparts as follow:
-BUCKn : 1-4.
Use standard regulator bindings for it ('regulator-off-in-suspend').
+ LDO20, LDO21, LDO22, BUCK8 and BUCK9 can be configured to GPIO enable
+ control. To turn this feature on this property must be added to the regulator
+ sub-node:
+ - maxim,ena-gpios : one GPIO specifier enable control (the gpio
+ flags are actually ignored and always
+ ACTIVE_HIGH is used)
Example:
@@ -65,4 +71,12 @@ Example:
regulator-always-on;
regulator-boot-on;
};
+
+ buck9_reg {
+ regulator-compatible = "BUCK9";
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <120>;
+ maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
+ };
}
--
1.9.1
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[PATCH v5 5/5] ARM: dts: exynos4412-trats: Switch max77686 regulators to GPIO control
Remove fixed regulators (duplicating what max77686 provides) and
add GPIO enable control to max77686 regulators.
This gives the system full control over those regulators. Previously
the state of such regulators was a mixture of what max77686 driver set
over I2C and what regulator-fixed set through GPIO.
Removal of 'regulator-always-on' from CAM_ISP_CORE_1.2V (buck9) allows
disabling it when it is not used. Previously this regulator was always
enabled because its enable state is a OR of:
- ENB9 GPIO (turned always on by regulator-fixed),
- BUCK9EN field in BUCK9CTRL register (off by max77686 through I2C).
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/exynos4412-trats2.dts | 25 +
1 file changed, 5 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 405d4f337e89..186c210680c1 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -58,15 +58,6 @@
#address-cells = <1>;
#size-cells = <0>;
- vemmc_reg: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <280>;
- regulator-max-microvolt = <280>;
- gpio = <&gpk0 2 0>;
- enable-active-high;
- };
-
cam_io_reg: voltage-regulator-1 {
compatible = "regulator-fixed";
regulator-name = "CAM_SENSOR_A";
@@ -94,16 +85,6 @@
enable-active-high;
};
- cam_isp_core_reg: voltage-regulator-4 {
- compatible = "regulator-fixed";
- regulator-name = "CAM_ISP_CORE_1.2V_EN";
- regulator-min-microvolt = <120>;
- regulator-max-microvolt = <120>;
- gpio = <&gpm0 3 0>;
- enable-active-high;
- regulator-always-on;
- };
-
ps_als_reg: voltage-regulator-5 {
compatible = "regulator-fixed";
regulator-name = "LED_A_3.0V";
@@ -405,6 +386,7 @@
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <280>;
regulator-max-microvolt = <280>;
+ maxim,ena-gpios = <&gpy2 0
GPIO_ACTIVE_HIGH>;
};
ldo22_reg: ldo22 {
@@ -412,6 +394,7 @@
regulator-name = "VMEM_VDD_2.8V";
regulator-min-microvolt = <280>;
regulator-max-microvolt = <280>;
+ maxim,ena-gpios = <&gpk0 2
GPIO_ACTIVE_HIGH>;
};
ldo23_reg: ldo23 {
@@ -518,6 +501,7 @@
regulator-name = "VMEM_VDDF_3.0V";
regulator-min-microvolt = <285>;
regulator-max-microvolt = <285>;
+ maxim,ena-gpios = <&gpk0 2
GPIO_ACTIVE_HIGH>;
};
buck9_reg: buck9 {
@@ -525,6 +509,7 @@
regulator-name = "CAM_ISP_CORE_1.2V";
regulator-min-microvolt = <100>;
regulator-max-microvolt = <120>;
+ maxim,ena-gpios = <&gpm0 3
GPIO_ACTIVE_HIGH>;
};
};
};
@@ -587,7 +572,7 @@
broken-cd;
non-removable;
card-detect-delay = <200>;
- vmmc-supply = <&vemmc_reg>;
+ vmmc-supply = <&ldo22_reg>;
clock-frequency = <4>;
samsung,dw-mshc-ciu-div = <0>;
samsung,dw-mshc-sdr-timing = <2 3>;
--
1.9.1
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[PATCH v5 2/5] regulator: Allow parsing custom properties when using simplified DT parsing
When drivers use simplified DT parsing method (they provide
'regulator_desc.of_match') they still may want to parse custom
properties for some of the regulators. For example some of the
regulators support GPIO enable control.
Add a driver-supplied callback for such case. This way the regulator
core parses common bindings offloading a lot of code from drivers and
still custom properties may be used.
The callback, called for each parsed regulator, may modify the
'regulator_config' initially passed to regulator_register().
Signed-off-by: Krzysztof Kozlowski
---
drivers/regulator/core.c | 2 +-
drivers/regulator/internal.h | 2 ++
drivers/regulator/of_regulator.c | 11 +++
include/linux/regulator/driver.h | 13 +
4 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index c13b557a560e..5fae8cabd254 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -3635,7 +3635,7 @@ regulator_register(const struct regulator_desc
*regulator_desc,
return ERR_PTR(-ENOMEM);
}
- init_data = regulator_of_get_init_data(dev, regulator_desc,
+ init_data = regulator_of_get_init_data(dev, regulator_desc, config,
&rdev->dev.of_node);
if (!init_data) {
init_data = config->init_data;
diff --git a/drivers/regulator/internal.h b/drivers/regulator/internal.h
index 80ba2a35a04b..c74ac8734023 100644
--- a/drivers/regulator/internal.h
+++ b/drivers/regulator/internal.h
@@ -38,11 +38,13 @@ struct regulator {
#ifdef CONFIG_OF
struct regulator_init_data *regulator_of_get_init_data(struct device *dev,
const struct regulator_desc *desc,
+struct regulator_config *config,
struct device_node **node);
#else
static inline struct regulator_init_data *
regulator_of_get_init_data(struct device *dev,
const struct regulator_desc *desc,
+ struct regulator_config *config,
struct device_node **node)
{
return NULL;
diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c
index 91eaaf010524..24e812c48d93 100644
--- a/drivers/regulator/of_regulator.c
+++ b/drivers/regulator/of_regulator.c
@@ -270,6 +270,7 @@ EXPORT_SYMBOL_GPL(of_regulator_match);
struct regulator_init_data *regulator_of_get_init_data(struct device *dev,
const struct regulator_desc *desc,
+ struct regulator_config *config,
struct device_node **node)
{
struct device_node *search, *child;
@@ -307,6 +308,16 @@ struct regulator_init_data
*regulator_of_get_init_data(struct device *dev,
break;
}
+ if (desc->of_parse_cb) {
+ if (desc->of_parse_cb(child, desc, config)) {
+ dev_err(dev,
+ "driver callback failed to parse DT for
regulator %s\n",
+ child->name);
+ init_data = NULL;
+ break;
+ }
+ }
+
of_node_get(child);
*node = child;
break;
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 5f1e9ca47417..d4ad5b5a02bb 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -21,6 +21,7 @@
struct regmap;
struct regulator_dev;
+struct regulator_config;
struct regulator_init_data;
struct regulator_enable_gpio;
@@ -205,6 +206,15 @@ enum regulator_type {
* @supply_name: Identifying the regulator supply
* @of_match: Name used to identify regulator in DT.
* @regulators_node: Name of node containing regulator definitions in DT.
+ * @of_parse_cb: Optional callback called only if of_match is present.
+ * Will be called for each regulator parsed from DT, during
+ * init_data parsing.
+ * The regulator_config passed as argument to the callback will
+ * be a copy of config passed to regulator_register, valid only
+ * for this particular call. Callback may freely change the
+ * config but it cannot store it for later usage.
+ * Callback should return 0 on success or negative ERRNO
+ * indicating failure.
* @id: Numerical identifier for the regulator.
* @ops: Regulator operations table.
* @irq: Interrupt number for the regulator.
@@ -251,6 +261,9 @@ struct regulator_desc {
const char *supply_name;
const char *of_match;
const char *regulators_node;
+ int (*of_parse_cb)(struct device_node *,
+
Re: [alsa-devel] [PATCH 1/3] ASoC: samsung: Add machine driver for Trats2
Hi,
A few small comments inline.
On 01/05/2015 12:25 PM, Inha Song wrote:
--- /dev/null
+++ b/sound/soc/samsung/trats2_wm1811.c
@@ -0,0 +1,216 @@
[...]
+#include
+#include
+#include
+#include
+#include
+#include "i2s.h"
+#include "i2s-regs.h"
You probably don't need i2s-regs.h
+#include "../codecs/wm8994.h"
+
+struct trats2_machine_priv {
+ struct clk *clk_mclk;
+};
+
+static struct trats2_machine_priv trats2_wm1811_priv;
+
+static const struct snd_kcontrol_new trats2_controls[] = {
+ SOC_DAPM_PIN_SWITCH("SPK"),
+};
+
+const struct snd_soc_dapm_widget trats2_dapm_widgets[] = {
static
+ SND_SOC_DAPM_SPK("SPK", NULL),
+};
+
+static int trats2_aif1_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
+ unsigned int sysclk_rate;
+ unsigned int mclk_rate =
+ (unsigned int)clk_get_rate(priv->clk_mclk);
+ int ret;
+
+ /* Set the codec DAI configuration to Master*/
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0) {
+ dev_err(codec_dai->dev,
+ "Failed to set codec dai format: %d\n", ret);
+ return ret;
+ }
+
+ /* Set the cpu DAI configuration to Slave */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev,
+ "Failed to set cpu dai format: %d\n", ret);
+ return ret;
+ }
Use the dai_fmt field in the dai_link struct to setup the DAI link format.
This will configure both the CPU and the CODEC DAI with the specified
format, no need to do it manually.
[...]
+static struct snd_soc_ops trats2_aif1_ops = {
const
+ .hw_params = trats2_aif1_hw_params,
+};
+
+static int trats2_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_codec *codec = rtd->codec;
+ struct snd_soc_card *card = rtd->card;
+ struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(card);
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk_mclk);
Maybe just do this in the platform device probe handler and you should have
a matching disable call somewhere.
+ if (ret) {
+ dev_err(codec->dev, "Failed to enable mclk: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
[...]
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Re: [PATCH] iommu: Fix build of allmod/allyes config on ARMv8 architecture
On Mon, Jan 05, 2015 at 12:09:03PM +0100, Krzysztof Kozlowski wrote: > Thanks, but... Few days after my patch Mark Brown posted something > similar: > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310743.html > > It was merged by Arnd Bergman and sent to Linus around 3.19-rc1. It is > merged in mainline now: > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=20911ce6078fd1503dbf73f761316c66738bf83b > > ... so my patch can be dropped. Okay, thanks. Patch is dropped. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[alsa-devel] [PATCH 2/3] ASoC: samsung: Document Trats2 audio subsystem bindings
This patch add Trats2 audio subsystem bindings document.
Signed-off-by: Inha Song
---
.../bindings/sound/samsung,trats2-wm1811.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt
diff --git a/Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt
b/Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt
new file mode 100644
index 000..9d4d3f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt
@@ -0,0 +1,31 @@
+Samsung Exynos Trats2 audio with WM1811 codec
+
+Required properties:
+
+ - compatible : Must be "samsung,trats2-audio"
+
+ - clocks : Reference to the codec master clock
+ - clock-names : The clock should be named "mclk"
+
+ - samsung,i2s-controller : The phandle of the I2S controller
+
+ - samsung,model : The user visible name of this sound
+
+ - samsung,audio-routing : A list of the connections between audio
+ components. each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's source
+
+Example:
+
+sound {
+ compatible = "samsung,trats2-audio";
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "mclk";
+ samsung,i2s-controller = <&i2s0>;
+ samsung,model = "wm1811";
+ samsung,audio-routing =
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+ "SPK", "SPKOUTRN",
+ "SPK", "SPKOUTRP";
+};
--
2.0.0.390.gcb682f8
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[alsa-devel] [PATCH 1/3] ASoC: samsung: Add machine driver for Trats2
This patch add the sound machine driver for Trats2 board.
The codec operate in master mode. So, Reference to the
codec master clock must be defined in DT.
Signed-off-by: Inha Song
---
sound/soc/samsung/Kconfig | 8 ++
sound/soc/samsung/Makefile| 2 +
sound/soc/samsung/trats2_wm1811.c | 216 ++
3 files changed, 226 insertions(+)
create mode 100644 sound/soc/samsung/trats2_wm1811.c
diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index fc67f97..8031423 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -245,3 +245,11 @@ config SND_SOC_ARNDALE_RT5631_ALC5631
depends on SND_SOC_SAMSUNG
select SND_SAMSUNG_I2S
select SND_SOC_RT5631
+
+config SND_SOC_SAMSUNG_TRATS2_WM1811
+ tristate "SoC I2S Audio support for WM1811 on Tizen Trats2 board"
+ depends on SND_SOC_SAMSUNG
+ select SND_SOC_WM8994
+ select SND_SAMSUNG_I2S
+ help
+ Say Y if you want to add support for SoC audio on the Tizen Trats2
board.
diff --git a/sound/soc/samsung/Makefile b/sound/soc/samsung/Makefile
index 31e3dba..e2b7b1b 100644
--- a/sound/soc/samsung/Makefile
+++ b/sound/soc/samsung/Makefile
@@ -46,6 +46,7 @@ snd-soc-littlemill-objs := littlemill.o
snd-soc-bells-objs := bells.o
snd-soc-odroidx2-max98090-objs := odroidx2_max98090.o
snd-soc-arndale-rt5631-objs := arndale_rt5631.o
+snd-soc-trats2-wm1811-objs := trats2_wm1811.o
obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o
obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
@@ -73,3 +74,4 @@ obj-$(CONFIG_SND_SOC_LITTLEMILL) += snd-soc-littlemill.o
obj-$(CONFIG_SND_SOC_BELLS) += snd-soc-bells.o
obj-$(CONFIG_SND_SOC_ODROIDX2) += snd-soc-odroidx2-max98090.o
obj-$(CONFIG_SND_SOC_ARNDALE_RT5631_ALC5631) += snd-soc-arndale-rt5631.o
+obj-$(CONFIG_SND_SOC_SAMSUNG_TRATS2_WM1811) += snd-soc-trats2-wm1811.o
diff --git a/sound/soc/samsung/trats2_wm1811.c
b/sound/soc/samsung/trats2_wm1811.c
new file mode 100644
index 000..fc96842
--- /dev/null
+++ b/sound/soc/samsung/trats2_wm1811.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "i2s.h"
+#include "i2s-regs.h"
+#include "../codecs/wm8994.h"
+
+struct trats2_machine_priv {
+ struct clk *clk_mclk;
+};
+
+static struct trats2_machine_priv trats2_wm1811_priv;
+
+static const struct snd_kcontrol_new trats2_controls[] = {
+ SOC_DAPM_PIN_SWITCH("SPK"),
+};
+
+const struct snd_soc_dapm_widget trats2_dapm_widgets[] = {
+ SND_SOC_DAPM_SPK("SPK", NULL),
+};
+
+static int trats2_aif1_hw_params(struct snd_pcm_substream *substream,
+struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
+ unsigned int sysclk_rate;
+ unsigned int mclk_rate =
+ (unsigned int)clk_get_rate(priv->clk_mclk);
+ int ret;
+
+ /* Set the codec DAI configuration to Master*/
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0) {
+ dev_err(codec_dai->dev,
+ "Failed to set codec dai format: %d\n", ret);
+ return ret;
+ }
+
+ /* Set the cpu DAI configuration to Slave */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev,
+ "Failed to set cpu dai format: %d\n", ret);
+ return ret;
+ }
+
+ /* SYSCLK must be greater than 4.096MHz */
+ if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ sysclk_rate = params_rate(params) * 512;
+ else
+ sysclk_rate = params_rate(params) * 256;
+
+ /* Set the codec FLL1 */
+ ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
+ mclk_rate, sysclk_rate);
+ if (ret < 0) {
+ dev_err(codec_dai->dev, "Failed to set FLL1: %d\n", ret);
+ return ret;
+ }
+
+ /* Set the codec SYSCLK */
+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
+
[alsa-devel] [PATCH 3/3] ARM: dts: Add sound nodes for exynos4412-trats2
This patch add WM1811 audio codec, I2S interface and the sound
machine nodes to enable audio on exynos4412-trats2 board.
Signed-off-by: Inha Song
---
arch/arm/boot/dts/exynos4412-trats2.dts | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 29231b4..2943ce7 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -203,6 +203,23 @@
};
};
+ i2c@138A {
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <10>;
+ pinctrl-0 = <&i2c4_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ wm1811: wm1811@1a {
+ compatible = "wlf,wm1811";
+ reg = <0x1a>;
+ DCVDD-supply = <&ldo3_reg>;
+ DBVDD1-supply = <&ldo3_reg>;
+ wlf,ldo1ena = <&gpj0 4 0>;
+ };
+ };
+
i2c@138D {
samsung,i2c-sda-delay = <100>;
samsung,i2c-slave-addr = <0x10>;
@@ -838,6 +855,27 @@
};
};
+ i2s0: i2s@0383 {
+ pinctrl-0 = <&i2s0_bus>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ sound {
+ compatible = "samsung,trats2-audio";
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "mclk";
+ assigned-clocks = <&pmu_system_controller 0>;
+ assigned-clock-parents = <&clock CLK_XUSBXTI>;
+ samsung,i2s-controller = <&i2s0>;
+ samsung,model = "wm1811";
+ samsung,audio-routing =
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+ "SPK", "SPKOUTRN",
+ "SPK", "SPKOUTRP";
+ };
+
exynos-usbphy@125B {
status = "okay";
};
--
2.0.0.390.gcb682f8
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[alsa-devel] [PATCH 0/3] Sound support for Exynos4412 Trats2 board
This patch-set adds basic sound support for the Trats2 boards. It just support primary I2s and external speaker playback. Inha Song (3): ASoC: samsung: Add machine driver for Trats2 ASoC: samsung: Document Trats2 audio subsystem bindings ARM: dts: Add sound nodes for exynos4412-trats2 .../bindings/sound/samsung,trats2-wm1811.txt | 31 +++ arch/arm/boot/dts/exynos4412-trats2.dts| 38 sound/soc/samsung/Kconfig | 8 + sound/soc/samsung/Makefile | 2 + sound/soc/samsung/trats2_wm1811.c | 216 + 5 files changed, 295 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/samsung,trats2-wm1811.txt create mode 100644 sound/soc/samsung/trats2_wm1811.c -- 2.0.0.390.gcb682f8 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] iommu: Fix build of allmod/allyes config on ARMv8 architecture
On pon, 2015-01-05 at 12:03 +0100, Joerg Roedel wrote: > On Fri, Dec 05, 2014 at 02:47:37PM +0100, Krzysztof Kozlowski wrote: > > drivers/iommu/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > Applied to iommu/fixes, thanks. Thanks, but... Few days after my patch Mark Brown posted something similar: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/310743.html It was merged by Arnd Bergman and sent to Linus around 3.19-rc1. It is merged in mainline now: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=20911ce6078fd1503dbf73f761316c66738bf83b ... so my patch can be dropped. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] iommu: Fix build of allmod/allyes config on ARMv8 architecture
On Fri, Dec 05, 2014 at 02:47:37PM +0100, Krzysztof Kozlowski wrote: > drivers/iommu/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to iommu/fixes, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/9] hwmon: dts: Doc: Add DTS doc to explain how to use PWM FAN as a cooling device
Hey Lukasz, Blame the holiday season for my late reply ;) On Fri, 2014-12-19 at 17:13 +0100, Lukasz Majewski wrote: > Hi Guenter, > > > On Fri, Dec 19, 2014 at 04:32:24PM +0100, Lukasz Majewski wrote: > > > Hi Sjoerd, > > > > > > Thanks for your feedback and sorry for a late reply. > > > > > > > On Thu, 2014-12-18 at 11:13 +0100, Lukasz Majewski wrote: > > > > > Several new properties to allow PWM fan working as a cooling > > > > > device have been combined into this single commit. > > > > > > > > > > Signed-off-by: Lukasz Majewski > > > > > --- > > > > > .../devicetree/bindings/hwmon/pwm-fan.txt | 28 > > > > > ++ 1 file changed, 28 insertions(+) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt > > > > > b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt index > > > > > 610757c..3877810 100644 --- > > > > > a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt +++ > > > > > b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt @@ -3,10 > > > > > +3,38 @@ Bindings for a fan connected to the PWM lines Required > > > > > properties: > > > > > - compatible : "pwm-fan" > > > > > - pwms : the PWM that is used to control the > > > > > PWM fan +- cooling-pwm-values : PWM duty cycle values > > > > > relative to > > > > > + cooling-max-pwm-value correspondig > > > > > to > > > > > + proper cooling states > > > > > +- default-pulse-width : Property specifying default pulse > > > > > width for FAN > > > > > + at system boot (zero to disable > > > > > FAN on boot). > > > > > + Allowed range is 0 to 255 > > > > > > > > The 0..255 range seems somewhat random. Would be nicer to either > > > > use the approach of pwm-backlight (iotw, have the range go from > > > > the first to the last entry of cooling-pwm-values) > > > > > > I'm OK to change the default-pulse-width to be similar to > > > "default-brightness-level" (as it is in > > > Documentation/devicetree/bindings/video/backlight/pwm-backlight.txt) > > > > > > > or simply have be the duty > > > > lenght in NS as entries instead of the current indirection. > > > > > > I'd prefer to keep the indirection - as it is utilized in the > > > current pwm-fan.c driver. > > > > > FWIW, devicetree information is supposed to be implementation > > independent. So this is a poor argument. > > Many other pwm drivers use the indirection - e.g. mentioned > pwm-backlight. I don't specifically mind the indirection, i was just thinking out loud whether it added value (but if it's quite common, might indeed be good to keep the pattern). What i do dislike is the number of levels is being set to an arbitrary levels, as that will very rarely match the actual number of distinct pwm levels you One thing though, when following the pattern of the pwm-backlight driver; In pwm-backlight the highest index of brightness-levels is always 100% duty cycle.. On e.g. XU3 the vendor kernel never drives the fan at 100% duty (maximum of 91%). So it would be nice if the dt bindigns could model that e.g. by having: pwm-levels = <20>; // 21 distinct pwm levels valid-pwm-level = <5 15 18>; /* 5 15 and 18 are usable levels - pwm will default to highest level */ > > > Enabling pan to full RPM was the default behaviour in the current > > > pwm-fan.c file. > > > > > > To be honest, there is no need to enable fan to full RPM speed in > > > this board for following reasons: > > > 1. In Odroid the FAN is optional (stacked on top of a heat sink) - > > > very often it is just enough to only have the heat sink. > > > > > > 2. Odroid has thermal enabled by default and IMHO it would be more > > > feasible to allow thermal to control fan from the very beginning. > > > > > > However, I can also understand if the policy for hwmon implies a > > > rule to enable by default all fans to full RPM speed. > > > > > Why and how does that all suggest that the current default behavior > > should be changed ? > > I wanted to avoid the unpleasant sound for full speed fan when thermal > is not enabled by default. > > But as I said, I fully understand the policy and I would be happy to > comply with it as thermal should reduce the fan speed anyway at boot > time. Yeah, what happens on my XU3 is that u-boot sets the pwm to 100% duty and the thermal infrastructure turns it off as soon as it gets into control, which works quite nicely (and keeps my sanity as that fan at 100% is *loud*)... So if you want to avoid unpleasant sounds, just build with thermal :p -- Sjoerd Simons Collabora Ltd. smime.p7s Description: S/MIME cryptographic signature
RE: kernel panic when booting on exynos 5440
Ming Lei wrote: > > Hi Guys, > Hi, Sorry for late response. > On Thu, Dec 25, 2014 at 6:32 PM, Pankaj Dubey > wrote: > > +CC: Thomas Abraham > > > > Hi Ming, > > > > On Thursday 25 December 2014 02:18 PM, Ming Lei wrote: > >> > >> Hi Pankaj, > >> > >> In your commit fce9e5bb2(ARM: EXYNOS: Add support for > >> mapping PMU base address via DT), 'pmu_base_addr' is > >> only parsed for very limited machines from the table of > >> 'exynos_dt_pmu_match'. For other boards, 'pmu_base_addr' > >> will keep its default value of null, then panic() is triggered. > >> > > > > Yes, it will. > > As exynos5440 DT does not have PMU device node, neither above mentioned > > patch added corresponding matching device_id. > > If I remember correctly, I might have missed this because exynos5440 DT was > > not having PMU node. > > > >> What do you think about the problem? > > > > > > I missed this part, and I should have taken care of this in original patch > > itself. Well as of now I can think of only one solution that if we really > > want to keep support for exynos5440 in mainline kernel, to avoid above issue > > we should skip pmu mapping for exynos5440. In this case following patch will > > do this work. > > > > Also I will like to know from Kukjin that what best can be done now. > > If he is OK with below solution I can post the same. > > > > --- > > > > Subject: [PATCH] ARM: EXYNOS: do not try to map PMU for exynos5440 > > > > Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care > > of mapping of exynos5440 PMU register which will result in kernel panic. > > As of now let's avoid mapping of exynos5440 PMU. > > > > Signed-off-by: Pankaj Dubey > > Is there any opportunity to merge the fix? Or exynos5440 will not be > supported in future? > Basically, I'm fine on the change like others for exynos5440 at this moment and if any other comments, I'll let you know on the patch in mailing list. Happy new year. Thanks, Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: do not try to map PMU for exynos5440
Hi,
On Monday 05 January 2015 03:22 PM, Sjoerd Simons wrote:
On Mon, 2015-01-05 at 14:44 +0530, Pankaj Dubey wrote:
Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
of mapping of exynos5440 PMU register which will result in kernel panic
on exynos5440.
As exynos5440 DTS does not have PMU node, and also we are skipping
exynos_pm_init in case of exynos5440, let's avoid mapping of exynos5440 PMU.
Reported-by: Ming Lei
Signed-off-by: Pankaj Dubey
---
arch/arm/mach-exynos/exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..1891b8c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -208,7 +208,8 @@ static void __init exynos_init_irq(void)
* DT is not unflatten so we can't use DT APIs before
* init_irq
*/
- exynos_map_pmu();
+ if (!of_machine_is_compatible("samsung,exynos5440"))
+ exynos_map_pmu();
}
static void __init exynos_dt_machine_init(void)
Why the blacklist approach rather then simply making exynos_map_pmu exit
rather then panicing if it couldn't find a pmu node in the dts?
exynos_map_pmu is panicking if it fails to iomap PMU, as for most of
exynos SoCs PMU based address is MUST for secondary core bootup in
platsmp.c, but with exynos5440 it is not the same case. In-fact
exynos_pm_init is also bypassed for exynos5440. For the same reason I
adopted this approach rather removing panic from exynos_map_pmu.
Thanks,
Pankaj Dubey
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[PATCH 1/2] clk: Add clk_unregister_{divider,gate,mux} to close memory leak
The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.
Add corresponding unregister functions which will release all resources.
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/clk-divider.c| 16
drivers/clk/clk-gate.c | 16
drivers/clk/clk-mux.c| 16
include/linux/clk-provider.h | 4
4 files changed, 52 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b335c5..c2bb9f679ec6 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -463,3 +463,19 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
width, clk_divider_flags, table, lock);
}
EXPORT_SYMBOL_GPL(clk_register_divider_table);
+
+void clk_unregister_divider(struct clk *clk)
+{
+ struct clk_divider *div;
+ struct clk_hw *hw;
+
+ hw = __clk_get_hw(clk);
+ if (!hw)
+ return;
+
+ div = to_clk_divider(hw);
+
+ clk_unregister(clk);
+ kfree(div);
+}
+EXPORT_SYMBOL_GPL(clk_unregister_divider);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 51fd87fb7ba6..186b96efeebf 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -162,3 +162,19 @@ struct clk *clk_register_gate(struct device *dev, const
char *name,
return clk;
}
EXPORT_SYMBOL_GPL(clk_register_gate);
+
+void clk_unregister_gate(struct clk *clk)
+{
+ struct clk_gate *gate;
+ struct clk_hw *hw;
+
+ hw = __clk_get_hw(clk);
+ if (!hw)
+ return;
+
+ gate = to_clk_gate(hw);
+
+ clk_unregister(clk);
+ kfree(gate);
+}
+EXPORT_SYMBOL_GPL(clk_unregister_gate);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 6e1ecf94bf58..69a094c3783d 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -177,3 +177,19 @@ struct clk *clk_register_mux(struct device *dev, const
char *name,
NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_register_mux);
+
+void clk_unregister_mux(struct clk *clk)
+{
+ struct clk_mux *mux;
+ struct clk_hw *hw;
+
+ hw = __clk_get_hw(clk);
+ if (!hw)
+ return;
+
+ mux = to_clk_mux(hw);
+
+ clk_unregister(clk);
+ kfree(mux);
+}
+EXPORT_SYMBOL_GPL(clk_unregister_mux);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d936409520f8..ebb7055a6d84 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -294,6 +294,7 @@ struct clk *clk_register_gate(struct device *dev, const
char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock);
+void clk_unregister_gate(struct clk *clk);
struct clk_div_table {
unsigned intval;
@@ -361,6 +362,7 @@ struct clk *clk_register_divider_table(struct device *dev,
const char *name,
void __iomem *reg, u8 shift, u8 width,
u8 clk_divider_flags, const struct clk_div_table *table,
spinlock_t *lock);
+void clk_unregister_divider(struct clk *clk);
/**
* struct clk_mux - multiplexer clock
@@ -411,6 +413,8 @@ struct clk *clk_register_mux_table(struct device *dev,
const char *name,
void __iomem *reg, u8 shift, u32 mask,
u8 clk_mux_flags, u32 *table, spinlock_t *lock);
+void clk_unregister_mux(struct clk *clk);
+
void of_fixed_factor_clk_setup(struct device_node *node);
/**
--
1.9.1
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[PATCH 2/2] clk: exynos-audss: Fix memory leak on driver unbind or probe failure
The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.
Use clk_unregister_{gate,divider,mux} to release all resources.
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/samsung/clk-exynos-audss.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index f2c2ccce49bb..454b02ae486a 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -82,6 +82,26 @@ static const struct of_device_id exynos_audss_clk_of_match[]
= {
{},
};
+static void exynos_audss_clk_teardown(void)
+{
+ int i;
+
+ for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_mux(clk_table[i]);
+ }
+
+ for (; i < EXYNOS_SRP_CLK; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_divider(clk_table[i]);
+ }
+
+ for (; i < clk_data.clk_num; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister_gate(clk_table[i]);
+ }
+}
+
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
@@ -219,10 +239,7 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
return 0;
unregister:
- for (i = 0; i < clk_data.clk_num; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister(clk_table[i]);
- }
+ exynos_audss_clk_teardown();
if (!IS_ERR(epll))
clk_disable_unprepare(epll);
@@ -232,18 +249,13 @@ unregister:
static int exynos_audss_clk_remove(struct platform_device *pdev)
{
- int i;
-
#ifdef CONFIG_PM_SLEEP
unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
of_clk_del_provider(pdev->dev.of_node);
- for (i = 0; i < clk_data.clk_num; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister(clk_table[i]);
- }
+ exynos_audss_clk_teardown();
if (!IS_ERR(epll))
clk_disable_unprepare(epll);
--
1.9.1
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Re: [PATCH] ARM: EXYNOS: do not try to map PMU for exynos5440
On Mon, 2015-01-05 at 14:44 +0530, Pankaj Dubey wrote:
> Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
> of mapping of exynos5440 PMU register which will result in kernel panic
> on exynos5440.
>
> As exynos5440 DTS does not have PMU node, and also we are skipping
> exynos_pm_init in case of exynos5440, let's avoid mapping of exynos5440 PMU.
> Reported-by: Ming Lei
> Signed-off-by: Pankaj Dubey
> ---
> arch/arm/mach-exynos/exynos.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> index c13d083..1891b8c 100644
> --- a/arch/arm/mach-exynos/exynos.c
> +++ b/arch/arm/mach-exynos/exynos.c
> @@ -208,7 +208,8 @@ static void __init exynos_init_irq(void)
>* DT is not unflatten so we can't use DT APIs before
>* init_irq
>*/
> - exynos_map_pmu();
> + if (!of_machine_is_compatible("samsung,exynos5440"))
> + exynos_map_pmu();
> }
>
> static void __init exynos_dt_machine_init(void)
Why the blacklist approach rather then simply making exynos_map_pmu exit
rather then panicing if it couldn't find a pmu node in the dts?
--
Sjoerd Simons
Collabora Ltd.
smime.p7s
Description: S/MIME cryptographic signature
Re: [PATCH] ARM: samsung: add exynos-chipid binding information
Gentle Ping.
On Wednesday 03 December 2014 01:14 PM, Pankaj Dubey wrote:
Exynos SoC's DT files are using Chipid device nodes, but it's binding
information is missing. This patch adds exynos-chipid binding information.
Signed-off-by: Pankaj Dubey
---
.../bindings/arm/samsung/exynos-chipid.txt | 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
new file mode 100644
index 000..85c5dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
@@ -0,0 +1,12 @@
+SAMSUNG Exynos SoCs Chipid driver.
+
+Required properties:
+- compatible : Should at least contain "samsung,exynos4210-chipid".
+
+- reg: offset and length of the register set
+
+Example:
+ chipid@1000 {
+ compatible = "samsung,exynos4210-chipid";
+ reg = <0x1000 0x100>;
+ };
Thanks,
Pankaj Dubey
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[RESEND PATCH v6] ARM: EXYNOS: Remove i2c sys configuration related code
As all these code has been moved into i2c driver, now we can
safely remove them from machine files.
CC: Russell King
Signed-off-by: Pankaj Dubey
---
This patch is leftover patch from patch series [1], resending it after rebasing.
It can be cleanly applied on kgene/for-next and linux-next/next-20150103.
[1]: http://www.spinics.net/lists/linux-samsung-soc/msg39440.html
arch/arm/mach-exynos/exynos.c | 39 ++---
arch/arm/mach-exynos/include/mach/map.h | 3 ---
arch/arm/mach-exynos/pm.c | 3 ++-
arch/arm/mach-exynos/regs-sys.h | 22 ---
arch/arm/mach-exynos/suspend.c | 7 --
5 files changed, 4 insertions(+), 70 deletions(-)
delete mode 100644 arch/arm/mach-exynos/regs-sys.h
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..2c84439 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -27,20 +27,16 @@
#include
#include
+#include
+
#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"
-#include "regs-sys.h"
void __iomem *pmu_base_addr;
static struct map_desc exynos4_iodesc[] __initdata = {
{
- .virtual= (unsigned long)S3C_VA_SYS,
- .pfn= __phys_to_pfn(EXYNOS4_PA_SYSCON),
- .length = SZ_64K,
- .type = MT_DEVICE,
- }, {
.virtual= (unsigned long)S5P_VA_SROMC,
.pfn= __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
@@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
static struct map_desc exynos5_iodesc[] __initdata = {
{
- .virtual= (unsigned long)S3C_VA_SYS,
- .pfn= __phys_to_pfn(EXYNOS5_PA_SYSCON),
- .length = SZ_64K,
- .type = MT_DEVICE,
- }, {
.virtual= (unsigned long)S5P_VA_SROMC,
.pfn= __phys_to_pfn(EXYNOS5_PA_SROMC),
.length = SZ_4K,
@@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)
static void __init exynos_dt_machine_init(void)
{
- struct device_node *i2c_np;
- const char *i2c_compat = "samsung,s3c2440-i2c";
- unsigned int tmp;
- int id;
-
- /*
-* Exynos5's legacy i2c controller and new high speed i2c
-* controller have muxed interrupt sources. By default the
-* interrupts for 4-channel HS-I2C controller are enabled.
-* If node for first four channels of legacy i2c controller
-* are available then re-configure the interrupts via the
-* system register.
-*/
- if (soc_is_exynos5()) {
- for_each_compatible_node(i2c_np, NULL, i2c_compat) {
- if (of_device_is_available(i2c_np)) {
- id = of_alias_get_id(i2c_np, "i2c");
- if (id < 4) {
- tmp = readl(EXYNOS5_SYS_I2C_CFG);
- writel(tmp & ~(0x1 << id),
- EXYNOS5_SYS_I2C_CFG);
- }
- }
- }
- }
-
/*
* This is called from smp_prepare_cpus if we've built for SMP, but
* we still need to set it up for PM and firmware ops if not.
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 1ad3f49..de3ae59 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -24,9 +24,6 @@
#define EXYNOS_PA_CHIPID 0x1000
-#define EXYNOS4_PA_SYSCON 0x1001
-#define EXYNOS5_PA_SYSCON 0x10050100
-
#define EXYNOS4_PA_CMU 0x1003
#define EXYNOS5_PA_CMU 0x1001
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 86f3ecd..dfc8594 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,12 +23,13 @@
#include
#include
+#include
+
#include
#include "common.h"
#include "exynos-pmu.h"
#include "regs-pmu.h"
-#include "regs-sys.h"
static inline void __iomem *exynos_boot_vector_addr(void)
{
diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h
deleted file mode 100644
index 84332b0..000
--- a/arch/arm/mach-exynos/regs-sys.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2014 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - system register definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYS_H
-#define __ASM_ARCH_REGS_
[PATCH] ARM: EXYNOS: do not try to map PMU for exynos5440
Commit id: 2e94ac42898f84d76e3c21dd91bc is not taking care
of mapping of exynos5440 PMU register which will result in kernel panic
on exynos5440.
As exynos5440 DTS does not have PMU node, and also we are skipping
exynos_pm_init in case of exynos5440, let's avoid mapping of exynos5440 PMU.
Reported-by: Ming Lei
Signed-off-by: Pankaj Dubey
---
arch/arm/mach-exynos/exynos.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c13d083..1891b8c 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -208,7 +208,8 @@ static void __init exynos_init_irq(void)
* DT is not unflatten so we can't use DT APIs before
* init_irq
*/
- exynos_map_pmu();
+ if (!of_machine_is_compatible("samsung,exynos5440"))
+ exynos_map_pmu();
}
static void __init exynos_dt_machine_init(void)
--
2.2.0
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Re: [PATCH RESEND] ARM: exynos_defconfig: Enable options for display panel support
Hello Krzysztof,
>> Hello Kukjin,
>>
>> You dropped this patch since exynos drm was causing boot hangs on some
>> platforms but the fix for that issue is already in linux-next (commit:
>> f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable
>> failure due to domain being gated) so I think it makes sense to enable
>> the display options again.
>
> I think these issues were unrelated to each other. DRM was disabled
> because of infinite deferred probing of DRM components. I saw Inki was
> sending some patches for it but I am not sure if they were merged.
>
Ups, you are completely right and it was my bad for pasting the wrong
commit fixing the boot hang when DRM was enabled, I actually meant commit:
("820687be drm/exynos: move Exynos platform drivers registration to init")
which also landed in v3.19-rc1.
Sorry for the confusion.
> Best regards,
> Krzysztof
Best regards,
Javier
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Re: [PATCH RESEND] ARM: exynos_defconfig: Enable options for display panel support
On pią, 2015-01-02 at 17:11 +0100, Javier Martinez Canillas wrote: > Many Exynos devices have a display panel. Most of them just have > a simple panel while others have more complex configurations that > requires an embedded DisplayPort (eDP) to LVDS bridges. > > This patch enables the following features to be built in the kernel > image to support both setups: > > - Direct Rendering Manager (DRM) > - DRM bridge registration and lookup framework > - Parade ps8622/ps8625 eDP/LVDS bridge > - NXP ptn3460 eDP/LVDS bridge > - Exynos Fully Interactive Mobile Display controller (FIMD) > - Panel registration and lookup framework > - Simple panels > - Backlight & LCD device support > > Signed-off-by: Javier Martinez Canillas > Tested-by: Kevin Hilman > Signed-off-by: Kukjin Kim > --- > > Hello Kukjin, > > You dropped this patch since exynos drm was causing boot hangs on some > platforms but the fix for that issue is already in linux-next (commit: > f1e9203 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable > failure due to domain being gated) so I think it makes sense to enable > the display options again. I think these issues were unrelated to each other. DRM was disabled because of infinite deferred probing of DRM components. I saw Inki was sending some patches for it but I am not sure if they were merged. Best regards, Krzysztof > > NOTE: Display panel is still not working since patch "arm: dts: Exynos5: > Use pmu_system_controller phandle for dp phy" is needed [0] but I think > we should enable display options to catch the regressions easier. > > Best regards, > Javier > > [0]: https://lkml.org/lkml/2014/11/24/10 > > arch/arm/configs/exynos_defconfig | 15 +++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/configs/exynos_defconfig > b/arch/arm/configs/exynos_defconfig > index 22beed3..27cdd52 100644 > --- a/arch/arm/configs/exynos_defconfig > +++ b/arch/arm/configs/exynos_defconfig > @@ -111,11 +111,26 @@ CONFIG_REGULATOR_S2MPA01=y > CONFIG_REGULATOR_S2MPS11=y > CONFIG_REGULATOR_S5M8767=y > CONFIG_REGULATOR_TPS65090=y > +CONFIG_DRM=y > +CONFIG_DRM_BRIDGE=y > +CONFIG_DRM_PTN3460=y > +CONFIG_DRM_PS8622=y > +CONFIG_DRM_EXYNOS=y > +CONFIG_DRM_EXYNOS_FIMD=y > +CONFIG_DRM_EXYNOS_DP=y > +CONFIG_DRM_PANEL=y > +CONFIG_DRM_PANEL_SIMPLE=y > CONFIG_FB=y > CONFIG_FB_MODE_HELPERS=y > CONFIG_FB_SIMPLE=y > CONFIG_EXYNOS_VIDEO=y > CONFIG_EXYNOS_MIPI_DSI=y > +CONFIG_BACKLIGHT_LCD_SUPPORT=y > +CONFIG_LCD_CLASS_DEVICE=y > +CONFIG_LCD_PLATFORM=y > +CONFIG_BACKLIGHT_CLASS_DEVICE=y > +CONFIG_BACKLIGHT_GENERIC=y > +CONFIG_BACKLIGHT_PWM=y > CONFIG_FRAMEBUFFER_CONSOLE=y > CONFIG_FONTS=y > CONFIG_FONT_7x14=y -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: Add dts file for odroid XU3 board
Hi Sjoerd,
On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> same as the vendors naming, which means it's prefixed with exynos5422
> instead of exynos5800 as the SoC name even though it includes the
> exyno5800 dtsi.
>
> Signed-off-by: Sjoerd Simons
> ---
> Changes since v1:
> * Add chosen/linux,stdout-path to point the serial console device
> * Change memory start offset to 0x4000 to match the vendors DTS (pointed
> out by Heesub Shin)
> * Declare base address & size for the memory banks to be used by the MFC
>
> Kevin, Tyler, even though the changes are small i didn't want to just stick
> your Tested-By on. Could you both be so kind to retest this on your XU3's ?
>
> Heesub, I would still love to know the reason for having the memory start
> address at 0x4000 for this board?
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos5422-odroidxu3.dts | 332
> +
> 2 files changed, 333 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos5422-odroidxu3.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 38c89ca..0a898cc 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
> exynos5420-arndale-octa.dtb \
> exynos5420-peach-pit.dtb \
> exynos5420-smdk5420.dtb \
> + exynos5422-odroidxu3.dtb \
> exynos5440-sd5v1.dtb \
> exynos5440-ssdk5440.dtb \
> exynos5800-peach-pi.dtb
> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> new file mode 100644
> index 000..0dc9cf8
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
> @@ -0,0 +1,332 @@
> +/*
> + * Hardkernel Odroid XU3 board device tree source
> + *
> + * Copyright (c) 2014 Collabora Ltd.
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +#include "exynos5800.dtsi"
> +
> +/ {
> + model = "Hardkernel Odroid XU3";
> + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800",
> "samsung,exynos5";
> +
> + memory {
> + reg = <0x4000 0x8000>;
> + };
> +
> + chosen {
> + linux,stdout-path = &serial_2;
> + };
> +
> + fimd@1440 {
> + status = "okay";
> + };
> +
> + firmware@02073000 {
> + compatible = "samsung,secure-firmware";
> + reg = <0x02073000 0x1000>;
> + };
> +
> + fixed-rate-clocks {
> + oscclk {
> + compatible = "samsung,exynos5420-oscclk";
> + clock-frequency = <2400>;
> + };
> + };
> +
> + hsi2c_4: i2c@12CA {
> + status = "okay";
> +
> + s2mps11_pmic@66 {
> + compatible = "samsung,s2mps11-pmic";
> + reg = <0x66>;
> + s2mps11,buck2-ramp-delay = <12>;
> + s2mps11,buck34-ramp-delay = <12>;
> + s2mps11,buck16-ramp-delay = <12>;
> + s2mps11,buck6-ramp-enable = <1>;
> + s2mps11,buck2-ramp-enable = <1>;
> + s2mps11,buck3-ramp-enable = <1>;
> + s2mps11,buck4-ramp-enable = <1>;
> +
> + s2mps11_osc: clocks {
> + #clock-cells = <1>;
> + clock-output-names = "s2mps11_ap",
> + "s2mps11_cp", "s2mps11_bt";
> + };
> +
> + regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "vdd_ldo1";
> + regulator-min-microvolt = <100>;
> + regulator-max-microvolt = <100>;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "vdd_ldo3";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "vdd_ldo5";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> +
