[PATCH v2] PM / OPP: Fix parsing of opp-microvolt and opp-microamp properties
Commit 01fb4d3c39d3 ("PM / OPP: Parse 'opp--'
bindings") broke support for parsing standard opp-microvolt and
opp-microamp properties. Fix it by setting 'name' string to
proper value for !prop cases.
Cc: Viresh Kumar
Cc: Lee Jones
Cc: Rafael J. Wysocki
Fixes: 01fb4d3c39d3 ("PM / OPP: Parse 'opp-- 'bindings")
Signed-off-by: Bartlomiej Zolnierkiewicz
---
v2:
- rework the changes as requested by Viresh
This fixes Exynos4x12 cpufreq-dt suppport regression present in
linux-pm/linux-next tree. Rafael, please apply. Thank you.
drivers/base/power/opp/core.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: b/drivers/base/power/opp/core.c
===
--- a/drivers/base/power/opp/core.c 2015-12-17 18:57:27.358981831 +0100
+++ b/drivers/base/power/opp/core.c 2015-12-17 18:58:04.550982529 +0100
@@ -814,7 +814,7 @@ static int opp_parse_supplies(struct dev
if (!prop) {
/* Search for "opp-microvolt" */
- name[13] = '\0';
+ sprintf(name, "opp-microvolt");
prop = of_find_property(opp->np, name, NULL);
/* Missing property isn't a problem, but an invalid entry is */
@@ -855,7 +855,7 @@ static int opp_parse_supplies(struct dev
if (!prop) {
/* Search for "opp-microamp" */
- name[12] = '\0';
+ sprintf(name, "opp-microamp");
prop = of_find_property(opp->np, name, NULL);
}
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[PATCH] PM / OPP: Fix parsing of opp-microvolt and opp-microamp properties
Commit 01fb4d3c39d3 ("PM / OPP: Parse 'opp--'
bindings") broke support for parsing standard opp-microvolt and
opp-microamp properties. Fix it by setting 'name' string to
proper value for !dev_opp->prop_name cases.
Cc: Viresh Kumar
Cc: Lee Jones
Cc: Rafael J. Wysocki
Fixes: 01fb4d3c39d3 ("PM / OPP: Parse 'opp-- 'bindings")
Signed-off-by: Bartlomiej Zolnierkiewicz
---
This fixes Exynos4x12 cpufreq-dt support regression present in
linux-pm/linux-next tree. Rafael, please apply. Thank you.
drivers/base/power/opp/core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Index: b/drivers/base/power/opp/core.c
===
--- a/drivers/base/power/opp/core.c 2015-12-16 16:10:13.509171420 +0100
+++ b/drivers/base/power/opp/core.c 2015-12-16 16:21:18.385183902 +0100
@@ -806,11 +806,11 @@ static int opp_parse_supplies(struct dev
struct property *prop = NULL;
char name[NAME_MAX];
+ sprintf(name, "opp-microvolt-%s", dev_opp->prop_name);
+
/* Search for "opp-microvolt-" */
- if (dev_opp->prop_name) {
- sprintf(name, "opp-microvolt-%s", dev_opp->prop_name);
+ if (dev_opp->prop_name)
prop = of_find_property(opp->np, name, NULL);
- }
if (!prop) {
/* Search for "opp-microvolt" */
@@ -848,10 +848,10 @@ static int opp_parse_supplies(struct dev
/* Search for "opp-microamp-" */
prop = NULL;
- if (dev_opp->prop_name) {
- sprintf(name, "opp-microamp-%s", dev_opp->prop_name);
+ sprintf(name, "opp-microamp-%s", dev_opp->prop_name);
+
+ if (dev_opp->prop_name)
prop = of_find_property(opp->np, name, NULL);
- }
if (!prop) {
/* Search for "opp-microamp" */
--
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[PATCH v6 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420
The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v6 7/7] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v6 6/7] ARM: dts: Exynos5800: fix CPU OPP
Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Thomas Abraham
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5800.dtsi | 108 ++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi
b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..8213016 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -23,6 +23,114 @@
compatible = "samsung,exynos5800-clock";
};
+&cluster_a15_opp_table {
+ opp@17 {
+ opp-microvolt = <125>;
+ };
+ opp@16 {
+ opp-microvolt = <125>;
+ };
+ opp@15 {
+ opp-microvolt = <110>;
+ };
+ opp@14 {
+ opp-microvolt = <110>;
+ };
+ opp@13 {
+ opp-microvolt = <110>;
+ };
+ opp@12 {
+ opp-microvolt = <100>;
+ };
+ opp@11 {
+ opp-microvolt = <100>;
+ };
+ opp@10 {
+ opp-microvolt = <100>;
+ };
+ opp@9 {
+ opp-microvolt = <100>;
+ };
+ opp@8 {
+ opp-microvolt = <90>;
+ };
+ opp@7 {
+ opp-microvolt = <90>;
+ };
+ opp@6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+};
+
+&cluster_a7_opp_table {
+ opp@13 {
+ opp-microvolt = <125>;
+ };
+ opp@12 {
+ opp-microvolt = <125>;
+ };
+ opp@11 {
+ opp-microvolt = <125>;
+ };
+ opp@10 {
+ opp-microvolt = <110>;
+ };
+ opp@9 {
+ opp-microvolt = <110>;
+ };
+ opp@8 {
+ opp-microvolt = <110>;
+ };
+ opp@7 {
+ opp-microvolt = <100>;
+ };
+ opp@6 {
+ opp-microvolt = <100>;
+ };
+ opp@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+};
+
&mfc {
compatible = "samsung,mfc-v8";
};
--
1.9.1
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[PATCH v6 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Acked-by: Sylwester Nawrocki
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data
exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst =
{
+ { 200, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 190, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 140, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 130, E5420_KFC_DIV(3, 5, 2), },
{ 120, E5420_KFC_DIV(3, 5, 2), },
{ 110, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d),
0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d),
0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
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[PATCH v6 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
From: Thomas Abraham
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Acked-by: Sylwester Nawrocki
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 58 --
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls]
__initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst =
{
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 130, E5420_KFC_DIV(3, 5, 2), },
+ { 120, E5420_KFC_DIV(3, 5, 2), },
+ { 110, E5420_KFC_DIV(3, 5, 2), },
+ { 100, E5420_KFC_DIV(3, 5, 2), },
+ { 90, E5420_KFC_DIV(3, 5, 2), },
+ { 80, E5420_KFC_DIV(3, 5, 2), },
+ { 70, E5420_KFC_DIV(3, 4, 2), },
+ { 60, E5420_KFC_DIV(3, 4, 2), },
+ { 50, E5420_KFC_DIV(3, 4, 2), },
+ { 40, E5420_KFC_DIV(3, 3, 2), },
+ { 30, E5420_KFC_DIV(3, 3, 2), },
+ { 20, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 10
[PATCH v6 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties
Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Thomas Abraham
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 365eec6..762f6ff 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -53,6 +53,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 61a0c0d..f7b31e1 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 1935a0b..0785fed 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -90,6 +90,14 @@
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 9134217..1bd507b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -67,6 +67,14 @@
<1920>;
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 279322b..4731dbb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
--
1.9.1
--
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[PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
Hi, This patch series adds generic cpufreq-dt driver support for Exynos542x/5800 (using the new CPU clock type which allows it). It has been tested on Exynos5422 based ODROID-XU3 Lite board. Depends on: - next-20151211 branch of linux-next kernel tree - "[PATCH] ARM: dts: Make CPU configuration more readable for exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107) Changes since v5: - rebased over next-20151211 branch (something is broken in newer branches, namely next-2015121[45]) - rebased on top of "ARM: dts: Make CPU configuration more readable for exynos542x/5800" patch - renamed cpu0_opp_table to cluster_a15_opp_table and cpu1_opp_table to cluster_a7_opp_table - added Reviewed-by from Krzysztof Changes since v4: - renamed oppXX@hz to opp@hz - put Odroid changes in exynos5422-odroidxu3-common.dtsi - override CPU OPP properties for Exynos5422/5800 instead of duplicating them - merged "ARM: dts: Exynos5422: fix OPP tables" patch with "ARM: dts: Exynos5420: add CPU OPP properties" one - added missing Thomas' SoB line to "ARM: dts: Exynos5420: add CPU OPP properties" patch - updated authorship of "ARM: Exynos: use generic cpufreq driver for Exynos5420" and "ARM: Exynos: use generic cpufreq driver for Exynos5422/5800" patches - updated Javier's and Mike's e-mail adresses - removed non-working e-mail address of Sachin Kamat Changes since v3: - switched to using cpufreq-dt driver - updated patch descriptions to cover Exynos5422 support - added Acked-by from Sylwester to clock driver patches Changes since v2: - ported over next-20151124 branch - integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3 (from Anand Moon) - added regulator supply properties for ODROID-XU3 Lite and ODROID-XU4 in patch #2 - ported CPU OPPs to operating-points-v2 (from Ben Gamari) - added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben Gamari) - added "cpufreq: arm-big-little: accept operating-points-v2 nodes" patch (from Ben Gamari) - renamed OPP nodes as opp@ Changes since v1: - added CPU cluster regulator supply properties to exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts, exynos5420-smdk5420.dts and exynos5800-peach-pi.dts Changes over Thomas' original v12 code: - split Exynos5420 and Exynos5800 support - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c - disabled cpufreq if big.LITTLE switcher support is enabled - enhanced arm_big_little[_dt] driver with CPU cluster regulator support - fixed CPU clock configuration data for Exynos5800 - fixed CPU operating points setup for Exynos5800 - added CPU cluster regulator supplies for ODROID-XU3 board Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): ARM: dts: Exynos542x/5800: add cluster regulator supply properties ARM: Exynos: use generic cpufreq driver for Exynos5420 clk: samsung: exynos5422/5800: fix cpu clock configuration data ARM: dts: Exynos5800: fix CPU OPP ARM: Exynos: use generic cpufreq driver for Exynos5422/5800 Thomas Abraham (2): clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos542x/5800: add CPU OPP properties arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++ arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 ++ arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++ arch/arm/boot/dts/exynos5420.dtsi | 110 + arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 ++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++ arch/arm/boot/dts/exynos5800.dtsi | 108 arch/arm/mach-exynos/exynos.c | 4 + drivers/clk/samsung/clk-exynos5420.c | 88 - include/dt-bindings/clock/exynos5420.h | 2 + 12 files changed, 370 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
From: Thomas Abraham
For Exynos542x/5800 platforms, add CPU operating points
for migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- merged Exynos5422 fixes from Ben
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Signed-off-by: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++
arch/arm/boot/dts/exynos5420.dtsi | 110 +
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
3 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi
b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 7aaf031..261d251 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -29,8 +29,10 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu1: cpu@1 {
@@ -39,6 +41,7 @@
reg = <0x1>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu2: cpu@2 {
@@ -47,6 +50,7 @@
reg = <0x2>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu3: cpu@3 {
@@ -55,14 +59,17 @@
reg = <0x3>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu5: cpu@101 {
@@ -71,6 +78,7 @@
reg = <0x101>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu6: cpu@102 {
@@ -79,6 +87,7 @@
reg = <0x102>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu7: cpu@103 {
@@ -87,6 +96,7 @@
reg = <0x103>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 29b7cba..2458bdf 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cluster_a15_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = &l
[PATCH v5 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
Hi, This patch series adds generic cpufreq-dt driver support for Exynos542x/5800 (using the new CPU clock type which allows it). It has been tested on Exynos5422 based ODROID-XU3 Lite board. Depends on: - next-20151124 branch of linux-next kernel tree Changes since v4: - renamed oppXX@hz to opp@hz - put Odroid changes in exynos5422-odroidxu3-common.dtsi - override CPU OPP properties for Exynos5422/5800 instead of duplicating them - merged "ARM: dts: Exynos5422: fix OPP tables" patch with "ARM: dts: Exynos5420: add CPU OPP properties" one - added missing Thomas' SoB line to "ARM: dts: Exynos5420: add CPU OPP properties" patch - updated authorship of "ARM: Exynos: use generic cpufreq driver for Exynos5420" and "ARM: Exynos: use generic cpufreq driver for Exynos5422/5800" patches - updated Javier's and Mike's e-mail adresses - removed non-working e-mail address of Sachin Kamat Changes since v3: - switched to using cpufreq-dt driver - updated patch descriptions to cover Exynos5422 support - added Acked-by from Sylwester to clock driver patches Changes since v2: - ported over next-20151124 branch - integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3 (from Anand Moon) - added regulator supply properties for ODROID-XU3 Lite and ODROID-XU4 in patch #2 - ported CPU OPPs to operating-points-v2 (from Ben Gamari) - added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben Gamari) - added "cpufreq: arm-big-little: accept operating-points-v2 nodes" patch (from Ben Gamari) - renamed OPP nodes as opp@ Changes since v1: - added CPU cluster regulator supply properties to exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts, exynos5420-smdk5420.dts and exynos5800-peach-pi.dts Changes over Thomas' original v12 code: - split Exynos5420 and Exynos5800 support - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c - disabled cpufreq if big.LITTLE switcher support is enabled - enhanced arm_big_little[_dt] driver with CPU cluster regulator support - fixed CPU clock configuration data for Exynos5800 - fixed CPU operating points setup for Exynos5800 - added CPU cluster regulator supplies for ODROID-XU3 board Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): ARM: dts: Exynos542x/5800: add cluster regulator supply properties ARM: Exynos: use generic cpufreq driver for Exynos5420 clk: samsung: exynos5422/5800: fix cpu clock configuration data ARM: dts: Exynos5800: fix CPU OPP ARM: Exynos: use generic cpufreq driver for Exynos5422/5800 Thomas Abraham (2): clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos542x/5800: add CPU OPP properties arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++ arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++ arch/arm/boot/dts/exynos5420.dtsi | 122 + arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 ++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++ arch/arm/boot/dts/exynos5800.dtsi | 108 ++ arch/arm/mach-exynos/exynos.c | 4 + drivers/clk/samsung/clk-exynos5420.c | 88 ++- include/dt-bindings/clock/exynos5420.h | 2 + 11 files changed, 372 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties
Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4ecef69..4229641 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -52,6 +52,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..df071b33 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -143,6 +143,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..124a9ba 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -89,6 +89,14 @@
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 9134217..1bd507b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -67,6 +67,14 @@
<1920>;
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..2f6d8ac 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -137,6 +137,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
From: Thomas Abraham
For Exynos542x/5800 platforms, add CPU operating points
for migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- merged Exynos5422 fixes from Ben
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Signed-off-by: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420.dtsi | 122 +
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
2 files changed, 132 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..616c2d0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <14>;
+ };
+ opp@15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <14>;
+ };
+ opp@14 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <14>;
+ };
+ opp@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <14>;
+ };
+ opp@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <14>;
+ };
+ opp@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <14>;
+ };
+ opp@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <14>;
+ };
+ opp@8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <14>;
+ };
+ opp@7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <14>;
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <14>;
+ };
+ opp@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <14>;
+ };
+ opp@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp@9 {
+ opp-hz = /bits/ 64 <
[PATCH v5 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
From: Thomas Abraham
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Acked-by: Sylwester Nawrocki
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 58 --
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls]
__initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst =
{
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 130, E5420_KFC_DIV(3, 5, 2), },
+ { 120, E5420_KFC_DIV(3, 5, 2), },
+ { 110, E5420_KFC_DIV(3, 5, 2), },
+ { 100, E5420_KFC_DIV(3, 5, 2), },
+ { 90, E5420_KFC_DIV(3, 5, 2), },
+ { 80, E5420_KFC_DIV(3, 5, 2), },
+ { 70, E5420_KFC_DIV(3, 4, 2), },
+ { 60, E5420_KFC_DIV(3, 4, 2), },
+ { 50, E5420_KFC_DIV(3, 4, 2), },
+ { 40, E5420_KFC_DIV(3, 3, 2), },
+ { 30, E5420_KFC_DIV(3, 3, 2), },
+ { 20, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 10
[PATCH v5 6/7] ARM: dts: Exynos5800: fix CPU OPP
Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5800.dtsi | 108 ++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi
b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..b3c16f6 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -23,6 +23,114 @@
compatible = "samsung,exynos5800-clock";
};
+&cpu0_opp_table {
+ opp@17 {
+ opp-microvolt = <125>;
+ };
+ opp@16 {
+ opp-microvolt = <125>;
+ };
+ opp@15 {
+ opp-microvolt = <110>;
+ };
+ opp@14 {
+ opp-microvolt = <110>;
+ };
+ opp@13 {
+ opp-microvolt = <110>;
+ };
+ opp@12 {
+ opp-microvolt = <100>;
+ };
+ opp@11 {
+ opp-microvolt = <100>;
+ };
+ opp@10 {
+ opp-microvolt = <100>;
+ };
+ opp@9 {
+ opp-microvolt = <100>;
+ };
+ opp@8 {
+ opp-microvolt = <90>;
+ };
+ opp@7 {
+ opp-microvolt = <90>;
+ };
+ opp@6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+};
+
+&cpu1_opp_table {
+ opp@13 {
+ opp-microvolt = <125>;
+ };
+ opp@12 {
+ opp-microvolt = <125>;
+ };
+ opp@11 {
+ opp-microvolt = <125>;
+ };
+ opp@10 {
+ opp-microvolt = <110>;
+ };
+ opp@9 {
+ opp-microvolt = <110>;
+ };
+ opp@8 {
+ opp-microvolt = <110>;
+ };
+ opp@7 {
+ opp-microvolt = <100>;
+ };
+ opp@6 {
+ opp-microvolt = <100>;
+ };
+ opp@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+};
+
&mfc {
compatible = "samsung,mfc-v8";
};
--
1.9.1
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[PATCH v5 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Acked-by: Sylwester Nawrocki
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data
exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst =
{
+ { 200, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 190, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 140, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 130, E5420_KFC_DIV(3, 5, 2), },
{ 120, E5420_KFC_DIV(3, 5, 2), },
{ 110, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d),
0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d),
0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
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[PATCH v5 7/7] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v5 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420
The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
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Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables
Hi, On Tuesday, December 08, 2015 05:13:26 PM Krzysztof Kozlowski wrote: > On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote: > > From: Ben Gamari > > > > The Exynos 5422 is identical to the 5800 except for the fact that it > > boots from the A7 cores. Consequently, the core numbering is different: > > cores 0-3 are A7s whereas 4-7 are A15s. > > > > We can reuse the device tree of the 5800 for the 5422 but we must take > > care to override the OPP tables and CPU clocks. These are otherwise > > inherited from the exynos5800 devicetree, which has the CPU clusters > > reversed compared to the 5422. This results in the A15 cores only > > reaching 1.4GHz, the maximum rate of the KFC clock. > > > > Cc: Javier Martinez Canillas > > Signed-off-by: Ben Gamari > > Signed-off-by: Bartlomiej Zolnierkiewicz > > --- > > arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++ > > 1 file changed, 10 insertions(+) > > > > This looks like a very-non-atomic way of handling a change. You added > opp tables to exynos5420 before so at that time they will be applied to > Odroid XU3 family which uses different CPU order. After that you are > fixing the tables to proper CPU order. Direct bisectability probably > won't be an issue because all of DTS would go to separate branch... but > the logic behind confuses. It was done this way to preserve original authorship of changes and bisectability should not be affected unless patch #8 is merged before patch #7. > I think this should be squashed into 3/8. OK. > Best regards, > Krzysztof Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420
Hi,
On Tuesday, December 08, 2015 04:36:12 PM Krzysztof Kozlowski wrote:
> On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote:
> > From: Thomas Abraham
> >
> > The new CPU clock type allows the use of cpufreq-dt driver
> > for Exynos5420.
> >
> > Changes by Bartlomiej:
> > - split Exynos5420 support from the original patch
> > - disable cpufreq if big.LITTLE switcher support is enabled
> > - switch to using cpufreq-dt driver
> >
> > Cc: Tomasz Figa
> > Cc: Kukjin Kim
> > Cc: Javier Martinez Canillas
> > Signed-off-by: Thomas Abraham
> > Signed-off-by: Bartlomiej Zolnierkiewicz
> > ---
> > arch/arm/mach-exynos/exynos.c | 3 +++
> > 1 file changed, 3 insertions(+)
>
> I think this is actually now your patch, not Thomas any more. :)
It seems so, I'll update the patch.
> > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> > index 1c47aee..7a89c9d 100644
> > --- a/arch/arm/mach-exynos/exynos.c
> > +++ b/arch/arm/mach-exynos/exynos.c
> > @@ -230,6 +230,9 @@ static const struct of_device_id
> > exynos_cpufreq_matches[] = {
> > { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> > +#ifndef CONFIG_BL_SWITCHER
> > + { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
> > +#endif
>
> Why not on BL_SWITCHER? Shouldn't be enough to disable ARM_DT_BL_CPUFREQ?
ARM_DT_BL_CPUFREQ is not relevant here (it requires to be explicitly
enabled by platform code, just like cpufreq-dt) and the dependency on
!BL_SWITCHER is needed because when BL_SWITCHER is enabled big and
LITTLE cores are grouped in pairs and presented as "virtual" CPUs to
the system:
...
[0.002630] CPU0: update cpu_capacity 448
[0.002646] CPU0: thread -1, cpu 0, socket 1, mpidr 8100
[0.002835] Setting up static identity map for 0x40008280 - 0x400082d8
[0.003106] ARM CCI driver probed
[0.003351] Exynos MCPM support installed
[0.045350] CPU1: update cpu_capacity 448
[0.045358] CPU1: thread -1, cpu 1, socket 1, mpidr 8101
[0.060326] CPU2: update cpu_capacity 448
[0.060334] CPU2: thread -1, cpu 2, socket 1, mpidr 8102
[0.075326] CPU3: update cpu_capacity 448
[0.075334] CPU3: thread -1, cpu 3, socket 1, mpidr 8103
[0.090337] CPU4: update cpu_capacity 1535
[0.090345] CPU4: thread -1, cpu 0, socket 0, mpidr 8000
[0.105314] CPU5: update cpu_capacity 1535
[0.105321] CPU5: thread -1, cpu 1, socket 0, mpidr 8001
[0.120338] CPU6: update cpu_capacity 1535
[0.120345] CPU6: thread -1, cpu 2, socket 0, mpidr 8002
[0.135330] CPU7: update cpu_capacity 1535
[0.135338] CPU7: thread -1, cpu 3, socket 0, mpidr 8003
[0.135466] Brought up 8 CPUs
...
[3.027498] big.LITTLE switcher initializing
[3.031761] CPU0 paired with CPU7
[3.035055] CPU1 paired with CPU6
[3.038332] CPU2 paired with CPU5
[3.041598] CPU3 paired with CPU4
[3.044930] GIC ID for CPU 0 cluster 1 is 4
[3.049078] GIC ID for CPU 1 cluster 1 is 5
[3.053258] GIC ID for CPU 2 cluster 1 is 6
[3.057370] GIC ID for CPU 3 cluster 1 is 7
[3.061558] GIC ID for CPU 0 cluster 0 is 0
[3.083336] IRQ53 no longer affine to CPU4
[3.084336] CPU4: shutdown
[3.107059] GIC ID for CPU 1 cluster 0 is 1
[3.123303] IRQ54 no longer affine to CPU5
[3.124213] CPU5: shutdown
[3.146387] GIC ID for CPU 2 cluster 0 is 2
[3.158143] cpu cpu0: 1100 MHz, 1250 mV --> 900 MHz, 1100 mV
[3.168228] IRQ55 no longer affine to CPU6
[3.169135] CPU6: shutdown
[3.191485] GIC ID for CPU 3 cluster 0 is 3
[3.208264] IRQ56 no longer affine to CPU7
[3.209166] CPU7: shutdown
[3.236752] big.LITTLE switcher initialized
...
Only arm_big_little_dt driver knows how to handle this setup
correctly. cpufreq-dt just treats "virtual" CPUs as a LITTLE
ones. Thus when "virtual CPU"'s current core is switched to
a big one cpufreq-dt is unable to update its voltage.
[ I tried using BL_SWITCHER_DUMMY_IF functionality to simulate
this with:
echo 0,0 > /dev/b.L_switcher
but it doesn't seem to work for some reason (from looking at
arch/arm/common/bL_switcher_dummy_if.c code it seems that at
least "bL_switcher_write" line should get logged but it does
not happen). ]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
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[PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties
From: Thomas Abraham
For Exynos5420 platforms, add CPU operating points for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420.dtsi | 122 ++
1 file changed, 122 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..f8f70a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp01@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp02@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <14>;
+ };
+ opp03@15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <14>;
+ };
+ opp04@14 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp05@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <14>;
+ };
+ opp06@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <14>;
+ };
+ opp07@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <14>;
+ };
+ opp08@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <14>;
+ };
+ opp09@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <14>;
+ };
+ opp10@8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <14>;
+ };
+ opp11@7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <14>;
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <14>;
+ };
+ opp01@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp02@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <14>;
+ };
+ opp03@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp04@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt =
[PATCH v4 4/8] ARM: Exynos: use generic cpufreq driver for Exynos5420
From: Thomas Abraham
The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v4 5/8] clk: samsung: exynos5422/5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Acked-by: Sylwester Nawrocki
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data
exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst =
{
+ { 200, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 190, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 140, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 130, E5420_KFC_DIV(3, 5, 2), },
{ 120, E5420_KFC_DIV(3, 5, 2), },
{ 110, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d),
0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d),
0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
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[PATCH v4 2/8] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
From: Thomas Abraham
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Acked-by: Sylwester Nawrocki
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 58 --
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls]
__initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst =
{
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 130, E5420_KFC_DIV(3, 5, 2), },
+ { 120, E5420_KFC_DIV(3, 5, 2), },
+ { 110, E5420_KFC_DIV(3, 5, 2), },
+ { 100, E5420_KFC_DIV(3, 5, 2), },
+ { 90, E5420_KFC_DIV(3, 5, 2), },
+ { 80, E5420_KFC_DIV(3, 5, 2), },
+ { 70, E5420_KFC_DIV(3, 4, 2), },
+ { 60, E5420_KFC_DIV(3, 4, 2), },
+ { 50, E5420_KFC_DIV(3, 4, 2), },
+ { 40, E5420_KFC_DIV(3, 3, 2), },
+ { 30, E5420_KFC_DIV(3, 3, 2), },
+ { 20, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 10
[PATCH v4 1/8] ARM: dts: Exynos542x/5800: add cluster regulator supply properties
Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 8
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8
7 files changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4ecef69..4229641 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -52,6 +52,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..30f146b 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -676,6 +676,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..fdfe4e6 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -423,3 +423,11 @@
&usbdrd_phy1 {
vbus-supply = <&usb301_vbus_reg>;
};
+
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf4..0bfd981 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -54,6 +54,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406d..b19561c 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -53,6 +53,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&i2c_0 {
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 2faf886..bdc7106 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -32,6 +32,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..03ff1ceb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -638,6 +638,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
--
1.9.1
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[PATCH v4 8/8] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
From: Thomas Abraham
The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.
Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
- switch to using cpufreq-dt driver
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables
From: Ben Gamari
The Exynos 5422 is identical to the 5800 except for the fact that it
boots from the A7 cores. Consequently, the core numbering is different:
cores 0-3 are A7s whereas 4-7 are A15s.
We can reuse the device tree of the 5800 for the 5422 but we must take
care to override the OPP tables and CPU clocks. These are otherwise
inherited from the exynos5800 devicetree, which has the CPU clusters
reversed compared to the 5422. This results in the A15 cores only
reaching 1.4GHz, the maximum rate of the KFC clock.
Cc: Javier Martinez Canillas
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi
b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index b7f60c8..9a5131d 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -20,8 +20,10 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu1 {
@@ -30,6 +32,7 @@
reg = <0x101>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu2 {
@@ -38,6 +41,7 @@
reg = <0x102>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu3 {
@@ -46,14 +50,17 @@
reg = <0x103>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu4 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu5 {
@@ -62,6 +69,7 @@
reg = <0x1>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu6 {
@@ -70,6 +78,7 @@
reg = <0x2>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu7 {
@@ -78,4 +87,5 @@
reg = <0x3>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
--
1.9.1
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[PATCH v4 6/8] ARM: dts: Exynos5800: fix CPU OPP
Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5800.dtsi | 165 ++
1 file changed, 165 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi
b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..e417218 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,8 +17,173 @@
/ {
compatible = "samsung,exynos5800", "samsung,exynos5";
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp01@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp02@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp03@15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp04@14 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp05@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp06@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp07@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp08@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp09@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp10@8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp11@7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp12@6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp13@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp14@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp15@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp16@2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>
[PATCH v4 0/8] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
Hi, This patch series adds generic cpufreq-dt driver support for Exynos542x/5800 (using the new CPU clock type which allows it). It has been tested on Exynos5422 based ODROID-XU3 Lite board. Depends on: - next-20151124 branch of linux-next kernel tree Changes since v3: - switched to using cpufreq-dt driver - updated patch descriptions to cover Exynos5422 support - added Acked-by from Sylwester to clock driver patches Changes since v2: - ported over next-20151124 branch - integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3 (from Anand Moon) - added regulator supply properties for ODROID-XU3 Lite and ODROID-XU4 in patch #2 - ported CPU OPPs to operating-points-v2 (from Ben Gamari) - added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben Gamari) - added "cpufreq: arm-big-little: accept operating-points-v2 nodes" patch (from Ben Gamari) - renamed OPP nodes as opp@ Changes since v1: - added CPU cluster regulator supply properties to exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts, exynos5420-smdk5420.dts and exynos5800-peach-pi.dts Changes over Thomas' original v12 code: - split Exynos5420 and Exynos5800 support - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c - disabled cpufreq if big.LITTLE switcher support is enabled - enhanced arm_big_little[_dt] driver with CPU cluster regulator support - fixed CPU clock configuration data for Exynos5800 - fixed CPU operating points setup for Exynos5800 - added CPU cluster regulator supplies for ODROID-XU3 board Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (3): ARM: dts: Exynos542x/5800: add cluster regulator supply properties clk: samsung: exynos5422/5800: fix cpu clock configuration data ARM: dts: Exynos5800: fix CPU OPP Ben Gamari (1): ARM: dts: Exynos5422: fix OPP tables Thomas Abraham (4): clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos5420: add CPU OPP and regulator supply property ARM: Exynos: use generic cpufreq driver for Exynos5420 ARM: Exynos: use generic cpufreq driver for Exynos5422/5800 arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++ arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++ arch/arm/boot/dts/exynos5420.dtsi | 122 ++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++ arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8 ++ arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8 ++ arch/arm/boot/dts/exynos5422-odroidxu4.dts | 8 ++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++ arch/arm/boot/dts/exynos5800.dtsi | 165 arch/arm/mach-exynos/exynos.c | 4 + drivers/clk/samsung/clk-exynos5420.c| 88 - include/dt-bindings/clock/exynos5420.h | 2 + 13 files changed, 445 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 0/10] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
Hi, On Saturday, December 05, 2015 09:24:44 AM Viresh Kumar wrote: > On 04-12-15, 18:30, Bartlomiej Zolnierkiewicz wrote: > > Hi, > > > > This patch series adds generic arm_big_little_dt cpufreq driver > > support for Exynos542x/5800 (using the new CPU clock type which > > allows it). It also: > > - enhances arm_big_little[_dt] driver with CPU cluster regulator > > support > > - adds CPU clock configuration data and CPU operating points > > setup for Exynos542x/5800 > > - adds CPU cluster regulator supplies for Exynos542x/5800 boards > > > > This patch series has been tested on Exynos5422 based ODROID-XU3 > > Lite board. > > > > Please note that this is not a final version of the patchset. > > I just wanted to push out current work-in-progress patches that > > integrate changes from Anand, Ben and me. > > What's going on guys, Ben tried exactly same thing few days back: > > http://marc.info/?l=linux-kernel&m=144909193925508&w=2 Why I appreciate Ben's work this not exactly the same thing as the above patchset lacks critical CLK_RECALC_NEW_RATES bugfix and few other minor fixes. > And the comments given there applies to you as well. Yes, sure. That's why I wrote that this is work-in-progress and put the TODO in the cover letter. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 04/10] ARM: dts: Exynos5420: add CPU OPP and regulator supply property
From: Thomas Abraham
For Exynos5420 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420.dtsi | 122 ++
1 file changed, 122 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..f8f70a5 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp01@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp02@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <14>;
+ };
+ opp03@15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <14>;
+ };
+ opp04@14 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp05@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <14>;
+ };
+ opp06@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <14>;
+ };
+ opp07@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <14>;
+ };
+ opp08@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <14>;
+ };
+ opp09@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <14>;
+ };
+ opp10@8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <14>;
+ };
+ opp11@7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <14>;
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <14>;
+ };
+ opp01@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <14>;
+ };
+ opp02@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <14>;
+ };
+ opp03@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <14>;
+ };
+ opp04@9 {
+ opp-hz = /bits/ 64 <9&g
[PATCH v3 0/10] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
Hi, This patch series adds generic arm_big_little_dt cpufreq driver support for Exynos542x/5800 (using the new CPU clock type which allows it). It also: - enhances arm_big_little[_dt] driver with CPU cluster regulator support - adds CPU clock configuration data and CPU operating points setup for Exynos542x/5800 - adds CPU cluster regulator supplies for Exynos542x/5800 boards This patch series has been tested on Exynos5422 based ODROID-XU3 Lite board. Please note that this is not a final version of the patchset. I just wanted to push out current work-in-progress patches that integrate changes from Anand, Ben and me. TODO: - porting the Exynos542x/5800 support over cpufreq-dt Depends on: - next-20151124 branch of linux-next kernel tree Changes since v2: - ported over next-20151124 branch - integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3 (from Anand Moon) - added regulator supply properties for ODROID-XU3 Lite and ODROID-XU4 in patch #2 - ported CPU OPPs to operating-points-v2 (from Ben Gamari) - added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben Gamari) - added "cpufreq: arm-big-little: accept operating-points-v2 nodes" patch (from Ben Gamari) - renamed OPP nodes as opp@ Changes since v1: - added CPU cluster regulator supply properties to exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts, exynos5420-smdk5420.dts and exynos5800-peach-pi.dts Changes over Thomas' original v12 code: - split Exynos5420 and Exynos5800 support - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c - disabled cpufreq if big.LITTLE switcher support is enabled - enhanced arm_big_little[_dt] driver with CPU cluster regulator support - fixed CPU clock configuration data for Exynos5800 - fixed CPU operating points setup for Exynos5800 - added CPU cluster regulator supplies for ODROID-XU3 board Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (4): cpufreq: arm_big_little: add cluster regulator support ARM: dts: Exynos5420/5800: add cluster regulator supply properties clk: samsung: exynos5800: fix cpu clock configuration data ARM: dts: Exynos5800: fix CPU OPP Ben Gamari (2): ARM: dts: Exynos5422: fix OPP tables cpufreq: arm-big-little: accept operating-points-v2 nodes Thomas Abraham (4): clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos5420: add CPU OPP and regulator supply property ARM: Exynos: use generic cpufreq driver for Exynos5420 ARM: Exynos: use generic cpufreq driver for Exynos5800 .../bindings/cpufreq/arm_big_little_dt.txt | 4 + arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 + arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 + arch/arm/boot/dts/exynos5420.dtsi | 122 ++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++ arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts| 8 + arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8 + arch/arm/boot/dts/exynos5422-odroidxu4.dts | 8 + arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 + arch/arm/boot/dts/exynos5800.dtsi | 165 +++ arch/arm/mach-exynos/exynos.c | 8 + drivers/clk/samsung/clk-exynos5420.c | 88 ++- drivers/cpufreq/arm_big_little.c | 175 + drivers/cpufreq/arm_big_little_dt.c| 12 +- include/dt-bindings/clock/exynos5420.h | 2 + 16 files changed, 608 insertions(+), 34 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 02/10] ARM: dts: Exynos5420/5800: add cluster regulator supply properties
Add cluster regulator supply properties as a preparation to
adding generic arm_big_little_dt cpufreq driver support for
Exynos5420 and Exynos5800 based boards.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 8
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8
7 files changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 4ecef69..24b8a35 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -52,6 +52,14 @@
};
};
+&cpu0 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..2b74230 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -676,6 +676,14 @@
};
};
+&cpu0 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..9e2dc5f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -423,3 +423,11 @@
&usbdrd_phy1 {
vbus-supply = <&usb301_vbus_reg>;
};
+
+&cpu0 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf4..6f1de7c 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -54,6 +54,14 @@
};
};
+&cpu0 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406d..6b64122 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -53,6 +53,14 @@
};
};
+&cpu0 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
&i2c_0 {
status = "okay";
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 2faf886..516a40f 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -32,6 +32,14 @@
};
};
+&cpu0 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7b018e4..34cd 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -638,6 +638,14 @@
};
};
+&cpu0 {
+ cpu-cluster.0-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-cluster.1-supply = <&buck6_reg>;
+};
+
&i2c_2 {
status = "okay";
samsung,i2c-sda-delay = <100>;
--
1.9.1
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[PATCH v3 03/10] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
From: Thomas Abraham
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 58 --
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls]
__initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst =
{
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 130, E5420_KFC_DIV(3, 5, 2), },
+ { 120, E5420_KFC_DIV(3, 5, 2), },
+ { 110, E5420_KFC_DIV(3, 5, 2), },
+ { 100, E5420_KFC_DIV(3, 5, 2), },
+ { 90, E5420_KFC_DIV(3, 5, 2), },
+ { 80, E5420_KFC_DIV(3, 5, 2), },
+ { 70, E5420_KFC_DIV(3, 4, 2), },
+ { 60, E5420_KFC_DIV(3, 4, 2), },
+ { 50, E5420_KFC_DIV(3, 4, 2), },
+ { 40, E5420_KFC_DIV(3, 3, 2), },
+ { 30, E5420_KFC_DIV(3, 3, 2), },
+ { 20, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 100644
--- a/include/dt-b
[PATCH v3 05/10] ARM: Exynos: use generic cpufreq driver for Exynos5420
From: Thomas Abraham
The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..6d97145 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,13 @@ static const struct of_device_id exynos_cpufreq_matches[]
= {
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+/*
+ * FIXME: When big.LITTLE switcher is enabled system lockups during
+ * ondemand governor stress testing (observed on ODROID-XU3 board).
+ */
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v3 06/10] clk: samsung: exynos5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5800 (it uses
higher PCLK_DBG divider values than Exynos5420 and supports
additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa
Cc: Mike Turquette
Cc: Javier Martinez Canillas
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos5420.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data
exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst =
{
+ { 200, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 190, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 180, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 170, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 160, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 150, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 140, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 130, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 120, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 110, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 100, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 90, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 80, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 70, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 60, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 50, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 40, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 30, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 20, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk)
\
kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst =
{
+ { 140, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 130, E5420_KFC_DIV(3, 5, 2), },
{ 120, E5420_KFC_DIV(3, 5, 2), },
{ 110, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d),
0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d),
0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
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[PATCH v3 08/10] ARM: dts: Exynos5422: fix OPP tables
From: Ben Gamari
The Exynos 5422 is identical to the 5800 except for the fact that it
boots from the A7 cores. Consequently, the core numbering is different:
cores 0-3 are A7s whereas 4-7 are A15s.
We can reuse the device tree of the 5800 for the 5422 but we must take
care to override the OPP tables and CPU clocks. These are otherwise
inherited from the exynos5800 devicetree, which has the CPU clusters
reversed compared to the 5422. This results in the A15 cores only
reaching 1.4GHz, the maximum rate of the KFC clock.
Cc: Javier Martinez Canillas
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi
b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index b7f60c8..9a5131d 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -20,8 +20,10 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu1 {
@@ -30,6 +32,7 @@
reg = <0x101>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu2 {
@@ -38,6 +41,7 @@
reg = <0x102>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu3 {
@@ -46,14 +50,17 @@
reg = <0x103>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cpu1_opp_table>;
};
&cpu4 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu5 {
@@ -62,6 +69,7 @@
reg = <0x1>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu6 {
@@ -70,6 +78,7 @@
reg = <0x2>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
&cpu7 {
@@ -78,4 +87,5 @@
reg = <0x3>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
--
1.9.1
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[PATCH v3 10/10] cpufreq: arm-big-little: accept operating-points-v2 nodes
From: Ben Gamari
The arm_big_little cpufreq driver can use operating points from
operating-points-v2 nodes without any trouble.
Cc: Javier Martinez Canillas
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/arm_big_little_dt.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/arm_big_little_dt.c
b/drivers/cpufreq/arm_big_little_dt.c
index 16ddeef..be7f632 100644
--- a/drivers/cpufreq/arm_big_little_dt.c
+++ b/drivers/cpufreq/arm_big_little_dt.c
@@ -35,12 +35,16 @@ static struct device_node *get_cpu_node_with_valid_op(int
cpu)
{
struct device_node *np = of_cpu_device_node_get(cpu);
- if (!of_get_property(np, "operating-points", NULL)) {
- of_node_put(np);
- np = NULL;
+ if (of_get_property(np, "operating-points-v2", NULL)) {
+ return np;
}
- return np;
+ if (of_get_property(np, "operating-points", NULL)) {
+ return np;
+ }
+
+ of_node_put(np);
+ return NULL;
}
static int dt_init_opp_table(struct device *cpu_dev)
--
1.9.1
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[PATCH v3 09/10] ARM: Exynos: use generic cpufreq driver for Exynos5800
From: Thomas Abraham
The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5800.
Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Javier Martinez Canillas
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6d97145..73853de 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -236,6 +236,7 @@ static const struct of_device_id exynos_cpufreq_matches[] =
{
*/
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "arm-bL-cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "arm-bL-cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v3 07/10] ARM: dts: Exynos5800: fix CPU OPP
Fix CPU operating points for Exynos5800 (it uses different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) until there is a separate DTS for
ODROID-XU3 Lite board (which doesn't support these higher
OPPs).
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Ben Gamari
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5800.dtsi | 165 ++
1 file changed, 165 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi
b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..e417218 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,8 +17,173 @@
/ {
compatible = "samsung,exynos5800", "samsung,exynos5";
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00@18 {
+ opp-hz = /bits/ 64 <18>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp01@17 {
+ opp-hz = /bits/ 64 <17>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp02@16 {
+ opp-hz = /bits/ 64 <16>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <14>;
+ };
+ opp03@15 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp04@14 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp05@13 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <14>;
+ };
+ opp06@12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp07@11 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp08@10 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp09@9 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <14>;
+ };
+ opp10@8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp11@7 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp12@6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp13@5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp14@4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp15@3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <14>;
+ };
+ opp16@2 {
+ opp-hz = /bits/ 64 <2>
[PATCH v3 01/10] cpufreq: arm_big_little: add cluster regulator support
Add cluster regulator support as a preparation to adding
generic arm_big_little_dt cpufreq_dt driver support for
ODROID-XU3 board. This allows arm_big_little[_dt] driver
to set not only the frequency but also the voltage (which
is obtained from operating point's voltage value) for CPU
clusters.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Cc: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
.../bindings/cpufreq/arm_big_little_dt.txt | 4 +
drivers/cpufreq/arm_big_little.c | 175 +
2 files changed, 151 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
b/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
index 0715695..8ca4a12 100644
--- a/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
+++ b/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
@@ -18,6 +18,10 @@ Required properties:
Optional properties:
- clock-latency: Specify the possible maximum transition latency for clock,
in unit of nanoseconds.
+- cpu-cluster.0-supply: Provides the regulator node supplying voltage to CPU
+ cluster 0.
+- cpu-cluster.1-supply: Provides the regulator node supplying voltage to CPU
+ cluster 1.
Examples:
diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c
index c5d256c..8b05137 100644
--- a/drivers/cpufreq/arm_big_little.c
+++ b/drivers/cpufreq/arm_big_little.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include "arm_big_little.h"
@@ -57,6 +58,9 @@ static bool bL_switching_enabled;
static struct cpufreq_arm_bL_ops *arm_bL_ops;
static struct clk *clk[MAX_CLUSTERS];
+static struct regulator *reg[MAX_CLUSTERS];
+static struct device *cpu_devs[MAX_CLUSTERS];
+static int transition_latencies[MAX_CLUSTERS];
static struct cpufreq_frequency_table *freq_table[MAX_CLUSTERS + 1];
static atomic_t cluster_usage[MAX_CLUSTERS + 1];
@@ -125,30 +129,53 @@ static unsigned int bL_cpufreq_get_rate(unsigned int cpu)
}
}
-static unsigned int
-bL_cpufreq_set_rate(u32 cpu, u32 old_cluster, u32 new_cluster, u32 rate)
+static int
+bL_cpufreq_set_rate_cluster(u32 cpu, u32 cluster, u32 new_rate)
{
- u32 new_rate, prev_rate;
+ unsigned long volt = 0, volt_old = 0;
+ long freq_Hz;
+ u32 old_rate;
int ret;
- bool bLs = is_bL_switching_enabled();
- mutex_lock(&cluster_lock[new_cluster]);
+ freq_Hz = new_rate * 1000;
+ old_rate = clk_get_rate(clk[cluster]) / 1000;
- if (bLs) {
- prev_rate = per_cpu(cpu_last_req_freq, cpu);
- per_cpu(cpu_last_req_freq, cpu) = rate;
- per_cpu(physical_cluster, cpu) = new_cluster;
+ if (!IS_ERR(reg[cluster])) {
+ struct dev_pm_opp *opp;
+ unsigned long opp_freq;
- new_rate = find_cluster_maxfreq(new_cluster);
- new_rate = ACTUAL_FREQ(new_cluster, new_rate);
- } else {
- new_rate = rate;
+ rcu_read_lock();
+ opp = dev_pm_opp_find_freq_ceil(cpu_devs[cluster], &freq_Hz);
+ if (IS_ERR(opp)) {
+ rcu_read_unlock();
+ pr_err("%s: cpu %d, cluster: %d, failed to find OPP for
%ld\n",
+ __func__, cpu, cluster, freq_Hz);
+ return PTR_ERR(opp);
+ }
+ volt = dev_pm_opp_get_voltage(opp);
+ opp_freq = dev_pm_opp_get_freq(opp);
+ rcu_read_unlock();
+ volt_old = regulator_get_voltage(reg[cluster]);
+ pr_debug("%s: cpu %d, cluster: %d, Found OPP: %ld kHz, %ld
uV\n",
+ __func__, cpu, cluster, opp_freq / 1000, volt);
}
- pr_debug("%s: cpu: %d, old cluster: %d, new cluster: %d, freq: %d\n",
- __func__, cpu, old_cluster, new_cluster, new_rate);
+ pr_debug("%s: cpu %d, cluster: %d, %u MHz, %ld mV --> %u MHz, %ld mV\n",
+ __func__, cpu, cluster,
+ old_rate / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
+ new_rate / 1000, volt ? volt / 1000 : -1);
- ret = clk_set_rate(clk[new_cluster], new_rate * 1000);
+ /* scaling up? scale voltage before frequency */
+ if (!IS_ERR(reg[cluster]) && new_rate > old_rate) {
+ ret = regulator_set_voltage_tol(reg[cluster], volt, 0);
+ if (ret) {
+ pr_err("%s: cpu: %d, cluster: %d, failed to scale
voltage up: %d\n",
+ __func__, cpu, cluster, ret);
+ return ret;
+ }
+ }
+
+ ret = clk_set_rate(clk[cluster], new_rate * 1000);
if (!ret) {
/*
Re: [PATCH 3/3] mfd: sec-core: Disable buck voltage reset on watchdog falling edge
Hi,
On Friday, October 02, 2015 05:25:51 PM Krzysztof Kozlowski wrote:
> The WRSTBI bit (disabled by default but enabled by bootloader), when
> set, is responsible for resetting voltages to default values of
> certain bucks on falling edge of Warm Reset Input pin from AP.
>
> However on some boards (with S2MPS13) the pin is pulled down so any
> suspend will effectively trigger the reset of bucks supplying the power
> to the little and big cores. In the same time when resuming, these bucks
> must provide voltage greater or equal to voltage before suspend to match
> the frequency chosen by cpufreq. If voltage (default value of voltage
> after reset) is lower than one set by cpufreq before suspend, then
> system will hang during resuming.
>
> Signed-off-by: Krzysztof Kozlowski
I tested this (with some additional Exynos5433 patches) and it works
like expected (suspend/resume issue is fixed).
Tested-by: Bartlomiej Zolnierkiewicz
You could also add:
Reported-by: Bartlomiej Zolnierkiewicz
(since the issue got narrowed down and reported to you by me :).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> ---
> drivers/mfd/sec-core.c | 26 ++
> include/linux/mfd/samsung/core.h| 2 ++
> include/linux/mfd/samsung/s2mps13.h | 1 +
> 3 files changed, 29 insertions(+)
>
> diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c
> index 589e5efc2d7f..2626fc0b5b8c 100644
> --- a/drivers/mfd/sec-core.c
> +++ b/drivers/mfd/sec-core.c
> @@ -262,6 +262,29 @@ static void sec_pmic_dump_rev(struct sec_pmic_dev
> *sec_pmic)
> dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val);
> }
>
> +static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic)
> +{
> + int err;
> +
> + if (sec_pmic->device_type != S2MPS13X)
> + return;
> +
> + if (sec_pmic->pdata->disable_wrstbi) {
> + /*
> + * If WRSTBI pin is pulled down this feature must be disabled
> + * because each Suspend to RAM will trigger buck voltage reset
> + * to default values.
> + */
> + err = regmap_update_bits(sec_pmic->regmap_pmic,
> + S2MPS13_REG_WRSTBI,
> + S2MPS13_REG_WRSTBI_MASK, 0x0);
> + if (err)
> + dev_warn(sec_pmic->dev,
> + "Cannot initialize WRSTBI config: %d\n",
> + err);
> + }
> +}
> +
> #ifdef CONFIG_OF
> /*
> * Only the common platform data elements for s5m8767 are parsed here from
> the
> @@ -289,6 +312,8 @@ static struct sec_platform_data
> *sec_pmic_i2c_parse_dt_pdata(
>
> pd->manual_poweroff = of_property_read_bool(dev->of_node,
> "samsung,s2mps11-acokb-ground");
> + pd->disable_wrstbi = of_property_read_bool(dev->of_node,
> +
> "samsung,s2mps11-wrstbi-ground");
> return pd;
> }
> #else
> @@ -434,6 +459,7 @@ static int sec_pmic_probe(struct i2c_client *i2c,
> goto err_mfd;
>
> device_init_wakeup(sec_pmic->dev, sec_pmic->wakeup);
> + sec_pmic_configure(sec_pmic);
> sec_pmic_dump_rev(sec_pmic);
>
> return ret;
> diff --git a/include/linux/mfd/samsung/core.h
> b/include/linux/mfd/samsung/core.h
> index aa78957e092f..a06098639399 100644
> --- a/include/linux/mfd/samsung/core.h
> +++ b/include/linux/mfd/samsung/core.h
> @@ -134,6 +134,8 @@ struct sec_platform_data {
> int buck4_init;
> /* Whether or not manually set PWRHOLD to low during shutdown. */
> boolmanual_poweroff;
> + /* Disable the WRSTBI (buck voltage warm reset) when probing? */
> + booldisable_wrstbi;
> };
>
> /**
> diff --git a/include/linux/mfd/samsung/s2mps13.h
> b/include/linux/mfd/samsung/s2mps13.h
> index b1fd675fa36f..239e977ba45d 100644
> --- a/include/linux/mfd/samsung/s2mps13.h
> +++ b/include/linux/mfd/samsung/s2mps13.h
> @@ -184,5 +184,6 @@ enum s2mps13_regulators {
> * Let's assume that default value will be set.
> */
> #define S2MPS13_BUCK_RAMP_DELAY 12500
> +#define S2MPS13_REG_WRSTBI_MASK BIT(5)
>
> #endif /* __LINUX_MFD_S2MPS13_H */
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Re: [PATCH 4/4] ARM64: dts: exynos5433: add jpeg node
Hi, On Monday, September 28, 2015 05:52:13 PM Krzysztof Kozlowski wrote: > W dniu 21.09.2015 o 18:59, Andrzej Pietrasiewicz pisze: > > Hi Hans, > > > > W dniu 21.09.2015 o 11:50, Hans Verkuil pisze: > >> On 18-09-15 16:21, Andrzej Pietrasiewicz wrote: > >>> From: Marek Szyprowski > >>> > >>> Add Exynos 5433 jpeg h/w codec node. > >>> > >>> Signed-off-by: Marek Szyprowski > >>> Signed-off-by: Andrzej Pietrasiewicz > >>> --- > >>> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 21 + > >>> 1 file changed, 21 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi > >>> b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > >> > >> This dtsi file doesn't exist in the media-git tree. What is the story > >> here? > >> > >> Should this go through a different subsystem? > >> > >> I think the media subsystem can take patches 1-3 and whoever does DT > >> patches can > >> take this patch, right? > >> > > > > The cover letter explains that the series is rebased onto Mauro's > > master with Kukjin's branch merged. The latter does contain > > the exynos5433.dtsi. That said, yes, taking patches 1-3 in > > media subsystem and leaving DT patch to someone else is the > > way to go. > > Although Kukjin picked Exynos 5433 ARM64 patches but they were not > accepted upstream by arm-soc. He rolled it for few releases but: > 1. Reason for not accepting by arm-soc was not resolved - there is no DTS. > 2. Kukjin did not rebase the branch for 4.4... which maybe means that he > wants to drop it? > 3. Anyone (but me...) can send Galaxy Note4 (Exynos5433) DTS file based > on sources on opensource.samsung.com. The DTS there is for 32-bit but it > can be probably easily adjusted for ARM64. > > All of this means that Device Tree support for this driver can't be > merged now and effort for mainlining 5433 may be unfortunately wasted... Exynos5433 support is being incrementally merged (clocks, drm, phy, pinctrl, thermal and tty support is already in upstream or -next). I don't know why DTS changes got stuck in Kukjin's tree (Kukjin, could you please explain?) but I think that this shouldn't not stop us from continuing Exynos5433 upstreaming effort. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] clk: samsung: fix cpu clock's flags checking
[ + Stephen on cc: ]
On Friday, August 28, 2015 01:49:35 PM Bartlomiej Zolnierkiewicz wrote:
> CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
> incorrectly used as a bit numbers. Fix it.
>
> Tested on Exynos4210 based Origen board and on Exynos5250 based
> Arndale board.
>
> Cc: Tomasz Figa
> Cc: Michael Turquette
> Cc: Thomas Abraham
> Fixes: ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks")
> Reported-by: Dan Carpenter
> Reviewed-by: Krzysztof Kozlowski
> Reviewed-by: Javier Martinez Canillas
> Acked-by: Sylwester Nawrocki
> Signed-off-by: Bartlomiej Zolnierkiewicz
> ---
> v2:
> - added Reviewed-by, Acked-by and Fixes tags (no code changes)
>
> Michael, please apply. Thank you.
Gentle ping.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> drivers/clk/samsung/clk-cpu.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
> index 7c1e1f5..2fe37f7 100644
> --- a/drivers/clk/samsung/clk-cpu.c
> +++ b/drivers/clk/samsung/clk-cpu.c
> @@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct
> clk_notifier_data *ndata,
>* the values for DIV_COPY and DIV_HPM dividers need not be set.
>*/
> div0 = cfg_data->div0;
> - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
> + if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
> div1 = cfg_data->div1;
> if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
> div1 = readl(base + E4210_DIV_CPU1) &
> @@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct
> clk_notifier_data *ndata,
> alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
> WARN_ON(alt_div >= MAX_DIV);
>
> - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
> + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
> /*
>* In Exynos4210, ATB clock parent is also mout_core. So
>* ATB clock also needs to be mantained at safe speed.
> @@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct
> clk_notifier_data *ndata,
> writel(div0, base + E4210_DIV_CPU0);
> wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
>
> - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
> + if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
> writel(div1, base + E4210_DIV_CPU1);
> wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
> DIV_MASK_ALL);
> @@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct
> clk_notifier_data *ndata,
> unsigned long mux_reg;
>
> /* find out the divider values to use for clock data */
> - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
> + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
> while ((cfg_data->prate * 1000) != ndata->new_rate) {
> if (cfg_data->prate == 0)
> return -EINVAL;
> @@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct
> clk_notifier_data *ndata,
> writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
> wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
>
> - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
> + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
> div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
> div_mask |= E4210_DIV0_ATB_MASK;
> }
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[PATCH] cpufreq: s5pv210: remove superfluous CONFIG_PM ifdefs
CONFIG_PM ifdefs are superfluous and can be removed.
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/s5pv210-cpufreq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c
b/drivers/cpufreq/s5pv210-cpufreq.c
index 9e231f5..ef5282b 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -576,10 +576,8 @@ static struct cpufreq_driver s5pv210_driver = {
.get= cpufreq_generic_get,
.init = s5pv210_cpu_init,
.name = "s5pv210",
-#ifdef CONFIG_PM
.suspend= cpufreq_generic_suspend,
.resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ
again */
-#endif
};
static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
--
1.9.1
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[PATCH v5 2/4] cpufreq: allow cpufreq_generic_suspend() to work without suspend frequency
Some cpufreq drivers may set suspend frequency only for
selected setups but still would like to use the generic
suspend handler. Thus don't treat !policy->suspend_freq
condition as an incorrect one.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index b3d9368..a634fcb 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1626,8 +1626,8 @@ int cpufreq_generic_suspend(struct cpufreq_policy *policy)
int ret;
if (!policy->suspend_freq) {
- pr_err("%s: suspend_freq can't be zero\n", __func__);
- return -EINVAL;
+ pr_debug("%s: suspend_freq not defined\n", __func__);
+ return 0;
}
pr_debug("%s: Setting suspend-freq: %u\n", __func__,
--
1.9.1
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[PATCH v5 1/4] PM / OPP: add dev_pm_opp_get_suspend_opp() helper
Add dev_pm_opp_get_suspend_opp() helper to obtain suspend opp.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/base/power/opp.c | 30 ++
include/linux/pm_opp.h | 6 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index eb25449..3d948ea 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -341,6 +341,36 @@ unsigned long dev_pm_opp_get_max_clock_latency(struct
device *dev)
EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_clock_latency);
/**
+ * dev_pm_opp_get_suspend_opp() - Get suspend opp
+ * @dev: device for which we do this operation
+ *
+ * Return: This function returns pointer to the suspend opp if it is
+ * defined, otherwise it returns NULL.
+ *
+ * Locking: This function must be called under rcu_read_lock(). opp is a rcu
+ * protected pointer. The reason for the same is that the opp pointer which is
+ * returned will remain valid for use with opp_get_{voltage, freq} only while
+ * under the locked area. The pointer returned must be used prior to unlocking
+ * with rcu_read_unlock() to maintain the integrity of the pointer.
+ */
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ struct device_opp *dev_opp;
+ struct dev_pm_opp *opp;
+
+ opp_rcu_lockdep_assert();
+
+ dev_opp = _find_device_opp(dev);
+ if (IS_ERR(dev_opp))
+ opp = NULL;
+ else
+ opp = dev_opp->suspend_opp;
+
+ return opp;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_get_suspend_opp);
+
+/**
* dev_pm_opp_get_opp_count() - Get number of opps available in the opp list
* @dev: device for which we do this operation
*
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index cab7ba5..e817722 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -34,6 +34,7 @@ bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp);
int dev_pm_opp_get_opp_count(struct device *dev);
unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev);
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev);
struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq,
@@ -80,6 +81,11 @@ static inline unsigned long
dev_pm_opp_get_max_clock_latency(struct device *dev)
return 0;
}
+static inline struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ return NULL;
+}
+
static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq, bool available)
{
--
1.9.1
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[PATCH v5 3/4] cpufreq-dt: add suspend frequency support
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq-dt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index c3583cd..9b5e7c9 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -196,6 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
struct device *cpu_dev;
struct regulator *cpu_reg;
struct clk *cpu_clk;
+ struct dev_pm_opp *suspend_opp;
unsigned long min_uV = ~0, max_uV = 0;
unsigned int transition_latency;
bool need_update = false;
@@ -329,6 +330,13 @@ static int cpufreq_init(struct cpufreq_policy *policy)
policy->driver_data = priv;
policy->clk = cpu_clk;
+
+ rcu_read_lock();
+ suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
+ if (suspend_opp)
+ policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
+ rcu_read_unlock();
+
ret = cpufreq_table_validate_and_show(policy, freq_table);
if (ret) {
dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
@@ -419,6 +427,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.ready = cpufreq_ready,
.name = "cpufreq-dt",
.attr = cpufreq_dt_attr,
+ .suspend = cpufreq_generic_suspend,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
--
1.9.1
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[PATCH v5 4/4] ARM: dts: add suspend opp to exynos4412
Mark 800MHz OPP as a suspend opp for Exynos4412 based
boards so effectively cpufreq-dt driver behavior w.r.t.
suspend frequency matches what the old exynos-cpufreq
driver has been doing.
This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Acked-by: Viresh Kumar
Acked-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos4412.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index ca0e3c1..294cfe4 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -98,6 +98,7 @@
opp-hz = /bits/ 64 <8>;
opp-microvolt = <100>;
clock-latency-ns = <20>;
+ opp-suspend;
};
opp07 {
opp-hz = /bits/ 64 <9>;
--
1.9.1
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[PATCH v5 0/4] cpufreq-dt: add suspend frequency support
Hi, This patch series adds suspend frequency support (using opp-v2 bindings and suspend-opp functionality) to cpufreq-dt driver and then adds suspend opp for Exynos4412 based boards. This patch series fixes suspend/resume support on Exynos4412 based Trats2 board and reboot hang on Exynos4412 based Odroid U3 board. Changes since v4: - removed superfluous CONFIG_PM ifdefs - added Acked-by tag from Krzysztof to patch #4 - added Acked-by tag from Viresh to patches #1-3 Changes since v3: - fixed dev_pm_opp_get_suspend_opp() locking - shortened variable name in dev_pm_opp_get_suspend_opp() - adjusted cpufreq_generic_suspend() to work with cpufreq-dt - removed no longer needed cpufreq_dt_suspend() - added Acked-by tag from Viresh to patch #4 Changes since v2: - rewrote to use suspend-opp functionality Changes since v1: - removed superfluous ";" Depends on: - next-20150902 branch of linux-next kernel tree Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (4): PM / OPP: add dev_pm_opp_get_suspend_opp() helper cpufreq: allow cpufreq_generic_suspend() to work without suspend frequency cpufreq-dt: add suspend frequency support ARM: dts: add suspend opp to exynos4412 arch/arm/boot/dts/exynos4412.dtsi | 1 + drivers/base/power/opp.c | 30 ++ drivers/cpufreq/cpufreq-dt.c | 9 + drivers/cpufreq/cpufreq.c | 4 ++-- include/linux/pm_opp.h| 6 ++ 5 files changed, 48 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 4/4] ARM: dts: add suspend opp to exynos4412
Mark 800MHz OPP as a suspend opp for Exynos4412 based
boards so effectively cpufreq-dt driver behavior w.r.t.
suspend frequency matches what the old exynos-cpufreq
driver has been doing.
This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos4412.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index ca0e3c1..294cfe4 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -98,6 +98,7 @@
opp-hz = /bits/ 64 <8>;
opp-microvolt = <100>;
clock-latency-ns = <20>;
+ opp-suspend;
};
opp07 {
opp-hz = /bits/ 64 <9>;
--
1.9.1
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[PATCH v4 3/4] cpufreq-dt: add suspend frequency support
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional).
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq-dt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index c3583cd..e08ae40 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -196,6 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
struct device *cpu_dev;
struct regulator *cpu_reg;
struct clk *cpu_clk;
+ struct dev_pm_opp *suspend_opp;
unsigned long min_uV = ~0, max_uV = 0;
unsigned int transition_latency;
bool need_update = false;
@@ -329,6 +330,13 @@ static int cpufreq_init(struct cpufreq_policy *policy)
policy->driver_data = priv;
policy->clk = cpu_clk;
+
+ rcu_read_lock();
+ suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
+ if (suspend_opp)
+ policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
+ rcu_read_unlock();
+
ret = cpufreq_table_validate_and_show(policy, freq_table);
if (ret) {
dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
@@ -419,6 +427,9 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.ready = cpufreq_ready,
.name = "cpufreq-dt",
.attr = cpufreq_dt_attr,
+#ifdef CONFIG_PM
+ .suspend = cpufreq_generic_suspend,
+#endif
};
static int dt_cpufreq_probe(struct platform_device *pdev)
--
1.9.1
--
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[PATCH v4 2/4] cpufreq: allow cpufreq_generic_suspend() to work without suspend frequency
Some cpufreq drivers may set suspend frequency only for
selected setups but still would like to use the generic
suspend handler. Thus don't treat !policy->suspend_freq
condition as an incorrect one.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index b3d9368..a634fcb 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1626,8 +1626,8 @@ int cpufreq_generic_suspend(struct cpufreq_policy *policy)
int ret;
if (!policy->suspend_freq) {
- pr_err("%s: suspend_freq can't be zero\n", __func__);
- return -EINVAL;
+ pr_debug("%s: suspend_freq not defined\n", __func__);
+ return 0;
}
pr_debug("%s: Setting suspend-freq: %u\n", __func__,
--
1.9.1
--
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[PATCH v4 1/4] PM / OPP: add dev_pm_opp_get_suspend_opp() helper
Add dev_pm_opp_get_suspend_opp() helper to obtain suspend opp.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/base/power/opp.c | 30 ++
include/linux/pm_opp.h | 6 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index eb25449..3d948ea 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -341,6 +341,36 @@ unsigned long dev_pm_opp_get_max_clock_latency(struct
device *dev)
EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_clock_latency);
/**
+ * dev_pm_opp_get_suspend_opp() - Get suspend opp
+ * @dev: device for which we do this operation
+ *
+ * Return: This function returns pointer to the suspend opp if it is
+ * defined, otherwise it returns NULL.
+ *
+ * Locking: This function must be called under rcu_read_lock(). opp is a rcu
+ * protected pointer. The reason for the same is that the opp pointer which is
+ * returned will remain valid for use with opp_get_{voltage, freq} only while
+ * under the locked area. The pointer returned must be used prior to unlocking
+ * with rcu_read_unlock() to maintain the integrity of the pointer.
+ */
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ struct device_opp *dev_opp;
+ struct dev_pm_opp *opp;
+
+ opp_rcu_lockdep_assert();
+
+ dev_opp = _find_device_opp(dev);
+ if (IS_ERR(dev_opp))
+ opp = NULL;
+ else
+ opp = dev_opp->suspend_opp;
+
+ return opp;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_get_suspend_opp);
+
+/**
* dev_pm_opp_get_opp_count() - Get number of opps available in the opp list
* @dev: device for which we do this operation
*
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index cab7ba5..e817722 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -34,6 +34,7 @@ bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp);
int dev_pm_opp_get_opp_count(struct device *dev);
unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev);
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev);
struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq,
@@ -80,6 +81,11 @@ static inline unsigned long
dev_pm_opp_get_max_clock_latency(struct device *dev)
return 0;
}
+static inline struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ return NULL;
+}
+
static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq, bool available)
{
--
1.9.1
--
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[PATCH v4 0/4] cpufreq-dt: add suspend frequency support
Hi, This patch series adds suspend frequency support (using opp-v2 bindings and suspend-opp functionality) to cpufreq-dt driver and then adds suspend opp for Exynos4412 based boards. This patch series fixes suspend/resume support on Exynos4412 based Trats2 board and reboot hang on Exynos4412 based Odroid U3 board. Changes since v3: - fixed dev_pm_opp_get_suspend_opp() locking - shortened variable name in dev_pm_opp_get_suspend_opp() - adjusted cpufreq_generic_suspend() to work with cpufreq-dt - removed no longer needed cpufreq_dt_suspend() - added Acked-by tag from Viresh to patch #4 Changes since v2: - rewrote to use suspend-opp functionality Changes since v1: - removed superfluous ";" Depends on: - next-20150902 branch of linux-next kernel tree Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (4): PM / OPP: add dev_pm_opp_get_suspend_opp() helper cpufreq: allow cpufreq_generic_suspend() to work without suspend frequency cpufreq-dt: add suspend frequency support ARM: dts: add suspend opp to exynos4412 arch/arm/boot/dts/exynos4412.dtsi | 1 + drivers/base/power/opp.c | 30 ++ drivers/cpufreq/cpufreq-dt.c | 11 +++ drivers/cpufreq/cpufreq.c | 4 ++-- include/linux/pm_opp.h| 6 ++ 5 files changed, 50 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/3] cpufreq-dt: add suspend frequency support
Hi, This patch series adds suspend frequency support (using opp-v2 bindings and suspend-opp functionality) to cpufreq-dt driver and then adds suspend opp for Exynos4412 based boards. This patch series fixes suspend/resume support on Exynos4412 based Trats2 board and reboot hang on Exynos4412 based Odroid U3 board. Changes since v2: - rewrited to use suspend-opp functionality Changes since v1: - removed superfluous ";" Depends on: - next-20150902 branch of linux-next kernel tree Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (3): PM / OPP: add dev_pm_opp_get_suspend_opp() helper cpufreq-dt: add suspend frequency support ARM: dts: add suspend opp to exynos4412 arch/arm/boot/dts/exynos4412.dtsi | 1 + drivers/base/power/opp.c | 28 drivers/cpufreq/cpufreq-dt.c | 32 include/linux/pm_opp.h| 6 ++ 4 files changed, 67 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/3] PM / OPP: add dev_pm_opp_get_suspend_opp() helper
Add dev_pm_opp_get_suspend_opp() helper to obtain suspend opp.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/base/power/opp.c | 28
include/linux/pm_opp.h | 6 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
index eb25449..eaafca7 100644
--- a/drivers/base/power/opp.c
+++ b/drivers/base/power/opp.c
@@ -341,6 +341,34 @@ unsigned long dev_pm_opp_get_max_clock_latency(struct
device *dev)
EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_clock_latency);
/**
+ * dev_pm_opp_get_suspend_opp() - Get suspend opp
+ * @dev: device for which we do this operation
+ *
+ * Return: This function returns pointer to the suspend opp if it is
+ * defined, otherwise it returns NULL.
+ *
+ * Locking: This function takes rcu_read_lock().
+ */
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ struct device_opp *dev_opp;
+ struct dev_pm_opp *suspend_opp;
+
+ rcu_read_lock();
+
+ dev_opp = _find_device_opp(dev);
+ if (IS_ERR(dev_opp))
+ suspend_opp = NULL;
+ else
+ suspend_opp = dev_opp->suspend_opp;
+
+ rcu_read_unlock();
+
+ return suspend_opp;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_get_suspend_opp);
+
+/**
* dev_pm_opp_get_opp_count() - Get number of opps available in the opp list
* @dev: device for which we do this operation
*
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index cab7ba5..e817722 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -34,6 +34,7 @@ bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp);
int dev_pm_opp_get_opp_count(struct device *dev);
unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev);
+struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev);
struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq,
@@ -80,6 +81,11 @@ static inline unsigned long
dev_pm_opp_get_max_clock_latency(struct device *dev)
return 0;
}
+static inline struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev)
+{
+ return NULL;
+}
+
static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
unsigned long freq, bool available)
{
--
1.9.1
--
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[PATCH v3 3/3] ARM: dts: add suspend opp to exynos4412
Mark 800MHz OPP as a suspend opp for Exynos4412 based
boards so effectively cpufreq-dt driver behavior w.r.t.
suspend frequency matches what the old exynos-cpufreq
driver has been doing.
This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos4412.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4412.dtsi
b/arch/arm/boot/dts/exynos4412.dtsi
index ca0e3c1..294cfe4 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -98,6 +98,7 @@
opp-hz = /bits/ 64 <8>;
opp-microvolt = <100>;
clock-latency-ns = <20>;
+ opp-suspend;
};
opp07 {
opp-hz = /bits/ 64 <9>;
--
1.9.1
--
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[PATCH v3 2/3] cpufreq-dt: add suspend frequency support
Add suspend frequency support and if needed set it to
the frequency obtained from the suspend opp (can be defined
using opp-v2 bindings and is optional). Also implement
custom suspend method (needed to not error out on platforms
which don't require suspend frequency).
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq-dt.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index c3583cd..ba4ca85 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -196,6 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
struct device *cpu_dev;
struct regulator *cpu_reg;
struct clk *cpu_clk;
+ struct dev_pm_opp *suspend_opp;
unsigned long min_uV = ~0, max_uV = 0;
unsigned int transition_latency;
bool need_update = false;
@@ -329,6 +330,11 @@ static int cpufreq_init(struct cpufreq_policy *policy)
policy->driver_data = priv;
policy->clk = cpu_clk;
+
+ suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
+ if (suspend_opp)
+ policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
+
ret = cpufreq_table_validate_and_show(policy, freq_table);
if (ret) {
dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
@@ -409,6 +415,31 @@ static void cpufreq_ready(struct cpufreq_policy *policy)
of_node_put(np);
}
+#ifdef CONFIG_PM
+static int cpufreq_dt_suspend(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ if (!policy->suspend_freq) {
+ pr_debug("%s: suspend_freq not defined\n", __func__);
+ return 0;
+ }
+
+ pr_debug("%s: Setting suspend-freq: %u\n", __func__,
+ policy->suspend_freq);
+
+ ret = __cpufreq_driver_target(policy, policy->suspend_freq,
+ CPUFREQ_RELATION_H);
+ if (ret)
+ pr_err("%s: unable to set suspend-freq: %u. err: %d\n",
+ __func__, policy->suspend_freq, ret);
+
+ return ret;
+}
+#else
+#define cpufreq_dt_suspend NULL
+#endif
+
static struct cpufreq_driver dt_cpufreq_driver = {
.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
.verify = cpufreq_generic_frequency_table_verify,
@@ -419,6 +450,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.ready = cpufreq_ready,
.name = "cpufreq-dt",
.attr = cpufreq_dt_attr,
+ .suspend = cpufreq_dt_suspend,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
--
1.9.1
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[PATCH v2] cpufreq-dt: add suspend frequency support
Add suspend frequency support and set it to the boot frequency,
this matches what the old exynos-cpufreq driver has been doing.
This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
This patch supersedes "[PATCH] ARM: dts: exynos4412-odroid-*: add
workaround for CPUfreq/reboot issue" one from yesterday.
v2:
- remove superfluous ";"
drivers/cpufreq/cpufreq-dt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index c3583cd..c9138c7 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -329,6 +329,10 @@ static int cpufreq_init(struct cpufreq_policy *policy)
policy->driver_data = priv;
policy->clk = cpu_clk;
+
+ /* capture boot frequency */
+ policy->suspend_freq = clk_get_rate(cpu_clk) / 1000;
+
ret = cpufreq_table_validate_and_show(policy, freq_table);
if (ret) {
dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
@@ -419,6 +423,9 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.ready = cpufreq_ready,
.name = "cpufreq-dt",
.attr = cpufreq_dt_attr,
+#ifdef CONFIG_PM
+ .suspend = cpufreq_generic_suspend,
+#endif
};
static int dt_cpufreq_probe(struct platform_device *pdev)
--
1.9.1
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[PATCH] cpufreq-dt: add suspend frequency support
Add suspend frequency support and set it to the boot frequency,
this matches what the old exynos-cpufreq driver has been doing.
This patch fixes suspend/resume support on Exynos4412 based
Trats2 board and reboot hang on Exynos4412 based Odroid U3
board.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Cc: Marek Szyprowski
Cc: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
This patch supersedes "[PATCH] ARM: dts: exynos4412-odroid-*: add
workaround for CPUfreq/reboot issue" one from yesterday.
drivers/cpufreq/cpufreq-dt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index c3583cd..c9138c7 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -329,6 +329,10 @@ static int cpufreq_init(struct cpufreq_policy *policy)
policy->driver_data = priv;
policy->clk = cpu_clk;
+
+ /* capture boot frequency */
+ policy->suspend_freq = clk_get_rate(cpu_clk) / 1000;;
+
ret = cpufreq_table_validate_and_show(policy, freq_table);
if (ret) {
dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
@@ -419,6 +423,9 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.ready = cpufreq_ready,
.name = "cpufreq-dt",
.attr = cpufreq_dt_attr,
+#ifdef CONFIG_PM
+ .suspend = cpufreq_generic_suspend,
+#endif
};
static int dt_cpufreq_probe(struct platform_device *pdev)
--
1.9.1
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Re: [PATCH] ARM: dts: exynos4412-odroid-*: add workaround for CPUfreq/reboot issue
Hi, On Tuesday, September 01, 2015 10:57:37 PM Krzysztof Kozlowski wrote: > 2015-09-01 22:08 GMT+09:00 Marek Szyprowski : > > Exynos4412-based Odroid boards (X2, U3, U3+) don't reset PMIC > > configuration during hardware reset. This causes serious issues with > > CPUfreq, when ARM voltage is set below 1.0V. When one resets the board > > when CPUfreq selected one of lower Exynos 4412 operating points (for > > example: 200MHz and 0.9V), the bootloader crashes and it is not possible > > s/crashes/hangs/ ? I did not observe a crash but a silent hang. > > > to restart the board without turning power off. > > > > This patch provides a workaround for this issue by increasing the start > > of valid range for vdd_arm regulator from 1.0V. After such change, > > CPUfreq can still use lower operating points, but the voltage won't be > > decreased below 1.0V and as a result it will be possible to reset board > > at any time. > > > > Signed-off-by: Marek Szyprowski > > Do you plan to send the same fix for Trats2 board? Everything above > applies there as well plus suspend is affected. The board cannot > properly resume. > > > --- > > Hello, > > > > This issue was there from the beggining, but I was not able to reproduce > > it. It has been already reported by Tobias in early Feb 2015 > > (http://www.spinics.net/lists/linux-samsung-soc/msg42294.html). > > Recently, after CPUfreq changes (conversion to generic cpufreq dt and > > enabling cpufreq in exynos_defconfig) it was much easier to observe this > > issue. > > > > This workaround lets one still use CPUfreq and avoid unexpect board > > crashes during reboot (both 'standard' and emergency). > > Work-around looks nice and clean. It still allows to use cpufreq and > reduce the energy consumption. The patch should go along with > cpufreq-dt support for Exynos4412 which hopefully would be for v4.3. > If cpufreq-dt for Exynos4412 won't get to v4.3 we can figure out > proper solution, not a work-around. This work-around is needed also for the old exynos-cpufreq driver as the problem was already there on some Odroid setups (please read the mail from February pointed by Marek for details). We don't have a better fix for the time being so I think that it should be merged now regardless of cpufreq-dt changes status. > Anyway for the time being: > Reviewed-by: Krzysztof Kozlowski > > Thanks Marek, > BR Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: CPUIdle for Exynos5422 Odroid-XU3/XU4 boards.
Hi, On Friday, August 28, 2015 09:42:35 PM Krzysztof Kozlowski wrote: > W dniu 28.08.2015 o 17:35, Javier Martinez Canillas pisze: > > Hello Bartlomiej and Lorenzo, > > > > Thanks a lot for your explanations. > > > > On 08/27/2015 06:58 PM, Bartlomiej Zolnierkiewicz wrote: > > > >> If somebody wants to implement a separate Exynos542x/Exynos5800 > >> big.LITTLE cpuidle driver for them I see no problem with it and I'm > >> willing to help in maintaining it. > >> > > > > Ok, I'll see if I can take a look what is needed to implement a Exynos542x > > CPUidle > > driver. I'm quite busy with other stuff right now but I should be less busy > > in a > > couple of weeks. > > The only useful users of Exynos542x cpuidle would be Chromebooks. > Probably the same goes with suspend to RAM. Non-mobile devices could > leave without it. > > In the same time cpuidle and S2R would require a significant amount of > work. Testing would have to be performed on Chromebooks. I have doubts > it would work on Odroid XU3. > > I dug into S2R issues on Odroid XU3 and after fixing trivial imprecise > abort I don't have clue. It just dies somewhere in firmware/bootloader. > Vendor code has a lot more stuff related to suspend and testing it > one-by-one whether it fixes the issue is frustrating. > > Do we really need cpuidle or S2R on Exynos542x/5800? > > > > > Maybe is a little bit out of topic but since Anand also asked about CPUFreq > > support, > > are you planning on re-posting your "cpufreq: add generic cpufreq driver > > support > > for Exynos5250/5800 platforms" [0] series? > > That would be useful. Bartlomiej, do you have plans for continuing the work? Yes. It is still on my TODO but may take a while (1-2 weeks) before I find some time to actually do it. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] clk: samsung: fix cpu clock's flags checking
CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
incorrectly used as a bit numbers. Fix it.
Tested on Exynos4210 based Origen board and on Exynos5250 based
Arndale board.
Cc: Tomasz Figa
Cc: Michael Turquette
Cc: Thomas Abraham
Fixes: ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks")
Reported-by: Dan Carpenter
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Javier Martinez Canillas
Acked-by: Sylwester Nawrocki
Signed-off-by: Bartlomiej Zolnierkiewicz
---
v2:
- added Reviewed-by, Acked-by and Fixes tags (no code changes)
Michael, please apply. Thank you.
drivers/clk/samsung/clk-cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 7c1e1f5..2fe37f7 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct
clk_notifier_data *ndata,
* the values for DIV_COPY and DIV_HPM dividers need not be set.
*/
div0 = cfg_data->div0;
- if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
+ if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
div1 = cfg_data->div1;
if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
div1 = readl(base + E4210_DIV_CPU1) &
@@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct
clk_notifier_data *ndata,
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
- if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
/*
* In Exynos4210, ATB clock parent is also mout_core. So
* ATB clock also needs to be mantained at safe speed.
@@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct
clk_notifier_data *ndata,
writel(div0, base + E4210_DIV_CPU0);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
- if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {
+ if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
writel(div1, base + E4210_DIV_CPU1);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
DIV_MASK_ALL);
@@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct
clk_notifier_data *ndata,
unsigned long mux_reg;
/* find out the divider values to use for clock data */
- if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
while ((cfg_data->prate * 1000) != ndata->new_rate) {
if (cfg_data->prate == 0)
return -EINVAL;
@@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct
clk_notifier_data *ndata,
writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
- if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {
+ if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
div_mask |= E4210_DIV0_ATB_MASK;
}
--
1.9.1
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Re: [PATCH] clk: samsung: fix cpu clock's flags checking
Michael/Sylwester, could you please merge this patch?
It is a bugfix for ddeac8d968d41d13a52582d6e80395a329e9b1ff ("clk:
samsung: add infrastructure to register cpu clocks") which got
merged in v4.2-rc1.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
On Tuesday, June 30, 2015 08:27:36 AM Javier Martinez Canillas wrote:
> On Tue, Jun 30, 2015 at 2:06 AM, Krzysztof Kozlowski
> wrote:
> > On 30.06.2015 02:29, Bartlomiej Zolnierkiewicz wrote:
> >> CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were
> >> incorrectly used as a bit numbers. Fix it.
> >>
> >> Tested on Exynos4210 based Origen board and on Exynos5250 based
> >> Arndale board.
> >>
> >> Cc: Tomasz Figa
> >> Cc: Michael Turquette
> >> Cc: Javier Martinez Canillas
> >> Cc: Thomas Abraham
> >> Reported-by: Dan Carpenter
> >> Signed-off-by: Bartlomiej Zolnierkiewicz
> >> ---
> >> drivers/clk/samsung/clk-cpu.c | 10 +-
> >> 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > Reviewed-by: Krzysztof Kozlowski
> >
>
> Looks good to me as well.
>
> Reviewed-by: Javier Martinez Canillas
>
> > Best regards,
> > Krzysztof
> >
>
> Best regards,
> Javier
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Re: CPUIdle for Exynos5422 Odroid-XU3/XU4 boards.
Hi, On Tuesday, August 25, 2015 05:09:32 PM Lorenzo Pieralisi wrote: > On Tue, Aug 25, 2015 at 03:35:29PM +0100, Bartlomiej Zolnierkiewicz wrote: > > > > [ added Lorenzo and linux-pm to Cc: ] > > > > Hi, > > > > On Tuesday, August 25, 2015 11:43:38 AM Javier Martinez Canillas wrote: > > > [adding Kevin Hilman as cc who was also interested in CPUidle for Exynos] > > > > > > Hello Krzysztof, > > > > > > On 08/23/2015 03:26 AM, Krzysztof Kozlowski wrote: > > > > > > [snip] > > > > > > > 2015-08-21 16:21 GMT+09:00 Javier Martinez Canillas > > > > : > > > > > > > > The big.LITTLE cpuidle driver is not a typical Exynos cpuidle driver. > > > > It only executes CPU suspend on a cluster which essentially is a power > > > > down operation. > > > > > > > > > > You are correct, looking at the the big.LITTLE CPUidle driver I see that > > > it only has two C-states: C0 (normal WFI) and C1 (single CPU power-down) > > > which as you said, places the CPU into power-down mode by using the MCPM > > > infrastructure so it's basically a CPU suspend AFAIU. > > > > > > So what you are saying is that there are deeper C-states supported by the > > > Exynos 542x SoC family but these are not handled by the b.L CPUidle > > > driver. > > > > > > > When we talk about cpuidle on Exynos, we have in mind one of sleep > > > > modes: AFTR or LPA (sometimes instead of LPA there is LPD or W-AFTR). > > > > Actually this is more like a system idle mode, not CPU idle. The power > > > > savings are much bigger than disabling only one cluster. > > > > > > > > > > Interesting, I was not aware of AFTR and LPA but I looked in the manual > > > now. > > > Thanks a lot for the information. > > > > > > I see that the Exynos CPUidle driver (drivers/cpuidle/cpuidle-exynos.c) > > > also > > > has only two C-states (WFI and C1) but C1 makes the system to enter in > > > AFTR > > > (system-level power gating). > > > > > > This is similar to what the downstream ChromiumOS 3.8 kernel CPUidle > > > driver > > > does IIUC [0]. > > > > Yes but upstream does it in a clean way, has support for platforms > > requiring secure firmware operations and also implements coupled > > AFTR mode on a few platforms. > > > > > > So the question is still valid - whether someone wants or plans to > > > > implement cpuidle for Exynos 542x family. Odroid XU3 is not a priority > > > > here because energy consumption is not an issue there. This is not a > > > > mobile device. > > > > > > > > > > That's true but it will be interesting for the 5420 and 5800 based > > > Chromebooks since optimizing power consumption would be useful there. > > > > I would be happy to help with reviewing patches etc. but personally > > I don't have any plans for doing this work. I may look into adding > > support for newer ARM64 SoCs (Exynos5433) if I find some extra time > > (quite unlikely currently). > > > > > I thought that big.LITTLE platforms were encouraged to use the generic b.L > > > CPUidle driver just like DT platforms should use the generic CPUFreq DT > > > driver but I guess I misunderstood. > > > > > > So the b.L CPUidle driver is only to have minimum CPUidle support but a > > > SoC > > > specific driver is needed to fine tune and get most out of the platform? > > > > > > Or should the b.L CPUidle driver be extended to add per platform C-states? > > > > This is a good question. Daniel/Lorenzo? > > To move the b.L driver to multiple C-states we should first convert it to > the generic CPUidle driver (by defining an MCPM enable-method): > > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/cpuidle/cpuidle-arm.c?id=refs/tags/v4.2-rc8 > > Then we have to figure out how to determine how many CPUidle drivers we > have to create (since idle states are different on different CPUs), since > using the MIDR does not really scale. > > For certain I won't support coupled C-states in the DT idle states code, > and every platform requiring them is considered buggy and not worth > merging in the mainline kernel from now onwards, HW should be fixed, > eventually, I am not willing to see code like > drivers/cpuidle/cpuidle-exynos.c in the mainline kernel anymore, > I am sor
Re: CPUIdle for Exynos5422 Odroid-XU3/XU4 boards.
[ added Lorenzo and linux-pm to Cc: ] Hi, On Tuesday, August 25, 2015 11:43:38 AM Javier Martinez Canillas wrote: > [adding Kevin Hilman as cc who was also interested in CPUidle for Exynos] > > Hello Krzysztof, > > On 08/23/2015 03:26 AM, Krzysztof Kozlowski wrote: > > [snip] > > > 2015-08-21 16:21 GMT+09:00 Javier Martinez Canillas > > : > > > > The big.LITTLE cpuidle driver is not a typical Exynos cpuidle driver. > > It only executes CPU suspend on a cluster which essentially is a power > > down operation. > > > > You are correct, looking at the the big.LITTLE CPUidle driver I see that > it only has two C-states: C0 (normal WFI) and C1 (single CPU power-down) > which as you said, places the CPU into power-down mode by using the MCPM > infrastructure so it's basically a CPU suspend AFAIU. > > So what you are saying is that there are deeper C-states supported by the > Exynos 542x SoC family but these are not handled by the b.L CPUidle driver. > > > When we talk about cpuidle on Exynos, we have in mind one of sleep > > modes: AFTR or LPA (sometimes instead of LPA there is LPD or W-AFTR). > > Actually this is more like a system idle mode, not CPU idle. The power > > savings are much bigger than disabling only one cluster. > > > > Interesting, I was not aware of AFTR and LPA but I looked in the manual now. > Thanks a lot for the information. > > I see that the Exynos CPUidle driver (drivers/cpuidle/cpuidle-exynos.c) also > has only two C-states (WFI and C1) but C1 makes the system to enter in AFTR > (system-level power gating). > > This is similar to what the downstream ChromiumOS 3.8 kernel CPUidle driver > does IIUC [0]. Yes but upstream does it in a clean way, has support for platforms requiring secure firmware operations and also implements coupled AFTR mode on a few platforms. > > So the question is still valid - whether someone wants or plans to > > implement cpuidle for Exynos 542x family. Odroid XU3 is not a priority > > here because energy consumption is not an issue there. This is not a > > mobile device. > > > > That's true but it will be interesting for the 5420 and 5800 based > Chromebooks since optimizing power consumption would be useful there. I would be happy to help with reviewing patches etc. but personally I don't have any plans for doing this work. I may look into adding support for newer ARM64 SoCs (Exynos5433) if I find some extra time (quite unlikely currently). > I thought that big.LITTLE platforms were encouraged to use the generic b.L > CPUidle driver just like DT platforms should use the generic CPUFreq DT > driver but I guess I misunderstood. > > So the b.L CPUidle driver is only to have minimum CPUidle support but a SoC > specific driver is needed to fine tune and get most out of the platform? > > Or should the b.L CPUidle driver be extended to add per platform C-states? This is a good question. Daniel/Lorenzo? > > Best regards, > > Krzysztof > > > > [0]: > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-3.8/arch/arm/mach-exynos/cpuidle.c Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFT PATCH] arm: s3c2410_defconfig: convert to use libata PATA drivers
IDE subsystem has been deprecated since 2009 and the majority (if not all) of Linux distributions have switched to use libata for ATA support exclusively. However there are still some users (mostly old or/and embedded non-x86 systems) that have not converted from using IDE subsystem to libata PATA drivers. This doesn't seem to be good thing in the long-term for Linux as while there is less and less PATA systems left in use: * testing efforts are divided between two subsystems * having duplicate drivers for same hardware confuses users This patch converts s3c2410_defconfig to use libata PATA drivers. Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: linux-samsung-soc@vger.kernel.org Cc: Ben Dooks Cc: Vincent Sanders Cc: Simtec Linux Team Signed-off-by: Bartlomiej Zolnierkiewicz --- Build tested only. If you have affected hardware please test. Thank you. arch/arm/configs/s3c2410_defconfig | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index f314236..f44fa09 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -220,20 +220,16 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_UB=m CONFIG_BLK_DEV_RAM=y CONFIG_ATA_OVER_ETH=m -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDETAPE=m -CONFIG_BLK_DEV_PLATFORM=y -CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_ATA=y +CONFIG_PATA_PLATFORM=y CONFIG_NETDEVICES=y CONFIG_DM9000=y CONFIG_INPUT_EVDEV=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] cpufreq-dt: make scaling_boost_freqs sysfs attr available when boost is enabled
Make scaling_boost_freqs sysfs attribute is available when
cpufreq-dt driver is used and boost support is enabled.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Suggested-by: Viresh Kumar
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
v2: Removed leftover prototype.
v3: added missing Acked-by
Sorry for two resends, this is not my day..
Rafael, please apply for v4.3.
drivers/cpufreq/cpufreq-dt.c | 9 -
include/linux/cpufreq.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index b9259ab..c3583cd 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -36,6 +36,12 @@ struct private_data {
unsigned int voltage_tolerance; /* in percentage */
};
+static struct freq_attr *cpufreq_dt_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL, /* Extra space for boost-attr if required */
+ NULL,
+};
+
static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
@@ -336,6 +342,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
ret = cpufreq_enable_boost_support();
if (ret)
goto out_free_cpufreq_table;
+ cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
}
policy->cpuinfo.transition_latency = transition_latency;
@@ -411,7 +418,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.exit = cpufreq_exit,
.ready = cpufreq_ready,
.name = "cpufreq-dt",
- .attr = cpufreq_generic_attr,
+ .attr = cpufreq_dt_attr,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 95f0186..657542d 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -609,6 +609,7 @@ struct cpufreq_frequency_table
*cpufreq_frequency_get_table(unsigned int cpu);
/* the following are really really optional */
extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;
+extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs;
extern struct freq_attr *cpufreq_generic_attr[];
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);
--
1.9.1
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[PATCH v2] cpufreq-dt: make scaling_boost_freqs sysfs attr available when boost is enabled
Make scaling_boost_freqs sysfs attribute is available when
cpufreq-dt driver is used and boost support is enabled.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Suggested-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
v2: Removed leftover prototype.
drivers/cpufreq/cpufreq-dt.c | 9 -
include/linux/cpufreq.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index b9259ab..c3583cd 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -36,6 +36,12 @@ struct private_data {
unsigned int voltage_tolerance; /* in percentage */
};
+static struct freq_attr *cpufreq_dt_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL, /* Extra space for boost-attr if required */
+ NULL,
+};
+
static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
@@ -336,6 +342,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
ret = cpufreq_enable_boost_support();
if (ret)
goto out_free_cpufreq_table;
+ cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
}
policy->cpuinfo.transition_latency = transition_latency;
@@ -411,7 +418,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.exit = cpufreq_exit,
.ready = cpufreq_ready,
.name = "cpufreq-dt",
- .attr = cpufreq_generic_attr,
+ .attr = cpufreq_dt_attr,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 95f0186..657542d 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -609,6 +609,7 @@ struct cpufreq_frequency_table
*cpufreq_frequency_get_table(unsigned int cpu);
/* the following are really really optional */
extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;
+extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs;
extern struct freq_attr *cpufreq_generic_attr[];
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);
--
1.9.1
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[PATCH] cpufreq-dt: make scaling_boost_freqs sysfs attr available when boost is enabled
Make scaling_boost_freqs sysfs attribute is available when
cpufreq-dt driver is used and boost support is enabled.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Suggested-by: Viresh Kumar
Acked-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
Rafael, please apply for v4.3. Thanks!
drivers/cpufreq/cpufreq-dt.c | 11 ++-
include/linux/cpufreq.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index b9259ab..c6a3b98 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -36,6 +36,12 @@ struct private_data {
unsigned int voltage_tolerance; /* in percentage */
};
+static struct freq_attr *cpufreq_dt_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL, /* Extra space for boost-attr if required */
+ NULL,
+};
+
static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
@@ -182,6 +188,8 @@ try_again:
return ret;
}
+static struct cpufreq_driver dt_cpufreq_driver;
+
static int cpufreq_init(struct cpufreq_policy *policy)
{
struct cpufreq_frequency_table *freq_table;
@@ -336,6 +344,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
ret = cpufreq_enable_boost_support();
if (ret)
goto out_free_cpufreq_table;
+ cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
}
policy->cpuinfo.transition_latency = transition_latency;
@@ -411,7 +420,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.exit = cpufreq_exit,
.ready = cpufreq_ready,
.name = "cpufreq-dt",
- .attr = cpufreq_generic_attr,
+ .attr = cpufreq_dt_attr,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 95f0186..657542d 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -609,6 +609,7 @@ struct cpufreq_frequency_table
*cpufreq_frequency_get_table(unsigned int cpu);
/* the following are really really optional */
extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;
+extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs;
extern struct freq_attr *cpufreq_generic_attr[];
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);
--
1.9.1
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Re: [PATCH v4 0/6] cpufreq: use generic cpufreq drivers for Exynos4x12 platform
On Friday, August 07, 2015 05:09:50 PM Viresh Kumar wrote: > On 07-08-15, 13:31, Bartlomiej Zolnierkiewicz wrote: > > Users don't need to enable the config option to get boost > > functionality working. It is only needed to get scaling_boost_freqs > > sysfs attribute visible (which lists available boost freqs) when > > using cpufreq-dt driver. Also the config option in question is not > > user visible. > > By users I meant the people who will prepare the build images for the > release. They can just enable the config option :) OK. > > The worst thing that happens if these 2 PM patches don't make it > > in time is that there will be no scaling_boost_freqs available > > when using cpufreq-dt driver. Which is not very important from > > Exynos4x12 POV as it only supports single boost freq currently. > > Right. So, now that your patch is Acked, send 1/6 and 6/6 separately > to pm-list and Rafael can get them merged himself.. > > I hope, your 6/6 patch will change a bit now ? Hmm, wait. Patch 6/6 depends on earlier changes. I cannot remove the config option in question now as it is currently used by exynos-cpufreq specific boost support. Patch 1/6 can be applied now but 6/6 needs to wait for patches 2-5 to be applied first. Actually 6/6 is trivial and can be applied later in v4.3 cycle or even in v4.4 one. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/6] cpufreq: use generic cpufreq drivers for Exynos4x12 platform
Hi, On Friday, August 07, 2015 10:48:26 AM Viresh Kumar wrote: > On 07-08-15, 13:52, Krzysztof Kozlowski wrote: > > Thanks for explanation. As fair as I understand, Bartlomiej wanted to > > merge this in a way which would avoid loosing the boost mode. Kukjin > > prepared topic branches for previous cpu-freq/clk stuff so maybe > > everything could go through PM? > > We aren't loosing anything at all. There can be two cases here: > > 1. Patch 1/6 and 6/6 make it to 4.3 (with suggested changes) via PM tree: > - All will work fine in this case, no issues at all.. > > 2. They don't make it: > - Even in this case, nothing will break. Users can just enable a > config option and that's all.. Users don't need to enable the config option to get boost functionality working. It is only needed to get scaling_boost_freqs sysfs attribute visible (which lists available boost freqs) when using cpufreq-dt driver. Also the config option in question is not user visible. The worst thing that happens if these 2 PM patches don't make it in time is that there will be no scaling_boost_freqs available when using cpufreq-dt driver. Which is not very important from Exynos4x12 POV as it only supports single boost freq currently. > So, no need to divert things into another tree this late. I agree. > Over that, Rafael will not be around for 2 weeks now (Plumbers and > other stuff) .. > > So, just target the cpufreq core changes via PM tree.. rest is just > fine. > > I hope that makes sense :) Yes. :) Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/6] cpufreq: make scaling_boost_freqs sysfs attr available when boost is enabled
On Friday, August 07, 2015 04:11:56 PM Viresh Kumar wrote:
> On 07-08-15, 12:34, Bartlomiej Zolnierkiewicz wrote:
> > > I would suggest you sending such patches as reply to the earlier
> > > threads only, instead of a new chain. This will save your time.
> >
> > Please explain it more. This patch needs to be first for cpufreq-dt
> > switch to be complete. scaling_boost_freqs is available currently
> > for exynos-cpufreq users when boost is enabled and ideally we would
> > like it to be available immediately after the switch to cpufreq-dt.
>
> I wasn't talking about the ordering of the patches here, but when to
> send patches.
>
> So, you now sent these patches again, but what you could have done
> is: only send the first patch in reply to the earlier thread. And ask
> if it looks fine. If yes, resend the whole series properly or keep
> fixing there only..
>
> That makes things really fast. You don't have to resend the series and
> people wouldn't stay away from it. I stayed away from this series to
> find enough available time to see your 6 patches. Had it been just a
> reply, I would have replied immediately like now.
>
> Look at how updated versions in the same mail chain in case of OPP
> series..
Please find updated patch below. It can be moved just before
patch #6 and all patches in the series would still apply fine.
-----8<---
>From 993ebb6fc632ec7b61654c9610c90ff4dca4be34 Mon Sep 17 00:00:00 2001
From: Bartlomiej Zolnierkiewicz
Date: Fri, 7 Aug 2015 13:07:51 +0200
Subject: [PATCH] cpufreq-dt: make scaling_boost_freqs sysfs attr available
when boost is enabled
Make scaling_boost_freqs sysfs attribute is available when
cpufreq-dt driver is used and boost support is enabled.
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Suggested-by: Viresh Kumar
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq-dt.c | 11 ++-
include/linux/cpufreq.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index b9259ab..c6a3b98 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -36,6 +36,12 @@ struct private_data {
unsigned int voltage_tolerance; /* in percentage */
};
+static struct freq_attr *cpufreq_dt_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL, /* Extra space for boost-attr if required */
+ NULL,
+};
+
static int set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
@@ -182,6 +188,8 @@ try_again:
return ret;
}
+static struct cpufreq_driver dt_cpufreq_driver;
+
static int cpufreq_init(struct cpufreq_policy *policy)
{
struct cpufreq_frequency_table *freq_table;
@@ -336,6 +344,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
ret = cpufreq_enable_boost_support();
if (ret)
goto out_free_cpufreq_table;
+ cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
}
policy->cpuinfo.transition_latency = transition_latency;
@@ -411,7 +420,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
.exit = cpufreq_exit,
.ready = cpufreq_ready,
.name = "cpufreq-dt",
- .attr = cpufreq_generic_attr,
+ .attr = cpufreq_dt_attr,
};
static int dt_cpufreq_probe(struct platform_device *pdev)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 95f0186..657542d 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -609,6 +609,7 @@ struct cpufreq_frequency_table
*cpufreq_frequency_get_table(unsigned int cpu);
/* the following are really really optional */
extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;
+extern struct freq_attr cpufreq_freq_attr_scaling_boost_freqs;
extern struct freq_attr *cpufreq_generic_attr[];
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);
--
1.9.1
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Re: [PATCH v4 1/6] cpufreq: make scaling_boost_freqs sysfs attr available when boost is enabled
Hi,
On Friday, August 07, 2015 09:11:28 AM Viresh Kumar wrote:
> Hi,
>
> I would suggest you sending such patches as reply to the earlier
> threads only, instead of a new chain. This will save your time.
Please explain it more. This patch needs to be first for cpufreq-dt
switch to be complete. scaling_boost_freqs is available currently
for exynos-cpufreq users when boost is enabled and ideally we would
like it to be available immediately after the switch to cpufreq-dt.
> For example, you will need to resend other patches unnecessarily if I
> NAK this patch :)
>
> On 06-08-15, 15:41, Bartlomiej Zolnierkiewicz wrote:
> > Add cpufreq_boost_enabled_generic_attr table and use it in
> > cpufreq-dt driver instead of cpufreq_generic_attr one when
> > boost support is enabled. As a result scaling_boost_freqs
> > sysfs attribute is available when cpufreq-dt driver is
> > used and boost support is enabled.
> >
> > Cc: Viresh Kumar
> > Cc: Thomas Abraham
> > Cc: Javier Martinez Canillas
> > Cc: Krzysztof Kozlowski
> > Signed-off-by: Bartlomiej Zolnierkiewicz
> > ---
> > drivers/cpufreq/cpufreq-dt.c | 3 +++
> > drivers/cpufreq/freq_table.c | 7 +++
> > include/linux/cpufreq.h | 1 +
> > 3 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
> > index b9259ab..7b091c0 100644
> > --- a/drivers/cpufreq/cpufreq-dt.c
> > +++ b/drivers/cpufreq/cpufreq-dt.c
> > @@ -182,6 +182,8 @@ try_again:
> > return ret;
> > }
> >
> > +static struct cpufreq_driver dt_cpufreq_driver;
> > +
> > static int cpufreq_init(struct cpufreq_policy *policy)
> > {
> > struct cpufreq_frequency_table *freq_table;
> > @@ -336,6 +338,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> > ret = cpufreq_enable_boost_support();
> > if (ret)
> > goto out_free_cpufreq_table;
> > + dt_cpufreq_driver.attr = cpufreq_boost_enabled_generic_attr;
> > }
> >
> > policy->cpuinfo.transition_latency = transition_latency;
> > diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c
> > index a8f1daf..5a00a09 100644
> > --- a/drivers/cpufreq/freq_table.c
> > +++ b/drivers/cpufreq/freq_table.c
> > @@ -300,6 +300,13 @@ struct freq_attr *cpufreq_generic_attr[] = {
> > };
> > EXPORT_SYMBOL_GPL(cpufreq_generic_attr);
> >
> > +struct freq_attr *cpufreq_boost_enabled_generic_attr[] = {
> > + &cpufreq_freq_attr_scaling_available_freqs,
> > + &cpufreq_freq_attr_scaling_boost_freqs,
> > + NULL,
> > +};
> > +EXPORT_SYMBOL_GPL(cpufreq_boost_enabled_generic_attr);
>
> This isn't scalable. We can't create a new generic structure every time
> a entry comes in. Rather we should leave the generic attr for
boost entry is rather generic one so I imagine that other cpufreq
drivers that add support for boost would also like to use it.
Anyway since there are no such drivers currently I agree that
making a new generic structure may be premature and I will re-do
this patch according to your request.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> cpufreq-dt and do something like this in the cpufreq-dt driver (And
> that patch should rather go via cpufreq tree and not ARM SoC)..
>
> diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
> index a5b6a854661f..e229258ad791 100644
> --- a/drivers/cpufreq/cpufreq-dt.c
> +++ b/drivers/cpufreq/cpufreq-dt.c
> @@ -36,6 +36,12 @@ struct private_data {
> unsigned int voltage_tolerance; /* in percentage */
> };
>
> +static struct freq_attr *cpufreq_dt_attr[] = {
> + &cpufreq_freq_attr_scaling_available_freqs,
> + NULL, /* Extra space for boost-attr if required */
> + NULL,
> +};
> +
> static int set_target(struct cpufreq_policy *policy, unsigned int index)
> {
> struct dev_pm_opp *opp;
> @@ -337,6 +343,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
> ret = cpufreq_enable_boost_support();
> if (ret)
> goto out_free_cpufreq_table;
> + cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
> }
>
> policy->cpuinfo.transition_latency = transition_latency;
> @@ -412,7 +419,7 @@ static struct cpufreq_driver dt_cpufreq_driver = {
> .exit = cpufreq_exit,
> .ready = cpufreq_ready,
> .name = "cpufreq-dt",
> - .attr = cpufreq_generic_attr,
> + .attr = cpufreq_dt_attr,
> };
>
> static int dt_cpufreq_probe(struct platform_device *pdev)
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[PATCH v4 1/6] cpufreq: make scaling_boost_freqs sysfs attr available when boost is enabled
Add cpufreq_boost_enabled_generic_attr table and use it in
cpufreq-dt driver instead of cpufreq_generic_attr one when
boost support is enabled. As a result scaling_boost_freqs
sysfs attribute is available when cpufreq-dt driver is
used and boost support is enabled.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/cpufreq-dt.c | 3 +++
drivers/cpufreq/freq_table.c | 7 +++
include/linux/cpufreq.h | 1 +
3 files changed, 11 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index b9259ab..7b091c0 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -182,6 +182,8 @@ try_again:
return ret;
}
+static struct cpufreq_driver dt_cpufreq_driver;
+
static int cpufreq_init(struct cpufreq_policy *policy)
{
struct cpufreq_frequency_table *freq_table;
@@ -336,6 +338,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
ret = cpufreq_enable_boost_support();
if (ret)
goto out_free_cpufreq_table;
+ dt_cpufreq_driver.attr = cpufreq_boost_enabled_generic_attr;
}
policy->cpuinfo.transition_latency = transition_latency;
diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c
index a8f1daf..5a00a09 100644
--- a/drivers/cpufreq/freq_table.c
+++ b/drivers/cpufreq/freq_table.c
@@ -300,6 +300,13 @@ struct freq_attr *cpufreq_generic_attr[] = {
};
EXPORT_SYMBOL_GPL(cpufreq_generic_attr);
+struct freq_attr *cpufreq_boost_enabled_generic_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ &cpufreq_freq_attr_scaling_boost_freqs,
+ NULL,
+};
+EXPORT_SYMBOL_GPL(cpufreq_boost_enabled_generic_attr);
+
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table)
{
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 95f0186..25937ff 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -610,6 +610,7 @@ struct cpufreq_frequency_table
*cpufreq_frequency_get_table(unsigned int cpu);
/* the following are really really optional */
extern struct freq_attr cpufreq_freq_attr_scaling_available_freqs;
extern struct freq_attr *cpufreq_generic_attr[];
+extern struct freq_attr *cpufreq_boost_enabled_generic_attr[];
int cpufreq_table_validate_and_show(struct cpufreq_policy *policy,
struct cpufreq_frequency_table *table);
--
1.9.1
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[PATCH v4 2/6] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by Thomas Abraham.
Cc: Tomasz Figa
Cc: Michael Turquette
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrocki
Tested-by: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos4.c | 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 251f48d..7f370d3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data
e4210_armclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
+ { 150, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 140, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 130, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 120, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 110, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
+ { 100, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
+ { 90, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 80, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 70, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 60, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 50, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 40, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 30, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 20, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
+ { 0 },
+};
+
+#define E4412_CPU_DIV1(cores, hpm, copy) \
+ (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
+ { 150, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
+ { 140, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
+ { 130, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
+ { 120, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
+ { 110, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
+ { 100, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
+ { 90, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
+ { 80, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 70, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 60, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 50, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 40, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 30, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 20, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
+ { 0 },
+};
+
/* register exynos4 clocks */
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
@@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4x12_fixed_factor_clks,
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+ if (of_machine_is_compatible("samsung,exynos4412")) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ }
}
samsung_clk_register_alias(ctx, exynos4_aliases,
--
1.9.1
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[PATCH v4 3/6] ARM: dts: Exynos4x12: add CPU OPP and regulator supply property
For Exynos4x12 platforms, add CPU operating points (using
opp-v2 bindings) and CPU regulator supply properties for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Based on the earlier work by Thomas Abraham.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Andreas Faerber
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Viresh Kumar
Tested-by: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos4212.dtsi | 81
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 ++
arch/arm/boot/dts/exynos4412-origen.dts | 4 ++
arch/arm/boot/dts/exynos4412-trats2.dts | 4 ++
arch/arm/boot/dts/exynos4412.dtsi | 83 +
5 files changed, 176 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index d9c8efee..5389011 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -30,6 +30,9 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA00>;
+ clocks = <&clock CLK_ARM_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
cooling-min-level = <13>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
@@ -39,6 +42,84 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <20>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <20>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <20>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <20>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <20>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <987500>;
+ clock-latency-ns = <20>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <20>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <20>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <1087500>;
+ clock-latency-ns = <20>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <20>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1187500>;
+ clock-latency-ns = <20>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <20>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <1287500>;
+ clock-latency-ns = <20>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <15>
[PATCH v4 5/6] cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support
Exynos4x12 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Also once Exynos4x12 based platforms support have been removed
the shared exynos-cpufreq driver is no longer needed and can
be deleted.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Viresh Kumar
Tested-by: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/Kconfig.arm | 38 --
drivers/cpufreq/Makefile | 2 -
drivers/cpufreq/exynos-cpufreq.c | 236 ---
drivers/cpufreq/exynos-cpufreq.h | 72 ---
drivers/cpufreq/exynos4x12-cpufreq.c | 236 ---
5 files changed, 584 deletions(-)
delete mode 100644 drivers/cpufreq/exynos-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos-cpufreq.h
delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 9ab6388c1..8a24bd8 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -24,44 +24,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
This add the CPUfreq driver support for Versatile Express
big.LITTLE platforms using SPC for power management.
-
-config ARM_EXYNOS_CPUFREQ
- tristate "SAMSUNG EXYNOS CPUfreq Driver"
- depends on CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412 ||
SOC_EXYNOS5250
- depends on THERMAL
- help
- This adds the CPUFreq driver for Samsung EXYNOS platforms.
- Supported SoC versions are:
-Exynos4210, Exynos4212, Exynos4412, and Exynos5250.
-
- If in doubt, say N.
-
-config ARM_EXYNOS4X12_CPUFREQ
- bool "SAMSUNG EXYNOS4x12"
- depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
- depends on ARM_EXYNOS_CPUFREQ
- default y
- help
- This adds the CPUFreq driver for Samsung EXYNOS4X12
- SoC (EXYNOS4212 or EXYNOS4412).
-
- If in doubt, say N.
-
-config ARM_EXYNOS_CPU_FREQ_BOOST_SW
- bool "EXYNOS Frequency Overclocking - Software"
- depends on ARM_EXYNOS_CPUFREQ && THERMAL
- select CPU_FREQ_BOOST_SW
- select EXYNOS_THERMAL
- help
- This driver supports software managed overclocking (BOOST).
- It allows usage of special frequencies for Samsung Exynos
- processors if thermal conditions are appropriate.
-
- It requires, for safe operation, thermal framework with properly
- defined trip points.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
tristate "SAMSUNG EXYNOS5440"
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 6414958..bbc4a9f 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -53,8 +53,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += arm-exynos-cpufreq.o
-arm-exynos-cpufreq-y := exynos-cpufreq.o
-arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)+= exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)+= hisi-acpu-cpufreq.o
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
deleted file mode 100644
index 567a6ab..000
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - CPU frequency scaling support for EXYNOS series
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "exynos-cpufreq.h"
-
-static struct exynos_dvfs_info *exynos_info;
-static struct thermal_cooling_device *cdev;
-static struct regulator *arm_regulator;
-static unsigned int locking_frequency;
-
-static int exynos_cpufreq_get_index(unsigned int freq)
-{
- struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
- struct cpufreq_frequency_table *pos;
-
- cpufreq_for_each_entry(pos, freq_table)
- if (pos->frequency == freq)
- break;
-
- if (pos->frequency == CPUFREQ_TABLE_END)
- return -EINVAL;
-
- return p
[PATCH v4 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4x12 to using generic cpufreq driver.
Previously (when exynos-cpufreq driver was used with boost
functionality) ARM_EXYNOS_CPU_FREQ_BOOST_SW config option
(which enabled boost functionality) selected EXYNOS_THERMAL
one. After switching Exynos4x12 platforms to use cpufreq-dt
driver boost support is enabled in the cpufreq-dt driver
itself (because there are turbo OPPs defined in the board's
DTS file). However we still would like to allow enabling
boost support only if thermal support is also enabled for
Exynos platforms. To achieve this make ARCH_EXYNOS config
option select THERMAL and EXYNOS_THERMAL ones.
Please also note that the switch to use the generic cpufreq-dt
driver fixes the minor issue present with the old code (support
for 'boost' mode in the exynos-cpufreq driver was enabled for
all supported SoCs even though 'boost' frequency was provided
only for Exynos4x12 ones).
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Viresh Kumar
Tested-by: Tobias Jakobi
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/Kconfig | 2 ++
arch/arm/mach-exynos/exynos.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4c4858c..143e332 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -25,6 +25,8 @@ menuconfig ARCH_EXYNOS
select S5P_DEV_MFC
select SRAM
select MFD_SYSCON
+ select THERMAL
+ select EXYNOS_THERMAL
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 77ac021..1c47aee 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,8 @@ static void __init exynos_init_irq(void)
static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos3250", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
{ /* sentinel */ }
};
--
1.9.1
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[PATCH v4 6/6] cpufreq: remove no longer needed CPU_FREQ_BOOST_SW config option
Remove no longer needed CPU_FREQ_BOOST_SW config option.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/Kconfig | 4
drivers/cpufreq/freq_table.c | 3 ---
2 files changed, 7 deletions(-)
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 659879a..aacc0ef 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -21,10 +21,6 @@ if CPU_FREQ
config CPU_FREQ_GOV_COMMON
bool
-config CPU_FREQ_BOOST_SW
- bool
- depends on THERMAL
-
config CPU_FREQ_STAT
tristate "CPU frequency translation statistics"
default y
diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c
index 5a00a09..2c6a325 100644
--- a/drivers/cpufreq/freq_table.c
+++ b/drivers/cpufreq/freq_table.c
@@ -293,9 +293,6 @@ EXPORT_SYMBOL_GPL(cpufreq_freq_attr_scaling_boost_freqs);
struct freq_attr *cpufreq_generic_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
-#ifdef CONFIG_CPU_FREQ_BOOST_SW
- &cpufreq_freq_attr_scaling_boost_freqs,
-#endif
NULL,
};
EXPORT_SYMBOL_GPL(cpufreq_generic_attr);
--
1.9.1
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[PATCH v4 0/6] cpufreq: use generic cpufreq drivers for Exynos4x12 platform
Hi, This patch series removes the use of Exynos4x12 specific support from cpufreq-exynos driver and enables the use of cpufreq-dt driver for this platform. This patch series has been tested on Exynos4412 based Odroid-U3 and Trats2 boards. Depends on: - next-20150806 branch of linux-next kernel tree - "[PATCH V3 00/16] OPP: Add code to support operating-points-v2 bindings" (http://www.spinics.net/lists/arm-kernel/msg435408.html) Changes since v3 (http://thread.gmane.org/gmane.linux.power-management.general/63464): - rebased on top of next-20150806 branch of linux-next kernel tree - made ARCH_EXYNOS config option select thermal support - made scaling_boost_freqs sysfs attribute available only when boost support is enabled - added Acked-by tag from Viresh to patches #3, #4 and #5 - added Tested-by tag from Tobias to patches #2-5 - added Reviewed-by tag from Krzysztof to patch #4 Changes since v2 (http://thread.gmane.org/gmane.linux.kernel.samsung-soc/46653): - rebased on top of next-20150730 branch of linux-next kernel tree - ported over V3 of opp-v2 bindings support patch series - put cpu0 nodes in alphabetical order in dts files - added Reviewed-by tags from Javier and Krzysztof - added Acked-by tag from Sylwester Changes since v1 (http://thread.gmane.org/gmane.linux.kernel.samsung-soc/44361): - rebased on top of next-20150629 branch of linux-next kernel tree - rebased on top of Exynos5250 cpufreq-dt support patch series - fixed if-statement in exynos4_clk_init() (noticed by Tobias Jakobi) - ported over opp-v2 bindings (requested by Viresh Kumar) Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (6): cpufreq: make scaling_boost_freqs sysfs attr available when boost is enabled clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos4x12: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12 cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support cpufreq: remove no longer needed CPU_FREQ_BOOST_SW config option arch/arm/boot/dts/exynos4212.dtsi | 81 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 + arch/arm/boot/dts/exynos4412-origen.dts | 4 + arch/arm/boot/dts/exynos4412-trats2.dts | 4 + arch/arm/boot/dts/exynos4412.dtsi | 83 + arch/arm/mach-exynos/Kconfig| 2 + arch/arm/mach-exynos/exynos.c | 2 + drivers/clk/samsung/clk-exynos4.c | 50 + drivers/cpufreq/Kconfig | 4 - drivers/cpufreq/Kconfig.arm | 38 drivers/cpufreq/Makefile| 2 - drivers/cpufreq/cpufreq-dt.c| 3 + drivers/cpufreq/exynos-cpufreq.c| 236 drivers/cpufreq/exynos-cpufreq.h| 72 drivers/cpufreq/exynos4x12-cpufreq.c| 236 drivers/cpufreq/freq_table.c| 10 +- include/linux/cpufreq.h | 1 + 17 files changed, 241 insertions(+), 591 deletions(-) delete mode 100644 drivers/cpufreq/exynos-cpufreq.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
On Monday, August 03, 2015 09:20:41 PM Viresh Kumar wrote:
> On 03-08-15, 15:55, Bartlomiej Zolnierkiewicz wrote:
> > diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> > index 81064cd..491914c 100644
> > --- a/arch/arm/mach-exynos/Kconfig
> > +++ b/arch/arm/mach-exynos/Kconfig
> > @@ -25,6 +25,8 @@ menuconfig ARCH_EXYNOS
> > select S5P_DEV_MFC
> > select SRAM
> > select MFD_SYSCON
> > + select THERMAL
> > + select EXYNOS_THERMAL
>
> Why do you need to select both of them?
Because otherwise you can disable the whole THERMAL subsystem support
(effectively disabling EXYNOS_THERMAL in the process).
This is the same way in which ARCH_EXYNOS handles PINCTRL_EXYNOS
support currently (it also selects PINCTRL subsystem).
> > help
> > Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
> >
> > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> > index 77ac021..1c47aee 100644
> > --- a/arch/arm/mach-exynos/exynos.c
> > +++ b/arch/arm/mach-exynos/exynos.c
> > @@ -227,6 +227,8 @@ static void __init exynos_init_irq(void)
> > static const struct of_device_id exynos_cpufreq_matches[] = {
> > { .compatible = "samsung,exynos3250", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
> > + { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
> > + { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> > { /* sentinel */ }
> > };
>
> Otherwise looks fine:
>
> Acked-by: Viresh Kumar
Thanks!
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
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Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
Hi, On Monday, August 03, 2015 08:15:13 PM Krzysztof Kozlowski wrote: > W dniu 03.08.2015 o 19:36, Bartlomiej Zolnierkiewicz pisze: > > On Monday, August 03, 2015 03:59:26 PM Viresh Kumar wrote: > >> On 03-08-15, 12:17, Bartlomiej Zolnierkiewicz wrote: > >>> > >>> Hi, > >>> > >>> On Saturday, August 01, 2015 04:47:21 PM Viresh Kumar wrote: > >>>> On 31-07-15, 20:49, Bartlomiej Zolnierkiewicz wrote: > >>>>> diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig > >>>>> index 659879a..bf6d596 100644 > >>>>> --- a/drivers/cpufreq/Kconfig > >>>>> +++ b/drivers/cpufreq/Kconfig > >>>>> @@ -191,6 +191,7 @@ config CPUFREQ_DT > >>>>> # if CPU_THERMAL is on and THERMAL=m, CPUFREQ_DT cannot be =y: > >>>>> depends on !CPU_THERMAL || THERMAL > >>>>> select PM_OPP > >>>>> + select EXYNOS_THERMAL if ARCH_EXYNOS > >>>>> help > >>>>> This adds a generic DT based cpufreq driver for frequency > >>>>> management. > >>>>> It supports both uniprocessor (UP) and symmetric > >>>>> multiprocessor (SMP) > >>>> > >>>> No, we shouldn't pollute generic Kconfig options with platform specific > >>>> stuff. > >>> > >>> The old code depended on this. You couldn't enable boost support > >>> without enabling thermal support (ARM_EXYNOS_CPU_FREQ_BOOST_SW > >>> config option selected EXYNOS_THERMAL). > >>> > >>>> Why don't you enable thermal in your .config? > >>> > >>> It is enabled in exynos_defconfig but without the above change it > >>> can disabled manually which is something that we don't want. > >> > >> You are not getting it. I am not asking you to not select thermal, but > >> to select it from within your architecture Kconfig option if you want. > > > > OK. Krzysztof/Kukjin do you agree with selecting EXYNOS_THERMAL > > from ARCH_EXYNOS in the platform code? > > I agree, with your explanation it seems good. Can you just add this > justification to the commit message? Updated patch below (I'm not resending the whole series as all other patches remain unchanged). > > > >> Over that, thermal is really an option, not a dependency. So, if > >> someone manually disables it, its his problem not yours :) > > > > I would really like it to be dependency not an option (+ I think > > that ideally it should be checked at runtime, IOW we should be > > checking from cpufreq-dt driver if the thermal support is enabled > > before enabling boost support). > > That would be the best. It is fine with me if you want to do this in > consecutive patches (after applying patch selecting/depending on it in > mach-exynos code). -8<--- >From 2595b5e6164a2d1b76626e14302b148b7af5e050 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 3 Aug 2015 15:49:06 +0200 Subject: [PATCH] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12 The new CPU clock type allows the use of generic CPUfreq driver. Switch Exynos4x12 to using generic cpufreq driver. Previously (when exynos-cpufreq driver was used with boost functionality) ARM_EXYNOS_CPU_FREQ_BOOST_SW config option (which enabled boost functionality) selected EXYNOS_THERMAL one. After switching Exynos4x12 platforms to use cpufreq-dt driver boost support is enabled in the cpufreq-dt driver itself (because there are turbo OPPs defined in the board's DTS file). However we still would like to allow enabling boost support only if thermal support is also enabled for Exynos platforms. To achieve this make ARCH_EXYNOS config option select THERMAL and EXYNOS_THERMAL ones. Please also note that the switch to use the generic cpufreq-dt driver fixes the minor issue present with the old code (support for 'boost' mode in the exynos-cpufreq driver was enabled for all supported SoCs even though 'boost' frequency was provided only for Exynos4x12 ones). Cc: Tomasz Figa Cc: Kukjin Kim Cc: Thomas Abraham Cc: Javier Martinez Canillas Signed-off-by: Bartlomiej Zolnierkiewicz --- arch/arm/mach-exynos/Kconfig | 2 ++ arch/arm/mach-exynos/exynos.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 81064cd..491914c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -25,6 +25,8 @@ menuconfig ARCH_EXYNOS select S5P_DEV_MFC
Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
On Monday, August 03, 2015 04:10:44 PM Viresh Kumar wrote: > On 03-08-15, 12:36, Bartlomiej Zolnierkiewicz wrote: > > I would really like it to be dependency not an option (+ I think > > that ideally it should be checked at runtime, IOW we should be > > checking from cpufreq-dt driver if the thermal support is enabled > > before enabling boost support). > > I don't think boost has any dependency on thermal support. Yeah, it > may be true for your platform but we can't force it. People might have > different algorithms to control boost modes, thermal is just one > option they may look at. For few, enabling boost may not be a thermal > issue, but power. So, they want to allow it only when they want, but > that wouldn't burn their chip. OK, I see your point (I have not thought about power being the boost limitation previously). > So, a platform can choose how it wants to have it. :) I'll re-do this patch. Thank you. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
On Monday, August 03, 2015 03:59:26 PM Viresh Kumar wrote: > On 03-08-15, 12:17, Bartlomiej Zolnierkiewicz wrote: > > > > Hi, > > > > On Saturday, August 01, 2015 04:47:21 PM Viresh Kumar wrote: > > > On 31-07-15, 20:49, Bartlomiej Zolnierkiewicz wrote: > > > > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig > > > > index 659879a..bf6d596 100644 > > > > --- a/drivers/cpufreq/Kconfig > > > > +++ b/drivers/cpufreq/Kconfig > > > > @@ -191,6 +191,7 @@ config CPUFREQ_DT > > > > # if CPU_THERMAL is on and THERMAL=m, CPUFREQ_DT cannot be =y: > > > > depends on !CPU_THERMAL || THERMAL > > > > select PM_OPP > > > > + select EXYNOS_THERMAL if ARCH_EXYNOS > > > > help > > > > This adds a generic DT based cpufreq driver for frequency > > > > management. > > > > It supports both uniprocessor (UP) and symmetric > > > > multiprocessor (SMP) > > > > > > No, we shouldn't pollute generic Kconfig options with platform specific > > > stuff. > > > > The old code depended on this. You couldn't enable boost support > > without enabling thermal support (ARM_EXYNOS_CPU_FREQ_BOOST_SW > > config option selected EXYNOS_THERMAL). > > > > > Why don't you enable thermal in your .config? > > > > It is enabled in exynos_defconfig but without the above change it > > can disabled manually which is something that we don't want. > > You are not getting it. I am not asking you to not select thermal, but > to select it from within your architecture Kconfig option if you want. OK. Krzysztof/Kukjin do you agree with selecting EXYNOS_THERMAL from ARCH_EXYNOS in the platform code? > Over that, thermal is really an option, not a dependency. So, if > someone manually disables it, its his problem not yours :) I would really like it to be dependency not an option (+ I think that ideally it should be checked at runtime, IOW we should be checking from cpufreq-dt driver if the thermal support is enabled before enabling boost support). Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
[ added Zhang & Eduardo to Cc: ]
Hi,
On Saturday, August 01, 2015 04:43:58 PM Krzysztof Kozlowski wrote:
> W dniu 01.08.2015 o 03:49, Bartlomiej Zolnierkiewicz pisze:
> > The new CPU clock type allows the use of generic CPUfreq driver.
> > Switch Exynos4x12 to using generic cpufreq driver.
> >
> > Also make CPUFREQ_DT config option select Exynos thermal driver
> > if Exynos platform support is enabled.
>
> Why? I think this wasn't in your previous patch.
Previous patch kept ARM_EXYNOS_CPU_FREQ_BOOST_SW config option
which selected EXYNOS_THERMAL. After recent changes (boost
support enabled in the cpufreq-dt driver when there are turbo
OPPs in board's dts file) ARM_EXYNOS_CPU_FREQ_BOOST_SW config
option become redundant and was removed. However we still
would like to allow enabling boost support only if thermal
support is also enabled for Exynos platforms.
[ There may be a better way to do this in the future (runtime
checking for thermal support being enabled) but currently
there seems to be no thermal infrastructure to allow this. ]
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> Best regards,
> Krzysztof
>
>
> >
> > Please also note that the switch to use the generic cpufreq-dt
> > driver fixes the minor issue present with the old code (support
> > for 'boost' mode in the exynos-cpufreq driver was enabled for
> > all supported SoCs even though 'boost' frequency was provided
> > only for Exynos4x12 ones).
> >
> > Cc: Tomasz Figa
> > Cc: Kukjin Kim
> > Cc: Thomas Abraham
> > Cc: Javier Martinez Canillas
> > Signed-off-by: Bartlomiej Zolnierkiewicz
> > ---
> > arch/arm/mach-exynos/exynos.c | 2 ++
> > drivers/cpufreq/Kconfig | 1 +
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
> > index 77ac021..1c47aee 100644
> > --- a/arch/arm/mach-exynos/exynos.c
> > +++ b/arch/arm/mach-exynos/exynos.c
> > @@ -227,6 +227,8 @@ static void __init exynos_init_irq(void)
> > static const struct of_device_id exynos_cpufreq_matches[] = {
> > { .compatible = "samsung,exynos3250", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
> > + { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
> > + { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
> > { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
> > { /* sentinel */ }
> > };
> > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
> > index 659879a..bf6d596 100644
> > --- a/drivers/cpufreq/Kconfig
> > +++ b/drivers/cpufreq/Kconfig
> > @@ -191,6 +191,7 @@ config CPUFREQ_DT
> > # if CPU_THERMAL is on and THERMAL=m, CPUFREQ_DT cannot be =y:
> > depends on !CPU_THERMAL || THERMAL
> > select PM_OPP
> > + select EXYNOS_THERMAL if ARCH_EXYNOS
> > help
> > This adds a generic DT based cpufreq driver for frequency management.
> > It supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
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Re: [PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
Hi, On Saturday, August 01, 2015 04:47:21 PM Viresh Kumar wrote: > On 31-07-15, 20:49, Bartlomiej Zolnierkiewicz wrote: > > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig > > index 659879a..bf6d596 100644 > > --- a/drivers/cpufreq/Kconfig > > +++ b/drivers/cpufreq/Kconfig > > @@ -191,6 +191,7 @@ config CPUFREQ_DT > > # if CPU_THERMAL is on and THERMAL=m, CPUFREQ_DT cannot be =y: > > depends on !CPU_THERMAL || THERMAL > > select PM_OPP > > + select EXYNOS_THERMAL if ARCH_EXYNOS > > help > > This adds a generic DT based cpufreq driver for frequency management. > > It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) > > No, we shouldn't pollute generic Kconfig options with platform specific stuff. The old code depended on this. You couldn't enable boost support without enabling thermal support (ARM_EXYNOS_CPU_FREQ_BOOST_SW config option selected EXYNOS_THERMAL). > Why don't you enable thermal in your .config? It is enabled in exynos_defconfig but without the above change it can disabled manually which is something that we don't want. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/7] cpufreq: opp: fix handling of turbo modes
On Thursday, July 30, 2015 11:37:27 PM Kukjin Kim wrote: > On 07/27/15 20:47, Bartlomiej Zolnierkiewicz wrote: > > On Monday, July 27, 2015 05:06:41 PM Viresh Kumar wrote: > >> On 27-07-15, 13:14, Bartlomiej Zolnierkiewicz wrote: > >>> Sorry but you don't seem to understand the issue. > >> > >> :) > >> > >> No, I did. I understand that if someone uses opp bindings today with > >> some entries as turbo OPPs, cpufreq will use them as normal > >> frequencies. And that may harm the board. > >> > >> BUT, opp-v2 code isn't ready to be used yet. And platforms should see > >> what all is implemented before trying to use them. > > > > OK. > > > >> All I was saying is, this isn't a FIX as we haven't introduced the > >> feature yet. Otherwise I had no issues with the patch. > > > > I will update the description for the next patchset revision. > > > Hi Bart, Hi, > When will you re-post v3? Because I have a plan to send a pull-request > to arm-soc until this weekend... I have just posted v3. I hope that it is not too late.. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/5] cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support
Exynos4x12 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Also once Exynos4x12 based platforms support have been removed
the shared exynos-cpufreq driver is no longer needed and can
be deleted.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/Kconfig.arm | 38 --
drivers/cpufreq/Makefile | 2 -
drivers/cpufreq/exynos-cpufreq.c | 236 ---
drivers/cpufreq/exynos-cpufreq.h | 72 ---
drivers/cpufreq/exynos4x12-cpufreq.c | 236 ---
5 files changed, 584 deletions(-)
delete mode 100644 drivers/cpufreq/exynos-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos-cpufreq.h
delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 9ab6388c1..8a24bd8 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -24,44 +24,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
This add the CPUfreq driver support for Versatile Express
big.LITTLE platforms using SPC for power management.
-
-config ARM_EXYNOS_CPUFREQ
- tristate "SAMSUNG EXYNOS CPUfreq Driver"
- depends on CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412 ||
SOC_EXYNOS5250
- depends on THERMAL
- help
- This adds the CPUFreq driver for Samsung EXYNOS platforms.
- Supported SoC versions are:
-Exynos4210, Exynos4212, Exynos4412, and Exynos5250.
-
- If in doubt, say N.
-
-config ARM_EXYNOS4X12_CPUFREQ
- bool "SAMSUNG EXYNOS4x12"
- depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
- depends on ARM_EXYNOS_CPUFREQ
- default y
- help
- This adds the CPUFreq driver for Samsung EXYNOS4X12
- SoC (EXYNOS4212 or EXYNOS4412).
-
- If in doubt, say N.
-
-config ARM_EXYNOS_CPU_FREQ_BOOST_SW
- bool "EXYNOS Frequency Overclocking - Software"
- depends on ARM_EXYNOS_CPUFREQ && THERMAL
- select CPU_FREQ_BOOST_SW
- select EXYNOS_THERMAL
- help
- This driver supports software managed overclocking (BOOST).
- It allows usage of special frequencies for Samsung Exynos
- processors if thermal conditions are appropriate.
-
- It requires, for safe operation, thermal framework with properly
- defined trip points.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
tristate "SAMSUNG EXYNOS5440"
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 6414958..bbc4a9f 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -53,8 +53,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += arm-exynos-cpufreq.o
-arm-exynos-cpufreq-y := exynos-cpufreq.o
-arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)+= exynos4x12-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)+= hisi-acpu-cpufreq.o
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
deleted file mode 100644
index 567a6ab..000
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - CPU frequency scaling support for EXYNOS series
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "exynos-cpufreq.h"
-
-static struct exynos_dvfs_info *exynos_info;
-static struct thermal_cooling_device *cdev;
-static struct regulator *arm_regulator;
-static unsigned int locking_frequency;
-
-static int exynos_cpufreq_get_index(unsigned int freq)
-{
- struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
- struct cpufreq_frequency_table *pos;
-
- cpufreq_for_each_entry(pos, freq_table)
- if (pos->frequency == freq)
- break;
-
- if (pos->frequency == CPUFREQ_TABLE_END)
- return -EINVAL;
-
- return pos - freq_table;
-}
-
-static int exynos_cpufreq_scale(
[PATCH v3 1/5] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by Thomas Abraham.
Cc: Tomasz Figa
Cc: Michael Turquette
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrocki
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/clk/samsung/clk-exynos4.c | 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 251f48d..7f370d3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data
e4210_armclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
+ { 150, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 140, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
+ { 130, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 120, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
+ { 110, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
+ { 100, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
+ { 90, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 80, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
+ { 70, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 60, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 50, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 40, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 30, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
+ { 20, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
+ { 0 },
+};
+
+#define E4412_CPU_DIV1(cores, hpm, copy) \
+ (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
+
+static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
+ { 150, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
+ { 140, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
+ { 130, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
+ { 120, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
+ { 110, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
+ { 100, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
+ { 90, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
+ { 80, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 70, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
+ { 60, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 50, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
+ { 40, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 30, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
+ { 20, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
+ { 0 },
+};
+
/* register exynos4 clocks */
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
@@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4x12_fixed_factor_clks,
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+ if (of_machine_is_compatible("samsung,exynos4412")) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
+ e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
+ }
}
samsung_clk_register_alias(ctx, exynos4_aliases,
--
1.9.1
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[PATCH v3 0/5] cpufreq: use generic cpufreq drivers for Exynos4x12 platform
Hi, This patch series removes the use of Exynos4x12 specific support from cpufreq-exynos driver and enables the use of cpufreq-dt driver for this platform. This patch series has been tested on Exynos4412 based Odroid-U3 and Trats2 boards. Depends on: - next-20150730 branch of linux-next kernel tree - "[PATCH V3 00/16] OPP: Add code to support operating-points-v2 bindings" (http://www.spinics.net/lists/arm-kernel/msg435408.html) Changes since v2 (http://thread.gmane.org/gmane.linux.kernel.samsung-soc/46653): - rebased on top of next-20150730 branch of linux-next kernel tree - ported over V3 of opp-v2 bindings support patch series - put cpu0 nodes in alphabetical order in dts files - added Reviewed-by tags from Javier and Krzysztof - added Acked-by tag from Sylwester Changes since v1 (http://thread.gmane.org/gmane.linux.kernel.samsung-soc/44361): - rebased on top of next-20150629 branch of linux-next kernel tree - rebased on top of Exynos5250 cpufreq-dt support patch series - fixed if-statement in exynos4_clk_init() (noticed by Tobias Jakobi) - ported over opp-v2 bindings (requested by Viresh Kumar) Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos4x12: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12 cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support cpufreq: remove no longer needed CPU_FREQ_BOOST_SW config option arch/arm/boot/dts/exynos4212.dtsi | 81 arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 + arch/arm/boot/dts/exynos4412-origen.dts | 4 + arch/arm/boot/dts/exynos4412-trats2.dts | 4 + arch/arm/boot/dts/exynos4412.dtsi | 83 + arch/arm/mach-exynos/exynos.c | 2 + drivers/clk/samsung/clk-exynos4.c | 50 + drivers/cpufreq/Kconfig | 5 +- drivers/cpufreq/Kconfig.arm | 38 drivers/cpufreq/Makefile| 2 - drivers/cpufreq/exynos-cpufreq.c| 236 drivers/cpufreq/exynos-cpufreq.h| 72 drivers/cpufreq/exynos4x12-cpufreq.c| 236 drivers/cpufreq/freq_table.c| 2 - 14 files changed, 229 insertions(+), 590 deletions(-) delete mode 100644 drivers/cpufreq/exynos-cpufreq.c delete mode 100644 drivers/cpufreq/exynos-cpufreq.h delete mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 5/5] cpufreq: remove no longer needed CPU_FREQ_BOOST_SW config option
Remove no longer needed CPU_FREQ_BOOST_SW config option.
As a result scaling_boost_freqs sysfs attribute is available
when cpufreq-dt driver is used and boost support is enabled.
Cc: Viresh Kumar
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Cc: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/cpufreq/Kconfig | 4
drivers/cpufreq/freq_table.c | 2 --
2 files changed, 6 deletions(-)
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index bf6d596..de00a52 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -21,10 +21,6 @@ if CPU_FREQ
config CPU_FREQ_GOV_COMMON
bool
-config CPU_FREQ_BOOST_SW
- bool
- depends on THERMAL
-
config CPU_FREQ_STAT
tristate "CPU frequency translation statistics"
default y
diff --git a/drivers/cpufreq/freq_table.c b/drivers/cpufreq/freq_table.c
index a8f1daf..4c5de5b 100644
--- a/drivers/cpufreq/freq_table.c
+++ b/drivers/cpufreq/freq_table.c
@@ -293,9 +293,7 @@ EXPORT_SYMBOL_GPL(cpufreq_freq_attr_scaling_boost_freqs);
struct freq_attr *cpufreq_generic_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
-#ifdef CONFIG_CPU_FREQ_BOOST_SW
&cpufreq_freq_attr_scaling_boost_freqs,
-#endif
NULL,
};
EXPORT_SYMBOL_GPL(cpufreq_generic_attr);
--
1.9.1
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[PATCH v3 3/5] ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4x12 to using generic cpufreq driver.
Also make CPUFREQ_DT config option select Exynos thermal driver
if Exynos platform support is enabled.
Please also note that the switch to use the generic cpufreq-dt
driver fixes the minor issue present with the old code (support
for 'boost' mode in the exynos-cpufreq driver was enabled for
all supported SoCs even though 'boost' frequency was provided
only for Exynos4x12 ones).
Cc: Tomasz Figa
Cc: Kukjin Kim
Cc: Thomas Abraham
Cc: Javier Martinez Canillas
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/mach-exynos/exynos.c | 2 ++
drivers/cpufreq/Kconfig | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 77ac021..1c47aee 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -227,6 +227,8 @@ static void __init exynos_init_irq(void)
static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos3250", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4210", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
{ /* sentinel */ }
};
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 659879a..bf6d596 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -191,6 +191,7 @@ config CPUFREQ_DT
# if CPU_THERMAL is on and THERMAL=m, CPUFREQ_DT cannot be =y:
depends on !CPU_THERMAL || THERMAL
select PM_OPP
+ select EXYNOS_THERMAL if ARCH_EXYNOS
help
This adds a generic DT based cpufreq driver for frequency management.
It supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
--
1.9.1
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[PATCH v3 2/5] ARM: dts: Exynos4x12: add CPU OPP and regulator supply property
For Exynos4x12 platforms, add CPU operating points (using
opp-v2 bindings) and CPU regulator supply properties for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Based on the earlier work by Thomas Abraham.
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Andreas Faerber
Cc: Thomas Abraham
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos4212.dtsi | 81
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 ++
arch/arm/boot/dts/exynos4412-origen.dts | 4 ++
arch/arm/boot/dts/exynos4412-trats2.dts | 4 ++
arch/arm/boot/dts/exynos4412.dtsi | 83 +
5 files changed, 176 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index d9c8efee..5389011 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -30,6 +30,9 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA00>;
+ clocks = <&clock CLK_ARM_CLK>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
cooling-min-level = <13>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
@@ -39,6 +42,84 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0xA01>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <20>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <90>;
+ clock-latency-ns = <20>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <925000>;
+ clock-latency-ns = <20>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <20>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <20>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <7>;
+ opp-microvolt = <987500>;
+ clock-latency-ns = <20>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <100>;
+ clock-latency-ns = <20>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <9>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <20>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <10>;
+ opp-microvolt = <1087500>;
+ clock-latency-ns = <20>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <11>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <20>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1187500>;
+ clock-latency-ns = <20>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <13>;
+ opp-microvolt = <125>;
+ clock-latency-ns = <20>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <14>;
+ opp-microvolt = <1287500>;
+ clock-latency-ns = <20>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <135
Re: [PATCH v2 3/7] cpufreq-dt: add turbo modes support
On Monday, July 27, 2015 05:03:40 PM Viresh Kumar wrote: > On 27-07-15, 13:01, Bartlomiej Zolnierkiewicz wrote: > > First of all, please don't be angry :).. We can discuss and get things > sorted out ... OK :) > > This change was in the original patch posted in April: > > https://lkml.org/lkml/2015/4/10/646 > > Yeah, and I already apologized for missing the request :) > > > your review from a month ago didn't contain this request: > > https://lkml.org/lkml/2015/6/22/667 > > Your patch inserted almost 116 lines and most of the stuff was around > adding new bindings to get things working with cpufreq-dt driver. > > And so I replied to the most important stuff, i.e. don't add new > bindings, we will sort it out with opp-v2. > > And frankly that wasn't the time where we could have discussed how > exactly we are going to use it. Ofcourse we should get it via DT, > platform data is just not required. > > So, me not NAK ing this approach was fine as it wasn't about keeping > this data in the platform data part. > > > and now (after nearly 4 months) you are telling me that > > I will say a month, as we discarded most of that patch recently :) > > > I should change this because you are planning to do some > > more changes in the future. > > Its not about me doing some changes. But the whole point of doing the > opp-v2 thing was to get rid of such platform data things.. > > Just that your work is competing with opp-v2 code :) > > > Could we please keep it as it is for now and change it > > later (after independent_clocks configuration will get > > ported to use device tree)? > > I thought we can get your work to a better shape, with all credit to > you. But if you have some dependency on this for 4.3, then I don't > mind killing this structure after you have polluted it a bit more :) Thank you. This is exactly the case here (I would like to get Exynos4x12 conversion to use cpufreq-dt + exynos-cpufreq removal in v4.3 if possible and adding new DT bindings will most likely slow down the process considerably). Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/7] cpufreq: opp: fix handling of turbo modes
On Monday, July 27, 2015 05:06:41 PM Viresh Kumar wrote: > On 27-07-15, 13:14, Bartlomiej Zolnierkiewicz wrote: > > Sorry but you don't seem to understand the issue. > > :) > > No, I did. I understand that if someone uses opp bindings today with > some entries as turbo OPPs, cpufreq will use them as normal > frequencies. And that may harm the board. > > BUT, opp-v2 code isn't ready to be used yet. And platforms should see > what all is implemented before trying to use them. OK. > All I was saying is, this isn't a FIX as we haven't introduced the > feature yet. Otherwise I had no issues with the patch. I will update the description for the next patchset revision. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/7] cpufreq: opp: fix handling of turbo modes
Hi, On Monday, July 27, 2015 04:05:21 PM Viresh Kumar wrote: > On 27-07-15, 12:24, Bartlomiej Zolnierkiewicz wrote: > > Have you read my explanation of the issue? > > > > With your OPP-v2 patches cpufreq-dt picks turbo frequencies and uses > > them as normal ones. > > > > (More at: http://www.spinics.net/lists/arm-kernel/msg430397.html) > > Yes I did. I understand that the turbo frequencies are not considered > as such by OPP/cpufreq core and it requires your changes to get it > working. Sorry but you don't seem to understand the issue. The problem is that without my patch and with your OPP-v2 patches turbo frequencies get picked by OPP/cpufreq core and then by cpufreq-dt. This happens without enabling any boost & thermal etc. support for turbo frequencies. > But its not an issue or bug we are fixing, the problem is that the > code for opp-v2 isn't complete yet and your patches is putting things > in place. So, we are still doing the bring up here and not fixing a > bug really. I consider the possibility to use turbo frequencies without explicitly enabling boost support to be a buggy behavior. While it is unlikely that somebody defines turbo frequencies in their dts file in the near future (except Exynos ones) it costs as nearly nothing to prevent such behavior now. Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 3/7] cpufreq-dt: add turbo modes support
Hi,
On Monday, July 27, 2015 02:07:54 PM Viresh Kumar wrote:
> On 09-07-15, 17:43, Bartlomiej Zolnierkiewicz wrote:
> > diff --git a/include/linux/cpufreq-dt.h b/include/linux/cpufreq-dt.h
> > index 0414009..483ca1b 100644
> > --- a/include/linux/cpufreq-dt.h
> > +++ b/include/linux/cpufreq-dt.h
> > @@ -17,6 +17,7 @@ struct cpufreq_dt_platform_data {
> > * clock.
> > */
> > bool independent_clocks;
> > + bool boost_supported;
> > };
>
> I am planning to kill this structure soon, don't add anything to it.
> We should be doing this based on DT.
This change was in the original patch posted in April:
https://lkml.org/lkml/2015/4/10/646
your review from a month ago didn't contain this request:
https://lkml.org/lkml/2015/6/22/667
and now (after nearly 4 months) you are telling me that
I should change this because you are planning to do some
more changes in the future.
Could we please keep it as it is for now and change it
later (after independent_clocks configuration will get
ported to use device tree)?
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
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Re: [PATCH v2 2/7] cpufreq: opp: fix handling of turbo modes
Hi, On Monday, July 27, 2015 02:05:31 PM Viresh Kumar wrote: > $subject is a bit wrong, we aren't fixing any issue here. We are > supporting a new feature and so it should be like: Have you read my explanation of the issue? With your OPP-v2 patches cpufreq-dt picks turbo frequencies and uses them as normal ones. (More at: http://www.spinics.net/lists/arm-kernel/msg430397.html) Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics > cpufreq: Mark boost frequencies based on OPP's turbo mode > > On 09-07-15, 17:43, Bartlomiej Zolnierkiewicz wrote: > > Turbo modes should be marked with CPUFREQ_BOOST_FREQ flag in > > the frequency table entry. > > > > Cc: Tomasz Figa > > Cc: Michael Turquette > > Cc: Javier Martinez Canillas > > Cc: Thomas Abraham > > Cc: Viresh Kumar > > Signed-off-by: Bartlomiej Zolnierkiewicz > > --- > > drivers/cpufreq/cpufreq_opp.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/cpufreq/cpufreq_opp.c b/drivers/cpufreq/cpufreq_opp.c > > index 773bcde..f0cf502 100644 > > --- a/drivers/cpufreq/cpufreq_opp.c > > +++ b/drivers/cpufreq/cpufreq_opp.c > > @@ -75,6 +75,8 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev, > > } > > freq_table[i].driver_data = i; > > freq_table[i].frequency = rate / 1000; > > + if (dev_pm_opp_get_turbo_mode_setting(opp) == true) > > + freq_table[i].flags |= CPUFREQ_BOOST_FREQ; > > } > > > > freq_table[i].driver_data = i; > > Rest look fine. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
