In big-endian CPU mode l2x0_saved_regs structure stores registers values in BE
format. In order to maintain BE CPU mode, these values and immediate constants
must be converted back to LE format before writing them to cache controller.
Signed-off-by: Dmitry Osipenko dig...@gmail.com
Acked-by: Russell King rmk+ker...@arm.linux.org.uk
---
Changelog:
V2: no code change, fixed patch numbering, extended mail recipients list
V3: added missed register reverse for 'ldr' instructions
arch/arm/mm/l2c-l2x0-resume.S | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
index fda415e4..ecb5b74 100644
--- a/arch/arm/mm/l2c-l2x0-resume.S
+++ b/arch/arm/mm/l2c-l2x0-resume.S
@@ -30,9 +30,19 @@ ENTRY(l2c310_early_resume)
teq r1, #0
reteq lr
+ @ Reverse for big-endian kernel
+ARM_BE8(revr2, r2)
+ARM_BE8(revr3, r3)
+ARM_BE8(revr4, r4)
+ARM_BE8(revr5, r5)
+ARM_BE8(revr6, r6)
+ARM_BE8(revr7, r7)
+ARM_BE8(revr8, r8)
+
@ The prefetch and power control registers are revision dependent
@ and can be written whether or not the L2 cache is enabled
ldr r0, [r1, #L2X0_CACHE_ID]
+ARM_BE8(revr0, r0)
and r0, r0, #L2X0_CACHE_ID_RTL_MASK
cmp r0, #L310_CACHE_ID_RTL_R2P0
strcs r7, [r1, #L310_PREFETCH_CTRL]
@@ -41,6 +51,7 @@ ENTRY(l2c310_early_resume)
@ Don't setup the L2 cache if it is already enabled
ldr r0, [r1, #L2X0_CTRL]
+ARM_BE8(revr0, r0)
tst r0, #L2X0_CTRL_EN
retne lr
@@ -51,6 +62,7 @@ ENTRY(l2c310_early_resume)
str r2, [r1, #L2X0_AUX_CTRL]
mov r9, #L2X0_CTRL_EN
+ARM_BE8(revr9, r9)
str r9, [r1, #L2X0_CTRL]
ret lr
ENDPROC(l2c310_early_resume)
--
2.3.2
--
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