Re: [PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
+ linux-samsung-soc mailing list.
On Wed, Dec 4, 2013 at 10:05 AM, Shirish S shir...@chromium.org wrote:
Hi Tomasz,
Thanks for the reivew, please see my replies inline.
On Fri, Nov 29, 2013 at 10:56 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Shirish,
Please see my comments inline.
On Monday 25 of November 2013 14:24:39 Shirish S wrote:
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S s.shir...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt | 31
drivers/gpu/drm/exynos/exynos_hdmi.c | 77
+++-
2 files changed, 104 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..6eeb333 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,30 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- hdmiphy-configs: following information about the hdmiphy config settings.
Is this node required or optional? If it's required, then it breaks
compatibility with already existing DTBs, which is not desirable.
Yes its an Optional-but-recommended node, and i have mentioned the same
in this document in next patch set(v9).
+ a) configN: configN specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
Node names should not have any semantic meaning for parsing code. I know
that there are already existing bindings which rely on presence of
particularly named nodes, but that's not right and new bindings should
not follow that.
I referred Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
for the implementation, am not clear with what you want me to do here, however
the requirement seems similar as pinctrl, can u kindly suggest any
existing newer
implementations to refer.
Also what do you need the label of each config node for?
Each label here is a different pixel clock and corresponding phy setting, and
it may vary from one pixel clock to other hence i need one for each config
node.
Generally from parsing perspective you shouldn't really care about node
names. All you seem to do in the driver is iterating over all specified
nodes and matching them with internal driver data using pixel clock
frequency.
True, that is what i intended to do.I think for the requirement
at hand, this should be fine.
+ pixel-clock specifies the pixel clock
Vendor-specific properties should have vendor prefix, so this one should
be called samsung,pixel-clock.
Agreed, updated in the next patch set(v9).
+ conifig-de-emphasis-level provides fine control of TMDS data
Typo: s/conifig/config
Also it should be called samsung,de-emphasis-level.
Agreed, updated in the next patch set(v9).
+ pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy@38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy@38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ config-clock-level provides fine control of TMDS data
samsung,clock-level
Agreed, updated in the next patch set(v9).
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
[snip]
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 32ce9a6..5f599e3 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
[snip]
+static int drm_hdmi_dt_parse_phy_conf(struct platform_device *pdev,
+ struct hdmi_context *hdata)
+{
+ struct device *dev = pdev-dev;
+ struct device_node *dev_np = dev-of_node;
+ struct device_node *phy_conf, *cfg_np;
+ int i, pixel_clock = 0;
+
+ /* Initialize with default config */
+ hdata-confs = hdmiphy_v14_configs;
+ hdata-nr_confs = ARRAY_SIZE(hdmiphy_v14_configs);
+
+ phy_conf = of_find_node_by_name(dev_np, hdmiphy-configs);
of_find_node_by_name() does not do what you need here. Please refer to
its implementation to learn why.
What you need here is of_get_child_by_name().
Agreed, updated in the next patch set(v9).
+ if (phy_conf == NULL) {
+ hdata-nr_confs = ARRAY_SIZE(hdmiphy_v14_configs);
+ DRM_ERROR(Did not find hdmiphy
[PATCH 2/4] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-arndale.dts | 74 ++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..6bc562c 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -475,6 +475,80 @@
vdd_osc-supply = ldo10_reg;
vdd_pll-supply = ldo8_reg;
vdd-supply = ldo8_reg;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = 2520;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config1: config1 {
+ samsung,pixel-clock = 2700;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config2: config2 {
+ samsung,pixel-clock = 27027000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config3: config3 {
+ samsung,pixel-clock = 3600;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config4: config4 {
+ samsung,pixel-clock = 4000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config5: config5 {
+ samsung,pixel-clock = 6500;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config6: config6 {
+ samsung,pixel-clock = 74176000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config7: config7 {
+ samsung,pixel-clock = 7425;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config8: config8 {
+ samsung,pixel-clock = 8350;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config9: config9 {
+ samsung,pixel-clock = 10650;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config10: config10 {
+ samsung,pixel-clock = 10800;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config11: config11 {
+ samsung,pixel-clock = 14625;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config12: config12 {
+ samsung,pixel-clock = 14850;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ };
};
regulators {
--
1.7.9.5
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[PATCH 4/4] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S s.shir...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt | 34
drivers/gpu/drm/exynos/exynos_hdmi.c | 89
2 files changed, 105 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..0766e6e 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -13,6 +13,31 @@ Required properties:
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+Optional-but-recommended properties:
+- hdmiphy-configs: following information about the hdmiphy config settings.
+ a) configN: configN specifies the phy configuration settings,
+ where 'N' denotes the number of configuration, since every
+ pixel clock can have its unique configuration.
+ samsung,pixel-clock specifies the pixel clock
+ samsung,de-emphasis-level provides fine control of TMDS data
+pre emphasis, below shown is example for
+ data de-emphasis register at address 0x145D0040.
+ hdmiphy@38[16] for bits[3:0] permitted values are in
+ the range of 760 mVdiff to 1400 mVdiff at 20mVdiff
+ increments for every LSB
+ hdmiphy@38[16] for bits[7:4] permitted values are in
+ the range of 0dB to -7.45dB at increments of -0.45dB
+ for every LSB.
+ samsung,clock-level provides fine control of TMDS data
+ amplitude for each channel,
+ for example if 0x145D005C is the address of clock level
+ register then,
+ hdmiphy@38[23] for bits [1:0] permitted values are in
+ the range of 0 mVdiff 60 mVdiff for each channel at
+ increments 20 mVdiff of amplitude levels for every LSB,
+ hdmiphy@38[23] for bits [7:3] permitted values are in
+ the range of 790 and 1430 mV at 20mV increments for
+ every LSB.
Example:
hdmi {
@@ -20,4 +45,13 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ hdmiphy-configs {
+ config0: config0 {
+ samsung,pixel-clock = 2520;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+
+ /* ... */
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a0e10ae..2fa0074 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -200,6 +200,9 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
@@ -259,7 +262,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
+static struct hdmiphy_config hdmiphy_v14_configs[] = {
{
.pixel_clock = 2520,
.conf = {
@@ -771,20 +774,10 @@ static struct edid *hdmi_get_edid(void *ctx, struct
drm_connector *connector)
static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
{
- const struct hdmiphy_config *confs;
- int count, i;
-
- if (hdata-type == HDMI_TYPE13) {
- confs = hdmiphy_v13_configs;
- count = ARRAY_SIZE(hdmiphy_v13_configs);
- } else if (hdata-type == HDMI_TYPE14) {
- confs = hdmiphy_v14_configs;
- count = ARRAY_SIZE(hdmiphy_v14_configs);
- } else
- return -EINVAL;
+ int i;
- for (i = 0; i count; i++)
- if (confs[i].pixel_clock == pixel_clock)
+ for (i = 0; i hdata-nr_confs; i++)
+ if (hdata-confs[i].pixel_clock == pixel_clock)
return i;
DRM_DEBUG_KMS(Could not find phy config for %d\n, pixel_clock);
@@ -1363,10 +1356,7 @@ static void hdmiphy_conf_apply(struct hdmi_context
*hdata)
return;
}
- if (hdata-type == HDMI_TYPE13)
- hdmiphy_data = hdmiphy_v13_configs[i].conf;
- else
- hdmiphy_data = hdmiphy_v14_configs[i].conf;
+ hdmiphy_data = hdata-confs[i
[PATCH 0/4] Add dt support for exynos hdmiphy settings
For various revisions of a chipset if the signal pattern is changed for every revision, then the phy setting need to be updated correspondingly by measuring the signal. For getting correct signals the clock level and data de-emphasis levels needs to be adjusted. Since only these 2 values matter,we can move the same to dt, wherein we can have different dt files for every revision. This is an initial patchset towards achieving the same for exynos 5250 and can be later extended to future chipsets. V2: replaced moving of entire phy config structure with only required and justifiable conf registers. V3: Incorporated Mark Rutland's comments. V4: Rebased and included cros5250-common.dtsi. V5: removed nr-configs feild and also the constraint of having the exact number of configs in the dt file as in the driver, the programmer can add only the pixel clock that needs to be updated. V6: V7: removed nr-configs form the dtsi files. V8: Fixed build error V9: rebased and incorporated Tomasz comments. Shirish S (4): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings ARM: exynos: dts: cros5250: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 34 arch/arm/boot/dts/cros5250-common.dtsi | 74 arch/arm/boot/dts/exynos5250-arndale.dts | 74 arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 drivers/gpu/drm/exynos/exynos_hdmi.c | 89 5 files changed, 327 insertions(+), 18 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 74 +
1 file changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..10da02f 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,80 @@
hdmi {
hpd-gpio = gpx3 7 0;
+ hdmiphy-configs {
+ /*
+ * Eye diagram test passed for:
+ * Data de-emphasis: -0.7dB Data Level: 880mV
+ * i.e., 0010 0110 = 0x26
+ * and Clock level of 515mV and diff 1030mV
+ * i.e., 0x66
+ */
+ config0: config0 {
+ samsung,pixel-clock = 2520;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config1: config1 {
+ samsung,pixel-clock = 2700;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config2: config2 {
+ samsung,pixel-clock = 27027000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config3: config3 {
+ samsung,pixel-clock = 3600;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config4: config4 {
+ samsung,pixel-clock = 4000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config5: config5 {
+ samsung,pixel-clock = 6500;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config6: config6 {
+ samsung,pixel-clock = 74176000;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config7: config7 {
+ samsung,pixel-clock = 7425;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config8: config8 {
+ samsung,pixel-clock = 8350;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config9: config9 {
+ samsung,pixel-clock = 10650;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config10: config10 {
+ samsung,pixel-clock = 10800;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config11: config11 {
+ samsung,pixel-clock = 14625;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ config12: config12 {
+ samsung,pixel-clock = 14850;
+ samsung,de-emphasis-level = /bits/ 8 0x26;
+ samsung,clock-level = /bits/ 8 0x66;
+ };
+ };
};
codec@1100 {
--
1.7.9.5
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[PATCH 0/3] Add dt support for exynos hdmiphy settings
For various revision of chipset if the signal pattern is changed for every board, then the phy setting need to be updated correspondingly by measuring the signal. With the hdmiphy settings fixed in the driver the only way currently is to either add a new structure or add compile time option. To avoid this, we can move the same to dt, wherin we can have different dt files for every revision. This patchset can be considered as an initiative towards achieving the same for exynos 5250 and can be later extended to future chipsets. Also this patchset moves the entire structure to dt file as-is in the driver and hence we can find all the hex values, which are not logically explained similar to driver. Shirish S (3): ARM: dts: smdk5250: Add hdmi phy settings ARM: dts: arndale: Add hdmi phy settings drm: exynos: hdmi: Add dt support for hdmiphy settings .../devicetree/bindings/video/exynos_hdmi.txt | 18 +- arch/arm/boot/dts/exynos5250-arndale.dts | 120 arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++- 4 files changed, 320 insertions(+), 129 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.
Signed-off-by: Shirish S s.shir...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt | 18 +-
drivers/gpu/drm/exynos/exynos_hdmi.c | 191 +++-
2 files changed, 80 insertions(+), 129 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy-confs: following information about the hdmiphy conf settings.
+a) nr-confs specifies the number of pixel clocks supported.
+ b) confX: confX specifies the phy configuration settings,
+ clock-frequency specifies the pixel clock
+ conf specifies the setting for the corresponding pixel clock
Example:
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ hdmiphy-confs {
+ nr-confs = 1;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
};
+struct hdmiphy_config {
+ int pixel_clock;
+ u8 conf[32];
+};
+
struct hdmi_context {
struct device *dev;
struct drm_device *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
struct hdmi_resources res;
+ struct hdmiphy_config *confs;
+ int nr_confs;
+
int hpd_gpio;
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
/* list of phy config settings */
static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[]
= {
},
};
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
- {
- .pixel_clock = 2520,
- .conf = {
- 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
- 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
- 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
- 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
- },
- },
- {
- .pixel_clock = 3600,
- .conf = {
- 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
- },
- },
- {
- .pixel_clock = 4000,
- .conf = {
- 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
- 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
- 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
- 0x54
[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
hdmi {
hpd-gpio = gpx3 7 2;
+ hdmiphy-confs {
+ nr-confs = 13;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf1: conf1 {
+ clock-frequency = 2700;
+ conf = /bits/ 8
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf2: conf2 {
+ clock-frequency = 27027000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf3: conf3 {
+ clock-frequency = 3600;
+ conf = /bits/ 8
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf4: conf4 {
+ clock-frequency = 4000;
+ conf = /bits/ 8
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf5: conf5 {
+ clock-frequency = 6500;
+ conf = /bits/ 8
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf6: conf6 {
+ clock-frequency = 74176000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf7: conf7 {
+ clock-frequency = 7425;
+ conf = /bits/ 8
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf8: conf8
[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.
Signed-off-by: Shirish S s.shir...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 120 +
1 file changed, 120 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
hdmi {
hpd-gpio = gpx3 7 0;
+ hdmiphy-confs {
+ nr-confs = 13;
+ conf0: conf0 {
+ clock-frequency = 2520;
+ conf = /bits/ 8
+ 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+ 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf1: conf1 {
+ clock-frequency = 2700;
+ conf = /bits/ 8
+ 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+ 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+ 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf2: conf2 {
+ clock-frequency = 27027000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+ 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf3: conf3 {
+ clock-frequency = 3600;
+ conf = /bits/ 8
+ 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf4: conf4 {
+ clock-frequency = 4000;
+ conf = /bits/ 8
+ 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+ 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf5: conf5 {
+ clock-frequency = 6500;
+ conf = /bits/ 8
+ 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+ 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+ 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf6: conf6 {
+ clock-frequency = 74176000;
+ conf = /bits/ 8
+ 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+ 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+ 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+ ;
+ };
+ conf7: conf7 {
+ clock-frequency = 7425;
+ conf = /bits/ 8
+ 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+ 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+ 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+ 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+ ;
+ };
+ conf8: conf8
[PATCH] ARM: dts: Correct the pin configuration for eMMC
This patch corrects the pin function value of sd4_bus8 from 3
to 4.
This is verified on origen board for testing eMMC on
dw_mci controller.
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 8e6115a..099cec7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -661,7 +661,7 @@
sd4_bus8: sd4-bus-width8 {
samsung,pins = gpk1-3, gpk1-4, gpk1-5, gpk1-6;
- samsung,pin-function = 3;
+ samsung,pin-function = 4;
samsung,pin-pud = 4;
samsung,pin-drv = 3;
};
--
1.8.0
--
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[PATCH] ARM: dts: exynos4x12-pinctrl: Correct pin configuration of SD 4
This patch corrects the pin function value of sd4_bus8 from 3
to 4.
This is verified on origen board for testing eMMC on
dw_mci controller.
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 8e6115a..099cec7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -661,7 +661,7 @@
sd4_bus8: sd4-bus-width8 {
samsung,pins = gpk1-3, gpk1-4, gpk1-5, gpk1-6;
- samsung,pin-function = 3;
+ samsung,pin-function = 4;
samsung,pin-pud = 4;
samsung,pin-drv = 3;
};
--
1.8.0
--
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Re: Re: [PATCH] ARM: dts: Correct the pin configuration for eMMC
Done!
--- Original Message ---
Sender : Tomasz Figat.f...@samsung.com Junior Software Engineer/SRPOL-Linux
Platform (SSD)/Samsung Electronics
Date : Feb 11, 2013 15:20 (GMT+05:30)
Title : Re: [PATCH] ARM: dts: Correct the pin configuration for eMMC
Hi Shirish,
On Monday 11 of February 2013 05:01:28 Shirish S wrote:
This patch corrects the pin function value of sd4_bus8 from 3
to 4.
This is verified on origen board for testing eMMC on
dw_mci controller.
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
---
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 8e6115a..099cec7
100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -661,7 +661,7 @@
sd4_bus8: sd4-bus-width8 {
samsung,pins = gpk1-3, gpk1-4, gpk1-5, gpk1-6;
- samsung,pin-function = 3;
+ samsung,pin-function = 4;
samsung,pin-pud = 4;
samsung,pin-drv = 3;
};
IMHO name of the patch is a bit misleading, as on many Exynos4x12-based
boards sdhci-s3c is used for eMMC. I think following would be better:
ARM: dts: exynos4x12-pinctrl: Correct pin configuration of SD 4
Best regards,
--
Tomasz Figa
Samsung Poland RD Center
SW Solution Development, Linux Platform
pnbsp;/ppnbsp;/p
