[PATCH] mmc: dw_mmc: exynos: Add support for exynos7

[Yuvaraj Kumar C D]

From: Abhilash Kesavan 

The Exynos7 has a DWMMC controller (v2.70a) which is different from
prior versions. This patch adds new compatible strings for exynos7.
This patch also fixes the CLKSEL register offset on exynos7.

Signed-off-by: Abhilash Kesavan 
Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 +
 drivers/mmc/host/dw_mmc-exynos.c   |   91 +---
 2 files changed, 82 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6cd3525..ee4fc05 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -18,6 +18,10 @@ Required Properties:
  specific extensions.
- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
  specific extensions.
+   - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
+ specific extensions.
+   - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
+ specific extensions having an SMU.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 0fbc53a..509365c 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -25,6 +25,7 @@
 #define NUM_PINS(x)(x + 2)
 
 #define SDMMC_CLKSEL   0x09C
+#define SDMMC_CLKSEL64 0x0A8
 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)(((x) & 7) << 0)
 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)   (((x) & 7) << 24)
@@ -65,6 +66,8 @@ enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS5250,
DW_MCI_TYPE_EXYNOS5420,
DW_MCI_TYPE_EXYNOS5420_SMU,
+   DW_MCI_TYPE_EXYNOS7,
+   DW_MCI_TYPE_EXYNOS7_SMU,
 };
 
 /* Exynos implementation specific driver private data */
@@ -95,6 +98,12 @@ static struct dw_mci_exynos_compatible {
}, {
.compatible = "samsung,exynos5420-dw-mshc-smu",
.ctrl_type  = DW_MCI_TYPE_EXYNOS5420_SMU,
+   }, {
+   .compatible = "samsung,exynos7-dw-mshc",
+   .ctrl_type  = DW_MCI_TYPE_EXYNOS7,
+   }, {
+   .compatible = "samsung,exynos7-dw-mshc-smu",
+   .ctrl_type  = DW_MCI_TYPE_EXYNOS7_SMU,
},
 };
 
@@ -102,7 +111,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv = host->priv;
 
-   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
+   priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
mci_writel(host, MPSBEGIN0, 0);
mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
@@ -153,11 +163,22 @@ static int dw_mci_exynos_resume(struct device *dev)
 static int dw_mci_exynos_resume_noirq(struct device *dev)
 {
struct dw_mci *host = dev_get_drvdata(dev);
+   struct dw_mci_exynos_priv_data *priv = host->priv;
u32 clksel;
 
-   clksel = mci_readl(host, CLKSEL);
-   if (clksel & SDMMC_CLKSEL_WAKEUP_INT)
-   mci_writel(host, CLKSEL, clksel);
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
+   priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+   clksel = mci_readl(host, CLKSEL64);
+   else
+   clksel = mci_readl(host, CLKSEL);
+
+   if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
+   priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
+   mci_writel(host, CLKSEL64, clksel);
+   else
+   mci_writel(host, CLKSEL, clksel);
+   }
 
return 0;
 }
@@ -169,6 +190,7 @@ static int dw_mci_exynos_resume_noirq(struct device *dev)
 
 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
 {
+   struct dw_mci_exynos_priv_data *priv = host->priv;
/*
 * Exynos4412 and Exynos5250 extends the use of CMD register with the
 * use of bit 29 (which is reserved on standard MSHC controllers) for
@@ -176,8 +198,14 @@ static void dw_mci_exynos_prepare_command(struct dw_mci 
*host, u32 *cmdr)
 * HOLD register should be bypassed in case there is no phase shift
 * applied on CMD/DATA that is sent to the card.
 */
-   if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
-   *cmdr |= SDMMC_CMD_USE_HOLD_REG;
+

Re: [PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

[Yuvaraj Kumar]

On Wed, Aug 27, 2014 at 9:19 PM, Doug Anderson  wrote:
> Jaehoon,
>
> On Tue, Aug 26, 2014 at 9:47 PM, Jaehoon Chung  wrote:
>> Doug,
>>
>> On 08/27/2014 01:14 PM, Doug Anderson wrote:
>>> Jaehoon,
>>>
>>> On Tue, Aug 26, 2014 at 8:48 PM, Jaehoon Chung  
>>> wrote:
>>>> Hi, Doug,
>>>>
>>>> On 08/26/2014 12:25 AM, Doug Anderson wrote:
>>>>> Jaehoon,
>>>>>
>>>>> On Mon, Aug 25, 2014 at 1:50 AM, Jaehoon Chung  
>>>>> wrote:
>>>>>> On 08/25/2014 05:13 PM, Ulf Hansson wrote:
>>>>>>> On 22 August 2014 20:27, Sonny Rao  wrote:
>>>>>>>> On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson  
>>>>>>>> wrote:
>>>>>>>>> On 22 August 2014 15:47, Yuvaraj Kumar C D  
>>>>>>>>> wrote:
>>>>>>>>>> Exynos 5250 and 5420 based boards uses built-in CD# line for card
>>>>>>>>>> detection.But unfortunately CD# line is on the same voltage rails
>>>>>>>>>> as of I/O voltage rails. When we cut off vqmmc,the consequent card
>>>>>>>>>> detection will break in these boards.
>>>>>>
>>>>>> I didn't know that use CD# line for card detect.
>>>>>> And if CD# voltage rails and I/O voltage rail are same voltage, it 
>>>>>> doesn't make sense.
>>>>>> Which card is used with same voltages? (eMMC? SD? SDIO?)
>>>>>>
>>>>>> Well, I have checked Exynos5250 and 5420, but it looks like not same 
>>>>>> rails.
>>>>>
>>>>> I'm not sure I totally understood what you said.  In my manual I have
>>>>> a table titled "Table 2-1 Exynos 5420 Pin List".  Look in this table
>>>>> for XMMC2CDN and XMMC2DATA_0.  Look to the right of the table and
>>>>> you'll see the power domain.  For both it shows VDDQ_MMC2.  If that
>>>>> doesn't mean that the two are in the same voltage domain then I don't
>>>>> know what does.  Can you point to any examples where they have
>>>>> different voltage domains?
>>>> I think you're mis-understanding for it.
>>>> Right, It's described at exynos5420, but it's not connected.
>>>
>>> "It's not connected".  What do you mean?  If I were to guess I'd say
>>> that on some particular board you're looking at they don't happen to
>>> use the "CD" pin for card detect.  If this is what you mean, it
>>> doesn't help me.  exynos5420-peach-pit does use the CD pin for card
>>> detect.  You can look at the DTS file and confirm it.
>>
>> I didn't know how exynos5420-peach-pit's circuit is configured.
>> But i guess that almost all exynos5 boards are configured with the similar 
>> circuit.
>>
>> At Almost all Exynos5 board, CD-pin is used, but not included in Same power 
>> domain.
>> (CD-pin is external card-detect pin. - like XEINT_# pin)
>> You mentioned CD# and DATA# lines is used the same power domain, right?
>> In Circuit (not exynos5420-peach-pit), DATA# line and CMD/CLK(vqmmc) is same 
>> power supply, and vdd is used other power supply.
>> Not use the CD# pin, used the XEINT_# pin.
>> So i think we don't need to consider the CD#.
>> If exynos5420-peach-pit board is used the CD#-pin, then our discussion can 
>> be changed.
>
> Maybe on your board you have CD connected to a "gpx" line.  ...but not
> mine.  The guys who designed our hardware followed the SMDK5420
> reference schematics which connect the SD card slot card detect to
> "gpc2_2", which is the card detect pin.
>
> See "arch/arm/boot/dts/exynos5420-smdk5420.dts", specifically noting
> the lack of a GPIO card detect and the inclusion of "sd2_cd"
>
> mmc@1222 {
>   status = "okay";
>   card-detect-delay = <200>;
>   samsung,dw-mshc-ciu-div = <3>;
>   samsung,dw-mshc-sdr-timing = <2 3>;
>   samsung,dw-mshc-ddr-timing = <1 2>;
>   pinctrl-names = "default";
>   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
>   bus-width = <4>;
>   cap-sd-highspeed;
> };
>
> See "arch/arm/boot/dts/exynos5420-peach-pit.dts" too:
>
> &mmc_2 {
>   status = "okay";
>   num-slots = <1>;
>   cap-sd-highspeed;
>   card-detect-delay = &

Re: [PATCH 1/1] regulator: max77802: set opmode to normal if off is read from hw

[Yuvaraj Kumar]

Tested-by: Yuvaraj Kumar CD 

On Tue, Aug 26, 2014 at 5:07 PM, Javier Martinez Canillas
 wrote:
> The max77802 driver reads the default operating mode (opmode)
> set for regulators when enabled from the hardware registers.
>
> But if a regulator is disabled and the system warm restarted,
> the hardware reports OFF as the opmode so the regulator is
> not enabled. Default to operating mode NORMAL if OFF is read
> from the hardware register.
>
> Reported-by: Yuvaraj Cd 
> Signed-off-by: Javier Martinez Canillas 
> ---
>
> This patch fixes the issue reported in https://lkml.org/lkml/2014/8/25/69
>
>  drivers/regulator/max77802.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c
> index ad1caa9..967e109 100644
> --- a/drivers/regulator/max77802.c
> +++ b/drivers/regulator/max77802.c
> @@ -540,7 +540,17 @@ static int max77802_pmic_probe(struct platform_device 
> *pdev)
> config.of_node = pdata->regulators[i].of_node;
>
> ret = regmap_read(iodev->regmap, regulators[i].enable_reg, 
> &val);
> -   max77802->opmode[id] = val >> shift & MAX77802_OPMODE_MASK;
> +   val = val >> shift & MAX77802_OPMODE_MASK;
> +
> +   /*
> +* If the regulator is disabled and the system warm rebooted,
> +* the hardware reports OFF as the regulator operating mode.
> +* Default to operating mode NORMAL in that case.
> +*/
> +   if (val == MAX77802_OPMODE_OFF)
> +   max77802->opmode[id] = MAX77802_OPMODE_NORMAL;
> +   else
> +   max77802->opmode[id] = val;
>
> rdev = devm_regulator_register(&pdev->dev,
>®ulators[i], &config);
> --
> 2.0.1
>
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[PATCH V2 3/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

[Yuvaraj Kumar C D]

Exynos 5250 and 5420 based boards uses built-in CD# line for card
detection.But unfortunately CD# line is on the same voltage rails
as of I/O voltage rails. When we cut off vqmmc,the consequent card
detection will break in these boards.

These hosts (obviously) need to keep vqmmc (and thus vmmc) on all the
time, even when the mmc core tells them to power off. However, one
problem is that these cards won't properly handle mmc_power_cycle().
That's needed to handle error cases when trying to switch voltages
(see 0797e5f mmc:core: Fixup signal voltage switch).

This patch adds a new MMC_POWER_OFF_HARD mode when it's doing a power
cycle.  This mode differs from the normal MMC_POWER_OFF mode in that
the mmc core will promise to power the slot back on before it expects
the host to detect card insertion or removal.

Also if we let alone the vqmmc turned on when vmmc turned off, the
card could have half way powered and this can damage the card. So
this patch adds a check so that, if the board used the built-in
card detection mechanism i.e through CDETECT, it will not turned
down vqmmc and vmmc both.

Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Doug Anderson 
---
changes from v1:
1.added a new MMC_POWER_OFF_HARD mode as per Doug Anderson's suggestion.
2.added dw_mci_exynos_post_init() to perform the host specific post 
  initialisation.
3.added a new flag MMC_CAP2_CD_NEEDS_POWER for host->caps2.

 drivers/mmc/core/core.c  |   16 ++--
 drivers/mmc/core/debugfs.c   |3 +++
 drivers/mmc/host/dw_mmc-exynos.c |   12 
 drivers/mmc/host/dw_mmc.c|   25 +
 drivers/mmc/host/dw_mmc.h|2 ++
 include/linux/mmc/host.h |2 ++
 6 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 68f5f4b..79ced36 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1564,9 +1564,9 @@ void mmc_power_up(struct mmc_host *host, u32 ocr)
mmc_host_clk_release(host);
 }
 
-void mmc_power_off(struct mmc_host *host)
+void _mmc_power_off(struct mmc_host *host, unsigned char power_mode)
 {
-   if (host->ios.power_mode == MMC_POWER_OFF)
+   if (host->ios.power_mode == power_mode)
return;
 
mmc_host_clk_hold(host);
@@ -1579,6 +1579,7 @@ void mmc_power_off(struct mmc_host *host)
host->ios.chip_select = MMC_CS_DONTCARE;
}
host->ios.power_mode = MMC_POWER_OFF;
+   host->ios.power_mode = power_mode;
host->ios.bus_width = MMC_BUS_WIDTH_1;
host->ios.timing = MMC_TIMING_LEGACY;
mmc_set_ios(host);
@@ -1593,9 +1594,20 @@ void mmc_power_off(struct mmc_host *host)
mmc_host_clk_release(host);
 }
 
+void mmc_power_off(struct mmc_host *host)
+{
+   _mmc_power_off(host, MMC_POWER_OFF);
+}
+
 void mmc_power_cycle(struct mmc_host *host, u32 ocr)
 {
mmc_power_off(host);
+   /* If host normally ignores MMC_POWER_OFF, tell it to pay attention */
+   if (host->caps2 & MMC_CAP2_CD_NEEDS_POWER)
+   _mmc_power_off(host, MMC_POWER_OFF_HARD);
+   else
+   _mmc_power_off(host, MMC_POWER_OFF);
+
/* Wait at least 1 ms according to SD spec */
mmc_delay(1);
mmc_power_up(host, ocr);
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index 91eb162..3d9c5a3 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -108,6 +108,9 @@ static int mmc_ios_show(struct seq_file *s, void *data)
case MMC_POWER_ON:
str = "on";
break;
+   case MMC_POWER_OFF_HARD:
+   str = "hard off";
+   break;
default:
str = "invalid";
break;
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 0fbc53a..4e26049 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "dw_mmc.h"
@@ -217,6 +218,16 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, 
struct mmc_ios *ios)
}
 }
 
+static void dw_mci_exynos_post_init(struct dw_mci_slot *slot)
+{
+   struct dw_mci_board *brd = slot->host->pdata;
+   struct mmc_host *mmc = slot->mmc;
+
+   if (!(brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) &&
+   IS_ERR_VALUE(mmc_gpio_get_cd(mmc)))
+   mmc->caps2 |= MMC_CAP2_CD_NEEDS_POWER;
+}
+
 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv;
@@ -399,6 +410,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
.prepare_command= dw_mci_exynos_prepare_command,
.set_ios= dw_mci_exynos_set_io

[PATCH V2 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

[Yuvaraj Kumar C D]

This patch makes use of mmc_regulator_get_supply() to handle
the vmmc and vqmmc regulators.Also it moves the code handling
the these regulators to dw_mci_set_ios().It turned on the vmmc
and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
during MMC_POWER_OFF.

Signed-off-by: Yuvaraj Kumar C D 
---
changes from v1:
1.Used mmc_regulator_set_ocr() instead of regulator_enable() for vmmc.
2.Turned on vmmc and vqmmc during MMC_POWER_UP.
3. Removed the flags DW_MMC_CARD_POWERED and DW_MMC_IO_POWERED which
   added during the initial version of this patch.
4. Added error message, if it failed to turn on regulator's.

 drivers/mmc/host/dw_mmc.c  |   72 +---
 include/linux/mmc/dw_mmc.h |2 +-
 2 files changed, 36 insertions(+), 38 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 7f227e9..aadb0d6 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -936,6 +936,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
struct dw_mci_slot *slot = mmc_priv(mmc);
const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
u32 regs;
+   int ret;
 
switch (ios->bus_width) {
case MMC_BUS_WIDTH_4:
@@ -974,12 +975,38 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
 
switch (ios->power_mode) {
case MMC_POWER_UP:
+   if (!IS_ERR(mmc->supply.vmmc)) {
+   ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
+   ios->vdd);
+   if (ret) {
+   dev_err(slot->host->dev,
+   "failed to enable vmmc regulator\n");
+   /*return, if failed turn on vmmc*/
+   return;
+   }
+   }
+   if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
+   ret = regulator_enable(mmc->supply.vqmmc);
+   if (ret < 0)
+   dev_err(slot->host->dev,
+   "failed to enable vqmmc regulator\n");
+   else
+   slot->host->vqmmc_enabled = true;
+   }
set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
regs = mci_readl(slot->host, PWREN);
regs |= (1 << slot->id);
mci_writel(slot->host, PWREN, regs);
break;
case MMC_POWER_OFF:
+   if (!IS_ERR(mmc->supply.vmmc))
+   mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
+
+   if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
+   regulator_disable(mmc->supply.vqmmc);
+   slot->host->vqmmc_enabled = false;
+   }
+
regs = mci_readl(slot->host, PWREN);
regs &= ~(1 << slot->id);
mci_writel(slot->host, PWREN, regs);
@@ -2110,7 +2137,13 @@ static int dw_mci_init_slot(struct dw_mci *host, 
unsigned int id)
mmc->f_max = freq[1];
}
 
-   mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+   /*if there are external regulators, get them*/
+   ret = mmc_regulator_get_supply(mmc);
+   if (ret == -EPROBE_DEFER)
+   goto err_setup_bus;
+
+   if (!mmc->ocr_avail)
+   mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 
if (host->pdata->caps)
mmc->caps = host->pdata->caps;
@@ -2176,7 +2209,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned 
int id)
 
 err_setup_bus:
mmc_free_host(mmc);
-   return -EINVAL;
+   return ret;
 }
 
 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
@@ -2469,24 +2502,6 @@ int dw_mci_probe(struct dw_mci *host)
}
}
 
-   host->vmmc = devm_regulator_get_optional(host->dev, "vmmc");
-   if (IS_ERR(host->vmmc)) {
-   ret = PTR_ERR(host->vmmc);
-   if (ret == -EPROBE_DEFER)
-   goto err_clk_ciu;
-
-   dev_info(host->dev, "no vmmc regulator found: %d\n", ret);
-   host->vmmc = NULL;
-   } else {
-   ret = regulator_enable(host->vmmc);
-   if (ret) {
-   if (ret != -EPROBE_DEFER)
-   dev_err(host->dev,
-   "regulator_enable fail: %d\n", ret);
-   goto err_clk_ciu;
-   }
-   }
-
h

[PATCH V2 0/3] Adding UHS support for dw_mmc driver

[Yuvaraj Kumar C D]

This series adds UHS support for dw_mmc driver.
Patch[1] reworks the handling of vmmc and vqmmc regulators by mmc core 
regulator API's.

Patch[2] was taken from chrome tree originally developed by Doug Anderson.
Comments recieved for this patch to remove extra state machine for CMD11
handling is dropped since it's very much required to set the 
SDMMC_CMD_VOLT_SWITCH bit(28) for the proper working of clock update after 
the first VOLT_SWITCH interrupt occurs during the voltage switch scenario.
Though its not mentioned in Synopsys data book, its essential to complete
the voltage switchingi sequence.  

Patch[3] handles the case where in some boards uses built-in CD line for
card detection and connected to a same voltage domain as of the IO rails.
This version adds the changes for the concerned expressed by Doug Anderson
in prevoius version.

Doug Anderson (1):
 [2].mmc: dw_mmc: Support voltage changes

Yuvaraj Kumar C D (2):
 [1]. mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators
 [3]. mmc: dw_mmc: Dont cut off vqmmc and vmmc

 drivers/mmc/core/core.c  |   16 ++-
 drivers/mmc/core/debugfs.c   |3 +
 drivers/mmc/host/dw_mmc-exynos.c |   12 ++
 drivers/mmc/host/dw_mmc.c|  231 ++
 drivers/mmc/host/dw_mmc.h|7 +-
 include/linux/mmc/dw_mmc.h   |4 +-
 include/linux/mmc/host.h |2 +
 7 files changed, 225 insertions(+), 50 deletions(-)

-- 
1.7.10.4

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[PATCH V2 2/3] mmc: dw_mmc: Support voltage changes

[Yuvaraj Kumar C D]

From: Doug Anderson 

For UHS cards we need the ability to switch voltages from 3.3V to
1.8V.  Add support to the dw_mmc driver to handle this.  Note that
dw_mmc needs a little bit of extra code since the interface needs a
special bit programmed to the CMD register while CMD11 is progressing.
This means adding a few extra states to the state machine to track.

Signed-off-by: Doug Anderson 
Signed-off-by: Yuvaraj Kumar C D 
---
changes since v1:
1. Added error message and return error in case of 
regulator_set_voltage() fail.
2. changed  dw_mci_cmd_interrupt(host,pending | SDMMC_INT_CMD_DONE)
   to dw_mci_cmd_interrupt(host,pending).
3. Removed unnecessary comments.

 drivers/mmc/host/dw_mmc.c  |  134 +---
 drivers/mmc/host/dw_mmc.h  |5 +-
 include/linux/mmc/dw_mmc.h |2 +
 3 files changed, 131 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index aadb0d6..f20b4b8 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -234,10 +235,13 @@ err:
 }
 #endif /* defined(CONFIG_DEBUG_FS) */
 
+static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
+
 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command 
*cmd)
 {
struct mmc_data *data;
struct dw_mci_slot *slot = mmc_priv(mmc);
+   struct dw_mci *host = slot->host;
const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
u32 cmdr;
cmd->error = -EINPROGRESS;
@@ -253,6 +257,31 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, 
struct mmc_command *cmd)
else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 
+   if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+   u32 clk_en_a;
+
+   /* Special bit makes CMD11 not die */
+   cmdr |= SDMMC_CMD_VOLT_SWITCH;
+
+   /* Change state to continue to handle CMD11 weirdness */
+   WARN_ON(slot->host->state != STATE_SENDING_CMD);
+   slot->host->state = STATE_SENDING_CMD11;
+
+   /*
+* We need to disable clock stop while doing voltage switch
+* according to Voltage Switch Normal Scenario.
+* It's assumed that by the next time the CLKENA is updated
+* (when we set the clock next) that the voltage change will
+* be over, so we don't bother setting any bits to synchronize
+* with dw_mci_setup_bus().
+*/
+   clk_en_a = mci_readl(host, CLKENA);
+   clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
+   mci_writel(host, CLKENA, clk_en_a);
+   mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
+SDMMC_CMD_PRV_DAT_WAIT, 0);
+   }
+
if (cmd->flags & MMC_RSP_PRESENT) {
/* We expect a response, so set this bit */
cmdr |= SDMMC_CMD_RESP_EXP;
@@ -775,11 +804,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, 
bool force_clkinit)
unsigned int clock = slot->clock;
u32 div;
u32 clk_en_a;
+   u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
+
+   /* We must continue to set bit 28 in CMD until the change is complete */
+   if (host->state == STATE_WAITING_CMD11_DONE)
+   sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
 
if (!clock) {
mci_writel(host, CLKENA, 0);
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
} else if (clock != host->current_speed || force_clkinit) {
div = host->bus_hz / clock;
if (host->bus_hz % clock && host->bus_hz > clock)
@@ -803,15 +836,13 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, 
bool force_clkinit)
mci_writel(host, CLKSRC, 0);
 
/* inform CIU */
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 
/* set clock to desired speed */
mci_writel(host, CLKDIV, div);
 
/* inform CIU */
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 
/* enable clock; only low power if no SDIO */
clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
@@ -820,8 +851,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool 
force_clkinit)
   

Re: [PATCH 3/3] mmc: dw_mmc: Support voltage changes

[Yuvaraj Kumar]

On Mon, Jul 7, 2014 at 10:53 AM, Seungwon Jeon  wrote:
> On Fri, July 04, 2014, Seungwon Jeon wrote:
>> On Tue, July 01, 2014. Yuvaraj Kumar wrote:
>> > On Fri, Jun 27, 2014 at 4:48 PM, Seungwon Jeon  
>> > wrote:
>> > > Hi Yuvaraj,
>> > >
>> > > On Fri, June 27, 2014, Yuvaraj Kumar wrote:
>> > >> On Thu, Jun 26, 2014 at 10:20 PM, Doug Anderson  
>> > >> wrote:
>> > >> > Seungwon,
>> > >> >
>> > >> > On Thu, Jun 26, 2014 at 3:41 AM, Seungwon Jeon  
>> > >> > wrote:
>> > >> >> On Thu, June 26, 2014, Doug Anderson wrote:
>> > >> >>> Seungwon,
>> > >> >>>
>> > >> >>> On Wed, Jun 25, 2014 at 6:08 AM, Seungwon Jeon 
>> > >> >>>  wrote:
>> > >> >>> > On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
>> > >> >>> >> Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
>> > >> >>> >>
>> > >> >>> >> From: Doug Anderson 
>> > >> >>> >>
>> > >> >>> >> For UHS cards we need the ability to switch voltages from 3.3V to
>> > >> >>> >> 1.8V.  Add support to the dw_mmc driver to handle this.  Note 
>> > >> >>> >> that
>> > >> >>> >> dw_mmc needs a little bit of extra code since the interface 
>> > >> >>> >> needs a
>> > >> >>> >> special bit programmed to the CMD register while CMD11 is 
>> > >> >>> >> progressing.
>> > >> >>> >> This means adding a few extra states to the state machine to 
>> > >> >>> >> track.
>> > >> >>> >
>> > >> >>> > Overall new additional states makes it complicated.
>> > >> >>> > Can we do that in other way?
>> > >> >>>
>> > >> >>> That was the best I was able to figure out when I thought this
>> > >> >>> through.  If you have ideas for doing it another way I'd imagine 
>> > >> >>> that
>> > >> >>> Yuvaraj would be happy to take your feedback.
>> > >> >> Let's clean up SDMMC_CMD_VOLT_SWITCH.
>> > >> >> In turn, we may remove state-handling simply.
>> > >> >>
>> > >> >>>
>> > >> >>>
>> > >> >>> >> Signed-off-by: Doug Anderson 
>> > >> >>> >> Signed-off-by: Yuvaraj Kumar C D 
>> > >> >>> >>
>> > >> >>> >> ---
>> > >> >>> >>  drivers/mmc/host/dw_mmc.c  |  145 
>> > >> >>> >> +---
>> > >> >>> >>  drivers/mmc/host/dw_mmc.h  |5 +-
>> > >> >>> >>  include/linux/mmc/dw_mmc.h |2 +
>> > >> >>> >>  3 files changed, 142 insertions(+), 10 deletions(-)
>> > >> >>> >>
>> > >> >>> >> diff --git a/drivers/mmc/host/dw_mmc.c 
>> > >> >>> >> b/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> index e034bce..38eb548 100644
>> > >> >>> >> --- a/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> +++ b/drivers/mmc/host/dw_mmc.c
>> > >> >>> >> @@ -29,6 +29,7 @@
>> > >> >>> >>  #include 
>> > >> >>> >>  #include 
>> > >> >>> >>  #include 
>> > >> >>> >> +#include 
>> > >> >>> >>  #include 
>> > >> >>> >>  #include 
>> > >> >>> >>  #include 
>> > >> >>> >> @@ -235,10 +236,13 @@ err:
>> > >> >>> >>  }
>> > >> >>> >>  #endif /* defined(CONFIG_DEBUG_FS) */
>> > >> >>> >>
>> > >> >>> >> +static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 
>> > >> >>> >> arg);
>> > >> >>> >> +
>> > >> >>> >>  static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct 
>> > &

Re: [PATCH 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

[Yuvaraj Kumar]

On Thu, Jun 26, 2014 at 9:48 PM, Doug Anderson  wrote:
> Yuvaraj,
>
> On Thu, Jun 26, 2014 at 4:21 AM, Yuvaraj Kumar  wrote:
>> Doug
>>
>> On Tue, Jun 24, 2014 at 11:30 PM, Doug Anderson  
>> wrote:
>>> Yuvaraj,
>>>
>>> On Mon, Jun 23, 2014 at 3:45 AM, Yuvaraj Kumar C D  
>>> wrote:
>>>> This patch makes use of mmc_regulator_get_supply() to handle
>>>> the vmmc and vqmmc regulators.Also it moves the code handling
>>>> the these regulators to dw_mci_set_ios().It turned on the vmmc
>>>> and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
>>>> during MMC_POWER_OFF.
>>>>
>>>> Signed-off-by: Yuvaraj Kumar C D 
>>>> ---
>>>>  drivers/mmc/host/dw_mmc.c |   71 
>>>> ++---
>>>>  drivers/mmc/host/dw_mmc.h |2 ++
>>>>  2 files changed, 36 insertions(+), 37 deletions(-)
>>>
>>> Perhaps you could CC me on the whole series for the next version since
>>> I was involved in privately reviewing previous versions?
>> It was just accidental missing you in the CC .Surely i will add you in
>> CC for next versions.
>>>
>>> Overall caveat for my review is that I'm nowhere near an SD/MMC expert.
>>>
>>>
>>>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>>>> index 1ac227c..f5cabce 100644
>>>> --- a/drivers/mmc/host/dw_mmc.c
>>>> +++ b/drivers/mmc/host/dw_mmc.c
>>>> @@ -937,6 +937,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, 
>>>> struct mmc_ios *ios)
>>>> struct dw_mci_slot *slot = mmc_priv(mmc);
>>>> const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
>>>> u32 regs;
>>>> +   int ret;
>>>>
>>>> switch (ios->bus_width) {
>>>> case MMC_BUS_WIDTH_4:
>>>> @@ -975,16 +976,41 @@ static void dw_mci_set_ios(struct mmc_host *mmc, 
>>>> struct mmc_ios *ios)
>>>>
>>>> switch (ios->power_mode) {
>>>> case MMC_POWER_UP:
>>>> +   if ((!IS_ERR(mmc->supply.vmmc)) &&
>>>> +   !test_bit(DW_MMC_CARD_POWERED, 
>>>> &slot->flags)) {
>>>> +   ret = regulator_enable(mmc->supply.vmmc);
>>>> +   if (!ret)
>>>> +   set_bit(DW_MMC_CARD_POWERED, &slot->flags);
>>>> +   }
>>>
>>> As per below, I'm not sure why you'd want to turn on vqmmc and vmmc at
>>> different times.
>> As you can see people's have different opinion on this.When i had a
>> look at the other drivers in the subsystem which does in the same flow
>> as above.However i will change in the next version.
>
> Given my self proclaimed lack of SD/MMC knowledge, if others have a
> good reason for doing them separate then you should do it that way.
> So far I haven't heard that reason but I certainly could be wrong.
>
>
>>>> @@ -225,6 +225,8 @@ struct dw_mci_slot {
>>>> unsigned long   flags;
>>>>  #define DW_MMC_CARD_PRESENT0
>>>>  #define DW_MMC_CARD_NEED_INIT  1
>>>> +#define DW_MMC_CARD_POWERED2
>>>> +#define DW_MMC_IO_POWERED  3
>>>
>>> I don't really think you should have two bits here.  From my
>>> understanding of SD cards there should be very little reason to have
>>> vqmmc and vmmc not powered at the same time.
>> I think if i can use mmc_regulator_set_ocr(), we don't need additional
>> flag.But for tps65090 mmc_regulator_get_ocr() and
>> mmc_regulator_set_ocr() is failing as its a fixed-regulator.
>
> Can you explain more about what's failing?  It sure looks like mmc
> core is supposed to handle this given comments below
>
> /*
> * If we're using a fixed/static regulator, don't call
> * regulator_set_voltage; it would fail.
> */
tps65090 driver does not register through fixed regulator framework.It
uses normal regulator framework and supports only
enable/disable/is_enabled callbacks.Also it lacks certain callbacks
for list_voltage, get_voltage ,set_voltage etc.
[2.306476] dwmmc_exynos 1222.mmc: Failed getting OCR mask: -22
[2.393403] dwmmc_exynos 1222.mmc: could not set regulator OCR (-22)
For the above reason,regulator framework treats fet4 as unused
regulator and disables the vmmc regulator.
> voltage = regulator_get_voltage(supply);
>
> if (!regulator_can_change_voltage(supply))
>   min_uV = max_uV = voltage;
>
>
> -Doug
--
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Re: [PATCH 3/3] mmc: dw_mmc: Support voltage changes

[Yuvaraj Kumar]

On Thu, Jun 26, 2014 at 10:20 PM, Doug Anderson  wrote:
> Seungwon,
>
> On Thu, Jun 26, 2014 at 3:41 AM, Seungwon Jeon  wrote:
>> On Thu, June 26, 2014, Doug Anderson wrote:
>>> Seungwon,
>>>
>>> On Wed, Jun 25, 2014 at 6:08 AM, Seungwon Jeon  wrote:
>>> > On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
>>> >> Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
>>> >>
>>> >> From: Doug Anderson 
>>> >>
>>> >> For UHS cards we need the ability to switch voltages from 3.3V to
>>> >> 1.8V.  Add support to the dw_mmc driver to handle this.  Note that
>>> >> dw_mmc needs a little bit of extra code since the interface needs a
>>> >> special bit programmed to the CMD register while CMD11 is progressing.
>>> >> This means adding a few extra states to the state machine to track.
>>> >
>>> > Overall new additional states makes it complicated.
>>> > Can we do that in other way?
>>>
>>> That was the best I was able to figure out when I thought this
>>> through.  If you have ideas for doing it another way I'd imagine that
>>> Yuvaraj would be happy to take your feedback.
>> Let's clean up SDMMC_CMD_VOLT_SWITCH.
>> In turn, we may remove state-handling simply.
>>
>>>
>>>
>>> >> Signed-off-by: Doug Anderson 
>>> >> Signed-off-by: Yuvaraj Kumar C D 
>>> >>
>>> >> ---
>>> >>  drivers/mmc/host/dw_mmc.c  |  145 
>>> >> +---
>>> >>  drivers/mmc/host/dw_mmc.h  |5 +-
>>> >>  include/linux/mmc/dw_mmc.h |2 +
>>> >>  3 files changed, 142 insertions(+), 10 deletions(-)
>>> >>
>>> >> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>>> >> index e034bce..38eb548 100644
>>> >> --- a/drivers/mmc/host/dw_mmc.c
>>> >> +++ b/drivers/mmc/host/dw_mmc.c
>>> >> @@ -29,6 +29,7 @@
>>> >>  #include 
>>> >>  #include 
>>> >>  #include 
>>> >> +#include 
>>> >>  #include 
>>> >>  #include 
>>> >>  #include 
>>> >> @@ -235,10 +236,13 @@ err:
>>> >>  }
>>> >>  #endif /* defined(CONFIG_DEBUG_FS) */
>>> >>
>>> >> +static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
>>> >> +
>>> >>  static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct 
>>> >> mmc_command *cmd)
>>> >>  {
>>> >>   struct mmc_data *data;
>>> >>   struct dw_mci_slot *slot = mmc_priv(mmc);
>>> >> + struct dw_mci *host = slot->host;
>>> >>   const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
>>> >>   u32 cmdr;
>>> >>   cmd->error = -EINPROGRESS;
>>> >> @@ -254,6 +258,32 @@ static u32 dw_mci_prepare_command(struct mmc_host 
>>> >> *mmc, struct mmc_command
>>> *cmd)
>>> >>   else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
>>> >>   cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
>>> >>
>>> >> + if (cmd->opcode == SD_SWITCH_VOLTAGE) {
>>> >> + u32 clk_en_a;
>>> >> +
>>> >> + /* Special bit makes CMD11 not die */
>>> >> + cmdr |= SDMMC_CMD_VOLT_SWITCH;
>>> >> +
>>> >> + /* Change state to continue to handle CMD11 weirdness */
>>> >> + WARN_ON(slot->host->state != STATE_SENDING_CMD);
>>> >> + slot->host->state = STATE_SENDING_CMD11;
>>> >> +
>>> >> + /*
>>> >> +  * We need to disable clock stop while doing voltage switch
>>> >> +  * according to 7.4.1.2 Voltage Switch Normal Scenario.
>>> >> +  *
>>> >> +  * It's assumed that by the next time the CLKENA is updated
>>> >> +  * (when we set the clock next) that the voltage change 
>>> >> will
>>> >> +  * be over, so we don't bother setting any bits to 
>>> >> synchronize
>>> >> +  * with dw_mci_setup_bus().
>>> >> +  */
>>> >> 

Re: [PATCH 3/3] mmc: dw_mmc: Support voltage changes

[Yuvaraj Kumar]

On Wed, Jun 25, 2014 at 11:16 PM, Doug Anderson  wrote:
> Seungwon,
>
> On Wed, Jun 25, 2014 at 6:08 AM, Seungwon Jeon  wrote:
>> On Mon, June 23, 2014, Yuvaraj Kumar C D wrote:
>>> Subject: [PATCH 3/3] mmc: dw_mmc: Support voltage changes
>>>
>>> From: Doug Anderson 
>>>
>>> For UHS cards we need the ability to switch voltages from 3.3V to
>>> 1.8V.  Add support to the dw_mmc driver to handle this.  Note that
>>> dw_mmc needs a little bit of extra code since the interface needs a
>>> special bit programmed to the CMD register while CMD11 is progressing.
>>> This means adding a few extra states to the state machine to track.
>>
>> Overall new additional states makes it complicated.
>> Can we do that in other way?
>
> That was the best I was able to figure out when I thought this
> through.  If you have ideas for doing it another way I'd imagine that
> Yuvaraj would be happy to take your feedback.
Yes.
>
>
>>> Signed-off-by: Doug Anderson 
>>> Signed-off-by: Yuvaraj Kumar C D 
>>>
>>> ---
>>>  drivers/mmc/host/dw_mmc.c  |  145 
>>> +---
>>>  drivers/mmc/host/dw_mmc.h  |5 +-
>>>  include/linux/mmc/dw_mmc.h |2 +
>>>  3 files changed, 142 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>>> index e034bce..38eb548 100644
>>> --- a/drivers/mmc/host/dw_mmc.c
>>> +++ b/drivers/mmc/host/dw_mmc.c
>>> @@ -29,6 +29,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -235,10 +236,13 @@ err:
>>>  }
>>>  #endif /* defined(CONFIG_DEBUG_FS) */
>>>
>>> +static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
>>> +
>>>  static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command 
>>> *cmd)
>>>  {
>>>   struct mmc_data *data;
>>>   struct dw_mci_slot *slot = mmc_priv(mmc);
>>> + struct dw_mci *host = slot->host;
>>>   const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
>>>   u32 cmdr;
>>>   cmd->error = -EINPROGRESS;
>>> @@ -254,6 +258,32 @@ static u32 dw_mci_prepare_command(struct mmc_host 
>>> *mmc, struct mmc_command *cmd)
>>>   else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
>>>   cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
>>>
>>> + if (cmd->opcode == SD_SWITCH_VOLTAGE) {
>>> + u32 clk_en_a;
>>> +
>>> + /* Special bit makes CMD11 not die */
>>> + cmdr |= SDMMC_CMD_VOLT_SWITCH;
>>> +
>>> + /* Change state to continue to handle CMD11 weirdness */
>>> + WARN_ON(slot->host->state != STATE_SENDING_CMD);
>>> + slot->host->state = STATE_SENDING_CMD11;
>>> +
>>> + /*
>>> +  * We need to disable clock stop while doing voltage switch
>>> +  * according to 7.4.1.2 Voltage Switch Normal Scenario.
>>> +  *
>>> +  * It's assumed that by the next time the CLKENA is updated
>>> +  * (when we set the clock next) that the voltage change will
>>> +  * be over, so we don't bother setting any bits to synchronize
>>> +  * with dw_mci_setup_bus().
>>> +  */
>>> + clk_en_a = mci_readl(host, CLKENA);
>>> + clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
>>> + mci_writel(host, CLKENA, clk_en_a);
>>> + mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
>>> +  SDMMC_CMD_PRV_DAT_WAIT, 0);
>> dw_mci_disable_low_power() can be used here.
>
> Ah.  I guess we don't have that locally anymore.  Locally we have variants on:
> * https://patchwork.kernel.org/patch/3070311/
> * https://patchwork.kernel.org/patch/3070251/
> * https://patchwork.kernel.org/patch/3070221/
>
> ...which removed that function.  ...but I guess upstream never picked
> up those patches, huh?  Looking back it looks like you had some
> feedback and it needed another spin but somehow fell off my plate.  :(
>
> Maybe this is something Yuvaraj would like to pick up?
ok.
>
>>
>>> + }
>>> +
>>>   if (cmd->flags & MMC_RSP_PRESENT) {
>&g

Re: [PATCH 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

[Yuvaraj Kumar]

Doug

On Tue, Jun 24, 2014 at 11:30 PM, Doug Anderson  wrote:
> Yuvaraj,
>
> On Mon, Jun 23, 2014 at 3:45 AM, Yuvaraj Kumar C D  
> wrote:
>> This patch makes use of mmc_regulator_get_supply() to handle
>> the vmmc and vqmmc regulators.Also it moves the code handling
>> the these regulators to dw_mci_set_ios().It turned on the vmmc
>> and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
>> during MMC_POWER_OFF.
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  drivers/mmc/host/dw_mmc.c |   71 
>> ++---
>>  drivers/mmc/host/dw_mmc.h |2 ++
>>  2 files changed, 36 insertions(+), 37 deletions(-)
>
> Perhaps you could CC me on the whole series for the next version since
> I was involved in privately reviewing previous versions?
It was just accidental missing you in the CC .Surely i will add you in
CC for next versions.
>
> Overall caveat for my review is that I'm nowhere near an SD/MMC expert.
>
>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 1ac227c..f5cabce 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -937,6 +937,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
>> mmc_ios *ios)
>> struct dw_mci_slot *slot = mmc_priv(mmc);
>> const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
>> u32 regs;
>> +   int ret;
>>
>> switch (ios->bus_width) {
>> case MMC_BUS_WIDTH_4:
>> @@ -975,16 +976,41 @@ static void dw_mci_set_ios(struct mmc_host *mmc, 
>> struct mmc_ios *ios)
>>
>> switch (ios->power_mode) {
>> case MMC_POWER_UP:
>> +   if ((!IS_ERR(mmc->supply.vmmc)) &&
>> +   !test_bit(DW_MMC_CARD_POWERED, 
>> &slot->flags)) {
>> +   ret = regulator_enable(mmc->supply.vmmc);
>> +   if (!ret)
>> +   set_bit(DW_MMC_CARD_POWERED, &slot->flags);
>> +   }
>
> As per below, I'm not sure why you'd want to turn on vqmmc and vmmc at
> different times.
As you can see people's have different opinion on this.When i had a
look at the other drivers in the subsystem which does in the same flow
as above.However i will change in the next version.
>
> Also: if you fail to turn on either of the regulators it feels like
> you should print a pretty nasty error message since your device will
> almost certainly not work.
Yes. I will add a error message.
>
>
>> set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
>> regs = mci_readl(slot->host, PWREN);
>> regs |= (1 << slot->id);
>> mci_writel(slot->host, PWREN, regs);
>> break;
>> case MMC_POWER_OFF:
>> +   if (!IS_ERR(mmc->supply.vqmmc) &&
>> +   test_bit(DW_MMC_IO_POWERED, &slot->flags)) {
>> +   ret = regulator_disable(mmc->supply.vqmmc);
>> +   if (!ret)
>> +   clear_bit(DW_MMC_IO_POWERED, &slot->flags);
>> +   }
>> +   if (!IS_ERR(mmc->supply.vmmc) &&
>> +   test_bit(DW_MMC_CARD_POWERED, &slot->flags)) 
>> {
>> +   ret = regulator_disable(mmc->supply.vmmc);
>> +   if (!ret)
>> +   clear_bit(DW_MMC_CARD_POWERED, &slot->flags);
>> +   }
>> regs = mci_readl(slot->host, PWREN);
>> regs &= ~(1 << slot->id);
>> mci_writel(slot->host, PWREN, regs);
>> break;
>> +   case MMC_POWER_ON:
>> +   if (!IS_ERR(mmc->supply.vqmmc) &&
>> +   !test_bit(DW_MMC_IO_POWERED, &slot->flags)) {
>> +   ret = regulator_enable(mmc->supply.vqmmc);
>> +   if (!ret)
>> +   set_bit(DW_MMC_IO_POWERED, &slot->flags);
>> +   }
>> default:
>> break;
>> }
>> @@ -2067,7 +2093,13 @@ static int dw_mci_init_slot(struct dw_mci *host, 
>> unsigned int id)
>> mmc->f_max = freq[1];
>> }
>>
>> -   mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
>> +

[PATCH] ARM: dts: update mmc node with hs-200 mode

[Yuvaraj Kumar C D]

This patch updates hs-200 device tree property from
caps2-mmc-hs200-1.8v to mmc-hs200-1.8v for peach-pit
and peach-pi boards.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5420-peach-pit.dts |2 +-
 arch/arm/boot/dts/exynos5800-peach-pi.dts  |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts 
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 1cf9df0..056a6fa 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -186,7 +186,7 @@
status = "okay";
num-slots = <1>;
broken-cd;
-   caps2-mmc-hs200-1_8v;
+   mmc-hs200-1_8v;
supports-highspeed;
non-removable;
card-detect-delay = <200>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts 
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 2c2c137..bb3ee76 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -171,7 +171,7 @@
status = "okay";
num-slots = <1>;
broken-cd;
-   caps2-mmc-hs200-1_8v;
+   mmc-hs200-1_8v;
supports-highspeed;
non-removable;
card-detect-delay = <200>;
-- 
1.7.10.4

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[PATCH 1/3] mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators

[Yuvaraj Kumar C D]

This patch makes use of mmc_regulator_get_supply() to handle
the vmmc and vqmmc regulators.Also it moves the code handling
the these regulators to dw_mci_set_ios().It turned on the vmmc
and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
during MMC_POWER_OFF.

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |   71 ++---
 drivers/mmc/host/dw_mmc.h |2 ++
 2 files changed, 36 insertions(+), 37 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..f5cabce 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -937,6 +937,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
struct dw_mci_slot *slot = mmc_priv(mmc);
const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
u32 regs;
+   int ret;
 
switch (ios->bus_width) {
case MMC_BUS_WIDTH_4:
@@ -975,16 +976,41 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
 
switch (ios->power_mode) {
case MMC_POWER_UP:
+   if ((!IS_ERR(mmc->supply.vmmc)) &&
+   !test_bit(DW_MMC_CARD_POWERED, &slot->flags)) {
+   ret = regulator_enable(mmc->supply.vmmc);
+   if (!ret)
+   set_bit(DW_MMC_CARD_POWERED, &slot->flags);
+   }
set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
regs = mci_readl(slot->host, PWREN);
regs |= (1 << slot->id);
mci_writel(slot->host, PWREN, regs);
break;
case MMC_POWER_OFF:
+   if (!IS_ERR(mmc->supply.vqmmc) &&
+   test_bit(DW_MMC_IO_POWERED, &slot->flags)) {
+   ret = regulator_disable(mmc->supply.vqmmc);
+   if (!ret)
+   clear_bit(DW_MMC_IO_POWERED, &slot->flags);
+   }
+   if (!IS_ERR(mmc->supply.vmmc) &&
+   test_bit(DW_MMC_CARD_POWERED, &slot->flags)) {
+   ret = regulator_disable(mmc->supply.vmmc);
+   if (!ret)
+   clear_bit(DW_MMC_CARD_POWERED, &slot->flags);
+   }
regs = mci_readl(slot->host, PWREN);
regs &= ~(1 << slot->id);
mci_writel(slot->host, PWREN, regs);
break;
+   case MMC_POWER_ON:
+   if (!IS_ERR(mmc->supply.vqmmc) &&
+   !test_bit(DW_MMC_IO_POWERED, &slot->flags)) {
+   ret = regulator_enable(mmc->supply.vqmmc);
+   if (!ret)
+   set_bit(DW_MMC_IO_POWERED, &slot->flags);
+   }
default:
break;
}
@@ -2067,7 +2093,13 @@ static int dw_mci_init_slot(struct dw_mci *host, 
unsigned int id)
mmc->f_max = freq[1];
}
 
-   mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+   /*if there are external regulators, get them*/
+   ret = mmc_regulator_get_supply(mmc);
+   if (ret == -EPROBE_DEFER)
+   goto err_setup_bus;
+
+   if (!mmc->ocr_avail)
+   mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 
if (host->pdata->caps)
mmc->caps = host->pdata->caps;
@@ -2133,7 +2165,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned 
int id)
 
 err_setup_bus:
mmc_free_host(mmc);
-   return -EINVAL;
+   return ret;
 }
 
 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
@@ -2375,24 +2407,6 @@ int dw_mci_probe(struct dw_mci *host)
}
}
 
-   host->vmmc = devm_regulator_get_optional(host->dev, "vmmc");
-   if (IS_ERR(host->vmmc)) {
-   ret = PTR_ERR(host->vmmc);
-   if (ret == -EPROBE_DEFER)
-   goto err_clk_ciu;
-
-   dev_info(host->dev, "no vmmc regulator found: %d\n", ret);
-   host->vmmc = NULL;
-   } else {
-   ret = regulator_enable(host->vmmc);
-   if (ret) {
-   if (ret != -EPROBE_DEFER)
-   dev_err(host->dev,
-   "regulator_enable fail: %d\n", ret);
-   goto err_clk_ciu;
-   }
-   }
-
host->quirks = host->pdata->quirks;
 
spin_lock_init(&host->lock);
@@ -2536,8 +2550,6 @@ err_workqueue:
 err_dmaunmap:
if (host->use_dma && host->dma_ops->exit)
host->dma_ops->ex

[PATCH 3/3] mmc: dw_mmc: Support voltage changes

[Yuvaraj Kumar C D]

From: Doug Anderson 

For UHS cards we need the ability to switch voltages from 3.3V to
1.8V.  Add support to the dw_mmc driver to handle this.  Note that
dw_mmc needs a little bit of extra code since the interface needs a
special bit programmed to the CMD register while CMD11 is progressing.
This means adding a few extra states to the state machine to track.

Signed-off-by: Doug Anderson 
Signed-off-by: Yuvaraj Kumar C D 

---
 drivers/mmc/host/dw_mmc.c  |  145 +---
 drivers/mmc/host/dw_mmc.h  |5 +-
 include/linux/mmc/dw_mmc.h |2 +
 3 files changed, 142 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index e034bce..38eb548 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -235,10 +236,13 @@ err:
 }
 #endif /* defined(CONFIG_DEBUG_FS) */
 
+static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
+
 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command 
*cmd)
 {
struct mmc_data *data;
struct dw_mci_slot *slot = mmc_priv(mmc);
+   struct dw_mci *host = slot->host;
const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
u32 cmdr;
cmd->error = -EINPROGRESS;
@@ -254,6 +258,32 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, 
struct mmc_command *cmd)
else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 
+   if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+   u32 clk_en_a;
+
+   /* Special bit makes CMD11 not die */
+   cmdr |= SDMMC_CMD_VOLT_SWITCH;
+
+   /* Change state to continue to handle CMD11 weirdness */
+   WARN_ON(slot->host->state != STATE_SENDING_CMD);
+   slot->host->state = STATE_SENDING_CMD11;
+
+   /*
+* We need to disable clock stop while doing voltage switch
+* according to 7.4.1.2 Voltage Switch Normal Scenario.
+*
+* It's assumed that by the next time the CLKENA is updated
+* (when we set the clock next) that the voltage change will
+* be over, so we don't bother setting any bits to synchronize
+* with dw_mci_setup_bus().
+*/
+   clk_en_a = mci_readl(host, CLKENA);
+   clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
+   mci_writel(host, CLKENA, clk_en_a);
+   mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
+SDMMC_CMD_PRV_DAT_WAIT, 0);
+   }
+
if (cmd->flags & MMC_RSP_PRESENT) {
/* We expect a response, so set this bit */
cmdr |= SDMMC_CMD_RESP_EXP;
@@ -776,11 +806,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, 
bool force_clkinit)
unsigned int clock = slot->clock;
u32 div;
u32 clk_en_a;
+   u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
+
+   /* We must continue to set bit 28 in CMD until the change is complete */
+   if (host->state == STATE_WAITING_CMD11_DONE)
+   sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
 
if (!clock) {
mci_writel(host, CLKENA, 0);
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
} else if (clock != host->current_speed || force_clkinit) {
div = host->bus_hz / clock;
if (host->bus_hz % clock && host->bus_hz > clock)
@@ -804,15 +838,13 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, 
bool force_clkinit)
mci_writel(host, CLKSRC, 0);
 
/* inform CIU */
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 
/* set clock to desired speed */
mci_writel(host, CLKDIV, div);
 
/* inform CIU */
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 
/* enable clock; only low power if no SDIO */
clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
@@ -821,8 +853,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool 
force_clkinit)
mci_writel(host, CLKENA, clk_en_a);
 
/* inform CIU */
-   mci_send_cmd(slot,
-SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+   mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 
   

[PATCH 2/3] mmc: dw_mmc: Dont cut off vqmmc and vmmc

[Yuvaraj Kumar C D]

On exynos 5250 and 5420 based boards which uses built-in CD# line
for card detection.But unfortunately CD# line is on the same voltage
rails as of I/O voltage rails.When we cut off vqmmc,the consequent
card detection will break in these boards.

Also if we let alone the vqmmc turned on when vmmc turned off, the
card could have half way powered and this can damage the card.So
this patch adds a check so that, if the board used the built-in
card detection mechanism i.e through CDETECT, it will not turned
down vqmmc and vmmc both.

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |   23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index f5cabce..e034bce 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -932,6 +932,25 @@ static void dw_mci_request(struct mmc_host *mmc, struct 
mmc_request *mrq)
spin_unlock_bh(&host->lock);
 }
 
+/*
+ * some of the boards use controller CD line for card detection.Unfortunately
+ * CD line is bind to the same volatge domain as of the IO lines.If we turn off
+ * IO voltage domain, CD line wont work.
+ * Return true when controller CD line is used for card detection or return
+ * false.
+ */
+static bool dw_mci_builtin_cd(struct dw_mci_slot *slot)
+{
+   struct dw_mci_board *brd = slot->host->pdata;
+   struct mmc_host *mmc = slot->mmc;
+
+   if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) &&
+   !IS_ERR_VALUE(mmc_gpio_get_cd(mmc)))
+   return true;
+   else
+   return false;
+}
+
 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
struct dw_mci_slot *slot = mmc_priv(mmc);
@@ -988,6 +1007,10 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
mci_writel(slot->host, PWREN, regs);
break;
case MMC_POWER_OFF:
+   if (dw_mci_builtin_cd(slot) &&
+   !test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
+   return;
+
if (!IS_ERR(mmc->supply.vqmmc) &&
test_bit(DW_MMC_IO_POWERED, &slot->flags)) {
ret = regulator_disable(mmc->supply.vqmmc);
-- 
1.7.10.4

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[PATCH 0/3] Adding UHS support for dw_mmc driver

[Yuvaraj Kumar C D]

This series adds UHS support for dw_mmc driver.
Patch[1] reworks the handling of vmmc and vqmmc regulators.
Patch[2] handles the case where in some boards uses built-in CD line for
card detection and connected to a same voltage domain as of the IO rails.
Patch[3] was taken from chrome tree originally developed by Doug Anderson.

These patches were tested on exynos based chromebook with 3.16-rc1.

Doug Anderson (1):
  mmc: dw_mmc: Support voltage changes

Yuvaraj Kumar C D (2):
  mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators
  mmc: dw_mmc: Dont cut off vqmmc and vmmc

 drivers/mmc/host/dw_mmc.c  |  239 +++-
 drivers/mmc/host/dw_mmc.h  |7 +-
 include/linux/mmc/dw_mmc.h |2 +
 3 files changed, 201 insertions(+), 47 deletions(-)

-- 
1.7.10.4

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[PATCH] mmc: card: restrict access to RPMB partition

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

The RPMB partition should only be accessed through the RPMB ioctls
and not through read()/write().  This patch makes mmc_blk_open()
reject open attempts to the RPMB partition in read or write mode.

Signed-off-by: Andrew Bresticker 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/card/block.c |   10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 452782b..fd59090 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -297,7 +297,15 @@ static int mmc_blk_open(struct block_device *bdev, fmode_t 
mode)
check_disk_change(bdev);
ret = 0;
 
-   if ((mode & FMODE_WRITE) && md->read_only) {
+   /*
+* Reject read/write access to the RPMB partition.  It should
+* only be accessed through ioctls.
+*/
+   if ((mode & (FMODE_READ | FMODE_WRITE)) &&
+   md->area_type & MMC_BLK_DATA_AREA_RPMB) {
+   mmc_blk_put(md);
+   ret = -EACCES;
+   } else if ((mode & FMODE_WRITE) && md->read_only) {
mmc_blk_put(md);
ret = -EROFS;
}
-- 
1.7.10.4

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Re: [PATCH] mmc: dw_mmc: Make sure we don't get stuck when we get an error

[Yuvaraj Kumar]

Any comments on this patch?

On Thu, Mar 27, 2014 at 11:48 AM, Yuvaraj Kumar C D
 wrote:
> From: Doug Anderson 
>
> If we happened to get a data error at just the wrong time the dw_mmc
> driver could get into a state where it would never complete its
> request.  That would leave the caller just hanging there.
>
> We fix this two ways and both of the two fixes on their own appear to
> fix the problems we've seen:
>
> 1. Fix a race in the tasklet where the interrupt setting the data
>error happens _just after_ we check for it, then we get a
>EVENT_XFER_COMPLETE.  We fix this by repeating a bit of code.
> 2. Fix it so that if we detect that we've got an error in the "data
>busy" state and we're not going to do anything else we end the
>request and unblock anyone waiting.
>
> Signed-off-by: Doug Anderson 
> Signed-off-by: Yuvaraj Kumar C D 
> ---
>  drivers/mmc/host/dw_mmc.c |   47 
> +
>  1 file changed, 47 insertions(+)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 1d77431..4c589f1 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -1300,6 +1300,14 @@ static void dw_mci_tasklet_func(unsigned long priv)
> /* fall through */
>
> case STATE_SENDING_DATA:
> +   /*
> +* We could get a data error and never a transfer
> +* complete so we'd better check for it here.
> +*
> +* Note that we don't really care if we also got a
> +* transfer complete; stopping the DMA and sending an
> +* abort won't hurt.
> +*/
> if (test_and_clear_bit(EVENT_DATA_ERROR,
>&host->pending_events)) {
> dw_mci_stop_dma(host);
> @@ -1313,7 +1321,29 @@ static void dw_mci_tasklet_func(unsigned long priv)
> break;
>
> set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
> +
> +   /*
> +* Handle an EVENT_DATA_ERROR that might have shown up
> +* before the transfer completed.  This might not have
> +* been caught by the check above because the 
> interrupt
> +* could have gone off between the previous check and
> +* the check for transfer complete.
> +*
> +* Technically this ought not be needed assuming we
> +* get a DATA_COMPLETE eventually (we'll notice the
> +* error and end the request), but it shouldn't hurt.
> +*
> +* This has the advantage of sending the stop command.
> +*/
> +   if (test_and_clear_bit(EVENT_DATA_ERROR,
> +  &host->pending_events)) {
> +   dw_mci_stop_dma(host);
> +   send_stop_abort(host, data);
> +   state = STATE_DATA_ERROR;
> +   break;
> +   }
> prev_state = state = STATE_DATA_BUSY;
> +
> /* fall through */
>
> case STATE_DATA_BUSY:
> @@ -1336,6 +1366,23 @@ static void dw_mci_tasklet_func(unsigned long priv)
> /* stop command for open-ended transfer*/
> if (data->stop)
> send_stop_abort(host, data);
> +   } else {
> +   /*
> +* If we don't have a command complete now 
> we'll
> +* never get one since we just reset 
> everything;
> +* better end the request.
> +*
> +* If we do have a command complete we'll fall
> +* through to the SENDING_STOP command and
> +* everything will be peachy keen.
> +*
> +* TODO: I guess we shouldn't send a stop?
> +*/
> +   if (!test_bit(EVENT_CMD_COMPLETE,
> + 

Re: [PATCH] mmc: dw_mmc: change to use recommended reset procedure

[Yuvaraj Kumar]

Any comments on this patch?

On Wed, Mar 26, 2014 at 5:16 PM, Yuvaraj Kumar C D  wrote:
> From: Sonny Rao 
>
> This patch changes the fifo reset code to follow the reset procedure
> outlined in the documentation of Synopsys  Mobile storage host databook
> 7.2.13.
> Without this patch, we could able to see eMMC was not detected after
> multiple reboots due to driver hangs while eMMC tuning for HS200.
>
> Signed-off-by: Sonny Rao 
> Signed-off-by: Yuvaraj Kumar C D 
> ---
>  drivers/mmc/host/dw_mmc.c |   48 
> -
>  drivers/mmc/host/dw_mmc.h |1 +
>  2 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 32dd81d..1d77431 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -2220,7 +2220,53 @@ static inline bool dw_mci_fifo_reset(struct dw_mci 
> *host)
> host->sg = NULL;
> }
>
> -   return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
> +   /*
> +* The recommended method for resetting is to always reset the
> +* controller and the fifo, but differs slightly depending on the 
> mode.
> +* Note that this doesn't handle the "generic DMA" (not IDMAC) case.
> +*/
> +   if (dw_mci_ctrl_reset(host, SDMMC_CTRL_RESET | 
> SDMMC_CTRL_FIFO_RESET)) {
> +   unsigned long timeout = jiffies + msecs_to_jiffies(500);
> +   u32 status, rint;
> +
> +   /* if using dma we wait for dma_req to clear */
> +   if (host->using_dma) {
> +   do {
> +   status = mci_readl(host, STATUS);
> +   if (!(status & SDMMC_STATUS_DMA_REQ))
> +   break;
> +   cpu_relax();
> +   } while (time_before(jiffies, timeout));
> +
> +   if (status & SDMMC_STATUS_DMA_REQ)
> +   dev_err(host->dev,
> +   "%s: Timeout waiting for dma_req to "
> +   "clear during reset", __func__);
> +
> +   /* when using DMA next we reset the fifo again */
> +   dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
> +   }
> +   /*
> +* In all cases we clear the RAWINTS register to clear any
> +* interrupts.
> +*/
> +   rint = mci_readl(host, RINTSTS);
> +   rint = rint & (~mci_readl(host, MINTSTS));
> +   if (rint)
> +   mci_writel(host, RINTSTS, rint);
> +
> +   } else
> +   dev_err(host->dev, "%s: Reset bits didn't clear", __func__);
> +
> + #ifdef CONFIG_MMC_DW_IDMAC
> +   /* It is also recommended that we reset and reprogram idmac */
> +   dw_mci_idmac_reset(host);
> + #endif
> +
> +   /* After a CTRL reset we need to have CIU set clock registers  */
> +   mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
> +
> +   return true;
>  }
>
>  static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index 738fa24..037e47a 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -129,6 +129,7 @@
>  #define SDMMC_CMD_INDX(n)  ((n) & 0x1F)
>  /* Status register defines */
>  #define SDMMC_GET_FCNT(x)  (((x)>>17) & 0x1FFF)
> +#define SDMMC_STATUS_DMA_REQ   BIT(31)
>  /* FIFOTH register defines */
>  #define SDMMC_SET_FIFOTH(m, r, t)  (((m) & 0x7) << 28 | \
>  ((r) & 0xFFF) << 16 | \
> --
> 1.7.10.4
>
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[PATCH] mmc: dw_mmc: Make sure we don't get stuck when we get an error

[Yuvaraj Kumar C D]

From: Doug Anderson 

If we happened to get a data error at just the wrong time the dw_mmc
driver could get into a state where it would never complete its
request.  That would leave the caller just hanging there.

We fix this two ways and both of the two fixes on their own appear to
fix the problems we've seen:

1. Fix a race in the tasklet where the interrupt setting the data
   error happens _just after_ we check for it, then we get a
   EVENT_XFER_COMPLETE.  We fix this by repeating a bit of code.
2. Fix it so that if we detect that we've got an error in the "data
   busy" state and we're not going to do anything else we end the
   request and unblock anyone waiting.

Signed-off-by: Doug Anderson 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |   47 +
 1 file changed, 47 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1d77431..4c589f1 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1300,6 +1300,14 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* fall through */
 
case STATE_SENDING_DATA:
+   /*
+* We could get a data error and never a transfer
+* complete so we'd better check for it here.
+*
+* Note that we don't really care if we also got a
+* transfer complete; stopping the DMA and sending an
+* abort won't hurt.
+*/
if (test_and_clear_bit(EVENT_DATA_ERROR,
   &host->pending_events)) {
dw_mci_stop_dma(host);
@@ -1313,7 +1321,29 @@ static void dw_mci_tasklet_func(unsigned long priv)
break;
 
set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
+
+   /*
+* Handle an EVENT_DATA_ERROR that might have shown up
+* before the transfer completed.  This might not have
+* been caught by the check above because the interrupt
+* could have gone off between the previous check and
+* the check for transfer complete.
+*
+* Technically this ought not be needed assuming we
+* get a DATA_COMPLETE eventually (we'll notice the
+* error and end the request), but it shouldn't hurt.
+*
+* This has the advantage of sending the stop command.
+*/
+   if (test_and_clear_bit(EVENT_DATA_ERROR,
+  &host->pending_events)) {
+   dw_mci_stop_dma(host);
+   send_stop_abort(host, data);
+   state = STATE_DATA_ERROR;
+   break;
+   }
prev_state = state = STATE_DATA_BUSY;
+
/* fall through */
 
case STATE_DATA_BUSY:
@@ -1336,6 +1366,23 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* stop command for open-ended transfer*/
if (data->stop)
send_stop_abort(host, data);
+   } else {
+   /*
+* If we don't have a command complete now we'll
+* never get one since we just reset everything;
+* better end the request.
+*
+* If we do have a command complete we'll fall
+* through to the SENDING_STOP command and
+* everything will be peachy keen.
+*
+* TODO: I guess we shouldn't send a stop?
+*/
+   if (!test_bit(EVENT_CMD_COMPLETE,
+ &host->pending_events)) {
+   dw_mci_request_end(host, mrq);
+   goto unlock;
+   }
}
 
/*
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: change to use recommended reset procedure

[Yuvaraj Kumar C D]

From: Sonny Rao 

This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys  Mobile storage host databook
7.2.13.
Without this patch, we could able to see eMMC was not detected after
multiple reboots due to driver hangs while eMMC tuning for HS200.

Signed-off-by: Sonny Rao 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |   48 -
 drivers/mmc/host/dw_mmc.h |1 +
 2 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 32dd81d..1d77431 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2220,7 +2220,53 @@ static inline bool dw_mci_fifo_reset(struct dw_mci *host)
host->sg = NULL;
}
 
-   return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
+   /*
+* The recommended method for resetting is to always reset the
+* controller and the fifo, but differs slightly depending on the mode.
+* Note that this doesn't handle the "generic DMA" (not IDMAC) case.
+*/
+   if (dw_mci_ctrl_reset(host, SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET)) {
+   unsigned long timeout = jiffies + msecs_to_jiffies(500);
+   u32 status, rint;
+
+   /* if using dma we wait for dma_req to clear */
+   if (host->using_dma) {
+   do {
+   status = mci_readl(host, STATUS);
+   if (!(status & SDMMC_STATUS_DMA_REQ))
+   break;
+   cpu_relax();
+   } while (time_before(jiffies, timeout));
+
+   if (status & SDMMC_STATUS_DMA_REQ)
+   dev_err(host->dev,
+   "%s: Timeout waiting for dma_req to "
+   "clear during reset", __func__);
+
+   /* when using DMA next we reset the fifo again */
+   dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
+   }
+   /*
+* In all cases we clear the RAWINTS register to clear any
+* interrupts.
+*/
+   rint = mci_readl(host, RINTSTS);
+   rint = rint & (~mci_readl(host, MINTSTS));
+   if (rint)
+   mci_writel(host, RINTSTS, rint);
+
+   } else
+   dev_err(host->dev, "%s: Reset bits didn't clear", __func__);
+
+ #ifdef CONFIG_MMC_DW_IDMAC
+   /* It is also recommended that we reset and reprogram idmac */
+   dw_mci_idmac_reset(host);
+ #endif
+
+   /* After a CTRL reset we need to have CIU set clock registers  */
+   mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
+
+   return true;
 }
 
 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 738fa24..037e47a 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -129,6 +129,7 @@
 #define SDMMC_CMD_INDX(n)  ((n) & 0x1F)
 /* Status register defines */
 #define SDMMC_GET_FCNT(x)  (((x)>>17) & 0x1FFF)
+#define SDMMC_STATUS_DMA_REQ   BIT(31)
 /* FIFOTH register defines */
 #define SDMMC_SET_FIFOTH(m, r, t)  (((m) & 0x7) << 28 | \
 ((r) & 0xFFF) << 16 | \
-- 
1.7.10.4

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Re: [PATCH V2] mmc: dw_mmc: exynos: Turn SDIO interrupts on

[Yuvaraj Kumar]

On Mon, Mar 24, 2014 at 9:59 AM, Jaehoon Chung  wrote:
> Hi, Yuvaraj.
>
> NACK. we can use "mmc_of_parese()".
Thanks Jaehoon for the pointer.I will use "mmc_of_parse()".
>
> I have sent the patch that use "mmc_of_parse()".
> https://patchwork.kernel.org/patch/3750681/
>
> Best Regards,
> Jaehoon Chung
>
> On 03/24/2014 01:23 PM, Yuvaraj Kumar C D wrote:
>> The mmc part in exynos supports SDIO interrupts and they work fine, so
>> turn the capability on.  With this I see download speeds increase
>> about 10x.
>>
>> This V1 of this patch is posted to LKML at
>> https://patchwork.kernel.org/patch/2429661/) by Doug Anderson.
>>
>> Signed-off-by: Doug Anderson 
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  drivers/mmc/host/dw_mmc.c |3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 0c56faa..240949d 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -2417,6 +2417,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct 
>> dw_mci *host)
>>   if (of_get_property(np, "cd-inverted", NULL))
>>   pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
>>
>> + if (of_find_property(np, "cap-sdio-irq", NULL))
>> + pdata->caps |= MMC_CAP_SDIO_IRQ;
>> +
>>   return pdata;
>>  }
>>
>>
>
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Re: [PATCH] mmc: dw_mmc: Fix the max_blk_count in IDMAC

[Yuvaraj Kumar]

On Mon, Mar 24, 2014 at 9:36 AM, Jaehoon Chung  wrote:
> Hi,
>
> Did you know that Seungwon has sent the patch "[PATCH 1/7] mmc: dw_mmc: fix 
> the max_blk_count in IDMAC"?
> I think this patch looks like same, isn't it?
Yes.Its the same one.Please discard this patch.
> Plz check it.
>
> Best Regards,
> Jaehoon Chung
>
> On 03/24/2014 12:53 PM, Yuvaraj Kumar C D wrote:
>> From: Alim Akhtar 
>>
>> max_blk_count is currently set incorrectly, and the correct value can
>> be determined by looking at the maximum number of bytes which can be
>> transferred and the block size.  We use the maximum block size to
>> determine the minimum number of blocks that the controller should
>> support.  It could probably do more with a smaller block size but this
>> value should be sufficient for good performance.
>>
>> This improves sequential performance by 82% on write and 6% read on
>> one particular device.
>>
>> TEST= with this patch
>>   time dd if=/dev/zero of=/usr/local/100 bs=1M count=100 conv=fdatasync
>>   100+0 records in
>>   100+0 records out
>>   104857600 bytes (105 MB) copied, 2.62541 s, 39.9 MB/s
>>
>>   real0m2.638s
>>   user0m0.000s
>>   sys 0m0.645s
>>
>>   without this patch:
>>   time dd if=/dev/zero of=/usr/local/100 bs=1M count=100 conv=fdatasync
>>   100+0 records in
>>   100+0 records out
>>   104857600 bytes (105 MB) copied, 3.25873 s, 32.2 MB/s
>>
>>   real0m3.265s
>>   user0m0.005s
>>   sys 0m0.690s
>>
>> Signed-off-by: Seungwon Jeon 
>> Signed-off-by: Alim Akhtar 
>> Signed-off-by: Sonny Rao 
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  drivers/mmc/host/dw_mmc.c |   18 --
>>  1 file changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 0c56faa..2fc4030 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -2213,10 +2213,24 @@ static int dw_mci_init_slot(struct dw_mci *host, 
>> unsigned int id)
>>   /* Useful defaults if platform data is unset. */
>>  #ifdef CONFIG_MMC_DW_IDMAC
>>   mmc->max_segs = host->ring_size;
>> +
>> + /* the BLKSIZ register is 16-bits wide */
>>   mmc->max_blk_size = 65536;
>> - mmc->max_blk_count = host->ring_size;
>> +
>> + /*
>> +  * This value is calculated by taking the size of the
>> +  * 32-bit BYTCNT (byte count) register and dividing by the
>> +  * BLKSIZ (block size) register.  This is the minimum number
>> +  * of blocks which could be handled.
>> +  */
>> + mmc->max_blk_count = 0x;
>>   mmc->max_seg_size = 0x1000;
>> - mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
>> + /*
>> +  * Maximum request size should be total number of descriptors
>> +  * times the maximum amount of data each can reference
>> +  */
>> +
>> + mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
>>  #else
>>   mmc->max_segs = 64;
>>   mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
>>
>
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[PATCH V2] mmc: dw_mmc: exynos: Turn SDIO interrupts on

[Yuvaraj Kumar C D]

The mmc part in exynos supports SDIO interrupts and they work fine, so
turn the capability on.  With this I see download speeds increase
about 10x. 

This V1 of this patch is posted to LKML at
https://patchwork.kernel.org/patch/2429661/) by Doug Anderson.

Signed-off-by: Doug Anderson 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 0c56faa..240949d 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2417,6 +2417,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci 
*host)
if (of_get_property(np, "cd-inverted", NULL))
pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
 
+   if (of_find_property(np, "cap-sdio-irq", NULL))
+   pdata->caps |= MMC_CAP_SDIO_IRQ;
+
return pdata;
 }
 
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: Fix the max_blk_count in IDMAC

[Yuvaraj Kumar C D]

From: Alim Akhtar 

max_blk_count is currently set incorrectly, and the correct value can
be determined by looking at the maximum number of bytes which can be
transferred and the block size.  We use the maximum block size to
determine the minimum number of blocks that the controller should
support.  It could probably do more with a smaller block size but this
value should be sufficient for good performance.

This improves sequential performance by 82% on write and 6% read on
one particular device.

TEST= with this patch
time dd if=/dev/zero of=/usr/local/100 bs=1M count=100 conv=fdatasync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 2.62541 s, 39.9 MB/s

real0m2.638s
user0m0.000s
sys 0m0.645s

without this patch:
time dd if=/dev/zero of=/usr/local/100 bs=1M count=100 conv=fdatasync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 3.25873 s, 32.2 MB/s

real0m3.265s
user0m0.005s
sys 0m0.690s

Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
Signed-off-by: Sonny Rao 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc.c |   18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 0c56faa..2fc4030 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2213,10 +2213,24 @@ static int dw_mci_init_slot(struct dw_mci *host, 
unsigned int id)
/* Useful defaults if platform data is unset. */
 #ifdef CONFIG_MMC_DW_IDMAC
mmc->max_segs = host->ring_size;
+
+   /* the BLKSIZ register is 16-bits wide */
mmc->max_blk_size = 65536;
-   mmc->max_blk_count = host->ring_size;
+
+   /*
+* This value is calculated by taking the size of the
+* 32-bit BYTCNT (byte count) register and dividing by the
+* BLKSIZ (block size) register.  This is the minimum number
+* of blocks which could be handled.
+*/
+   mmc->max_blk_count = 0x;
mmc->max_seg_size = 0x1000;
-   mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
+   /*
+* Maximum request size should be total number of descriptors
+* times the maximum amount of data each can reference
+*/
+
+   mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
 #else
mmc->max_segs = 64;
mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
-- 
1.7.10.4

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[PATCH] mmc: dw_mmc: Support setting the ciu-div on exynos

[Yuvaraj Kumar C D]

From: Doug Anderson 

The existing dw_mmc code for exynos5250/exynos5420 read the ciu-div
property from the device tree and used it in calculations, but didn't
actually ever set it in hardware.  That means that if the hardware
value set by the firmware didn't match what was in the device tree
that we'd be clocking things incorrectly.

Signed-off-by: Doug Anderson 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-exynos.c |7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 3423c5e..07392ac 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -28,6 +28,7 @@
 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)(((x) & 7) << 0)
 #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)   (((x) & 7) << 24)
+#define SDMMC_CLKSEL_GET_SAMPLE(x)  (((x) >> 0) & 0x7)
 #define SDMMC_CLKSEL_GET_DRV_WD3(x)(((x) >> 16) & 0x7)
 #define SDMMC_CLKSEL_TIMING(x, y, z)   (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
SDMMC_CLKSEL_CCLK_DRIVE(y) |\
@@ -118,6 +119,12 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv = host->priv;
unsigned long rate = clk_get_rate(host->ciu_clk);
+   u32 clksel = mci_readl(host, CLKSEL);
+
+   clksel = SDMMC_CLKSEL_TIMING(SDMMC_CLKSEL_GET_SAMPLE(clksel),
+SDMMC_CLKSEL_GET_DRV_WD3(clksel),
+priv->ciu_div);
+   mci_writel(host, CLKSEL, clksel);
 
host->bus_hz = rate / (priv->ciu_div + 1);
return 0;
-- 
1.7.10.4

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[RFC 1/5] usb: ohci-exynos: enable async suspend/resume

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

USB host controllers can take a significant amount of time to suspend
and resume, adding several hundred miliseconds to the kernel resume
time. Since the Exynos OHCI controller has no outside dependencies
(other than clocks, which are suspended late/resumed early), allow it to
suspend and resume asynchronously.

Signed-off-by: Andrew Bresticker 
Reviewed-by: Julius Werner 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/usb/host/ohci-exynos.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 68588d8..faad2bdc 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -137,6 +137,8 @@ skip_phy:
if (exynos_ohci->otg)
exynos_ohci->otg->set_host(exynos_ohci->otg, &hcd->self);
 
+   device_enable_async_suspend(&pdev->dev);
+
platform_set_drvdata(pdev, hcd);
 
exynos_ohci_phy_enable(pdev);
-- 
1.7.9.5

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[RFC 2/5] usb: ehci-s5p: enable async suspend/resume

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

USB host controllers can take a significant amount of time to suspend
and resume, adding several hundred miliseconds to the kernel resume
time. Since the Exynos EHCI controller has no outside dependencies
(other than clocks, which are suspended late/resumed early), allow it to
suspend and resume asynchronously.

Signed-off-by: Andrew Bresticker 
Reviewed-by: Julius Werner 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/usb/host/ehci-exynos.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index f7ce8e2..e5125cd 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -165,6 +165,8 @@ skip_phy:
}
device_wakeup_enable(hcd->self.controller);
 
+   device_enable_async_suspend(&pdev->dev);
+
platform_set_drvdata(pdev, hcd);
 
return 0;
-- 
1.7.9.5

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[RFC 4/5] usb: dwc3-exynos: enable async suspend/resume

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

In addition to enabling async suspend/resume on the xhci-plat device,
we must enable it for the dwc3-exynos platform device in order to make
the full USB stack resume asynchronously.  Like the xhci-plat, ehci-s5p,
and ohci-exynos drivers, there are no outside dependencies which would
make resuming the dwc3-exynos driver asynchronously unsafe.

Signed-off-by: Andrew Bresticker 
Reviewed-by: Julius Werner 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/usb/dwc3/dwc3-exynos.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 8b20c70..57431b7 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -155,6 +155,8 @@ static int dwc3_exynos_probe(struct platform_device *pdev)
goto err2;
}
 
+   device_enable_async_suspend(dev);
+
return 0;
 
 err2:
-- 
1.7.9.5

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[RFC 3/5] usb: xhci-plat: enable async suspend/resume

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

USB host controllers can take a significant amount of time to suspend
and resume, adding several hundred miliseconds to the kernel resume
time. Since the XHCI controller has no outside dependencies (other than
clocks, which are suspended late/resumed early), allow it to suspend and
resume asynchronously.

Signed-off-by: Andrew Bresticker 
Reviewed-by: Julius Werner 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/usb/host/xhci-plat.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 8abda5c..1bc1565 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -162,6 +162,8 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (ret)
goto put_usb3_hcd;
 
+   device_enable_async_suspend(&pdev->dev);
+
return 0;
 
 put_usb3_hcd:
-- 
1.7.9.5

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[RFC 5/5] usb: dwc3: enable async suspend/resume

[Yuvaraj Kumar C D]

From: Andrew Bresticker 

In addition to enabling async suspend/resume on the xhci-plat device,
we must enable it for the dwc3 device (the parent of xhci-plat) in order
to make the full USB stack resume asynchronously.  Like the xhci-plat,
ehci-s5p, and ohci-exynos drivers, there are no outside dependencies
which would make resuming the dwc3 driver asynchronously unsafe.

Signed-off-by: Andrew Bresticker 
Reviewed-by: Julius Werner 
Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/usb/dwc3/core.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 59bb8d2..9c8a273 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -586,6 +586,8 @@ static int dwc3_probe(struct platform_device *pdev)
 
pm_runtime_allow(dev);
 
+   device_enable_async_suspend(dev);
+
return 0;
 
 err3:
-- 
1.7.9.5

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Re: [PATCH V2] i2c: s3c2410 : Add polling mode support

[Yuvaraj Kumar]

Dear Wolfram,
 Can you take this into your tree?

On Fri, Nov 22, 2013 at 11:32 AM, Yuvaraj Kumar  wrote:
> Any comments on this patch?
>
> On Mon, Nov 11, 2013 at 4:50 PM, Yuvaraj Kumar C D  
> wrote:
>> From: Vasanth Ananthan 
>>
>> This patch adds polling mode support for i2c-s3c2410 driver.The
>> SATA PHY controller's CMU and TRSV block's are of I2C register
>> map in exynos5250.These blocks can be configured using i2c.
>>
>> But i2c controller instance on which these block's sits lacks an
>> interrupt line.Also the current i2c-s3c2410 driver is only interrupt
>> driven, thus a polling mode support is required in the driver for
>> supporting this controller. This patch adds this support to the driver.
>>
>> Changes from V1:
>> 1.Changed the is_ack() to have even period b/w polls and
>>   used usleep_range() instead of udelay().
>>
>> Signed-off-by: Vasanth Ananthan 
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
>>  drivers/i2c/busses/i2c-s3c2410.c   |   66 
>> +---
>>  2 files changed, 58 insertions(+), 10 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt 
>> b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
>> index 296eb45..278de8e 100644
>> --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
>> +++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
>> @@ -10,6 +10,8 @@ Required properties:
>>inside HDMIPHY block found on several samsung SoCs
>>(d) "samsung, exynos5440-i2c", for s3c2440-like i2c used
>>on EXYNOS5440 which does not need GPIO configuration.
>> +  (e) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
>> +  a host to SATA PHY controller on an internal bus.
>>- reg: physical base address of the controller and length of memory mapped
>>  region.
>>- interrupts: interrupt number to the cpu.
>> diff --git a/drivers/i2c/busses/i2c-s3c2410.c 
>> b/drivers/i2c/busses/i2c-s3c2410.c
>> index 3747b9b..08ed126 100644
>> --- a/drivers/i2c/busses/i2c-s3c2410.c
>> +++ b/drivers/i2c/busses/i2c-s3c2410.c
>> @@ -85,6 +85,7 @@
>>  #define QUIRK_S3C2440  (1 << 0)
>>  #define QUIRK_HDMIPHY  (1 << 1)
>>  #define QUIRK_NO_GPIO  (1 << 2)
>> +#define QUIRK_POLL (1 << 3)
>>
>>  /* Max time to wait for bus to become idle after a xfer (in us) */
>>  #define S3C2410_IDLE_TIMEOUT   5000
>> @@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
>>  };
>>  MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
>>
>> +static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long 
>> iicstat);
>> +
>>  #ifdef CONFIG_OF
>>  static const struct of_device_id s3c24xx_i2c_match[] = {
>> { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
>> @@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
>>   .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
>> { .compatible = "samsung,exynos5440-i2c",
>>   .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
>> +   { .compatible = "samsung,exynos5-sata-phy-i2c",
>> + .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
>> {},
>>  };
>>  MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
>> @@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct 
>> s3c24xx_i2c *i2c, int ret)
>> if (ret)
>> i2c->msg_idx = ret;
>>
>> -   wake_up(&i2c->wait);
>> +   if (!(i2c->quirks & QUIRK_POLL))
>> +   wake_up(&i2c->wait);
>>  }
>>
>>  static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
>> @@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct 
>> s3c24xx_i2c *i2c)
>> writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
>>  }
>>
>> +static bool is_ack(struct s3c24xx_i2c *i2c)
>> +{
>> +   int tries;
>> +
>> +   for (tries = 50; tries; --tries) {
>> +   if (readl(i2c->regs + S3C2410_IICCON)
>> +   & S3C2410_IICCON_IRQPEND) {
>> +   if (!(readl(i2c->regs + S3C2410_IICSTAT)
>> +   & S3C241

[PATCH 2/2] ARM: dts:Move fifo-depth property from cros5250-common.dtsi

[Yuvaraj Kumar C D]

Commit 64c138a ("ARM: dts: Move fifo-depth property from exynos5250
board dts") missed out handling the exynos5250 snow dts file.
Deletes the fifo-depth property, as this property has been moved to
SOC specific exynos5250.dtsi file.

Signed-off-by : Abhilash Kesavan 

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/cros5250-common.dtsi |3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi 
b/arch/arm/boot/dts/cros5250-common.dtsi
index 1ceb62e..2dd70e9 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -233,7 +233,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -250,7 +249,6 @@
mmc@1222 {
num-slots = <1>;
supports-highspeed;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -269,7 +267,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
-- 
1.7.9.5

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[PATCH 1/2] ARM: dts: Fix status property of mmc nodes for snow board

[Yuvaraj Kumar C D]

Commit 0c3de788 ("ARM: dts: change status property of dwmmc nodes
for exynos5250") missed out handling the exynos5250 snow dts file.

Signed-off-by : Abhilash Kesavan 

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/cros5250-common.dtsi |4 
 arch/arm/boot/dts/exynos5250-snow.dts  |9 +
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi 
b/arch/arm/boot/dts/cros5250-common.dtsi
index 6470536..1ceb62e 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -247,10 +247,6 @@
};
};
 
-   mmc@1221 {
-   status = "disabled";
-   };
-
mmc@1222 {
num-slots = <1>;
supports-highspeed;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
b/arch/arm/boot/dts/exynos5250-snow.dts
index a9395c4..67484d1 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,11 +171,20 @@
};
};
 
+   mmc@1220 {
+   status = "okay";
+   };
+
+   mmc@1222 {
+   status = "okay";
+   };
+
/*
 * On Snow we've got SIP WiFi and so can keep drive strengths low to
 * reduce EMI.
 */
mmc@1223 {
+   status = "okay";
slot@0 {
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
-- 
1.7.9.5

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Re: [PATCH] ARM: dts: Fix mmc node on exynos5250 snow board

[Yuvaraj Kumar]

On Fri, Dec 6, 2013 at 12:19 AM, Sonny Rao  wrote:
> On Thu, Dec 5, 2013 at 2:06 AM, Yuvaraj Kumar C D  
> wrote:
>> Commits 64c138a ("ARM: dts: Move fifo-depth property from exynos5250
>> board dts") and 0c3de788 ("ARM: dts: change status property of dwmmc
>> nodes for exynos5250") missed out handling the exynos5250 snow dts file.
>> Delete the fifo-depth property and enable the mmc node in the snow dts
>> file.
>>
>
> Since this is really fixing two different issues, even though they
> both affect dw_mmc, would you mind splitting this up into two
> different commits?
 OK, I will split into two and repost.
>
>> Signed-off-by : Abhilash Kesavan 
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  arch/arm/boot/dts/cros5250-common.dtsi |7 ---
>>  arch/arm/boot/dts/exynos5250-snow.dts  |9 +
>>  2 files changed, 9 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/cros5250-common.dtsi 
>> b/arch/arm/boot/dts/cros5250-common.dtsi
>> index 6470536..2dd70e9 100644
>> --- a/arch/arm/boot/dts/cros5250-common.dtsi
>> +++ b/arch/arm/boot/dts/cros5250-common.dtsi
>> @@ -233,7 +233,6 @@
>> num-slots = <1>;
>> supports-highspeed;
>> broken-cd;
>> -   fifo-depth = <0x80>;
>
> Why are you deleting fifo-depth?
fifo-depth property has been moved to SOC specific file exynos5250.dtsi
>
>> card-detect-delay = <200>;
>> samsung,dw-mshc-ciu-div = <3>;
>> samsung,dw-mshc-sdr-timing = <2 3>;
>> @@ -247,14 +246,9 @@
>> };
>> };
>>
>> -   mmc@1221 {
>> -   status = "disabled";
>> -   };
>> -
>> mmc@1222 {
>> num-slots = <1>;
>> supports-highspeed;
>> -   fifo-depth = <0x80>;
>> card-detect-delay = <200>;
>> samsung,dw-mshc-ciu-div = <3>;
>> samsung,dw-mshc-sdr-timing = <2 3>;
>> @@ -273,7 +267,6 @@
>> num-slots = <1>;
>> supports-highspeed;
>> broken-cd;
>> -   fifo-depth = <0x80>;
>> card-detect-delay = <200>;
>> samsung,dw-mshc-ciu-div = <3>;
>> samsung,dw-mshc-sdr-timing = <2 3>;
>> diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
>> b/arch/arm/boot/dts/exynos5250-snow.dts
>> index a9395c4..67484d1 100644
>> --- a/arch/arm/boot/dts/exynos5250-snow.dts
>> +++ b/arch/arm/boot/dts/exynos5250-snow.dts
>> @@ -171,11 +171,20 @@
>> };
>> };
>>
>> +   mmc@1220 {
>> +   status = "okay";
>> +   };
>> +
>> +   mmc@1222 {
>> +   status = "okay";
>> +   };
>> +
>> /*
>>  * On Snow we've got SIP WiFi and so can keep drive strengths low to
>>  * reduce EMI.
>>  */
>> mmc@1223 {
>> +   status = "okay";
>> slot@0 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
>> --
>> 1.7.9.5
>>
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[PATCH] ARM: dts: Fix mmc node on exynos5250 snow board

[Yuvaraj Kumar C D]

Commits 64c138a ("ARM: dts: Move fifo-depth property from exynos5250
board dts") and 0c3de788 ("ARM: dts: change status property of dwmmc
nodes for exynos5250") missed out handling the exynos5250 snow dts file.
Delete the fifo-depth property and enable the mmc node in the snow dts
file.

Signed-off-by : Abhilash Kesavan 

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/cros5250-common.dtsi |7 ---
 arch/arm/boot/dts/exynos5250-snow.dts  |9 +
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi 
b/arch/arm/boot/dts/cros5250-common.dtsi
index 6470536..2dd70e9 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -233,7 +233,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -247,14 +246,9 @@
};
};
 
-   mmc@1221 {
-   status = "disabled";
-   };
-
mmc@1222 {
num-slots = <1>;
supports-highspeed;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -273,7 +267,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
b/arch/arm/boot/dts/exynos5250-snow.dts
index a9395c4..67484d1 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,11 +171,20 @@
};
};
 
+   mmc@1220 {
+   status = "okay";
+   };
+
+   mmc@1222 {
+   status = "okay";
+   };
+
/*
 * On Snow we've got SIP WiFi and so can keep drive strengths low to
 * reduce EMI.
 */
mmc@1223 {
+   status = "okay";
slot@0 {
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
-- 
1.7.9.5

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Re: [PATCH V2] i2c: s3c2410 : Add polling mode support

[Yuvaraj Kumar]

Any comments on this patch?

On Mon, Nov 11, 2013 at 4:50 PM, Yuvaraj Kumar C D  wrote:
> From: Vasanth Ananthan 
>
> This patch adds polling mode support for i2c-s3c2410 driver.The
> SATA PHY controller's CMU and TRSV block's are of I2C register
> map in exynos5250.These blocks can be configured using i2c.
>
> But i2c controller instance on which these block's sits lacks an
> interrupt line.Also the current i2c-s3c2410 driver is only interrupt
> driven, thus a polling mode support is required in the driver for
> supporting this controller. This patch adds this support to the driver.
>
> Changes from V1:
> 1.Changed the is_ack() to have even period b/w polls and
>   used usleep_range() instead of udelay().
>
> Signed-off-by: Vasanth Ananthan 
> Signed-off-by: Yuvaraj Kumar C D 
> ---
>  .../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
>  drivers/i2c/busses/i2c-s3c2410.c   |   66 
> +---
>  2 files changed, 58 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt 
> b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
> index 296eb45..278de8e 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
> @@ -10,6 +10,8 @@ Required properties:
>inside HDMIPHY block found on several samsung SoCs
>(d) "samsung, exynos5440-i2c", for s3c2440-like i2c used
>on EXYNOS5440 which does not need GPIO configuration.
> +  (e) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
> +  a host to SATA PHY controller on an internal bus.
>- reg: physical base address of the controller and length of memory mapped
>  region.
>- interrupts: interrupt number to the cpu.
> diff --git a/drivers/i2c/busses/i2c-s3c2410.c 
> b/drivers/i2c/busses/i2c-s3c2410.c
> index 3747b9b..08ed126 100644
> --- a/drivers/i2c/busses/i2c-s3c2410.c
> +++ b/drivers/i2c/busses/i2c-s3c2410.c
> @@ -85,6 +85,7 @@
>  #define QUIRK_S3C2440  (1 << 0)
>  #define QUIRK_HDMIPHY  (1 << 1)
>  #define QUIRK_NO_GPIO  (1 << 2)
> +#define QUIRK_POLL (1 << 3)
>
>  /* Max time to wait for bus to become idle after a xfer (in us) */
>  #define S3C2410_IDLE_TIMEOUT   5000
> @@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
>  };
>  MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
>
> +static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long 
> iicstat);
> +
>  #ifdef CONFIG_OF
>  static const struct of_device_id s3c24xx_i2c_match[] = {
> { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
> @@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
>   .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
> { .compatible = "samsung,exynos5440-i2c",
>   .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
> +   { .compatible = "samsung,exynos5-sata-phy-i2c",
> + .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
> {},
>  };
>  MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
> @@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct 
> s3c24xx_i2c *i2c, int ret)
> if (ret)
> i2c->msg_idx = ret;
>
> -   wake_up(&i2c->wait);
> +   if (!(i2c->quirks & QUIRK_POLL))
> +   wake_up(&i2c->wait);
>  }
>
>  static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
> @@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct 
> s3c24xx_i2c *i2c)
> writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
>  }
>
> +static bool is_ack(struct s3c24xx_i2c *i2c)
> +{
> +   int tries;
> +
> +   for (tries = 50; tries; --tries) {
> +   if (readl(i2c->regs + S3C2410_IICCON)
> +   & S3C2410_IICCON_IRQPEND) {
> +   if (!(readl(i2c->regs + S3C2410_IICSTAT)
> +   & S3C2410_IICSTAT_LASTBIT))
> +   return true;
> +   }
> +   usleep_range(1000, 2000);
> +   }
> +   dev_err(i2c->dev, "ack was not recieved\n");
> +   return false;
> +}
>
>  /* s3c24xx_i2c_message_start
>   *
> @@ -268,6 +290,16 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c 
> *i2c,
>
> stat |= S3C2410_IICSTAT_START;
> writel(stat, i2c->regs + S3C2410_IICSTAT);
> +
> +   if 

Re: [PATCH 2/3] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Tue, Nov 19, 2013 at 3:22 PM, Kishon Vijay Abraham I  wrote:
> On Friday 15 November 2013 11:17 AM, Yuvaraj Kumar wrote:
>> On Thu, Nov 14, 2013 at 11:18 AM, Kishon Vijay Abraham I  
>> wrote:
>>> Hi,
>>>
>>> On Monday 07 October 2013 07:35 PM, Yuvaraj Cd wrote:
>>>> On Tue, Oct 1, 2013 at 6:21 PM, Kishon Vijay Abraham I  
>>>> wrote:
>>>>> On Tuesday 01 October 2013 12:03 PM, Yuvaraj Kumar C D wrote:
>>>>>> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
>>>>>> phy comprises of CMU and TRSV blocks which are of I2C register Map.
>>>>>> So this patch also adds a i2c client driver, which is used configure
>>>>>> the CMU and TRSV block of exynos5250 SATA PHY.
>>>>>
>>>>> Why not make the Exynos5250 sata phy as a i2c client driver instead?
>>>>>>
>>>>>> This patch incorporates the generic phy framework to deal with sata
>>>>>> phy.
>>>>>>
>>>>>> This patch depends on the below patch
>>>>>>   [1].drivers: phy: add generic PHY framework
>>>>>>   by Kishon Vijay Abraham I
>>>>>>
>>>>>> Signed-off-by: Yuvaraj Kumar C D 
>>>>>> Signed-off-by: Girish K S 
>>>>>> Signed-off-by: Vasanth Ananthan 
>>>>>> ---
>>>>>>  drivers/phy/Kconfig  |6 +
>>>>>>  drivers/phy/Makefile |1 +
>>>>>>  drivers/phy/exynos/Kconfig   |5 +
>>>>>>  drivers/phy/exynos/Makefile  |5 +
>>>>>>  drivers/phy/exynos/exynos5250_phy_i2c.c  |   53 +++
>>>>>>  drivers/phy/exynos/sata_phy_exynos5250.c |  248 
>>>>>> ++
>>>>>>  drivers/phy/exynos/sata_phy_exynos5250.h |   33 
>>>>>>  7 files changed, 351 insertions(+)
>>>>>>  create mode 100644 drivers/phy/exynos/Kconfig
>>>>>>  create mode 100644 drivers/phy/exynos/Makefile
>>>>>>  create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
>>>>>>  create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
>>>>>>  create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h
>>>>>>
>>>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>>>>> index 5f85909..ab3d1c6 100644
>>>>>> --- a/drivers/phy/Kconfig
>>>>>> +++ b/drivers/phy/Kconfig
>>>>>> @@ -11,3 +11,9 @@ menuconfig GENERIC_PHY
>>>>>> devices present in the kernel. This layer will have the generic
>>>>>> API by which phy drivers can create PHY using the phy framework 
>>>>>> and
>>>>>> phy users can obtain reference to the PHY.
>>>>>> +
>>>>>> +if GENERIC_PHY
>>>>>
>>>>> NAK. Just select GENERIC_PHY from your driver Kconfig.
>>>>>> +
>>>>>> +source "drivers/phy/exynos/Kconfig"
>>>>>> +
>>>>>> +endif
>>>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>>>>> index 9e9560f..e0223d7 100644
>>>>>> --- a/drivers/phy/Makefile
>>>>>> +++ b/drivers/phy/Makefile
>>>>>> @@ -3,3 +3,4 @@
>>>>>>  #
>>>>>>
>>>>>>  obj-$(CONFIG_GENERIC_PHY)+= phy-core.o
>>>>>> +obj-$(CONFIG_PHY_SAMSUNG_SATA)   += exynos/
>>>>>
>>>>> simply have phy-exynos5250 in drivers/phy.
>>>> ok.
>>>>>> diff --git a/drivers/phy/exynos/Kconfig b/drivers/phy/exynos/Kconfig
>>>>>> new file mode 100644
>>>>>> index 000..fa125fb
>>>>>> --- /dev/null
>>>>>> +++ b/drivers/phy/exynos/Kconfig
>>>>>> @@ -0,0 +1,5 @@
>>>>>> +config PHY_SAMSUNG_SATA
>>>>>> + tristate "Samsung Sata SerDes/PHY driver"
>>>>>> + help
>>>>>> +   Support for Samsung sata SerDes/Phy found on Samsung
>>>>>> +   SoCs.
>>>>>> diff --git a/drivers/phy/exynos/Makefile b/drivers/phy/exynos/Makefile
>>>>>> new file mode 100644
>>>>>> index 000..50dc7eb
>>>>>> -

Re: [PATCH 2/3] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar]

On Thu, Nov 14, 2013 at 11:18 AM, Kishon Vijay Abraham I  wrote:
> Hi,
>
> On Monday 07 October 2013 07:35 PM, Yuvaraj Cd wrote:
>> On Tue, Oct 1, 2013 at 6:21 PM, Kishon Vijay Abraham I  wrote:
>>> On Tuesday 01 October 2013 12:03 PM, Yuvaraj Kumar C D wrote:
>>>> This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
>>>> phy comprises of CMU and TRSV blocks which are of I2C register Map.
>>>> So this patch also adds a i2c client driver, which is used configure
>>>> the CMU and TRSV block of exynos5250 SATA PHY.
>>>
>>> Why not make the Exynos5250 sata phy as a i2c client driver instead?
>>>>
>>>> This patch incorporates the generic phy framework to deal with sata
>>>> phy.
>>>>
>>>> This patch depends on the below patch
>>>>   [1].drivers: phy: add generic PHY framework
>>>>   by Kishon Vijay Abraham I
>>>>
>>>> Signed-off-by: Yuvaraj Kumar C D 
>>>> Signed-off-by: Girish K S 
>>>> Signed-off-by: Vasanth Ananthan 
>>>> ---
>>>>  drivers/phy/Kconfig  |6 +
>>>>  drivers/phy/Makefile |1 +
>>>>  drivers/phy/exynos/Kconfig   |5 +
>>>>  drivers/phy/exynos/Makefile  |5 +
>>>>  drivers/phy/exynos/exynos5250_phy_i2c.c  |   53 +++
>>>>  drivers/phy/exynos/sata_phy_exynos5250.c |  248 
>>>> ++
>>>>  drivers/phy/exynos/sata_phy_exynos5250.h |   33 
>>>>  7 files changed, 351 insertions(+)
>>>>  create mode 100644 drivers/phy/exynos/Kconfig
>>>>  create mode 100644 drivers/phy/exynos/Makefile
>>>>  create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
>>>>  create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
>>>>  create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h
>>>>
>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>>> index 5f85909..ab3d1c6 100644
>>>> --- a/drivers/phy/Kconfig
>>>> +++ b/drivers/phy/Kconfig
>>>> @@ -11,3 +11,9 @@ menuconfig GENERIC_PHY
>>>> devices present in the kernel. This layer will have the generic
>>>> API by which phy drivers can create PHY using the phy framework and
>>>> phy users can obtain reference to the PHY.
>>>> +
>>>> +if GENERIC_PHY
>>>
>>> NAK. Just select GENERIC_PHY from your driver Kconfig.
>>>> +
>>>> +source "drivers/phy/exynos/Kconfig"
>>>> +
>>>> +endif
>>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>>> index 9e9560f..e0223d7 100644
>>>> --- a/drivers/phy/Makefile
>>>> +++ b/drivers/phy/Makefile
>>>> @@ -3,3 +3,4 @@
>>>>  #
>>>>
>>>>  obj-$(CONFIG_GENERIC_PHY)+= phy-core.o
>>>> +obj-$(CONFIG_PHY_SAMSUNG_SATA)   += exynos/
>>>
>>> simply have phy-exynos5250 in drivers/phy.
>> ok.
>>>> diff --git a/drivers/phy/exynos/Kconfig b/drivers/phy/exynos/Kconfig
>>>> new file mode 100644
>>>> index 000..fa125fb
>>>> --- /dev/null
>>>> +++ b/drivers/phy/exynos/Kconfig
>>>> @@ -0,0 +1,5 @@
>>>> +config PHY_SAMSUNG_SATA
>>>> + tristate "Samsung Sata SerDes/PHY driver"
>>>> + help
>>>> +   Support for Samsung sata SerDes/Phy found on Samsung
>>>> +   SoCs.
>>>> diff --git a/drivers/phy/exynos/Makefile b/drivers/phy/exynos/Makefile
>>>> new file mode 100644
>>>> index 000..50dc7eb
>>>> --- /dev/null
>>>> +++ b/drivers/phy/exynos/Makefile
>>>> @@ -0,0 +1,5 @@
>>>> +#
>>>> +# Makefile for the exynos phy drivers.
>>>> +#
>>>> +ccflags-y := -Idrivers/phy/exynos
>>>> +obj-$(CONFIG_PHY_SAMSUNG_SATA)   += sata_phy_exynos5250.o 
>>>> exynos5250_phy_i2c.o
>>>> diff --git a/drivers/phy/exynos/exynos5250_phy_i2c.c 
>>>> b/drivers/phy/exynos/exynos5250_phy_i2c.c
>>>> new file mode 100644
>>>> index 000..9c75d3b
>>>> --- /dev/null
>>>> +++ b/drivers/phy/exynos/exynos5250_phy_i2c.c
>>>> @@ -0,0 +1,53 @@
>>>> +/*
>>>> + * Copyright (C) 2013 Samsung Electronics Co.Ltd
>>>> + * Author:
>>>> + *   Yuvaraj 

[PATCH V2] i2c: s3c2410 : Add polling mode support

[Yuvaraj Kumar C D]

From: Vasanth Ananthan 

This patch adds polling mode support for i2c-s3c2410 driver.The
SATA PHY controller's CMU and TRSV block's are of I2C register
map in exynos5250.These blocks can be configured using i2c.

But i2c controller instance on which these block's sits lacks an
interrupt line.Also the current i2c-s3c2410 driver is only interrupt
driven, thus a polling mode support is required in the driver for
supporting this controller. This patch adds this support to the driver.

Changes from V1:
1.Changed the is_ack() to have even period b/w polls and
  used usleep_range() instead of udelay().

Signed-off-by: Vasanth Ananthan 
Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
 drivers/i2c/busses/i2c-s3c2410.c   |   66 +---
 2 files changed, 58 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt 
b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index 296eb45..278de8e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
@@ -10,6 +10,8 @@ Required properties:
   inside HDMIPHY block found on several samsung SoCs
   (d) "samsung, exynos5440-i2c", for s3c2440-like i2c used
   on EXYNOS5440 which does not need GPIO configuration.
+  (e) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
+  a host to SATA PHY controller on an internal bus.
   - reg: physical base address of the controller and length of memory mapped
 region.
   - interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 3747b9b..08ed126 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -85,6 +85,7 @@
 #define QUIRK_S3C2440  (1 << 0)
 #define QUIRK_HDMIPHY  (1 << 1)
 #define QUIRK_NO_GPIO  (1 << 2)
+#define QUIRK_POLL (1 << 3)
 
 /* Max time to wait for bus to become idle after a xfer (in us) */
 #define S3C2410_IDLE_TIMEOUT   5000
@@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 
+static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long 
iicstat);
+
 #ifdef CONFIG_OF
 static const struct of_device_id s3c24xx_i2c_match[] = {
{ .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
@@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
  .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
{ .compatible = "samsung,exynos5440-i2c",
  .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
+   { .compatible = "samsung,exynos5-sata-phy-i2c",
+ .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
{},
 };
 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
@@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct 
s3c24xx_i2c *i2c, int ret)
if (ret)
i2c->msg_idx = ret;
 
-   wake_up(&i2c->wait);
+   if (!(i2c->quirks & QUIRK_POLL))
+   wake_up(&i2c->wait);
 }
 
 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
@@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct 
s3c24xx_i2c *i2c)
writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 }
 
+static bool is_ack(struct s3c24xx_i2c *i2c)
+{
+   int tries;
+
+   for (tries = 50; tries; --tries) {
+   if (readl(i2c->regs + S3C2410_IICCON)
+   & S3C2410_IICCON_IRQPEND) {
+   if (!(readl(i2c->regs + S3C2410_IICSTAT)
+   & S3C2410_IICSTAT_LASTBIT))
+   return true;
+   }
+   usleep_range(1000, 2000);
+   }
+   dev_err(i2c->dev, "ack was not recieved\n");
+   return false;
+}
 
 /* s3c24xx_i2c_message_start
  *
@@ -268,6 +290,16 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c 
*i2c,
 
stat |= S3C2410_IICSTAT_START;
writel(stat, i2c->regs + S3C2410_IICSTAT);
+
+   if (i2c->quirks & QUIRK_POLL) {
+   while ((i2c->msg_num != 0) && is_ack(i2c)) {
+   i2c_s3c_irq_nextbyte(i2c, stat);
+   stat = readl(i2c->regs + S3C2410_IICSTAT);
+
+   if (stat & S3C2410_IICSTAT_ARBITR)
+   dev_err(i2c->dev, "deal with arbitration 
loss\n");
+   }
+   }
 }
 
 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
@@ -675,6 +707,15 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
s3c24xx_i2c_enable_irq(i2c);
s

Re: [PATCH V4 0/4] exynos dwmmc device tree node cleanup

[Yuvaraj Kumar]

Gentle Ping...

On Thu, Sep 26, 2013 at 10:51 AM, Yuvaraj Cd  wrote:
> Hi Kukjin,
>  Can you please take this series to your tree?
>
> Best Regards
> Yuvaraj
>
> On Tue, Sep 3, 2013 at 1:41 PM, Tomasz Figa  wrote:
>> Hi Yuvaraj,
>>
>> On Tuesday 03 of September 2013 11:34:20 Yuvaraj Kumar C D wrote:
>>> changes from V3:
>>>   1.Added two new patch in the series
>>>   [1] ARM: dts: Move fifo-depth property from board dts
>>>   [2] ARM: dts: rename mmc dts node for exynos5 series
>>> changes from V2:
>>>   1.remove from exynos5.dtsi and add in exynos5250.dtsi
>>> in single patch.Suggested by Tomasz Figa.
>>>   2.Separate patch for changing status property of dwmmc node
>>> in smdk5250 and arndale board dts file.
>>>
>>> V1 Patches:
>>> 1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
>>> http://www.spinics.net/lists/linux-samsung-soc/msg21602.html
>>> 2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
>>>   http://www.spinics.net/lists/linux-samsung-soc/msg21603.html
>>>
>>> Yuvaraj Kumar C D (4):
>>>   ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
>>>   ARM: dts: exynos: change status property of dwmmc nodes
>>>   ARM: dts: Move fifo-depth property from board dts
>>>   ARM: dts: rename mmc dts node for exynos5 series
>>>
>>>  arch/arm/boot/dts/cros5250-common.dtsi|8 +++
>>>  arch/arm/boot/dts/exynos5.dtsi|   21 -
>>>  arch/arm/boot/dts/exynos5250-arndale.dts  |   16 -
>>>  arch/arm/boot/dts/exynos5250-smdk5250.dts |   16 -
>>>  arch/arm/boot/dts/exynos5250-snow.dts |2 +-
>>>  arch/arm/boot/dts/exynos5250.dtsi |   36
>>> ++--- 6 files changed, 41 insertions(+), 58
>>> deletions(-)
>>
>> Reviewed-by: Tomasz Figa 
>>
>> Best regards,
>> Tomasz
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
>> in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
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Re: [PATCH V7] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

Gentle Ping...

On Thu, Sep 26, 2013 at 12:13 PM, Yuvaraj Kumar  wrote:
> Hi Kukjin,
>  Can you please take this patch to your tree?
>
> Best Regards
> Yuvaraj
>
> On Tue, Sep 3, 2013 at 11:30 AM, Yuvaraj Kumar C D  
> wrote:
>> This patch adds the mmc device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>>
>> This patch depends on
>> [1]mmc: dw_mmc: exynos: configure SMU in exynos5420
>> [2]mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>> [3]mmc: dw_mmc: update binding document exynos-dw-mshc.txt
>>
>> changes since v6:
>> 1.renamed node name to mmc
>> 2.Used compatible string "samsung,exynos5420-dw-mshc"
>>   for controller instance which does not have SMU.
>> 3.Used compatible string "samsung,exynos5420-dw-mshc-smu"
>>   for controller instance which has SMU.
>>
>> changes since v5:
>> 1.removed instance index from node name.
>> 2.changed the node name to mshc.
>> 3.changed the reg property value for mshc_2.
>>
>> changes since v4:
>> 1.Droppped the bypass-smu binding property.
>> 2.Used compatible string "samsung,exynos5250-dw-mshc"
>>   for controller instance which does not have SMU.
>>
>> changes since V3:
>> 1.change fifo-depth size from 0x80 to 0x40
>> 2.Move the below properties
>> a.card-detect-delay
>> b.samsung,dw-mshc-ciu-div
>> c.samsung,dw-mshc-sdr-timing
>> d.samsung,dw-mshc-ddr-timing
>> from SOC dts to board dts file as suggested by Doug Anderson
>>
>> changes since V2:
>> 1.dropped num-slots property from node as its not required
>>   if number of card slots available is 1.
>>
>> 2.Move the below properties
>> a.fifo-depth
>> b.card-detect-delay
>> c.samsung,dw-mshc-ciu-div
>> d.samsung,dw-mshc-sdr-timing
>> e.samsung,dw-mshc-ddr-timing
>> from board dts to SOC dts,as these are not board specific properties.
>>
>> 3.Updated the binding document exynos-dw-mshc.txt.
>>
>> changes since V1:
>> 1.disable node by status = disabled in SOC file
>> 2.enable node by status = okay in board specific file
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33 +
>>  arch/arm/boot/dts/exynos5420.dtsi  |   39 
>> 
>>  3 files changed, 74 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index 6d1c098..84cd56f 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -16,6 +16,8 @@ Required Properties:
>>   specific extensions.
>> - "samsung,exynos5250-dw-mshc": for controllers with Samsung 
>> Exynos5250
>>   specific extensions.
>> +   - "samsung,exynos5420-dw-mshc": for controllers with Samsung 
>> Exynos5420
>> + specific extensions.
>>
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
>> interface
>>unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index bafba25..8df4ddc 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -31,6 +31,39 @@
>> };
>> };
>>
>> +   mmc@1220 {
>> +   status = "okay";
>> +   broken-cd;
>> +   supports-highspeed;
>> +   card-detect-delay = <200>;
>> +   samsung,dw-mshc-ciu-div = <3>;
>> +   samsung,dw-mshc-sdr-timing = <0 4>;
>> +   samsung,dw-mshc-ddr-timing = <0 2>;
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <&sd0_clk &

Re: [PATCH 1/3] ahci: exynos: add ahci sata support on Exynos platform

[Yuvaraj Kumar]

On Fri, Oct 4, 2013 at 6:03 AM, Jingoo Han  wrote:
> On Thursday, October 03, 2013 8:32 PM, Bartlomiej Zolnierkiewicz wrote:
>> On Tuesday, October 01, 2013 12:03:01 PM Yuvaraj Kumar C D wrote:
>> > Exynos5250 contains one Synopsys AHCI SATA controller.The avalaible
>> > ahci_platform driver is not sufficient to handle the AHCI PHY and PHY
>> > clock related initialization.
>> >
>> > This patch adds exynos specific ahci sata driver,contained the exynos
>> > specific initialized codes, re-use the generic ahci_platform driver, and
>> > keep the generic ahci_platform driver clean as much as possible.
>> >
>> > This patch depends on the below patch
>> > [1].drivers: phy: add generic PHY framework
>> > by Kishon Vijay Abraham I
>> >
>> > Signed-off-by: Yuvaraj Kumar C D 
>> > ---
>> >  drivers/ata/Kconfig   |9 ++
>> >  drivers/ata/Makefile  |1 +
>> >  drivers/ata/ahci_exynos.c |  226 
>> > +
>> >  3 files changed, 236 insertions(+)
>> >  create mode 100644 drivers/ata/ahci_exynos.c
>> >
>
>
> [.]
>
>> > +   priv->phy = devm_phy_get(dev , "sata-phy");
>> > +   if (IS_ERR(priv->phy))
>> > +   return PTR_ERR(priv->phy);
>
> [.]
>
>> Also please take a look at the following patch:
>>
>> https://lkml.org/lkml/2013/9/19/173
>>
>> it adds PHY support to ahci_platform driver, maybe it can be used
>> for your needs as well.
>
> I also agree with Bartlomiej Zolnierkiewicz's opinion.
> 'ahci_exynos.c' just calls PHY API, without any additional control
> for Exynos AHCI IP.
In addition to PHY handling,it also deals with the special clock
sclk_sata which is not dealt in ahci_platform.c(certainly exynos
specific).

Morever there is a wrapper driver to handle the platform specific
things for the sata.Please refer the  patch[1]
[1]ata: ti_sata: Add Texas Instruments SATA Wrapper driver
https://lkml.org/lkml/2013/9/19/166

[2]ahci_imx: add ahci sata support on imx platforms

I think, if we have platform specific driver like ahci_xxx.c , it
would be better to handle the sata PHY in ahci_xxx.c so that we can
retain and re-use the ahci_platform.c as it is.

Further comments will be much appreciated.

>
> Best regards,
> Jingoo Han
>
>>
>> > +   ret = phy_init(priv->phy);
>> > +   if (ret < 0) {
>> > +   dev_err(dev, "failed to init SATA PHY\n");
>> > +   return ret;
>> > +   }
>> > +
>
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[PATCH] i2c: s3c2410 : Add polling mode support

[Yuvaraj Kumar C D]

From: Vasanth Ananthan 

This patch adds polling mode support for i2c-s3c2410 driver.The
SATA PHY controller's CMU and TRSV block's are of I2C register
map in exynos5250.These blocks can be configured using i2c.

But i2c controller instance on which these block's sits lacks an
interrupt line.Also the current i2c-s3c2410 driver is only interrupt
driven, thus a polling mode support is required in the driver for
supporting this controller. This patch adds this support to the driver.

Signed-off-by: Vasanth Ananthan 
Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
 drivers/i2c/busses/i2c-s3c2410.c   |   68 
 2 files changed, 59 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt 
b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index 296eb45..bc928a0 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
@@ -10,6 +10,8 @@ Required properties:
   inside HDMIPHY block found on several samsung SoCs
   (d) "samsung, exynos5440-i2c", for s3c2440-like i2c used
   on EXYNOS5440 which does not need GPIO configuration.
+  (e) "samsung,exynos5-sata-phy-i2c", for s3c2440-like i2c used as
+  a host to SATA PHY controller on an internal bus.
   - reg: physical base address of the controller and length of memory mapped
 region.
   - interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 3535f3c..2b279d0 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -85,6 +85,7 @@
 #define QUIRK_S3C2440  (1 << 0)
 #define QUIRK_HDMIPHY  (1 << 1)
 #define QUIRK_NO_GPIO  (1 << 2)
+#define QUIRK_POLL (1 << 3)
 
 /* Max time to wait for bus to become idle after a xfer (in us) */
 #define S3C2410_IDLE_TIMEOUT   5000
@@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 
+static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long 
iicstat);
+
 #ifdef CONFIG_OF
 static const struct of_device_id s3c24xx_i2c_match[] = {
{ .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
@@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
  .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
{ .compatible = "samsung,exynos5440-i2c",
  .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
+   { .compatible = "samsung,exynos5-sata-phy-i2c",
+ .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
{},
 };
 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
@@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct 
s3c24xx_i2c *i2c, int ret)
if (ret)
i2c->msg_idx = ret;
 
-   wake_up(&i2c->wait);
+   if (!(i2c->quirks & QUIRK_POLL))
+   wake_up(&i2c->wait);
 }
 
 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
@@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct 
s3c24xx_i2c *i2c)
writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 }
 
+static bool is_ack(struct s3c24xx_i2c *i2c)
+{
+   u32 time_out = i2c->tx_setup;
+
+   while (--time_out) {
+   if (readl(i2c->regs + S3C2410_IICCON)
+   & S3C2410_IICCON_IRQPEND) {
+   if (!(readl(i2c->regs + S3C2410_IICSTAT)
+   & S3C2410_IICSTAT_LASTBIT))
+   return true;
+   }
+   udelay(time_out);
+   }
+
+   return false;
+}
 
 /* s3c24xx_i2c_message_start
  *
@@ -268,6 +290,16 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c 
*i2c,
 
stat |= S3C2410_IICSTAT_START;
writel(stat, i2c->regs + S3C2410_IICSTAT);
+
+   if (i2c->quirks & QUIRK_POLL) {
+   while ((i2c->msg_num != 0) && is_ack(i2c)) {
+   i2c_s3c_irq_nextbyte(i2c, stat);
+   stat = readl(i2c->regs + S3C2410_IICSTAT);
+
+   if (stat & S3C2410_IICSTAT_ARBITR)
+   dev_err(i2c->dev, "deal with arbitration 
loss\n");
+   }
+   }
 }
 
 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
@@ -675,6 +707,15 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
s3c24xx_i2c_enable_irq(i2c);
s3c24xx_i2c_message_start(i2c, msgs);
 
+   if (i2c->quirks & QUIRK_POLL) {
+   ret = i2c->msg_idx;
+
+   if (ret != num)
+   dev_dbg(i2

[PATCH 2/3] Phy: Exynos: Add Exynos5250 sata phy driver

[Yuvaraj Kumar C D]

This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
phy comprises of CMU and TRSV blocks which are of I2C register Map.
So this patch also adds a i2c client driver, which is used configure
the CMU and TRSV block of exynos5250 SATA PHY.

This patch incorporates the generic phy framework to deal with sata
phy.

This patch depends on the below patch
[1].drivers: phy: add generic PHY framework
by Kishon Vijay Abraham I

Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Girish K S 
Signed-off-by: Vasanth Ananthan 
---
 drivers/phy/Kconfig  |6 +
 drivers/phy/Makefile |1 +
 drivers/phy/exynos/Kconfig   |5 +
 drivers/phy/exynos/Makefile  |5 +
 drivers/phy/exynos/exynos5250_phy_i2c.c  |   53 +++
 drivers/phy/exynos/sata_phy_exynos5250.c |  248 ++
 drivers/phy/exynos/sata_phy_exynos5250.h |   33 
 7 files changed, 351 insertions(+)
 create mode 100644 drivers/phy/exynos/Kconfig
 create mode 100644 drivers/phy/exynos/Makefile
 create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
 create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
 create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5f85909..ab3d1c6 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -11,3 +11,9 @@ menuconfig GENERIC_PHY
  devices present in the kernel. This layer will have the generic
  API by which phy drivers can create PHY using the phy framework and
  phy users can obtain reference to the PHY.
+
+if GENERIC_PHY
+
+source "drivers/phy/exynos/Kconfig"
+
+endif
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9e9560f..e0223d7 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_GENERIC_PHY)  += phy-core.o
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += exynos/
diff --git a/drivers/phy/exynos/Kconfig b/drivers/phy/exynos/Kconfig
new file mode 100644
index 000..fa125fb
--- /dev/null
+++ b/drivers/phy/exynos/Kconfig
@@ -0,0 +1,5 @@
+config PHY_SAMSUNG_SATA
+   tristate "Samsung Sata SerDes/PHY driver"
+   help
+ Support for Samsung sata SerDes/Phy found on Samsung
+ SoCs.
diff --git a/drivers/phy/exynos/Makefile b/drivers/phy/exynos/Makefile
new file mode 100644
index 000..50dc7eb
--- /dev/null
+++ b/drivers/phy/exynos/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the exynos phy drivers.
+#
+ccflags-y := -Idrivers/phy/exynos
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += sata_phy_exynos5250.o exynos5250_phy_i2c.o
diff --git a/drivers/phy/exynos/exynos5250_phy_i2c.c 
b/drivers/phy/exynos/exynos5250_phy_i2c.c
new file mode 100644
index 000..9c75d3b
--- /dev/null
+++ b/drivers/phy/exynos/exynos5250_phy_i2c.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Author:
+ * Yuvaraj C D 
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include "sata_phy_exynos5250.h"
+
+static int exynos_sata_i2c_probe(struct i2c_client *client,
+   const struct i2c_device_id *i2c_id)
+{
+   sataphy_attach_i2c_client(client);
+
+   dev_info(&client->adapter->dev,
+   "attached %s into i2c adapter successfully\n",
+   client->name);
+
+   return 0;
+}
+
+static int exynos_sata_i2c_remove(struct i2c_client *client)
+{
+   dev_info(&client->adapter->dev,
+   "detached %s from i2c adapter successfully\n",
+   client->name);
+
+   return 0;
+}
+
+static const struct i2c_device_id phy_i2c_device_match[] = {
+   { "sata-phy-i2c", 0 },
+};
+MODULE_DEVICE_TABLE(of, phy_i2c_device_match);
+
+struct i2c_driver sataphy_i2c_driver = {
+   .probe= exynos_sata_i2c_probe,
+   .id_table = phy_i2c_device_match,
+   .remove = exynos_sata_i2c_remove,
+   .driver   = {
+   .name = "sata-phy-i2c",
+   .owner = THIS_MODULE,
+   .of_match_table = (void *)phy_i2c_device_match,
+   },
+};
diff --git a/drivers/phy/exynos/sata_phy_exynos5250.c 
b/drivers/phy/exynos/sata_phy_exynos5250.c
new file mode 100644
index 000..726c10e
--- /dev/null
+++ b/drivers/phy/exynos/sata_phy_exynos5250.c
@@ -0,0 +1,248 @@
+/*
+ * Samsung SATA SerDes(PHY) driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Authors: Girish K S 
+ * Yuvaraj Kumar C D 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the F

[PATCH 3/3] ARM: dts: Enable ahci sata and sata phy

[Yuvaraj Kumar C D]

This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5250-arndale.dts  |9 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts |6 +-
 arch/arm/boot/dts/exynos5250.dtsi |   21 +
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..50db341 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -363,7 +363,14 @@
};
 
i2c@121D {
-   status = "disabled";
+   samsung,i2c-sda-delay = <100>;
+   samsung,i2c-max-bus-freq = <4>;
+   samsung,i2c-slave-addr = <0x38>;
+
+   sata-phy {
+   compatible = "sata-phy-i2c";
+   reg = <0x38>;
+   };
};
 
dwmmc_0: dwmmc0@1220 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..21b4b25a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -91,15 +91,11 @@
samsung,i2c-slave-addr = <0x38>;
 
sata-phy {
-   compatible = "samsung,sata-phy";
+   compatible = "sata-phy-i2c";
reg = <0x38>;
};
};
 
-   sata@122F {
-   samsung,sata-freq = <66>;
-   };
-
i2c@12C8 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 668ce5d..46a0e3b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,7 @@
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
+   i2c9 = &i2c_9;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -216,16 +217,28 @@
};
 
sata@122F {
-   compatible = "samsung,exynos5-sata-ahci";
+   compatible = "samsung,exynos5250-sata-ahci";
+   samsung,sata-freq = <66>;
reg = <0x122F 0x1ff>;
interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
+   phys = <&sata_phy>;
+   phy-names = "sata-phy";
};
 
-   sata-phy@1217 {
-   compatible = "samsung,exynos5-sata-phy";
+   sata_phy:sata-phy@1217 {
+   compatible = "samsung,exynos5250-sata-phy";
reg = <0x1217 0x1ff>;
+   clocks = <&clock 287>;
+   clock-names = "sata_phyctrl";
+   #phy-cells = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   sataphy-pmu {
+   reg = <0x10040724 0x4>;
+   };
};
 
i2c_0: i2c@12C6 {
@@ -334,7 +347,7 @@
clock-names = "i2c";
};
 
-   i2c@121D {
+   i2c_9: i2c@121D {
 compatible = "samsung,exynos5-sata-phy-i2c";
 reg = <0x121D 0x100>;
 #address-cells = <1>;
-- 
1.7.9.5

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[PATCH 0/3] Exynos5250 SATA Support

[Yuvaraj Kumar C D]

This series adds the SATA support on exynos5250 SOC.Also it 
uses generic phy framework patch[1] posted by Kishon Vijay 
Abraham I. 
[1].drivers: phy: add generic PHY framework.

Yuvaraj Kumar C D (3):
  ahci: exynos: add ahci sata support on Exynos platform
  Phy: Exynos: Add Exynos5250 sata phy driver
  ARM: dts: Enable ahci sata and sata phy

 arch/arm/boot/dts/exynos5250-arndale.dts  |9 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts |6 +-
 arch/arm/boot/dts/exynos5250.dtsi |   21 ++-
 drivers/ata/Kconfig   |9 ++
 drivers/ata/Makefile  |1 +
 drivers/ata/ahci_exynos.c |  226 ++
 drivers/phy/Kconfig   |6 +
 drivers/phy/Makefile  |1 +
 drivers/phy/exynos/Kconfig|5 +
 drivers/phy/exynos/Makefile   |5 +
 drivers/phy/exynos/exynos5250_phy_i2c.c   |   53 ++
 drivers/phy/exynos/sata_phy_exynos5250.c  |  248 +
 drivers/phy/exynos/sata_phy_exynos5250.h  |   33 
 13 files changed, 613 insertions(+), 10 deletions(-)
 create mode 100644 drivers/ata/ahci_exynos.c
 create mode 100644 drivers/phy/exynos/Kconfig
 create mode 100644 drivers/phy/exynos/Makefile
 create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
 create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
 create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h

-- 
1.7.9.5

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[PATCH 1/3] ahci: exynos: add ahci sata support on Exynos platform

[Yuvaraj Kumar C D]

Exynos5250 contains one Synopsys AHCI SATA controller.The avalaible
ahci_platform driver is not sufficient to handle the AHCI PHY and PHY
clock related initialization.

This patch adds exynos specific ahci sata driver,contained the exynos
specific initialized codes, re-use the generic ahci_platform driver, and
keep the generic ahci_platform driver clean as much as possible.

This patch depends on the below patch
[1].drivers: phy: add generic PHY framework
by Kishon Vijay Abraham I

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/ata/Kconfig   |9 ++
 drivers/ata/Makefile  |1 +
 drivers/ata/ahci_exynos.c |  226 +
 3 files changed, 236 insertions(+)
 create mode 100644 drivers/ata/ahci_exynos.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4e73772..99b2392 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -106,6 +106,15 @@ config AHCI_IMX
 
  If unsure, say N.
 
+config AHCI_EXYNOS
+   tristate "Samsung Exynos AHCI SATA support"
+   depends on SATA_AHCI_PLATFORM
+   help
+ This option enables support for the Samsung's Exynos SoC's
+ onboard AHCI SATA.
+
+ If unsure, say N.
+
 config SATA_FSL
tristate "Freescale 3.0Gbps SATA support"
depends on FSL_SOC
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 46518c6..0e1f420f 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)  += sata_sil24.o
 obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
 obj-$(CONFIG_SATA_HIGHBANK)+= sata_highbank.o libahci.o
 obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
+obj-$(CONFIG_AHCI_EXYNOS)  += ahci_exynos.o
 
 # SFF w/ custom DMA
 obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
diff --git a/drivers/ata/ahci_exynos.c b/drivers/ata/ahci_exynos.c
new file mode 100644
index 000..7f0af00
--- /dev/null
+++ b/drivers/ata/ahci_exynos.c
@@ -0,0 +1,226 @@
+/*
+ * Samsung AHCI SATA platform driver
+ * Copyright 2013 Samsung Electronics Co., Ltd.
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "ahci.h"
+
+#define MHZ (1000 * 1000)
+
+struct exynos_ahci_priv {
+   struct platform_device *ahci_pdev;
+   struct clk *sclk;
+   unsigned int freq;
+   struct phy *phy;
+};
+
+static int exynos_sata_init(struct device *dev, void __iomem *mmio)
+{
+   struct exynos_ahci_priv *priv = dev_get_drvdata(dev->parent);
+   int ret;
+
+   priv->phy = devm_phy_get(dev , "sata-phy");
+   if (IS_ERR(priv->phy))
+   return PTR_ERR(priv->phy);
+
+   ret = phy_init(priv->phy);
+   if (ret < 0) {
+   dev_err(dev, "failed to init SATA PHY\n");
+   return ret;
+   }
+
+   ret = clk_prepare_enable(priv->sclk);
+   if (ret < 0) {
+   dev_err(dev, "failed to enable source clk\n");
+   return ret;
+   }
+
+   ret = clk_set_rate(priv->sclk, priv->freq * MHZ);
+   if (ret < 0) {
+   dev_err(dev, "failed to set clk frequency\n");
+   clk_disable_unprepare(priv->sclk);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void exynos_sata_exit(struct device *dev)
+{
+   struct exynos_ahci_priv *priv = dev_get_drvdata(dev->parent);
+   if (!IS_ERR(priv->sclk))
+   clk_disable_unprepare(priv->sclk);
+}
+
+static int exynos_sata_suspend(struct device *dev)
+{
+   struct exynos_ahci_priv *priv = dev_get_drvdata(dev->parent);
+
+   if (!IS_ERR(priv->sclk))
+   clk_disable_unprepare(priv->sclk);
+   phy_power_off(priv->phy);
+   return 0;
+}
+
+static int exynos_sata_resume(struct device *dev)
+{
+   struct exynos_ahci_priv *priv = dev_get_drvdata(dev->parent);
+   phy_power_on(priv->phy);
+   exynos_sata_init(dev, NULL);
+   return 0;
+}
+
+static struct ahci_platform_data exynos_sata_pdata = {
+   .init = exynos_sata_init,
+   .exit = exynos_sata_exit,
+   .suspend = exynos_sata_suspend,
+   .

Re: [PATCH V7] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

Hi Kukjin,
 Can you please take this patch to your tree?

Best Regards
Yuvaraj

On Tue, Sep 3, 2013 at 11:30 AM, Yuvaraj Kumar C D  wrote:
> This patch adds the mmc device tree node entries for exynos5420 SOC.
> Exynos5420 has a different version of DWMMC controller,so a new
> compatible string is used to distinguish it from the prior SOC's.
>
> This patch depends on
> [1]mmc: dw_mmc: exynos: configure SMU in exynos5420
> [2]mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
> [3]mmc: dw_mmc: update binding document exynos-dw-mshc.txt
>
> changes since v6:
> 1.renamed node name to mmc
> 2.Used compatible string "samsung,exynos5420-dw-mshc"
>   for controller instance which does not have SMU.
> 3.Used compatible string "samsung,exynos5420-dw-mshc-smu"
>   for controller instance which has SMU.
>
> changes since v5:
> 1.removed instance index from node name.
> 2.changed the node name to mshc.
> 3.changed the reg property value for mshc_2.
>
> changes since v4:
> 1.Droppped the bypass-smu binding property.
> 2.Used compatible string "samsung,exynos5250-dw-mshc"
>   for controller instance which does not have SMU.
>
> changes since V3:
> 1.change fifo-depth size from 0x80 to 0x40
> 2.Move the below properties
> a.card-detect-delay
> b.samsung,dw-mshc-ciu-div
> c.samsung,dw-mshc-sdr-timing
> d.samsung,dw-mshc-ddr-timing
> from SOC dts to board dts file as suggested by Doug Anderson
>
> changes since V2:
> 1.dropped num-slots property from node as its not required
>   if number of card slots available is 1.
>
> 2.Move the below properties
> a.fifo-depth
> b.card-detect-delay
> c.samsung,dw-mshc-ciu-div
> d.samsung,dw-mshc-sdr-timing
> e.samsung,dw-mshc-ddr-timing
> from board dts to SOC dts,as these are not board specific properties.
>
> 3.Updated the binding document exynos-dw-mshc.txt.
>
> changes since V1:
> 1.disable node by status = disabled in SOC file
> 2.enable node by status = okay in board specific file
>
> Signed-off-by: Yuvaraj Kumar C D 
> ---
>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33 +
>  arch/arm/boot/dts/exynos5420.dtsi  |   39 
> 
>  3 files changed, 74 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> index 6d1c098..84cd56f 100644
> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
> @@ -16,6 +16,8 @@ Required Properties:
>   specific extensions.
> - "samsung,exynos5250-dw-mshc": for controllers with Samsung 
> Exynos5250
>   specific extensions.
> +   - "samsung,exynos5420-dw-mshc": for controllers with Samsung 
> Exynos5420
> + specific extensions.
>
>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
>unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
> b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index bafba25..8df4ddc 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -31,6 +31,39 @@
> };
> };
>
> +   mmc@1220 {
> +   status = "okay";
> +   broken-cd;
> +   supports-highspeed;
> +   card-detect-delay = <200>;
> +   samsung,dw-mshc-ciu-div = <3>;
> +   samsung,dw-mshc-sdr-timing = <0 4>;
> +   samsung,dw-mshc-ddr-timing = <0 2>;
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
> +
> +   slot@0 {
> +   reg = <0>;
> +   bus-width = <8>;
> +   };
> +   };
> +
> +   mmc@1222 {
> +   status = "okay";
> +   supports-highspeed;
> +   card-detect-delay = <200>;
> +   samsung,dw-mshc-ciu-div = <3>;
> +   samsung,dw-mshc-sdr-timing = <2 3>;
>

Re: [PATCH] ARM: dts: Update arch timer node with clock frequency

[Yuvaraj Kumar]

Resending it as it bounced from kernel mailing group

On Wed, Sep 18, 2013 at 3:53 PM, Mark Rutland  wrote:
> [adding lakml]
>
> On Wed, Sep 18, 2013 at 11:11:53AM +0100, Yuvaraj Kumar C D wrote:
>> Without the "clock-frequency" property in arch timer node, could able
>> to see the below crash dump.
>
> Why does this cause the below crash specifically? What is CNTFRQ reading
> as?
Return value of arch_timer_get_cntfrq() is 0
>
> Your firmware or bootloader should set CNTFRQ -- setting the
> clock-frequency is a work-around for buggy firmware/bootloaders that
> should be avoided as far as possible.
Why kernel should depend on bootloader/firmware  to set CNTFRQ? Any
specific reasons?
Should'nt be indepenedent each other(kernel and bootloader/firmware)?
>
> Is it not possible to fix your firmware or bootlaoder to set CNTFRQ?
>
> Thanks,
> Mark.
>
>>
>> [] (unwind_backtrace+0x0/0xf4) from [] 
>> (show_stack+0x10/0x14)
>> [] (show_stack+0x10/0x14) from [] (dump_stack+0x7c/0xb0)
>> [] (dump_stack+0x7c/0xb0) from [] (Ldiv0_64+0x8/0x18)
>> [] (Ldiv0_64+0x8/0x18) from [] 
>> (clockevents_config.part.2+0x1c/0x74)
>> [] (clockevents_config.part.2+0x1c/0x74) from [] 
>> (clockevents_config_and_register+0x20/0x2c)
>> [] (clockevents_config_and_register+0x20/0x2c) from [] 
>> (arch_timer_setup+0xa8/0x134)
>> [] (arch_timer_setup+0xa8/0x134) from [] 
>> (arch_timer_init+0x1f4/0x24c)
>> [] (arch_timer_init+0x1f4/0x24c) from [] 
>> (clocksource_of_init+0x34/0x58)
>> [] (clocksource_of_init+0x34/0x58) from [] 
>> (time_init+0x20/0x2c)
>> [] (time_init+0x20/0x2c) from [] 
>> (start_kernel+0x1e0/0x39c)
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  arch/arm/boot/dts/exynos5250.dtsi |1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
>> b/arch/arm/boot/dts/exynos5250.dtsi
>> index 7d7cc77..668ce5d 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -96,6 +96,7 @@
>><1 14 0xf08>,
>><1 11 0xf08>,
>><1 10 0xf08>;
>> + clock-frequency = <2400>;
>>   };
>>
>>   mct@101C {
>> --
>> 1.7.9.5
>>
>>
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[PATCH] ARM: dts: Update arch timer node with clock frequency

[Yuvaraj Kumar C D]

Without the "clock-frequency" property in arch timer node, could able
to see the below crash dump.

[] (unwind_backtrace+0x0/0xf4) from [] 
(show_stack+0x10/0x14)
[] (show_stack+0x10/0x14) from [] (dump_stack+0x7c/0xb0)
[] (dump_stack+0x7c/0xb0) from [] (Ldiv0_64+0x8/0x18)
[] (Ldiv0_64+0x8/0x18) from [] 
(clockevents_config.part.2+0x1c/0x74)
[] (clockevents_config.part.2+0x1c/0x74) from [] 
(clockevents_config_and_register+0x20/0x2c)
[] (clockevents_config_and_register+0x20/0x2c) from [] 
(arch_timer_setup+0xa8/0x134)
[] (arch_timer_setup+0xa8/0x134) from [] 
(arch_timer_init+0x1f4/0x24c)
[] (arch_timer_init+0x1f4/0x24c) from [] 
(clocksource_of_init+0x34/0x58)
[] (clocksource_of_init+0x34/0x58) from [] 
(time_init+0x20/0x2c)
[] (time_init+0x20/0x2c) from [] (start_kernel+0x1e0/0x39c)

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5250.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc77..668ce5d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -96,6 +96,7 @@
 <1 14 0xf08>,
 <1 11 0xf08>,
 <1 10 0xf08>;
+   clock-frequency = <2400>;
};
 
mct@101C {
-- 
1.7.9.5

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Re: [RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar]

On Thu, Sep 5, 2013 at 1:01 AM, Dinh Nguyen  wrote:
> On Thu, 2013-08-29 at 20:59 +0900, Seungwon Jeon wrote:
>> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> > Currently platform specific private data initialisation is done by
>> > dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
>> > separate platform specific device tree parser dw_mci_socfpga_parse_dt,
>> > move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
>> > We can use the dw_mci_socfpga_priv_init to do some actual platform
>> > specific initialisation.
>
> I am looking to remove all of dw_mmc-socfpga file. The only reason for
> this file is to set the sdr timing values. But since the register that
> controls these SDR values are located out of the IP, it is probably best
> to implement the settings in platform specific code.
Well,This patch is included in this series becuase PATCHV4 3/4 of this
sereis will affect
dw_mmc-socfpga driver. However, if you are planning to remove the
whole file,still you can do
on top of this patch. :)
>
> Dinh
>> >
>> > This patch is compile tested only.
>> CC'ed Dinh Nguyen
>>
>> Thanks,
>> Seungwon Jeon
>>
>> >
>> > changes since V2: none
>> >
>> > Signed-off-by: Yuvaraj Kumar C D 
>> > ---
>> >  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++---
>> >  1 file changed, 14 insertions(+), 15 deletions(-)
>> >
>> > diff --git a/drivers/mmc/host/dw_mmc-socfpga.c 
>> > b/drivers/mmc/host/dw_mmc-socfpga.c
>> > index 14b5961..953f260 100644
>> > --- a/drivers/mmc/host/dw_mmc-socfpga.c
>> > +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> > @@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
>> >
>> >  static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> >  {
>> > -   struct dw_mci_socfpga_priv_data *priv;
>> > -
>> > -   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> > -   if (!priv) {
>> > -   dev_err(host->dev, "mem alloc failed for private data\n");
>> > -   return -ENOMEM;
>> > -   }
>> > -
>> > -   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> > -   if (IS_ERR(priv->sysreg)) {
>> > -   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> > -   return PTR_ERR(priv->sysreg);
>> > -   }
>> > -   host->priv = priv;
>> >
>> > return 0;
>> >  }
>> > @@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct 
>> > dw_mci *host, u32 *cmdr)
>> >
>> >  static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> >  {
>> > -   struct dw_mci_socfpga_priv_data *priv = host->priv;
>> > +   struct dw_mci_socfpga_priv_data *priv;
>> > struct device_node *np = host->dev->of_node;
>> > u32 timing[2];
>> > u32 div = 0;
>> > int ret;
>> >
>> > +   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> > +   if (!priv) {
>> > +   dev_err(host->dev, "mem alloc failed for private data\n");
>> > +   return -ENOMEM;
>> > +   }
>> > +
>> > +   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> > +   if (IS_ERR(priv->sysreg)) {
>> > +   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> > +   return PTR_ERR(priv->sysreg);
>> > +   }
>> > +
>> > ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
>> > if (ret)
>> > dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 
>> > 1");
>> > @@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> > return ret;
>> >
>> > priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
>> > +   host->priv = priv;
>> > return 0;
>> >  }
>> >
>> > --
>> > 1.7.9.5
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> > the body of a message to majord...@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>>
>
>
>
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Re: [PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Mon, Sep 2, 2013 at 5:51 PM, Tomasz Figa  wrote:
> On Monday 02 of September 2013 16:45:41 Yuvaraj Kumar wrote:
>> On Fri, Aug 30, 2013 at 12:29 PM, Yuvaraj Kumar 
> wrote:
>> > On Wed, Aug 28, 2013 at 5:52 PM, Tomasz Figa 
> wrote:
>> >> Hi Yuvaraj,
>> >>
>> >> On Wednesday 28 of August 2013 17:33:06 Yuvaraj Kumar C D wrote:
>> >>> This patch adds the device tree node entries for exynos5420 SOC.
>> >>> Exynos5420 has a different version of DWMMC controller,so a new
>> >>> compatible string is used to distinguish it from the prior SOC's.
>> >>>
>> >>> This patch depends on
>> >>>
>> >>>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>> >>>
>> >>> changes since v4:
>> >>>   1.Droppped the bypass-smu binding property.
>> >>>   2.Used compatible string "samsung,exynos5250-dw-mshc"
>> >>>
>> >>> for controller instance which does not have SMU.
>> >>>
>> >>> changes since V3:
>> >>>   1.change fifo-depth size from 0x80 to 0x40
>> >>>   2.Move the below properties
>> >>>
>> >>>   a.card-detect-delay
>> >>>   b.samsung,dw-mshc-ciu-div
>> >>>   c.samsung,dw-mshc-sdr-timing
>> >>>   d.samsung,dw-mshc-ddr-timing
>> >>>
>> >>>   from SOC dts to board dts file as suggested by Doug Anderson
>> >>>
>> >>> changes since V2:
>> >>>   1.dropped num-slots property from node as its not required
>> >>>
>> >>> if number of card slots available is 1.
>> >>>
>> >>>   2.Move the below properties
>> >>>
>> >>>   a.fifo-depth
>> >>>   b.card-detect-delay
>> >>>   c.samsung,dw-mshc-ciu-div
>> >>>   d.samsung,dw-mshc-sdr-timing
>> >>>   e.samsung,dw-mshc-ddr-timing
>> >>>
>> >>>   from board dts to SOC dts,as these are not board specific
>> >>>   properties.
>> >>>
>> >>>   3.Updated the binding document exynos-dw-mshc.txt.
>> >>>
>> >>> changes since V1:
>> >>>   1.disable node by status = disabled in SOC file
>> >>>   2.enable node by status = okay in board specific file
>> >>>
>> >>> Signed-off-by: Yuvaraj Kumar C D 
>> >>> ---
>> >>>
>> >>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>> >>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33
>> >>>
>> >>> + arch/arm/boot/dts/exynos5420.dtsi
>> >>> |
>> >>> 39  3 files changed, 74 insertions(+)
>> >>
>> >> This patch looks good to me now, except some minor comments below.
>> >>
>> >>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>> >>> 6d1c098..84cd56f 100644
>> >>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >>>
>> >>> @@ -16,6 +16,8 @@ Required Properties:
>> >>> specific extensions.
>> >>>
>> >>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung
>> >>>   Exynos5250
>> >>>
>> >>> specific extensions.
>> >>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung
>> >>> Exynos5420 +   specific extensions.
>> >>>
>> >>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>> >>>
>> >>> interface unit (ciu) clock. This property is applicable only for
>> >>> Exynos5
>> >>> SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> >>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..3ce5c97
>> >>> 100644
>> >>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> >>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> >>> @

[PATCH V4 3/4] ARM: dts: Move fifo-depth property from board dts

[Yuvaraj Kumar C D]

As fifo-depth property in dw_mmc device tree node is SOC
specific, move this property to exynos5250 SOC specific
file.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5250-arndale.dts  |2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts |2 --
 arch/arm/boot/dts/exynos5250.dtsi |4 
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index a4dc784..176ef16 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -371,7 +371,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -390,7 +389,6 @@
status = "okay";
num-slots = <1>;
supports-highspeed;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index bd19d55d..5a4831d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -145,7 +145,6 @@
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
@@ -163,7 +162,6 @@
status = "okay";
num-slots = <1>;
supports-highspeed;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 300e4e6..fb28d21 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -395,6 +395,7 @@
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
status = "disabled";
};
 
@@ -406,6 +407,7 @@
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
status = "disabled";
};
 
@@ -417,6 +419,7 @@
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
status = "disabled";
};
 
@@ -428,6 +431,7 @@
#size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
status = "disabled";
};
 
-- 
1.7.9.5

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[PATCH V4 2/4] ARM: dts: exynos: change status property of dwmmc nodes

[Yuvaraj Kumar C D]

According to ePAPR, chapter 2.3.4, the status property has
defined that it should be set to "disabled" when "the device
is not presently operational, but it might become operational
in the future".

So this patch disable dwmmc node by "status = disabled" in SOC
dts file and enable dwmmc node by "status = okay" in board specific
dts file.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5250-arndale.dts  |   10 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   10 ++
 arch/arm/boot/dts/exynos5250.dtsi |4 
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index cee55fa..a4dc784 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -367,6 +367,7 @@
};
 
dwmmc_0: dwmmc0@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -385,11 +386,8 @@
};
};
 
-   dwmmc_1: dwmmc1@1221 {
-   status = "disabled";
-   };
-
dwmmc_2: dwmmc2@1222 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -408,10 +406,6 @@
};
};
 
-   dwmmc_3: dwmmc3@1223 {
-   status = "disabled";
-   };
-
spi_0: spi@12d2 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
 
dwmmc0@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
 
-   dwmmc1@1221 {
-   status = "disabled";
-   };
-
dwmmc2@1222 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -180,10 +178,6 @@
};
};
 
-   dwmmc3@1223 {
-   status = "disabled";
-   };
-
spi_0: spi@12d2 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index d42844b..300e4e6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -395,6 +395,7 @@
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_1: dwmmc1@1221 {
@@ -405,6 +406,7 @@
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_2: dwmmc2@1222 {
@@ -415,6 +417,7 @@
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_3: dwmmc3@1223 {
@@ -425,6 +428,7 @@
#size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
i2s0: i2s@0383 {
-- 
1.7.9.5

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[PATCH V4 4/4] ARM: dts: rename mmc dts node for exynos5 series

[Yuvaraj Kumar C D]

This patch rename's the device tree mmc node's from "dwmmc" to "mmc".
According to ePAPR chapter 2.2.2 generic node name recommendation,
it has been opted change from dwmmc to mmc.Also this patch remove the
instance index from the node name.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/cros5250-common.dtsi|8 
 arch/arm/boot/dts/exynos5250-arndale.dts  |4 ++--
 arch/arm/boot/dts/exynos5250-smdk5250.dts |4 ++--
 arch/arm/boot/dts/exynos5250-snow.dts |2 +-
 arch/arm/boot/dts/exynos5250.dtsi |   16 
 5 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/cros5250-common.dtsi 
b/arch/arm/boot/dts/cros5250-common.dtsi
index dc259e8b..6470536 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -229,7 +229,7 @@
};
};
 
-   dwmmc0@1220 {
+   mmc@1220 {
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -247,11 +247,11 @@
};
};
 
-   dwmmc1@1221 {
+   mmc@1221 {
status = "disabled";
};
 
-   dwmmc2@1222 {
+   mmc@1222 {
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -269,7 +269,7 @@
};
};
 
-   dwmmc3@1223 {
+   mmc@1223 {
num-slots = <1>;
supports-highspeed;
broken-cd;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 176ef16..418f869 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -366,7 +366,7 @@
status = "disabled";
};
 
-   dwmmc_0: dwmmc0@1220 {
+   mmc_0: mmc@1220 {
status = "okay";
num-slots = <1>;
supports-highspeed;
@@ -385,7 +385,7 @@
};
};
 
-   dwmmc_2: dwmmc2@1222 {
+   mmc_2: mmc@1222 {
status = "okay";
num-slots = <1>;
supports-highspeed;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 5a4831d..99784ec 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -140,7 +140,7 @@
};
};
 
-   dwmmc0@1220 {
+   mmc@1220 {
status = "okay";
num-slots = <1>;
supports-highspeed;
@@ -158,7 +158,7 @@
};
};
 
-   dwmmc2@1222 {
+   mmc@1222 {
status = "okay";
num-slots = <1>;
supports-highspeed;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts 
b/arch/arm/boot/dts/exynos5250-snow.dts
index fd711e2..a9395c4 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -175,7 +175,7 @@
 * On Snow we've got SIP WiFi and so can keep drive strengths low to
 * reduce EMI.
 */
-   dwmmc3@1223 {
+   mmc@1223 {
slot@0 {
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index fb28d21..9922d1e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -33,10 +33,10 @@
gsc1 = &gsc_1;
gsc2 = &gsc_2;
gsc3 = &gsc_3;
-   mshc0 = &dwmmc_0;
-   mshc1 = &dwmmc_1;
-   mshc2 = &dwmmc_2;
-   mshc3 = &dwmmc_3;
+   mshc0 = &mmc_0;
+   mshc1 = &mmc_1;
+   mshc2 = &mmc_2;
+   mshc3 = &mmc_3;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
@@ -387,7 +387,7 @@
pinctrl-0 = <&spi2_bus>;
};
 
-   dwmmc_0: dwmmc0@1220 {
+   mmc_0: mmc@1220 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 75 0>;
#address-cells = <1>;
@@ -399,7 +399,7 @@
status = "disabled";
};
 
-   dwmmc_1: dwmmc1@1221 {
+   mmc_1: mmc@1221 {
compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 76 0>;
#address-cells = <1>;
@@ -411,7 +411,7 @@
status = "disabled";
};
 
-   dwmmc_2: dwmmc2@1222

[PATCH V4 0/4] exynos dwmmc device tree node cleanup

[Yuvaraj Kumar C D]

changes from V3:
1.Added two new patch in the series
[1] ARM: dts: Move fifo-depth property from board dts
[2] ARM: dts: rename mmc dts node for exynos5 series
changes from V2:
1.remove from exynos5.dtsi and add in exynos5250.dtsi
  in single patch.Suggested by Tomasz Figa.
2.Separate patch for changing status property of dwmmc node
  in smdk5250 and arndale board dts file.

V1 Patches:
1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
http://www.spinics.net/lists/linux-samsung-soc/msg21602.html
2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
http://www.spinics.net/lists/linux-samsung-soc/msg21603.html

Yuvaraj Kumar C D (4):
  ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
  ARM: dts: exynos: change status property of dwmmc nodes
  ARM: dts: Move fifo-depth property from board dts
  ARM: dts: rename mmc dts node for exynos5 series

 arch/arm/boot/dts/cros5250-common.dtsi|8 +++
 arch/arm/boot/dts/exynos5.dtsi|   21 -
 arch/arm/boot/dts/exynos5250-arndale.dts  |   16 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   16 -
 arch/arm/boot/dts/exynos5250-snow.dts |2 +-
 arch/arm/boot/dts/exynos5250.dtsi |   36 ++---
 6 files changed, 41 insertions(+), 58 deletions(-)

-- 
1.7.9.5

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[PATCH V4 1/4] ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi

[Yuvaraj Kumar C D]

Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source to SOC specific device tree source.

Changes since V3: none

Changes since V2:
1.remove from exynos5.dtsi and add in exynos5250.dtsi
  in single patch.

Changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5.dtsi|   21 -
 arch/arm/boot/dts/exynos5250.dtsi |   12 
 2 files changed, 12 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 074739d..e52b038 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = <1 9 0xf04>;
};
 
-   dwmmc_0: dwmmc0@1220 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 75 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
-   dwmmc_1: dwmmc1@1221 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 76 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
-   dwmmc_2: dwmmc2@1222 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 77 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
serial@12C0 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C0 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 864ae90..d42844b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -388,18 +388,30 @@
};
 
dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
};
 
dwmmc_1: dwmmc1@1221 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 76 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
};
 
dwmmc_2: dwmmc2@1222 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 77 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
-- 
1.7.9.5

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[PATCH V7] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the mmc device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

This patch depends on
[1]mmc: dw_mmc: exynos: configure SMU in exynos5420
[2]mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
[3]mmc: dw_mmc: update binding document exynos-dw-mshc.txt

changes since v6:
1.renamed node name to mmc
2.Used compatible string "samsung,exynos5420-dw-mshc"
  for controller instance which does not have SMU.
3.Used compatible string "samsung,exynos5420-dw-mshc-smu"
  for controller instance which has SMU.

changes since v5:
1.removed instance index from node name.
2.changed the node name to mshc.
3.changed the reg property value for mshc_2.

changes since v4:
1.Droppped the bypass-smu binding property.
2.Used compatible string "samsung,exynos5250-dw-mshc"
  for controller instance which does not have SMU.

changes since V3:
1.change fifo-depth size from 0x80 to 0x40
2.Move the below properties
a.card-detect-delay
b.samsung,dw-mshc-ciu-div
c.samsung,dw-mshc-sdr-timing
d.samsung,dw-mshc-ddr-timing
from SOC dts to board dts file as suggested by Doug Anderson

changes since V2:
1.dropped num-slots property from node as its not required
  if number of card slots available is 1.

2.Move the below properties
a.fifo-depth
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
from board dts to SOC dts,as these are not board specific properties.

3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33 +
 arch/arm/boot/dts/exynos5420.dtsi  |   39 
 3 files changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..8df4ddc 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
};
};
 
+   mmc@1220 {
+   status = "okay";
+   broken-cd;
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   mmc@1222 {
+   status = "okay";
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..897f7f4 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boo

Re: [PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Fri, Aug 30, 2013 at 12:29 PM, Yuvaraj Kumar  wrote:
> On Wed, Aug 28, 2013 at 5:52 PM, Tomasz Figa  wrote:
>> Hi Yuvaraj,
>>
>> On Wednesday 28 of August 2013 17:33:06 Yuvaraj Kumar C D wrote:
>>> This patch adds the device tree node entries for exynos5420 SOC.
>>> Exynos5420 has a different version of DWMMC controller,so a new
>>> compatible string is used to distinguish it from the prior SOC's.
>>>
>>> This patch depends on
>>>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>>>
>>> changes since v4:
>>>   1.Droppped the bypass-smu binding property.
>>>   2.Used compatible string "samsung,exynos5250-dw-mshc"
>>> for controller instance which does not have SMU.
>>>
>>> changes since V3:
>>>   1.change fifo-depth size from 0x80 to 0x40
>>>   2.Move the below properties
>>>   a.card-detect-delay
>>>   b.samsung,dw-mshc-ciu-div
>>>   c.samsung,dw-mshc-sdr-timing
>>>   d.samsung,dw-mshc-ddr-timing
>>>   from SOC dts to board dts file as suggested by Doug Anderson
>>>
>>> changes since V2:
>>>   1.dropped num-slots property from node as its not required
>>> if number of card slots available is 1.
>>>
>>>   2.Move the below properties
>>>   a.fifo-depth
>>>   b.card-detect-delay
>>>   c.samsung,dw-mshc-ciu-div
>>>   d.samsung,dw-mshc-sdr-timing
>>>   e.samsung,dw-mshc-ddr-timing
>>>   from board dts to SOC dts,as these are not board specific properties.
>>>
>>>   3.Updated the binding document exynos-dw-mshc.txt.
>>>
>>> changes since V1:
>>>   1.disable node by status = disabled in SOC file
>>>   2.enable node by status = okay in board specific file
>>>
>>> Signed-off-by: Yuvaraj Kumar C D 
>>> ---
>>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33
>>> + arch/arm/boot/dts/exynos5420.dtsi  |
>>> 39  3 files changed, 74 insertions(+)
>>
>> This patch looks good to me now, except some minor comments below.
>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>>> 6d1c098..84cd56f 100644
>>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>>> @@ -16,6 +16,8 @@ Required Properties:
>>> specific extensions.
>>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung 
>>> Exynos5250
>>> specific extensions.
>>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung 
>>> Exynos5420
>>> +   specific extensions.
>>>
>>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>>> interface unit (ciu) clock. This property is applicable only for Exynos5
>>> SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..3ce5c97
>>> 100644
>>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> @@ -31,6 +31,39 @@
>>>   };
>>>   };
>>>
>>> + dwmmc0@1220 {
>>
>> Node name should not contain instance index. Instead, according to ePAPR
>> recommendation, I would opt for a generic name such as mmc, mshc or sdio-
>> host. mshc is already used on Exynos 4 so it might be a good idea to use it
>> for consistency.
> If we change node name's to mshc, debug statements are look like below:
> dwmmc_exynos 1220.mshc: num-slots property not found, assuming 1
> slot is available
> dwmmc_exynos 1220.mshc: no vmmc regulator found: -19
> dwmmc_exynos 1220.mshc: Using internal DMA controller.
> dwmmc_exynos 1220.mshc: Version ID is 250a
> dwmmc_exynos 1220.mshc: DW MMC controller at irq 107, 64 bit host
> data width, 64 deep fifo
>
> "dwmmc_exynos" is platform driver name and "1220.mshc" from dt
> node.Is'nt it look like bit confusing?
Any comments on this?
>
>>
>> [Adding DT maintainers on CC]
>>
>> Best regards,
>> Tomasz
>>
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[PATCH] mmc: dw_mmc: update binding document exynos-dw-mshc.txt

[Yuvaraj Kumar C D]

This patch updates the exynos-dw-mshc.txt.Currently we are using
"pinctrl" binding property to describe the CMD and DATA line's
of Mobile Storage Host Controller(mshc) node.

Compatibility string is added in the driver with the patch.
[1] mmc: dw_mmc: exynos: configure SMU in exynos5420.

DT nodes has been added in separate patch.
[2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   39 +++-
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 84cd56f..0e1d4d9 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -7,9 +7,9 @@ differences between the core Synopsis dw mshc controller 
properties described
 by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific
 extensions to the Synopsis Designware Mobile Storage Host Controller.
 
-Required Properties:
+Required SoC Specific Properties:
 
-* compatible: should be
+* compatible: should be one of the following
- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
  specific extensions.
- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
@@ -17,7 +17,12 @@ Required Properties:
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
- specific extensions.
+ specific extensions which does not have SMU(Security Management Unit).
+   - "samsung,exynos5420-dw-mshc-smu": for controllers with Samsung
+ Exynos5420 specific extensions which has SMU(Security Management
+ Unit).
+
+Required Board Specific Properties:
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
@@ -46,44 +51,42 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
-
-* gpios: specifies a list of gpios used for command, clock and data bus. The
-  first gpio is the command line and the second gpio is the clock line. The
-  rest of the gpios (depending on the bus-width property) are the data lines in
-  no particular order. The format of the gpio specifier depends on the gpio
-  controller.
+* pinctrl-0: Should specify pin control groups used for this controller.
+* pinctrl-names: Should contain only one value - "default".
 
+Required properties for a slot:
+   Refer synopsis-dw-mshc.txt
 Example:
 
   The MSHC controller node can be split into two portions, SoC specific and
   board specific portions as listed below.
 
-   dwmmc0@1220 {
+   mshc@1220 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x1220 0x1000>;
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+   clocks = <&clock 351>, <&clock 132>;
+   clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
+   status = "disabled";
};
 
-   dwmmc0@1220 {
+   mshc@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
 
slot@0 {
reg = <0>;
bus-width = <8>;
-   gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
-   <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
-   <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
-   <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
-   <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
};
};
-- 
1.7.9.5

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[RFC V4 3/4] mmc: dw_mmc: move the platform specific init call

[Yuvaraj Kumar C D]

Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.

changes since V3: none
changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-pltfm.c |7 ---
 drivers/mmc/host/dw_mmc.c   |9 +
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index 2089752..5c49656 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -39,7 +39,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 {
struct dw_mci *host;
struct resource *regs;
-   int ret;
 
host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL);
if (!host)
@@ -59,12 +58,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
 
-   if (drv_data && drv_data->init) {
-   ret = drv_data->init(host);
-   if (ret)
-   return ret;
-   }
-
platform_set_drvdata(pdev, host);
return dw_mci_probe(host);
 }
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index beafb4c..0edec01 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2221,6 +2221,15 @@ int dw_mci_probe(struct dw_mci *host)
host->bus_hz = clk_get_rate(host->ciu_clk);
}
 
+   if (drv_data && drv_data->init) {
+   ret = drv_data->init(host);
+   if (ret) {
+   dev_err(host->dev,
+   "implementation specific init failed\n");
+   goto err_clk_ciu;
+   }
+   }
+
if (drv_data && drv_data->setup_clock) {
ret = drv_data->setup_clock(host);
if (ret) {
-- 
1.7.9.5

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[RFC V4 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
We can use the dw_mci_socfpga_priv_init to do some actual platform
specific initialisation.

This patch is compile tested only.

changes since V3: none
changes since V2: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-socfpga.c 
b/drivers/mmc/host/dw_mmc-socfpga.c
index 14b5961..953f260 100644
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
 
 static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-   if (IS_ERR(priv->sysreg)) {
-   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-   return PTR_ERR(priv->sysreg);
-   }
-   host->priv = priv;
 
return 0;
 }
@@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci 
*host, u32 *cmdr)
 
 static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv = host->priv;
+   struct dw_mci_socfpga_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(priv->sysreg)) {
+   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+   return PTR_ERR(priv->sysreg);
+   }
+
ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
if (ret)
dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
@@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
return ret;
 
priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[RFC V4 0/4] dw_mmc platform specific private data and SMU init

[Yuvaraj Kumar C D]

changes from V3: changes only in the patch
mmc: dw_mmc: exynos: configure SMU in exynos5420.
1.Added new compatible string "samsung,exynos5420-dw-mshc-smu" for
  the host with SMU.
2.Used compatible string "samsung,exynos5420-dw-mshc-smu"
  for controller instance which has SMU.
3.Used compatible string "samsung,exynos5420-dw-mshc"
  for controller instance which does not have SMU.

changes from V2:
1.dropped the bypass-smu quirk 
mmc: dw_mmc: exynos: configure SMU in exynos5420.
2.Changed the subject line for this patch
  add a quirk for SMU -> configure SMU in exynos5420

mmc: dw_mmc: exynos: configure SMU in exynos5420 
was earlier 
mmc: dw_mmc: exynos: add a quirk for SMU.

changes from V1:
1.Added a new RFC patch 
mmc: dw_mmc: socfpga: move socfpga private init
2.Avoid code duplication in
mmc: dw_mmc: exynos: add a quirk for SMU.


Yuvaraj Kumar C D (4):
  mmc: dw_mmc: exynos: move the exynos private init
  mmc: dw_mmc: socfpga: move socfpga private init
  mmc: dw_mmc: move the platform specific init call
  mmc: dw_mmc: exynos: configure SMU in exynos5420.

 drivers/mmc/host/dw_mmc-exynos.c  |   65 -
 drivers/mmc/host/dw_mmc-pltfm.c   |7 
 drivers/mmc/host/dw_mmc-socfpga.c |   29 -
 drivers/mmc/host/dw_mmc.c |9 +
 4 files changed, 73 insertions(+), 37 deletions(-)

-- 
1.7.9.5

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[RFC V4 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.

changes since V3: none
changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-exynos.c |   31 +++
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
 
 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv;
-   int idx;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
-   if (of_device_is_compatible(host->dev->of_node,
-   exynos_compat[idx].compatible))
-   priv->ctrl_type = exynos_compat[idx].ctrl_type;
-   }
+   struct dw_mci_exynos_priv_data *priv = host->priv;
 
-   host->priv = priv;
return 0;
 }
 
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, 
struct mmc_ios *ios)
 
 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv = host->priv;
+   struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
+   int idx;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
+   if (of_device_is_compatible(np, exynos_compat[idx].compatible))
+   priv->ctrl_type = exynos_compat[idx].ctrl_type;
+   }
+
of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
priv->ciu_div = div;
 
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
 
priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[RFC V4 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar C D]

Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
SMU for exynos5420.

This patch is on top of the below patches 
[1]mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT.
[2]ARM: dts: Add dwmmc DT nodes for exynos5420 SOC. 

changes since V3:
1.Added new compatible string "samsung,exynos5420-dw-mshc-smu" for
  the host with SMU.
2.Used compatible string "samsung,exynos5420-dw-mshc-smu"
  for controller instance which has SMU.
3.Used compatible string "samsung,exynos5420-dw-mshc"
  for controller instance which does not have SMU.

changes since V2:
1.Droppped the bypass-smu quirk.
2.Changed the subject line for this patch
  add a quirk for SMU -> configure SMU in exynos5420

changes since V1:
1.avoid code duplication by calling dw_mci_exynos_priv_init in
  resume path.

Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Alim Akhtar 
---
 drivers/mmc/host/dw_mmc-exynos.c |   38 +-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 19c845b..2f6ac82 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -35,12 +35,32 @@
 #define EXYNOS4210_FIXED_CIU_CLK_DIV   2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV   4
 
+/* Block number in eMMC */
+#define DWMCI_BLOCK_NUM0x
+
+#define SDMMC_EMMCP_BASE   0x1000
+#define SDMMC_MPSECURITY   (SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0  (SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control bits */
+#define DWMCI_MPSCTRL_SECURE_READ_BIT  BIT(7)
+#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT  BIT(5)
+#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
+#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
+#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
+#define DWMCI_MPSCTRL_ENCRYPTION   BIT(1)
+#define DWMCI_MPSCTRL_VALIDBIT(0)
+
 /* Variations in Exynos specific dw-mshc controller */
 enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS4210,
DW_MCI_TYPE_EXYNOS4412,
DW_MCI_TYPE_EXYNOS5250,
DW_MCI_TYPE_EXYNOS5420,
+   DW_MCI_TYPE_EXYNOS5420_SMU,
 };
 
 /* Exynos implementation specific driver private data */
@@ -67,6 +87,9 @@ static struct dw_mci_exynos_compatible {
}, {
.compatible = "samsung,exynos5420-dw-mshc",
.ctrl_type  = DW_MCI_TYPE_EXYNOS5420,
+   }, {
+   .compatible = "samsung,exynos5420-dw-mshc-smu",
+   .ctrl_type  = DW_MCI_TYPE_EXYNOS5420_SMU,
},
 };
 
@@ -74,6 +97,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv = host->priv;
 
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
+   mci_writel(host, MPSBEGIN0, 0);
+   mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
+   mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
+   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
+   DWMCI_MPSCTRL_VALID |
+   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+   }
+
return 0;
 }
 
@@ -82,7 +114,8 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
struct dw_mci_exynos_priv_data *priv = host->priv;
 
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
-   priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
+   priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 ||
+   priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU)
host->bus_hz /= (priv->ciu_div + 1);
else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
@@ -107,6 +140,7 @@ static int dw_mci_exynos_resume(struct device *dev)
 {
struct dw_mci *host = dev_get_drvdata(dev);
 
+   dw_mci_exynos_priv_init(host);
return dw_mci_resume(host);
 }
 
@@ -226,6 +260,8 @@ static const struct of_device_id dw_mci_exynos_match[] = {
.data = &exynos_drv_data, },
{ .compatible = "samsung,exynos5420-dw-mshc",
.data = &exynos_drv_data, },
+   { .compatible = "samsung,exynos5420-dw-mshc-smu",
+   .data = &exynos_drv_data, },
{},
 };
 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
-- 
1.7.9.5

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Re: [PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Wed, Aug 28, 2013 at 5:52 PM, Tomasz Figa  wrote:
> Hi Yuvaraj,
>
> On Wednesday 28 of August 2013 17:33:06 Yuvaraj Kumar C D wrote:
>> This patch adds the device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>>
>> This patch depends on
>>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>>
>> changes since v4:
>>   1.Droppped the bypass-smu binding property.
>>   2.Used compatible string "samsung,exynos5250-dw-mshc"
>> for controller instance which does not have SMU.
>>
>> changes since V3:
>>   1.change fifo-depth size from 0x80 to 0x40
>>   2.Move the below properties
>>   a.card-detect-delay
>>   b.samsung,dw-mshc-ciu-div
>>   c.samsung,dw-mshc-sdr-timing
>>   d.samsung,dw-mshc-ddr-timing
>>   from SOC dts to board dts file as suggested by Doug Anderson
>>
>> changes since V2:
>>   1.dropped num-slots property from node as its not required
>> if number of card slots available is 1.
>>
>>   2.Move the below properties
>>   a.fifo-depth
>>   b.card-detect-delay
>>   c.samsung,dw-mshc-ciu-div
>>   d.samsung,dw-mshc-sdr-timing
>>   e.samsung,dw-mshc-ddr-timing
>>   from board dts to SOC dts,as these are not board specific properties.
>>
>>   3.Updated the binding document exynos-dw-mshc.txt.
>>
>> changes since V1:
>>   1.disable node by status = disabled in SOC file
>>   2.enable node by status = okay in board specific file
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33
>> + arch/arm/boot/dts/exynos5420.dtsi  |
>> 39  3 files changed, 74 insertions(+)
>
> This patch looks good to me now, except some minor comments below.
>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>> 6d1c098..84cd56f 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -16,6 +16,8 @@ Required Properties:
>> specific extensions.
>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
>> specific extensions.
>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> +   specific extensions.
>>
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>> interface unit (ciu) clock. This property is applicable only for Exynos5
>> SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..3ce5c97
>> 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -31,6 +31,39 @@
>>   };
>>   };
>>
>> + dwmmc0@1220 {
>
> Node name should not contain instance index. Instead, according to ePAPR
> recommendation, I would opt for a generic name such as mmc, mshc or sdio-
> host. mshc is already used on Exynos 4 so it might be a good idea to use it
> for consistency.
If we change node name's to mshc, debug statements are look like below:
dwmmc_exynos 1220.mshc: num-slots property not found, assuming 1
slot is available
dwmmc_exynos 1220.mshc: no vmmc regulator found: -19
dwmmc_exynos 1220.mshc: Using internal DMA controller.
dwmmc_exynos 1220.mshc: Version ID is 250a
dwmmc_exynos 1220.mshc: DW MMC controller at irq 107, 64 bit host
data width, 64 deep fifo

"dwmmc_exynos" is platform driver name and "1220.mshc" from dt
node.Is'nt it look like bit confusing?

>
> [Adding DT maintainers on CC]
>
> Best regards,
> Tomasz
>
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[PATCH] ARM: dts: update binding document exynos-dw-mshc.txt

[Yuvaraj Kumar C D]

This patch updates the exynos-dw-mshc.txt.Currently we are using
"pinctrl" binding property to describe the CMD and DATA line's
of Mobile Storage Host Controller(mshc) node.

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |   34 ++--
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 84cd56f..646a902 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -7,9 +7,9 @@ differences between the core Synopsis dw mshc controller 
properties described
 by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific
 extensions to the Synopsis Designware Mobile Storage Host Controller.
 
-Required Properties:
+Required SoC Specific Properties:
 
-* compatible: should be
+* compatible: should be one of the following
- "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
  specific extensions.
- "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
@@ -19,6 +19,8 @@ Required Properties:
- "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
  specific extensions.
 
+Required Board Specific Properties:
+
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
   ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
@@ -46,44 +48,42 @@ Required Properties:
   - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 phase shift clocks should be 0.
 
-Required properties for a slot:
-
-* gpios: specifies a list of gpios used for command, clock and data bus. The
-  first gpio is the command line and the second gpio is the clock line. The
-  rest of the gpios (depending on the bus-width property) are the data lines in
-  no particular order. The format of the gpio specifier depends on the gpio
-  controller.
+* pinctrl-0: Should specify pin control groups used for this controller.
+* pinctrl-names: Should contain only one value - "default".
 
+Required properties for a slot:
+   Refer synopsis-dw-mshc.txt
 Example:
 
   The MSHC controller node can be split into two portions, SoC specific and
   board specific portions as listed below.
 
-   dwmmc0@1220 {
+   mshc@1220 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x1220 0x1000>;
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+   clocks = <&clock 351>, <&clock 132>;
+   clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
+   status = "disabled";
};
 
-   dwmmc0@1220 {
+   mshc@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
-   fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
 
slot@0 {
reg = <0>;
bus-width = <8>;
-   gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
-   <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
-   <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
-   <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
-   <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
};
};
-- 
1.7.9.5

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[PATCH V6] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

This patch depends on
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420

changes since v5:
1.removed instance index from node name.
2.changed the node name to mshc.
3.changed the reg property value for mshc_2.

changes since v4:
1.Droppped the bypass-smu binding property.
2.Used compatible string "samsung,exynos5250-dw-mshc"
  for controller instance which does not have SMU.

changes since V3:
1.change fifo-depth size from 0x80 to 0x40
2.Move the below properties
a.card-detect-delay
b.samsung,dw-mshc-ciu-div
c.samsung,dw-mshc-sdr-timing
d.samsung,dw-mshc-ddr-timing
from SOC dts to board dts file as suggested by Doug Anderson

changes since V2:
1.dropped num-slots property from node as its not required
  if number of card slots available is 1.

2.Move the below properties
a.fifo-depth
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
from board dts to SOC dts,as these are not board specific properties.

3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33 +
 arch/arm/boot/dts/exynos5420.dtsi  |   39 
 3 files changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..fe22f97 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
};
};
 
+   mshc@1220 {
+   status = "okay";
+   broken-cd;
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   mshc@1222 {
+   status = "okay";
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..65375f0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &mshc_0;
+   mshc1 = &mshc_1;
+   mshc2 = &mshc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,42 @@
clock-names = "mfc";
};
 
+   mshc_0: mshc@1220 {

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 3:34 PM, Yuvaraj Kumar  wrote:
> On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon  wrote:
>> On Thu, August 29, 2013, Alim Akhtar wrote:
>>> Hi Seungwon,
>>>
>>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon  wrote:
>>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>>> >> SMU for exynos5420.
>>> >>
>>> >> This patch is on top of the below patch by Doug Anderson.
>>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>> >>
>>> >> changes since V2:
>>> >>   1.Droppped the bypass-smu quirk.
>>> >>   2.Changed the subject line for this patch
>>> >> add a quirk for SMU -> configure SMU in exynos5420
>>> >>
>>> >> changes since V1:
>>> >>   1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>> >> resume path.
>>> >>
>>> >> Signed-off-by: Yuvaraj Kumar C D 
>>> >> Signed-off-by: Alim Akhtar 
>>> >> ---
>>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +
>>> >>  1 file changed, 29 insertions(+)
>>> >>
>>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>>> >> b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> index 19c845b..db28f10 100644
>>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> @@ -35,6 +35,25 @@
>>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>> >>
>>> >> +/* Block number in eMMC */
>>> >> +#define DWMCI_BLOCK_NUM  0x
>>> >> +
>>> >> +#define SDMMC_EMMCP_BASE 0x1000
>>> >> +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
>>> >> +#define SDMMC_MPSBEGIN0  (SDMMC_EMMCP_BASE + 0x0200)
>>> >> +#define SDMMC_MPSEND0(SDMMC_EMMCP_BASE + 0x0204)
>>> >> +#define SDMMC_MPSCTRL0   (SDMMC_EMMCP_BASE + 0x020C)
>>> >> +
>>> >> +/* SMU control bits */
>>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BITBIT(7)
>>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT   BIT(6)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BITBIT(5)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY   BIT(3)
>>> >> +#define DWMCI_MPSCTRL_ECB_MODE   BIT(2)
>>> >> +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
>>> >> +#define DWMCI_MPSCTRL_VALID  BIT(0)
>>> >> +
>>> >>  /* Variations in Exynos specific dw-mshc controller */
>>> >>  enum dw_mci_exynos_type {
>>> >>   DW_MCI_TYPE_EXYNOS4210,
>>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci 
>>> >> *host)
>>> >>  {
>>> >>   struct dw_mci_exynos_priv_data *priv = host->priv;
>>> >>
>>> >> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>>> >> + mci_writel(host, MPSBEGIN0, 0);
>>> >> + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>>> >> + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>>> >> + DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>>> >> + DWMCI_MPSCTRL_VALID |
>>> >> + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>>> > Yuvaraj,
>>> >
>>> > Just one thing to check.
>>> > ch#0 and #1 of three hosts are only valid for SMU control.
>>> > Did you consider #2 host?
>>> > It seems not.
>>> >
>>>
>>> Only host#0 and host#1 has SMU (On exynos5420).
>>> Host #2 does not contain SMU.
>> Let me clear it.
>> I mean that current change allows for ch2 to access registers related to SMU,
>> even though ch2 doesn't actually has SMU. It's not valid IO area.
> No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
 Below is the DT patch posted in another thread.(Sorry,earlier link
was bit older).
[PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg22074.html
I will resubmit the DT patch[1] with reg = <0x1222 0x1000> for host#2.
>
>>
>> Thanks,
>> Seungwon Jeon
>>
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Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon  wrote:
> On Thu, August 29, 2013, Alim Akhtar wrote:
>> Hi Seungwon,
>>
>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon  wrote:
>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> >> SMU for exynos5420.
>> >>
>> >> This patch is on top of the below patch by Doug Anderson.
>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>> >>
>> >> changes since V2:
>> >>   1.Droppped the bypass-smu quirk.
>> >>   2.Changed the subject line for this patch
>> >> add a quirk for SMU -> configure SMU in exynos5420
>> >>
>> >> changes since V1:
>> >>   1.avoid code duplication by calling dw_mci_exynos_priv_init in
>> >> resume path.
>> >>
>> >> Signed-off-by: Yuvaraj Kumar C D 
>> >> Signed-off-by: Alim Akhtar 
>> >> ---
>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +
>> >>  1 file changed, 29 insertions(+)
>> >>
>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> >> b/drivers/mmc/host/dw_mmc-exynos.c
>> >> index 19c845b..db28f10 100644
>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> >> @@ -35,6 +35,25 @@
>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>> >>
>> >> +/* Block number in eMMC */
>> >> +#define DWMCI_BLOCK_NUM  0x
>> >> +
>> >> +#define SDMMC_EMMCP_BASE 0x1000
>> >> +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
>> >> +#define SDMMC_MPSBEGIN0  (SDMMC_EMMCP_BASE + 0x0200)
>> >> +#define SDMMC_MPSEND0(SDMMC_EMMCP_BASE + 0x0204)
>> >> +#define SDMMC_MPSCTRL0   (SDMMC_EMMCP_BASE + 0x020C)
>> >> +
>> >> +/* SMU control bits */
>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BITBIT(7)
>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT   BIT(6)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BITBIT(5)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY   BIT(3)
>> >> +#define DWMCI_MPSCTRL_ECB_MODE   BIT(2)
>> >> +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
>> >> +#define DWMCI_MPSCTRL_VALID  BIT(0)
>> >> +
>> >>  /* Variations in Exynos specific dw-mshc controller */
>> >>  enum dw_mci_exynos_type {
>> >>   DW_MCI_TYPE_EXYNOS4210,
>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> >>  {
>> >>   struct dw_mci_exynos_priv_data *priv = host->priv;
>> >>
>> >> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> >> + mci_writel(host, MPSBEGIN0, 0);
>> >> + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> >> + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> >> + DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> >> + DWMCI_MPSCTRL_VALID |
>> >> + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>> > Yuvaraj,
>> >
>> > Just one thing to check.
>> > ch#0 and #1 of three hosts are only valid for SMU control.
>> > Did you consider #2 host?
>> > It seems not.
>> >
>>
>> Only host#0 and host#1 has SMU (On exynos5420).
>> Host #2 does not contain SMU.
> Let me clear it.
> I mean that current change allows for ch2 to access registers related to SMU,
> even though ch2 doesn't actually has SMU. It's not valid IO area.
No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
Below is the DT patch posted in another thread.
[1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.html
I will resubmit the DT patch[1] with reg = <0x1222 0x1000> for host#2.

>
> Thanks,
> Seungwon Jeon
>
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Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon  wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> SMU for exynos5420.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V2:
>>   1.Droppped the bypass-smu quirk.
>>   2.Changed the subject line for this patch
>> add a quirk for SMU -> configure SMU in exynos5420
>>
>> changes since V1:
>>   1.avoid code duplication by calling dw_mci_exynos_priv_init in
>> resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> Signed-off-by: Alim Akhtar 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   29 +
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..db28f10 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM  0x
>> +
>> +#define SDMMC_EMMCP_BASE 0x1000
>> +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0  (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0(SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0   (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BITBIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT   BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BITBIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY   BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE   BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
>> +#define DWMCI_MPSCTRL_VALID  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>   DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>   struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> + mci_writel(host, MPSBEGIN0, 0);
>> + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> + DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> + DWMCI_MPSCTRL_VALID |
>> + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> Yuvaraj,
>
> Just one thing to check.
> ch#0 and #1 of three hosts are only valid for SMU control.
> Did you consider #2 host?
> It seems not.
Yes.AFAIK, host#2 doesn't have SMU.
>
> Thanks,
> Seungwon Jeon
>
>> + }
>> +
>>   return 0;
>>  }
>>
>> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>   struct dw_mci *host = dev_get_drvdata(dev);
>>
>> + dw_mci_exynos_priv_init(host);
>>   return dw_mci_resume(host);
>>  }
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
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[RFC V3 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.

changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-exynos.c |   31 +++
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
 
 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv;
-   int idx;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
-   if (of_device_is_compatible(host->dev->of_node,
-   exynos_compat[idx].compatible))
-   priv->ctrl_type = exynos_compat[idx].ctrl_type;
-   }
+   struct dw_mci_exynos_priv_data *priv = host->priv;
 
-   host->priv = priv;
return 0;
 }
 
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, 
struct mmc_ios *ios)
 
 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv = host->priv;
+   struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
+   int idx;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
+   if (of_device_is_compatible(np, exynos_compat[idx].compatible))
+   priv->ctrl_type = exynos_compat[idx].ctrl_type;
+   }
+
of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
priv->ciu_div = div;
 
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
 
priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar C D]

Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
SMU for exynos5420.

This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

changes since V2:
1.Droppped the bypass-smu quirk.
2.Changed the subject line for this patch
  add a quirk for SMU -> configure SMU in exynos5420

changes since V1:
1.avoid code duplication by calling dw_mci_exynos_priv_init in
  resume path.

Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Alim Akhtar 
---
 drivers/mmc/host/dw_mmc-exynos.c |   29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 19c845b..db28f10 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -35,6 +35,25 @@
 #define EXYNOS4210_FIXED_CIU_CLK_DIV   2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV   4
 
+/* Block number in eMMC */
+#define DWMCI_BLOCK_NUM0x
+
+#define SDMMC_EMMCP_BASE   0x1000
+#define SDMMC_MPSECURITY   (SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0  (SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control bits */
+#define DWMCI_MPSCTRL_SECURE_READ_BIT  BIT(7)
+#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT  BIT(5)
+#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
+#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
+#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
+#define DWMCI_MPSCTRL_ENCRYPTION   BIT(1)
+#define DWMCI_MPSCTRL_VALIDBIT(0)
+
 /* Variations in Exynos specific dw-mshc controller */
 enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS4210,
@@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv = host->priv;
 
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
+   mci_writel(host, MPSBEGIN0, 0);
+   mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
+   mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
+   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
+   DWMCI_MPSCTRL_VALID |
+   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+   }
+
return 0;
 }
 
@@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
 {
struct dw_mci *host = dev_get_drvdata(dev);
 
+   dw_mci_exynos_priv_init(host);
return dw_mci_resume(host);
 }
 
-- 
1.7.9.5

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[RFC V3 0/4] dw_mmc platform specific private data and SMU init

[Yuvaraj Kumar C D]

changes from V2:
1.dropped the bypass-smu quirk 
mmc: dw_mmc: exynos: configure SMU in exynos5420.
2.Changed the subject line for this patch
  add a quirk for SMU -> configure SMU in exynos5420

mmc: dw_mmc: exynos: configure SMU in exynos5420 
was earlier 
mmc: dw_mmc: exynos: add a quirk for SMU.

changes from V1:
1.Added a new RFC patch 
mmc: dw_mmc: socfpga: move socfpga private init
2.Avoid code duplication in
mmc: dw_mmc: exynos: add a quirk for SMU.

Yuvaraj Kumar C D (4):
  mmc: dw_mmc: exynos: move the exynos private init
  mmc: dw_mmc: socfpga: move socfpga private init
  mmc: dw_mmc: move the platform specific init call
  mmc: dw_mmc: exynos: configure SMU in exynos5420.

 drivers/mmc/host/dw_mmc-exynos.c  |   56 +++--
 drivers/mmc/host/dw_mmc-pltfm.c   |7 -
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++-
 drivers/mmc/host/dw_mmc.c |9 ++
 4 files changed, 65 insertions(+), 36 deletions(-)

-- 
1.7.9.5

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[RFC V3 3/4] mmc: dw_mmc: move the platform specific init call

[Yuvaraj Kumar C D]

Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.

changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-pltfm.c |7 ---
 drivers/mmc/host/dw_mmc.c   |9 +
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index 2089752..5c49656 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -39,7 +39,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 {
struct dw_mci *host;
struct resource *regs;
-   int ret;
 
host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL);
if (!host)
@@ -59,12 +58,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
 
-   if (drv_data && drv_data->init) {
-   ret = drv_data->init(host);
-   if (ret)
-   return ret;
-   }
-
platform_set_drvdata(pdev, host);
return dw_mci_probe(host);
 }
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index beafb4c..0edec01 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2221,6 +2221,15 @@ int dw_mci_probe(struct dw_mci *host)
host->bus_hz = clk_get_rate(host->ciu_clk);
}
 
+   if (drv_data && drv_data->init) {
+   ret = drv_data->init(host);
+   if (ret) {
+   dev_err(host->dev,
+   "implementation specific init failed\n");
+   goto err_clk_ciu;
+   }
+   }
+
if (drv_data && drv_data->setup_clock) {
ret = drv_data->setup_clock(host);
if (ret) {
-- 
1.7.9.5

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[RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
We can use the dw_mci_socfpga_priv_init to do some actual platform
specific initialisation.

This patch is compile tested only.

changes since V2: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-socfpga.c 
b/drivers/mmc/host/dw_mmc-socfpga.c
index 14b5961..953f260 100644
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
 
 static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-   if (IS_ERR(priv->sysreg)) {
-   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-   return PTR_ERR(priv->sysreg);
-   }
-   host->priv = priv;
 
return 0;
 }
@@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci 
*host, u32 *cmdr)
 
 static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv = host->priv;
+   struct dw_mci_socfpga_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(priv->sysreg)) {
+   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+   return PTR_ERR(priv->sysreg);
+   }
+
ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
if (ret)
dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
@@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
return ret;
 
priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

This patch depends on
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420

changes since v4:
1.Droppped the bypass-smu binding property.
2.Used compatible string "samsung,exynos5250-dw-mshc"
  for controller instance which does not have SMU.

changes since V3:
1.change fifo-depth size from 0x80 to 0x40
2.Move the below properties
a.card-detect-delay
b.samsung,dw-mshc-ciu-div
c.samsung,dw-mshc-sdr-timing
d.samsung,dw-mshc-ddr-timing
from SOC dts to board dts file as suggested by Doug Anderson

changes since V2:
1.dropped num-slots property from node as its not required
  if number of card slots available is 1.

2.Move the below properties
a.fifo-depth
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
from board dts to SOC dts,as these are not board specific properties.

3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   33 +
 arch/arm/boot/dts/exynos5420.dtsi  |   39 
 3 files changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..3ce5c97 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
};
};
 
+   dwmmc0@1220 {
+   status = "okay";
+   broken-cd;
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   dwmmc2@1222 {
+   status = "okay";
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..ccfa235 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &dwmmc_0;
+   mshc1 = &dwmmc_1;
+   mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,42 @@
clock-names = "mfc";
};
 
+   dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1&

Re: [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Tue, Aug 27, 2013 at 7:39 PM, Mark Rutland  wrote:
> On Tue, Aug 27, 2013 at 01:02:52PM +0100, Yuvaraj Kumar wrote:
>> On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland  wrote:
>> > On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
>> >> This patch adds the device tree node entries for exynos5420 SOC.
>> >> Exynos5420 has a different version of DWMMC controller,so a new
>> >> compatible string is used to distinguish it from the prior SOC's.
>> >>
>> >> This patch depends on
>> >>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>> >>
>> >> changes since V3:
>> >>   1.change fifo-depth size from 0x80 to 0x40
>> >>   2.Move the below properties
>> >>   a.card-detect-delay
>> >>   b.samsung,dw-mshc-ciu-div
>> >>   c.samsung,dw-mshc-sdr-timing
>> >>   d.samsung,dw-mshc-ddr-timing
>> >>   from SOC dts to board dts file as suggested by Doug Anderson
>> >>
>> >> changes since V2:
>> >>   1.dropped num-slots property from node as its not required
>> >> if number of card slots available is 1.
>> >>
>> >>   2.Move the below properties
>> >>   a.fifo-depth
>> >>   b.card-detect-delay
>> >>   c.samsung,dw-mshc-ciu-div
>> >>   d.samsung,dw-mshc-sdr-timing
>> >>   e.samsung,dw-mshc-ddr-timing
>> >>   from board dts to SOC dts,as these are not board specific 
>> >> properties.
>> >>
>> >>   3.Updated the binding document exynos-dw-mshc.txt.
>> >>
>> >> changes since V1:
>> >>   1.disable node by status = disabled in SOC file
>> >>   2.enable node by status = okay in board specific file
>> >>
>> >> Signed-off-by: Yuvaraj Kumar C D 
>> >> ---
>> >>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 ++
>> >>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   34 
>> >> +
>> >>  arch/arm/boot/dts/exynos5420.dtsi  |   39 
>> >> 
>> >>  3 files changed, 77 insertions(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
>> >> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >> index 6d1c098..25368e8 100644
>> >> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >> @@ -16,6 +16,8 @@ Required Properties:
>> >> specific extensions.
>> >>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung 
>> >> Exynos5250
>> >> specific extensions.
>> >> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung 
>> >> Exynos5420
>> >> +   specific extensions.
>> >>
>> >>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
>> >> interface
>> >>unit (ciu) clock. This property is applicable only for Exynos5 SoC's 
>> >> and
>> >> @@ -31,6 +33,8 @@ Required Properties:
>> >>data rate mode operation. Refer notes below for the order of the cells 
>> >> and the
>> >>valid values.
>> >>
>> >> +* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and 
>> >> channel 1.
>> >> +
>> >
>> > Could you elaborate on why this is needed?
>> Exynos5420  Mobile Storage Host controller has a Security Management
>> Unit (SMU) for
>> channel 0 and channel 1 (mainly for eMMC). This binding property
>> requires to add a quirk
>> to bypass SMU as it is not being used yet.
>
> When you say it's not being used _yet_, what do you mean? That the
> driver doesn't have support for it, but will in future?
Yes.Currently we do not have full support for SMU."bypass-smu" was added
to do minimal configuration of SMU to make it usable with the eMMC.
>
> Can the driver not just choose to bypass it entirely for now, regardless
> of what's in the dt? Do we need to bypass it in future for some reason?
bypassing SMU entirely, will definitely not work as it requires some
minimal configuration such as
defining first sector and end sector of partitions.
As Tom

Re: [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Tue, Aug 27, 2013 at 6:31 PM, Tomasz Figa  wrote:
> Hi Yuvaraj,
>
> On Tuesday 27 of August 2013 17:32:52 Yuvaraj Kumar wrote:
>> On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland 
> wrote:
>> > On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
>> >> This patch adds the device tree node entries for exynos5420 SOC.
>> >> Exynos5420 has a different version of DWMMC controller,so a new
>> >> compatible string is used to distinguish it from the prior SOC's.
>> >>
>> >> This patch depends on
>> >>
>> >>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>> >>
>> >> changes since V3:
>> >>   1.change fifo-depth size from 0x80 to 0x40
>> >>   2.Move the below properties
>> >>
>> >>   a.card-detect-delay
>> >>   b.samsung,dw-mshc-ciu-div
>> >>   c.samsung,dw-mshc-sdr-timing
>> >>   d.samsung,dw-mshc-ddr-timing
>> >>
>> >>   from SOC dts to board dts file as suggested by Doug Anderson
>> >>
>> >> changes since V2:
>> >>   1.dropped num-slots property from node as its not required
>> >>
>> >> if number of card slots available is 1.
>> >>
>> >>   2.Move the below properties
>> >>
>> >>   a.fifo-depth
>> >>   b.card-detect-delay
>> >>   c.samsung,dw-mshc-ciu-div
>> >>   d.samsung,dw-mshc-sdr-timing
>> >>   e.samsung,dw-mshc-ddr-timing
>> >>
>> >>   from board dts to SOC dts,as these are not board specific
>> >>   properties.
>> >>
>> >>   3.Updated the binding document exynos-dw-mshc.txt.
>> >>
>> >> changes since V1:
>> >>   1.disable node by status = disabled in SOC file
>> >>   2.enable node by status = okay in board specific file
>> >>
>> >> Signed-off-by: Yuvaraj Kumar C D 
>> >> ---
>> >>
>> >>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 ++
>> >>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   34
>> >>  + arch/arm/boot/dts/exynos5420.dtsi
>> >>  |   39  3 files changed, 77 insertions(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>> >> 6d1c098..25368e8 100644
>> >> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> >>
>> >> @@ -16,6 +16,8 @@ Required Properties:
>> >> specific extensions.
>> >>
>> >>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung
>> >>   Exynos5250
>> >>
>> >> specific extensions.
>> >>
>> >> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung
>> >> Exynos5420 +   specific extensions.
>> >>
>> >>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>> >>  interface>>
>> >>unit (ciu) clock. This property is applicable only for Exynos5
>> >>SoC's and
>> >>
>> >> @@ -31,6 +33,8 @@ Required Properties:
>> >>data rate mode operation. Refer notes below for the order of the
>> >>cells and the valid values.
>> >>
>> >> +* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and
>> >> channel 1. +
>> >
>> > Could you elaborate on why this is needed?
>>
>> Exynos5420  Mobile Storage Host controller has a Security Management
>> Unit (SMU) for
>> channel 0 and channel 1 (mainly for eMMC). This binding property
>> requires to add a quirk
>> to bypass SMU as it is not being used yet.
>
> This looks like a configuration property, not hardware description to me
> then. If presence of SMU depends on particular channel, then either the
> property should be "snps,has-smu" or something like this, to indicate that
> particular channel supports it and it's up to the driver how to handle this
> feature.
>
>> > Is the SMU broken or not present in some hardware revisions?
>>
>> SMU is only present in channel 0 and channel 1,but not in channel 2.So
>> to distinguish this,
>> bypass-smu property has been added as quirks in the channel.
>
> Also a good question is what you mean with "channel". Is it the whole mshc
> entity having compatible property or its subnodes aka slots?
Its with the whole MSHC entity.
>
> If it's the former and channel 2 does not have SMU, making it compatible
> with "samsung,exynos5250-dw-mshc", then it should be marked as such. In
> this case the ideal solution would be to determine the SMU quirk only by
> compatible value.
Good one.I tried this,works perfect.Will repost the patch soon.
>
> Best regards,
> Tomasz
>
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Re: [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Tue, Aug 27, 2013 at 4:31 PM, Mark Rutland  wrote:
> On Tue, Aug 27, 2013 at 10:22:31AM +0100, Yuvaraj Kumar C D wrote:
>> This patch adds the device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>>
>> This patch depends on
>>   mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
>>
>> changes since V3:
>>   1.change fifo-depth size from 0x80 to 0x40
>>   2.Move the below properties
>>   a.card-detect-delay
>>   b.samsung,dw-mshc-ciu-div
>>   c.samsung,dw-mshc-sdr-timing
>>   d.samsung,dw-mshc-ddr-timing
>>   from SOC dts to board dts file as suggested by Doug Anderson
>>
>> changes since V2:
>>   1.dropped num-slots property from node as its not required
>> if number of card slots available is 1.
>>
>>   2.Move the below properties
>>   a.fifo-depth
>>   b.card-detect-delay
>>   c.samsung,dw-mshc-ciu-div
>>   d.samsung,dw-mshc-sdr-timing
>>   e.samsung,dw-mshc-ddr-timing
>>   from board dts to SOC dts,as these are not board specific properties.
>>
>>   3.Updated the binding document exynos-dw-mshc.txt.
>>
>> changes since V1:
>>   1.disable node by status = disabled in SOC file
>>   2.enable node by status = okay in board specific file
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 ++
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   34 +
>>  arch/arm/boot/dts/exynos5420.dtsi  |   39 
>> 
>>  3 files changed, 77 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index 6d1c098..25368e8 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -16,6 +16,8 @@ Required Properties:
>> specific extensions.
>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
>> specific extensions.
>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> +   specific extensions.
>>
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card 
>> interface
>>unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
>> @@ -31,6 +33,8 @@ Required Properties:
>>data rate mode operation. Refer notes below for the order of the cells 
>> and the
>>valid values.
>>
>> +* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and channel 
>> 1.
>> +
>
> Could you elaborate on why this is needed?
Exynos5420  Mobile Storage Host controller has a Security Management
Unit (SMU) for
channel 0 and channel 1 (mainly for eMMC). This binding property
requires to add a quirk
to bypass SMU as it is not being used yet.
>
> Is the SMU broken or not present in some hardware revisions?
SMU is only present in channel 0 and channel 1,but not in channel 2.So
to distinguish this,
bypass-smu property has been added as quirks in the channel.
>
>>Notes for the sdr-timing and ddr-timing values:
>>
>>  The order of the cells should be
>
> On an unrelated note, I see the binding in mainline defines a gpios
> property that doesn't seem to be used anywhere. Am I missing something,
> or do we just not have support for that part of the binding?
Yes,This document has been little outdated.I will update and post a
separate patch.
>
> Thanks,
> Mark.
>
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index bafba25..576066c 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -31,6 +31,40 @@
>>   };
>>   };
>>
>> + dwmmc0@1220 {
>> + status = "okay";
>> + broken-cd;
>> + bypass-smu;
>> + supports-highspeed;
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <0 4>;
>> + samsung,dw-mshc-ddr-timing = <0 2>;
>> + pinct

[PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

This patch depends on
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420

changes since V3:
1.change fifo-depth size from 0x80 to 0x40
2.Move the below properties
a.card-detect-delay
b.samsung,dw-mshc-ciu-div
c.samsung,dw-mshc-sdr-timing
d.samsung,dw-mshc-ddr-timing
from SOC dts to board dts file as suggested by Doug Anderson

changes since V2:
1.dropped num-slots property from node as its not required
  if number of card slots available is 1.

2.Move the below properties
a.fifo-depth
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
from board dts to SOC dts,as these are not board specific properties.

3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   34 +
 arch/arm/boot/dts/exynos5420.dtsi  |   39 
 3 files changed, 77 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..25368e8 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
@@ -31,6 +33,8 @@ Required Properties:
   data rate mode operation. Refer notes below for the order of the cells and 
the
   valid values.
 
+* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and channel 1.
+
   Notes for the sdr-timing and ddr-timing values:
 
 The order of the cells should be
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..576066c 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,40 @@
};
};
 
+   dwmmc0@1220 {
+   status = "okay";
+   broken-cd;
+   bypass-smu;
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   dwmmc2@1222 {
+   status = "okay";
+   supports-highspeed;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..3893f45 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &dwmmc_0;
+   mshc1 = &dwmmc_1;
+   mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,42 @@
clock-names = "mfc";
};
 
+   dwmmc_0: dwmmc0@1220 {
+ 

Re: [RFC V2 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar]

On Tue, Aug 27, 2013 at 8:04 AM, Jaehoon Chung  wrote:
> Dear Yuvaraj,
>
> On 08/26/2013 06:20 PM, Yuvaraj Kumar wrote:
>> On Fri, Aug 23, 2013 at 7:14 PM, Jaehoon Chung  
>> wrote:
>>> Hi Yuvaraj,
>>>
>>> On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
>>>> Currently platform specific private data initialisation is done by
>>>> dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
>>>> separate platform specific device tree parser dw_mci_exynos_parse_dt,
>>>> move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
>>>> We can use the dw_mci_exynos_priv_init to do some actual platform
>>>> specific initialisation of SMU and etc.
>>>>
>>>> changes since V1: none
>>>>
>>>> Signed-off-by: Yuvaraj Kumar C D 
>>>> ---
>>>>  drivers/mmc/host/dw_mmc-exynos.c |   31 +++
>>>>  1 file changed, 15 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>>>> b/drivers/mmc/host/dw_mmc-exynos.c
>>>> index 9990f98..19c845b 100644
>>>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>>> @@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
>>>>
>>>>  static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>>>  {
>>>> - struct dw_mci_exynos_priv_data *priv;
>>>> - int idx;
>>>> -
>>>> - priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>>>> - if (!priv) {
>>>> - dev_err(host->dev, "mem alloc failed for private data\n");
>>>> - return -ENOMEM;
>>>> - }
>>>> -
>>>> - for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
>>>> - if (of_device_is_compatible(host->dev->of_node,
>>>> - exynos_compat[idx].compatible))
>>>> - priv->ctrl_type = exynos_compat[idx].ctrl_type;
>>>> - }
>>>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>>>>
>>>> - host->priv = priv;
>>>>   return 0;
>>>>  }
>>>>
>>>> @@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci 
>>>> *host, struct mmc_ios *ios)
>>>>
>>>>  static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>>>  {
>>>> - struct dw_mci_exynos_priv_data *priv = host->priv;
>>>> + struct dw_mci_exynos_priv_data *priv;
>>>>   struct device_node *np = host->dev->of_node;
>>>>   u32 timing[2];
>>>>   u32 div = 0;
>>>> + int idx;
>>>>   int ret;
>>>>
>>>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>>>> + if (!priv) {
>>>> + dev_err(host->dev, "mem alloc failed for private data\n");
>>>> + return -ENOMEM;
>>>> + }
>>>> +
>>>> + for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
>>>> + if (of_device_is_compatible(np, 
>>>> exynos_compat[idx].compatible))
>>>> + priv->ctrl_type = exynos_compat[idx].ctrl_type;
>>>> + }
>>>> +
>>>>   of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
>>>>   priv->ciu_div = div;
>>>>
>>>> @@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>>>   return ret;
>>>>
>>>>   priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
>>>> + host->priv = priv;
>>>
>>> I'm not sure whether my thinking is right or not.
>>> if host->pdata is present, then dw_mci_parse_dt() didn't called at 
>>> dw_mci_probe.
>> Yes, you are right.
>>> then how host->priv set to priv?
>> Earlier host->priv set to priv in both non-DT and DT case.True, with
>> this patch it does it only in DT case.
>> Is there any platform/board which still uses dw_mmc and its platform
>> extension driver with non DT case?
> You're right. i didn't see the extension driver with non DT-case?
> Then we can also modify the host->pdata into dw_mci_probe().
I think its not necessary becuase dw_mmc-pci.c driver calls
dw_mci_probe with host->pdata NOT NULL.
Only dwmmc platform extension driver (exynos/socfpga) which are
basically DT based uses host->priv .
>
> Best Regards,
> Jaehoon Chung
>> I found a reference of non-DT case where host->pdata is present in
>> dw_mmc-pci.c driver but does not
>> use platform extension driver (exynos/socfpga).
>>>
>>> Best Regards,
>>> Jaehoon Chung
>>>
>>>>   return 0;
>>>>  }
>>>>
>>>>
>>>
>> --
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>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>
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Re: [RFC V2 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar]

On Fri, Aug 23, 2013 at 7:14 PM, Jaehoon Chung  wrote:
> Hi Yuvaraj,
>
> On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
>> Currently platform specific private data initialisation is done by
>> dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
>> separate platform specific device tree parser dw_mci_exynos_parse_dt,
>> move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
>> We can use the dw_mci_exynos_priv_init to do some actual platform
>> specific initialisation of SMU and etc.
>>
>> changes since V1: none
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   31 +++
>>  1 file changed, 15 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 9990f98..19c845b 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
>>
>>  static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>> - struct dw_mci_exynos_priv_data *priv;
>> - int idx;
>> -
>> - priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> - if (!priv) {
>> - dev_err(host->dev, "mem alloc failed for private data\n");
>> - return -ENOMEM;
>> - }
>> -
>> - for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
>> - if (of_device_is_compatible(host->dev->of_node,
>> - exynos_compat[idx].compatible))
>> - priv->ctrl_type = exynos_compat[idx].ctrl_type;
>> - }
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> - host->priv = priv;
>>   return 0;
>>  }
>>
>> @@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, 
>> struct mmc_ios *ios)
>>
>>  static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>  {
>> - struct dw_mci_exynos_priv_data *priv = host->priv;
>> + struct dw_mci_exynos_priv_data *priv;
>>   struct device_node *np = host->dev->of_node;
>>   u32 timing[2];
>>   u32 div = 0;
>> + int idx;
>>   int ret;
>>
>> + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv) {
>> + dev_err(host->dev, "mem alloc failed for private data\n");
>> + return -ENOMEM;
>> + }
>> +
>> + for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
>> + if (of_device_is_compatible(np, exynos_compat[idx].compatible))
>> + priv->ctrl_type = exynos_compat[idx].ctrl_type;
>> + }
>> +
>>   of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
>>   priv->ciu_div = div;
>>
>> @@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
>>   return ret;
>>
>>   priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
>> + host->priv = priv;
>
> I'm not sure whether my thinking is right or not.
> if host->pdata is present, then dw_mci_parse_dt() didn't called at 
> dw_mci_probe.
Yes, you are right.
> then how host->priv set to priv?
Earlier host->priv set to priv in both non-DT and DT case.True, with
this patch it does it only in DT case.
Is there any platform/board which still uses dw_mmc and its platform
extension driver with non DT case?
I found a reference of non-DT case where host->pdata is present in
dw_mmc-pci.c driver but does not
use platform extension driver (exynos/socfpga).
>
> Best Regards,
> Jaehoon Chung
>
>>   return 0;
>>  }
>>
>>
>
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Re: [RFC V2 4/4] mmc: dw_mmc: exynos: add a quirk for SMU.

[Yuvaraj Kumar]

Hi Jaehoon,

Yes,Its depend on the below patch.
mmc: dw_mmc: exynos: Add a new compatible string for exynos5420
http://permalink.gmane.org/gmane.linux.kernel.mmc/21060

Best Regards
Yuvaraj

On Fri, Aug 23, 2013 at 6:25 PM, Jaehoon Chung  wrote:
> Hi Yuvaraj,
>
> Is there dependency with other patch?
> I didn't see the defined "DW_MCI_TYPE_EXYNOS5420".
> If i missed something, let me know.
>
> Best Regards,
> Jaehoon Chung
>
> On 08/23/2013 08:15 PM, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch adds a
>> quirk to bypass SMU as it is not being used yet.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V1:
>>   1.avoid code duplication by calling dw_mci_exynos_priv_init in
>> resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> Signed-off-by: Alim Akhtar 
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   33 +
>>  drivers/mmc/host/dw_mmc.c|3 +++
>>  include/linux/mmc/dw_mmc.h   |2 ++
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c 
>> b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..8e70fc6 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM  0x
>> +
>> +#define SDMMC_EMMCP_BASE 0x1000
>> +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0  (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0(SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0   (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BITBIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT   BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BITBIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY   BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE   BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
>> +#define DWMCI_MPSCTRL_VALID  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>   DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,16 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>   struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 &&
>> + host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU) {
>> + mci_writel(host, MPSBEGIN0, 0);
>> + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> + DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> + DWMCI_MPSCTRL_VALID |
>> + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>> + }
>> +
>>   return 0;
>>  }
>>
>> @@ -106,7 +135,11 @@ static int dw_mci_exynos_suspend(struct device *dev)
>>  static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>   struct dw_mci *host = dev_get_drvdata(dev);
>> + struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 &&
>> + host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU)
>> + dw_mci_exynos_priv_init(host);
>>   return dw_mci_resume(host);
>>  }
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 0c0cada..49df69f 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -2107,6 +2107,9 @@ static struct dw_mci_of_quirks {
>>   }, {
>>   .quirk  = "broken-cd",
>>   .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
>> + }, {
>> + .quirk  = "bypass-smu",
>> + .id = DW_MCI_QUIRK_BYPASS_SMU,
>>   },
>>  };
>>
>> diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
>&g

[RFC V2 4/4] mmc: dw_mmc: exynos: add a quirk for SMU.

[Yuvaraj Kumar C D]

Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch adds a
quirk to bypass SMU as it is not being used yet.

This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

changes since V1:
1.avoid code duplication by calling dw_mci_exynos_priv_init in
  resume path.

Signed-off-by: Yuvaraj Kumar C D 
Signed-off-by: Alim Akhtar 
---
 drivers/mmc/host/dw_mmc-exynos.c |   33 +
 drivers/mmc/host/dw_mmc.c|3 +++
 include/linux/mmc/dw_mmc.h   |2 ++
 3 files changed, 38 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 19c845b..8e70fc6 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -35,6 +35,25 @@
 #define EXYNOS4210_FIXED_CIU_CLK_DIV   2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV   4
 
+/* Block number in eMMC */
+#define DWMCI_BLOCK_NUM0x
+
+#define SDMMC_EMMCP_BASE   0x1000
+#define SDMMC_MPSECURITY   (SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0  (SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control bits */
+#define DWMCI_MPSCTRL_SECURE_READ_BIT  BIT(7)
+#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT  BIT(5)
+#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
+#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
+#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
+#define DWMCI_MPSCTRL_ENCRYPTION   BIT(1)
+#define DWMCI_MPSCTRL_VALIDBIT(0)
+
 /* Variations in Exynos specific dw-mshc controller */
 enum dw_mci_exynos_type {
DW_MCI_TYPE_EXYNOS4210,
@@ -74,6 +93,16 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
struct dw_mci_exynos_priv_data *priv = host->priv;
 
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 &&
+   host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU) {
+   mci_writel(host, MPSBEGIN0, 0);
+   mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
+   mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
+   DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
+   DWMCI_MPSCTRL_VALID |
+   DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+   }
+
return 0;
 }
 
@@ -106,7 +135,11 @@ static int dw_mci_exynos_suspend(struct device *dev)
 static int dw_mci_exynos_resume(struct device *dev)
 {
struct dw_mci *host = dev_get_drvdata(dev);
+   struct dw_mci_exynos_priv_data *priv = host->priv;
 
+   if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 &&
+   host->pdata->quirks & DW_MCI_QUIRK_BYPASS_SMU)
+   dw_mci_exynos_priv_init(host);
return dw_mci_resume(host);
 }
 
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 0c0cada..49df69f 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2107,6 +2107,9 @@ static struct dw_mci_of_quirks {
}, {
.quirk  = "broken-cd",
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+   }, {
+   .quirk  = "bypass-smu",
+   .id = DW_MCI_QUIRK_BYPASS_SMU,
},
 };
 
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 198f0fa..2d3f83f 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -209,6 +209,8 @@ struct dw_mci_dma_ops {
 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
 /* Unreliable card detection */
 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
+/*Bypass the Security management unit*/
+#define DW_MCI_QUIRK_BYPASS_SMUBIT(4)
 
 /* Slot level quirks */
 /* This slot has no write protect */
-- 
1.7.9.5

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[RFC V2 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.

changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-exynos.c |   31 +++
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
 
 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv;
-   int idx;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
-   if (of_device_is_compatible(host->dev->of_node,
-   exynos_compat[idx].compatible))
-   priv->ctrl_type = exynos_compat[idx].ctrl_type;
-   }
+   struct dw_mci_exynos_priv_data *priv = host->priv;
 
-   host->priv = priv;
return 0;
 }
 
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, 
struct mmc_ios *ios)
 
 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_exynos_priv_data *priv = host->priv;
+   struct dw_mci_exynos_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
+   int idx;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
+   if (of_device_is_compatible(np, exynos_compat[idx].compatible))
+   priv->ctrl_type = exynos_compat[idx].ctrl_type;
+   }
+
of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
priv->ciu_div = div;
 
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
return ret;
 
priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[RFC V2 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
We can use the dw_mci_socfpga_priv_init to do some actual platform
specific initialisation.

This patch is compile tested only.

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-socfpga.c 
b/drivers/mmc/host/dw_mmc-socfpga.c
index 14b5961..953f260 100644
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
 
 static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv;
-
-   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-   if (!priv) {
-   dev_err(host->dev, "mem alloc failed for private data\n");
-   return -ENOMEM;
-   }
-
-   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-   if (IS_ERR(priv->sysreg)) {
-   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-   return PTR_ERR(priv->sysreg);
-   }
-   host->priv = priv;
 
return 0;
 }
@@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci 
*host, u32 *cmdr)
 
 static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
 {
-   struct dw_mci_socfpga_priv_data *priv = host->priv;
+   struct dw_mci_socfpga_priv_data *priv;
struct device_node *np = host->dev->of_node;
u32 timing[2];
u32 div = 0;
int ret;
 
+   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv) {
+   dev_err(host->dev, "mem alloc failed for private data\n");
+   return -ENOMEM;
+   }
+
+   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+   if (IS_ERR(priv->sysreg)) {
+   dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+   return PTR_ERR(priv->sysreg);
+   }
+
ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
if (ret)
dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
@@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
return ret;
 
priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+   host->priv = priv;
return 0;
 }
 
-- 
1.7.9.5

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[RFC V2 3/4] mmc: dw_mmc: move the platform specific init call

[Yuvaraj Kumar C D]

Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.

changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 drivers/mmc/host/dw_mmc-pltfm.c |7 ---
 drivers/mmc/host/dw_mmc.c   |9 +
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ee52556..a570da4 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -38,7 +38,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 {
struct dw_mci *host;
struct resource *regs;
-   int ret;
 
host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL);
if (!host)
@@ -58,12 +57,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
 
-   if (drv_data && drv_data->init) {
-   ret = drv_data->init(host);
-   if (ret)
-   return ret;
-   }
-
platform_set_drvdata(pdev, host);
return dw_mci_probe(host);
 }
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index ee5f167..0c0cada 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -,6 +,15 @@ int dw_mci_probe(struct dw_mci *host)
host->bus_hz = clk_get_rate(host->ciu_clk);
}
 
+   if (drv_data && drv_data->init) {
+   ret = drv_data->init(host);
+   if (ret) {
+   dev_err(host->dev,
+   "implementation specific init failed\n");
+   goto err_clk_ciu;
+   }
+   }
+
if (drv_data && drv_data->setup_clock) {
ret = drv_data->setup_clock(host);
if (ret) {
-- 
1.7.9.5

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[RFC V2 0/4] dw_mmc platform specific private data init

[Yuvaraj Kumar C D]

changes from V1:
1.Added a new RFC patch 
mmc: dw_mmc: socfpga: move socfpga private init
2.Avoid code duplication in
mmc: dw_mmc: exynos: add a quirk for SMU.

Yuvaraj Kumar C D (4):
  mmc: dw_mmc: exynos: move the exynos private init
  mmc: dw_mmc: socfpga: move socfpga private init
  mmc: dw_mmc: move the platform specific init call
  mmc: dw_mmc: exynos: add a quirk for SMU.

 drivers/mmc/host/dw_mmc-exynos.c  |   60 -
 drivers/mmc/host/dw_mmc-pltfm.c   |7 -
 drivers/mmc/host/dw_mmc-socfpga.c |   29 +-
 drivers/mmc/host/dw_mmc.c |   12 
 include/linux/mmc/dw_mmc.h|2 ++
 5 files changed, 74 insertions(+), 36 deletions(-)

-- 
1.7.9.5

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[PATCH V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

changes since V2:
1.dropped num-slots property from node as its not required
  if number of card slots available is 1.

2.Move the below properties
a.fifo-depth
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
from board dts to SOC dts,as these are not board specific properties.

3.Updated the binding document exynos-dw-mshc.txt.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |4 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   26 ++
 arch/arm/boot/dts/exynos5420.dtsi  |   51 
 3 files changed, 81 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..25368e8 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
@@ -31,6 +33,8 @@ Required Properties:
   data rate mode operation. Refer notes below for the order of the cells and 
the
   valid values.
 
+* bypass-smu: Bypass Security Management Unit of eMMC channel 0 and channel 1.
+
   Notes for the sdr-timing and ddr-timing values:
 
 The order of the cells should be
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..bc604d4 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,32 @@
};
};
 
+   dwmmc0@1220 {
+   status = "okay";
+   broken-cd;
+   bypass-smu;
+   supports-highspeed;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   dwmmc2@1222 {
+   status = "okay";
+   supports-highspeed;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..1f08d1b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &dwmmc_0;
+   mshc1 = &dwmmc_1;
+   mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,54 @@
clock-names = "mfc";
};
 
+   dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1220 0x2000>;
+   clocks = <&clock 351>, <&clock 132>;
+   clock-names = "biu", "ciu";
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   status = "disabled";
+   };
+
+   dwmmc_1: dwmmc1@1221 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 76 0>;
+   #address-cells = &

Re: [PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Wed, Aug 21, 2013 at 4:00 PM, Tomasz Figa  wrote:
> Hi Yuvaraj,
>
> On Wednesday 21 of August 2013 12:13:53 Yuvaraj Kumar C D wrote:
>> This patch adds the device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>
> What are the difference between both versions? Is there a patch adding the
> new compatible to the driver somewhere?
Exynos5250 has DWMMC controller of IP version 2.41a
Exynos5420 has DWMMC controller of IP version 2.50a
In addition Exynos5420 has Security Management Unit for eMMC.
>
>> changes since V1:
>>   1.disable node by status = disabled in SOC file
>>   2.enable node by status = okay in board specific file
>
> Ahh, so you fixed this already in this version, thanks. Haven't noticed
> this patch at first and commented on previous one. Sorry for the noise.
>
>>
>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   38
>>  arch/arm/boot/dts/exynos5420.dtsi
>> |   36 +++ 3 files changed, 76 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>> 6d1c098..84cd56f 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -16,6 +16,8 @@ Required Properties:
>> specific extensions.
>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
>> specific extensions.
>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> +   specific extensions.
>>
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>> interface unit (ciu) clock. This property is applicable only for Exynos5
>> SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..6e65278
>> 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -31,6 +31,44 @@
>>   };
>>   };
>>
>> + dwmmc0@1220 {
>> + status = "okay";
>> + num-slots = <1>;
>
> You don't have to specify this property if there is only one slot. Also are
> you sure that this is a board specific property?
Yes,If num-slots property is not defined dw_mmc driver assumes 1 slot
is available.
I think yes,its a board specific property as number of card slots is
board dependent.
>
>> + broken-cd;
>> + bypass-smu;
>
> This property doesn't seem to be documented nor used anywhere.
Sorry. I missed to add in binding document.Will add in next version.
>
>> + supports-highspeed;
>
> Is it a board specific property?
>
>> + fifo-depth = <0x80>;
>
> Ditto.
Ideally this can be move to SOC specific dts.But I am just following
,already merged smdk5250 board
dts convensions.
>
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <0 4>;
>> + samsung,dw-mshc-ddr-timing = <0 2>;
>
> Are the above three properties really board-specific?
>
> Same for remaining nodes.
>
> Best regards,
> Tomasz
>
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[PATCH V3 0/2]exynos dwmmc device tree node

[Yuvaraj Kumar C D]

These patches were V3 versions of below patches.
1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
http://www.spinics.net/lists/linux-samsung-soc/msg21602.html
2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
http://www.spinics.net/lists/linux-samsung-soc/msg21603.html 

changes from V2:
1.remove from exynos5.dtsi and add in exynos5250.dtsi
  in single patch.Suggested by Tomasz Figa.
2.Separate patch for changing status property of dwmmc node
  in smdk5250 and arndale board dts file.

Yuvaraj Kumar C D (2):
  ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
  ARM: dts: exynos: change status property of dwmmc nodes

 arch/arm/boot/dts/exynos5.dtsi|   21 -
 arch/arm/boot/dts/exynos5250-arndale.dts  |   10 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   10 ++
 arch/arm/boot/dts/exynos5250.dtsi |   16 
 4 files changed, 20 insertions(+), 37 deletions(-)

-- 
1.7.9.5

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[PATCH V3 1/2] ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi

[Yuvaraj Kumar C D]

Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source to SOC specific device tree source.

Changes since V2:
1.remove from exynos5.dtsi and add in exynos5250.dtsi
  in single patch.

Changes since V1: none

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5.dtsi|   21 -
 arch/arm/boot/dts/exynos5250.dtsi |   12 
 2 files changed, 12 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..24140f0 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = <1 9 0xf04>;
};
 
-   dwmmc_0: dwmmc0@1220 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 75 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
-   dwmmc_1: dwmmc1@1221 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 76 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
-   dwmmc_2: dwmmc2@1222 {
-   compatible = "samsung,exynos5250-dw-mshc";
-   interrupts = <0 77 0>;
-   #address-cells = <1>;
-   #size-cells = <0>;
-   };
-
serial@12C0 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C0 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..3c970fe 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,18 +387,30 @@
};
 
dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
};
 
dwmmc_1: dwmmc1@1221 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 76 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
};
 
dwmmc_2: dwmmc2@1222 {
+   compatible = "samsung,exynos5250-dw-mshc";
+   interrupts = <0 77 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
-- 
1.7.9.5

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[PATCH V3 2/2] ARM: dts: exynos: change status property of dwmmc nodes

[Yuvaraj Kumar C D]

According to ePAPR, chapter 2.3.4, the status property has
defined that it should be set to "disabled" when "the device
is not presently operational, but it might become operational
in the future".

So this patch disable dwmmc node by "status = disabled" in SOC
dts file and enable dwmmc node by "status = okay" in board specific
dts file.

Signed-off-by: Yuvaraj Kumar C D 
---
 arch/arm/boot/dts/exynos5250-arndale.dts  |   10 ++
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   10 ++
 arch/arm/boot/dts/exynos5250.dtsi |4 
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b0..b741dd4 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -367,6 +367,7 @@
};
 
dwmmc_0: dwmmc0@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -385,11 +386,8 @@
};
};
 
-   dwmmc_1: dwmmc1@1221 {
-   status = "disabled";
-   };
-
dwmmc_2: dwmmc2@1222 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -408,10 +406,6 @@
};
};
 
-   dwmmc_3: dwmmc3@1223 {
-   status = "disabled";
-   };
-
spi_0: spi@12d2 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
 
dwmmc0@1220 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
 
-   dwmmc1@1221 {
-   status = "disabled";
-   };
-
dwmmc2@1222 {
+   status = "okay";
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
@@ -180,10 +178,6 @@
};
};
 
-   dwmmc3@1223 {
-   status = "disabled";
-   };
-
spi_0: spi@12d2 {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 3c970fe..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -394,6 +394,7 @@
reg = <0x1220 0x1000>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_1: dwmmc1@1221 {
@@ -404,6 +405,7 @@
reg = <0x1221 0x1000>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_2: dwmmc2@1222 {
@@ -414,6 +416,7 @@
reg = <0x1222 0x1000>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
dwmmc_3: dwmmc3@1223 {
@@ -424,6 +427,7 @@
#size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
+   status = "disabled";
};
 
i2s0: i2s@0383 {
-- 
1.7.9.5

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Re: [PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar]

On Wed, Aug 21, 2013 at 3:40 PM, Tomasz Figa  wrote:
> Hi Yuvaraj,
>
> On Wednesday 21 of August 2013 12:05:33 Yuvaraj Kumar C D wrote:
>> This patch adds the device tree node entries for exynos5420 SOC.
>> Exynos5420 has a different version of DWMMC controller,so a new
>> compatible string is used to distinguish it from the prior SOC's.
>
> Is this patch a v3 of [1]?
>
> [1] - http://thread.gmane.org/gmane.linux.kernel.mmc/21981
>
> Why it is named patch 4/8?
>
Please ignore this patch. patch 4/8 was accidental.

>> Signed-off-by: Yuvaraj Kumar C D 
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   41
>>  arch/arm/boot/dts/exynos5420.dtsi
>> |   33  3 files changed, 76 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
>> 6d1c098..84cd56f 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -16,6 +16,8 @@ Required Properties:
>> specific extensions.
>>   - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
>> specific extensions.
>> + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
>> +   specific extensions.
>>
>>  * samsung,dw-mshc-ciu-div: Specifies the divider value for the card
>> interface unit (ciu) clock. This property is applicable only for Exynos5
>> SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 08607df..4530700
>> 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -30,4 +30,45 @@
>>   clock-frequency = <2400>;
>>   };
>>   };
>> +
>> + dwmmc0@1220 {
>> + num-slots = <1>;
>> + broken-cd;
>> + bypass-smu;
>> + supports-highspeed;
>> + fifo-depth = <0x80>;
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <0 4>;
>> + samsung,dw-mshc-ddr-timing = <0 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
>
> See below.
>
>> +
>> + slot@0 {
>> + reg = <0>;
>> + bus-width = <8>;
>> + };
>> + };
>> +
>> + dwmmc1@1221 {
>> + status = "disabled";
>
> You should rather keep things the other way around. A board dts shouldn't
> care about peripherals it doesn't use, so any peripheral requiring board-
> specific data in its node should have status set as "disabled" at top level
> and then overridden to "okay" at level in which it has all the required
> properties to operate (in board dts in this case).
>
>> + };
>> +
>> + dwmmc2@1222 {
>> + num-slots = <1>;
>> + supports-highspeed;
>> + fifo-depth = <0x80>;
>> + card-detect-delay = <200>;
>> + samsung,dw-mshc-ciu-div = <3>;
>> + samsung,dw-mshc-sdr-timing = <2 3>;
>> + samsung,dw-mshc-ddr-timing = <1 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
>
> Here would go status = "okay".
>
>> +
>> + slot@0 {
>> + reg = <0>;
>> + bus-width = <4>;
>> + };
>> + };
>> +
>>  };
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
>> b/arch/arm/boot/dts/exynos5420.dtsi index 9e90d1e..8559aa8 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -19,6 +19,9 @@
>>   compatible = "samsung,exynos5420";
>>
>>   aliases {
>> + mshc0 = &dwmmc_0;
>> + mshc1 = &dwmmc_1;
>> + mshc2 = &dwmmc_2;
>>   pinctrl0 = &pinctrl_0;
>>  

Re: [PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.

[Yuvaraj Kumar]

On Wed, Aug 21, 2013 at 4:04 PM, Tomasz Figa  wrote:
> Hi Yuvaraj,
>
> On Wednesday 21 of August 2013 12:07:38 yuvaraj...@gmail.com wrote:
>> From: Yuvaraj Kumar C D 
>>
>> Exynos5 series SOC's 5250 and 5420 have different versions of
>> DWMMC controller.So there is a new compatible string to distinguish
>> between them.So these nodes should be moved out of Exynos5 series
>> common device tree source.
>
> This series should be split in a different way, because patch 1/2 breaks
> dwmmc on Exynos5250 and only patch 2/2 fixes this, so bisection is broken.
 will make a single patch and resend.
>
> Also patch 2/2 contains two logically separate changes - moving dwmmc nodes
> and making status disabled by default. Those should be in separate patches.
 will separate patch2/2 and resend.
>
> Best regards,
> Tomasz
>
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[PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   38 
 arch/arm/boot/dts/exynos5420.dtsi  |   36 +++
 3 files changed, 76 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index bafba25..6e65278 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,44 @@
};
};
 
+   dwmmc0@1220 {
+   status = "okay";
+   num-slots = <1>;
+   broken-cd;
+   bypass-smu;
+   supports-highspeed;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   dwmmc2@1222 {
+   status = "okay";
+   num-slots = <1>;
+   supports-highspeed;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
dp-controller@145B {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32..694e7f1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &dwmmc_0;
+   mshc1 = &dwmmc_1;
+   mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -84,6 +87,39 @@
clock-names = "mfc";
};
 
+   dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1220 0x2000>;
+   clocks = <&clock 351>, <&clock 132>;
+   clock-names = "biu", "ciu";
+   status = "disabled";
+   };
+
+   dwmmc_1: dwmmc1@1221 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 76 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1221 0x2000>;
+   clocks = <&clock 352>, <&clock 133>;
+   clock-names = "biu", "ciu";
+   status = "disabled";
+   };
+
+   dwmmc_2: dwmmc2@1222 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 77 0>;
+   #address-cells =

[PATCH 4/8] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC

[Yuvaraj Kumar C D]

This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.

Signed-off-by: Yuvaraj Kumar C D 
---
 .../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 +
 arch/arm/boot/dts/exynos5420-smdk5420.dts  |   41 
 arch/arm/boot/dts/exynos5420.dtsi  |   33 
 3 files changed, 76 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt 
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
  specific extensions.
- "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
  specific extensions.
+   - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+ specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts 
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df..4530700 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,45 @@
clock-frequency = <2400>;
};
};
+
+   dwmmc0@1220 {
+   num-slots = <1>;
+   broken-cd;
+   bypass-smu;
+   supports-highspeed;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <0 4>;
+   samsung,dw-mshc-ddr-timing = <0 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   };
+   };
+
+   dwmmc1@1221 {
+   status = "disabled";
+   };
+
+   dwmmc2@1222 {
+   num-slots = <1>;
+   supports-highspeed;
+   fifo-depth = <0x80>;
+   card-detect-delay = <200>;
+   samsung,dw-mshc-ciu-div = <3>;
+   samsung,dw-mshc-sdr-timing = <2 3>;
+   samsung,dw-mshc-ddr-timing = <1 2>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   };
+   };
+
 };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..8559aa8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -19,6 +19,9 @@
compatible = "samsung,exynos5420";
 
aliases {
+   mshc0 = &dwmmc_0;
+   mshc1 = &dwmmc_1;
+   mshc2 = &dwmmc_2;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
@@ -65,6 +68,36 @@
#clock-cells = <1>;
};
 
+   dwmmc_0: dwmmc0@1220 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 75 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1220 0x2000>;
+   clocks = <&clock 351>, <&clock 132>;
+   clock-names = "biu", "ciu";
+   };
+
+   dwmmc_1: dwmmc1@1221 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 76 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1221 0x2000>;
+   clocks = <&clock 352>, <&clock 133>;
+   clock-names = "biu", "ciu";
+   };
+
+   dwmmc_2: dwmmc2@1222 {
+   compatible = "samsung,exynos5420-dw-mshc";
+   interrupts = <0 77 0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x1222 0x2000>;
+   clocks = <&clock 353>, <&clock 134>;
+   clock-names = "biu", "ciu";
+   };
+
mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0x800>;
-- 
1.7.9.5

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