Re: [PATCH 09/17] gpio: samsung: remov s5pc100 related gpio codes

[Linus Walleij]

On Mon, Jun 30, 2014 at 11:32 PM, Kukjin Kim kgene@samsung.com wrote:

 This patch removes gpio codes for s5pc100 SoC.

 Signed-off-by: Kukjin Kim kgene@samsung.com
 Cc: Linus Walleij linus.wall...@linaro.org

Acked-by: Linus Walleij linus.wall...@linaro.org

Yours,
Linus Walleij
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 09/17] gpio: samsung: remov s5pc100 related gpio codes

[Kukjin Kim]

This patch removes gpio codes for s5pc100 SoC.

Signed-off-by: Kukjin Kim kgene@samsung.com
Cc: Linus Walleij linus.wall...@linaro.org
---
 drivers/gpio/gpio-samsung.c |  276 ---
 1 file changed, 276 deletions(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index d12945c..7d4281e 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -1170,267 +1170,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
 };
 
 /*
- * S5PC100 GPIO bank summary:
- *
- * BankGPIOs   Style   INT Type
- * A0  8   4BitGPIO_INT0
- * A1  5   4BitGPIO_INT1
- * B   8   4BitGPIO_INT2
- * C   5   4BitGPIO_INT3
- * D   7   4BitGPIO_INT4
- * E0  8   4BitGPIO_INT5
- * E1  6   4BitGPIO_INT6
- * F0  8   4BitGPIO_INT7
- * F1  8   4BitGPIO_INT8
- * F2  8   4BitGPIO_INT9
- * F3  4   4BitGPIO_INT10
- * G0  8   4BitGPIO_INT11
- * G1  3   4BitGPIO_INT12
- * G2  7   4BitGPIO_INT13
- * G3  7   4BitGPIO_INT14
- * H0  8   4BitWKUP_INT
- * H1  8   4BitWKUP_INT
- * H2  8   4BitWKUP_INT
- * H3  8   4BitWKUP_INT
- * I   8   4BitGPIO_INT15
- * J0  8   4BitGPIO_INT16
- * J1  5   4BitGPIO_INT17
- * J2  8   4BitGPIO_INT18
- * J3  8   4BitGPIO_INT19
- * J4  4   4BitGPIO_INT20
- * K0  8   4BitNone
- * K1  6   4BitNone
- * K2  8   4BitNone
- * K3  8   4BitNone
- * L0  8   4BitNone
- * L1  8   4BitNone
- * L2  8   4BitNone
- * L3  8   4BitNone
- */
-
-static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
-#ifdef CONFIG_CPU_S5PC100
-   {
-   .chip   = {
-   .base   = S5PC100_GPA0(0),
-   .ngpio  = S5PC100_GPIO_A0_NR,
-   .label  = GPA0,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPA1(0),
-   .ngpio  = S5PC100_GPIO_A1_NR,
-   .label  = GPA1,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPB(0),
-   .ngpio  = S5PC100_GPIO_B_NR,
-   .label  = GPB,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPC(0),
-   .ngpio  = S5PC100_GPIO_C_NR,
-   .label  = GPC,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPD(0),
-   .ngpio  = S5PC100_GPIO_D_NR,
-   .label  = GPD,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPE0(0),
-   .ngpio  = S5PC100_GPIO_E0_NR,
-   .label  = GPE0,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPE1(0),
-   .ngpio  = S5PC100_GPIO_E1_NR,
-   .label  = GPE1,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPF0(0),
-   .ngpio  = S5PC100_GPIO_F0_NR,
-   .label  = GPF0,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPF1(0),
-   .ngpio  = S5PC100_GPIO_F1_NR,
-   .label  = GPF1,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPF2(0),
-   .ngpio  = S5PC100_GPIO_F2_NR,
-   .label  = GPF2,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPF3(0),
-   .ngpio  = S5PC100_GPIO_F3_NR,
-   .label  = GPF3,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPG0(0),
-   .ngpio  = S5PC100_GPIO_G0_NR,
-   .label  = GPG0,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPG1(0),
-   .ngpio  = S5PC100_GPIO_G1_NR,
-   .label  = GPG1,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPG2(0),
-   .ngpio  = S5PC100_GPIO_G2_NR,
-   .label  = GPG2,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPG3(0),
-   .ngpio  = S5PC100_GPIO_G3_NR,
-   .label  = GPG3,
-   },
-   }, {
-   .chip   = {
-   .base   = S5PC100_GPI(0),
-   .ngpio  = S5PC100_GPIO_I_NR,
-