[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:
ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)
Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas
---
drivers/clk/samsung/clk-exynos5420.c | 23 ---
include/dt-bindings/clock/exynos5420.h | 6 ++
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 848d602efc06..07d666cc6a29 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP3, 0, 1),
MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
SRC_TOP3, 4, 1),
- MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
- SRC_TOP3, 8, 1),
+ MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
+ mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
SRC_TOP3, 12, 1),
MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
SRC_TOP4, 28, 1),
- MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
- SRC_TOP5, 0, 1),
+ MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
+ mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
SRC_TOP5, 4, 1),
MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP5, 16, 1),
MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
SRC_TOP5, 20, 1),
- MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
- SRC_TOP5, 24, 1),
+ MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
+ mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
SRC_TOP5, 28, 1),
@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
SRC_TOP10, 0, 1),
MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
SRC_TOP10, 4, 1),
- MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
+ MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
+ SRC_TOP10, 8, 1),
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
SRC_TOP10, 12, 1),
MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
@@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
SRC_TOP11, 28, 1),
- MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
- SRC_TOP12, 4, 1),
+ MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
+ mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
SRC_TOP12, 8, 1),
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
@@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[]
__initdata = {
MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
SRC_TOP12, 20, 1),
- MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
- SRC_TOP12, 24, 1),
+ MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
+ mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
SRC_TOP12, 28, 1),
diff --git a/include/dt-bindings/clock/exynos5420.h
b/include/dt-bindings/clock/exynos5420.h
index 8dc0913f1775..99da0d117a7d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/i
Re: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
Hi, On 20/01/15 11:35, Javier Martinez Canillas wrote: > When a power domain is powered off on Exynos5420 SoC, the input clocks of > the devices attached to this power domain are re-parented to oscclk and > restored to the original parent after powering on the power domain. > > So a reference to the input and parent clocks for the devices attached to > a power domain are needed to be able to do the re-parenting. The DISP1 pd > includes modules which uses the following clocks: > > ACLK_200_DISP1 (MIXER and HDMILINK) > ACLK_300_DISP1 (FIMD1) > ACLK_400_DISP1 (Internal Buses) > > Each of these clocks are generated as the output of a clock mux so add an > ID for all of these clock muxes and their parents to be referenced in the > DISP1 power domain device node. > > Signed-off-by: Javier Martinez Canillas The patch looks OK to me, I'm fine with it being merged via Kukjin's tree due to the dts dependencies (including other pending dts patches touching the arch/arm/boot/dts/exynos5420.dtsi file). I think we need also Mike ACK for that, I could also queue the patch for the clk tree and create a topic branch, but merging both patches via arm-soc seems a more sane option in this case. Acked-by: Sylwester Nawrocki -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
Quoting Sylwester Nawrocki (2015-01-20 06:04:00) > Hi, > > On 20/01/15 11:35, Javier Martinez Canillas wrote: > > When a power domain is powered off on Exynos5420 SoC, the input clocks of > > the devices attached to this power domain are re-parented to oscclk and > > restored to the original parent after powering on the power domain. > > > > So a reference to the input and parent clocks for the devices attached to > > a power domain are needed to be able to do the re-parenting. The DISP1 pd > > includes modules which uses the following clocks: > > > > ACLK_200_DISP1 (MIXER and HDMILINK) > > ACLK_300_DISP1 (FIMD1) > > ACLK_400_DISP1 (Internal Buses) > > > > Each of these clocks are generated as the output of a clock mux so add an > > ID for all of these clock muxes and their parents to be referenced in the > > DISP1 power domain device node. > > > > Signed-off-by: Javier Martinez Canillas > > The patch looks OK to me, I'm fine with it being merged via Kukjin's tree > due to the dts dependencies (including other pending dts patches touching > the arch/arm/boot/dts/exynos5420.dtsi file). > I think we need also Mike ACK for that, I could also queue the patch for > the clk tree and create a topic branch, but merging both patches via > arm-soc seems a more sane option in this case. > > Acked-by: Sylwester Nawrocki Acked-by: Michael Turquette > > -- > Thanks, > Sylwester > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
Hello, On 01/20/2015 06:54 PM, Mike Turquette wrote: > Quoting Sylwester Nawrocki (2015-01-20 06:04:00) >> Hi, >> >> On 20/01/15 11:35, Javier Martinez Canillas wrote: >> > When a power domain is powered off on Exynos5420 SoC, the input clocks of >> > the devices attached to this power domain are re-parented to oscclk and >> > restored to the original parent after powering on the power domain. >> > >> > So a reference to the input and parent clocks for the devices attached to >> > a power domain are needed to be able to do the re-parenting. The DISP1 pd >> > includes modules which uses the following clocks: >> > >> > ACLK_200_DISP1 (MIXER and HDMILINK) >> > ACLK_300_DISP1 (FIMD1) >> > ACLK_400_DISP1 (Internal Buses) >> > >> > Each of these clocks are generated as the output of a clock mux so add an >> > ID for all of these clock muxes and their parents to be referenced in the >> > DISP1 power domain device node. >> > >> > Signed-off-by: Javier Martinez Canillas >> >> The patch looks OK to me, I'm fine with it being merged via Kukjin's tree >> due to the dts dependencies (including other pending dts patches touching >> the arch/arm/boot/dts/exynos5420.dtsi file). >> I think we need also Mike ACK for that, I could also queue the patch for >> the clk tree and create a topic branch, but merging both patches via >> arm-soc seems a more sane option in this case. >> >> Acked-by: Sylwester Nawrocki > > Acked-by: Michael Turquette > Thanks a lot Sylwester and Mike for your acks. Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1 power domain for exynos5420" through your tree? Best regards, Javier -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
Javier Martinez Canillas wrote: > > Hello, > Hi, > On 01/20/2015 06:54 PM, Mike Turquette wrote: > > Quoting Sylwester Nawrocki (2015-01-20 06:04:00) > >> Hi, > >> > >> On 20/01/15 11:35, Javier Martinez Canillas wrote: > >> > When a power domain is powered off on Exynos5420 SoC, the input clocks of > >> > the devices attached to this power domain are re-parented to oscclk and > >> > restored to the original parent after powering on the power domain. > >> > > >> > So a reference to the input and parent clocks for the devices attached to > >> > a power domain are needed to be able to do the re-parenting. The DISP1 pd > >> > includes modules which uses the following clocks: > >> > > >> > ACLK_200_DISP1 (MIXER and HDMILINK) > >> > ACLK_300_DISP1 (FIMD1) > >> > ACLK_400_DISP1 (Internal Buses) > >> > > >> > Each of these clocks are generated as the output of a clock mux so add an > >> > ID for all of these clock muxes and their parents to be referenced in the > >> > DISP1 power domain device node. > >> > > >> > Signed-off-by: Javier Martinez Canillas > >> > >> The patch looks OK to me, I'm fine with it being merged via Kukjin's tree > >> due to the dts dependencies (including other pending dts patches touching > >> the arch/arm/boot/dts/exynos5420.dtsi file). > >> I think we need also Mike ACK for that, I could also queue the patch for > >> the clk tree and create a topic branch, but merging both patches via > >> arm-soc seems a more sane option in this case. > >> > >> Acked-by: Sylwester Nawrocki > > > > Acked-by: Michael Turquette > > > > Thanks a lot Sylwester and Mike for your acks. > > Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1 > power domain for exynos5420" through your tree? > Sure, I will after applying Marek's generic power domain patch. Thanks, Kukjin -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain
Hello Kukjin, On 01/23/2015 07:51 AM, Kukjin Kim wrote: >> >> >> >> Acked-by: Sylwester Nawrocki >> > >> > Acked-by: Michael Turquette >> > >> >> Thanks a lot Sylwester and Mike for your acks. >> >> Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1 >> power domain for exynos5420" through your tree? >> > Sure, I will after applying Marek's generic power domain patch. > Awesome, thanks a lot for your help! > Thanks, > Kukjin > Best regards, Javier -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
