RE: [PATCH 2/9] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

2012-02-09 Thread Kukjin Kim 
Kyungmin Park wrote:
> 
> On 2/1/12, Kukjin Kim  wrote:

[snip]

> > +static int exynos5_clk_gate_block(struct clk *clk, int enable)
> exynos5_clk_block_ctrl?

OK, looks better, will change.

[snip]

> > +   .name   = "mfc",
> > +   .devname= "s3c-mfc",
> what's this?

typo :( should be s5p-mfc.

[snip]

> > +   .name   = "hdmi",
> > +   .devname= "exynos5-hdmi",
> I think exynos4x12 has same hdmi controller. so It will be changed as
> exynos-hdmi.

OK, let me check it but I'm not sure new exynos will have same hdmi later.

[snip]

> > +   .name   = "fimg2d",
> > +   .devname= "s5p-fimg2d",
> s5p? exynos?

Hmm, let me think again.

[snip]

Thanks :)

Best regards,
Kgene.
--
Kukjin Kim , Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

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Re: [PATCH 2/9] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

2012-01-31 Thread Kyungmin Park 
On 2/1/12, Kukjin Kim  wrote:
> Signed-off-by: Kukjin Kim 
> ---
>  arch/arm/mach-exynos/clock-exynos5.c   | 1258
> 
>  arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
Doesn't it better split the three header files?
regs-clock.h as wrapper. regs-clock-exynos4.h, regs-clock-exynos5.h
like clock C files.

>  arch/arm/plat-s5p/clock.c  |   36 +
>  arch/arm/plat-samsung/include/plat/s5p-clock.h |6 +
>  4 files changed, 1362 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-exynos/clock-exynos5.c
>
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> b/arch/arm/mach-exynos/clock-exynos5.c
> new file mode 100644
> index 000..b0c4478
> --- /dev/null
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -0,0 +1,1258 @@
> +/* linux/arch/arm/mach-exynos/clock-exynos5.c
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *   http://www.samsung.com
> + *
> + * EXYNOS5 - Clock support
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +#include "common.h"
> +
> +#ifdef CONFIG_PM_SLEEP
> +static struct sleep_save exynos5_clock_save[] = {
> + /* will be implemented */
> +};
> +#endif
> +
> +static struct clk exynos5_clk_sclk_dptxphy = {
> + .name   = "sclk_dptx",
> +};
> +
> +static struct clk exynos5_clk_sclk_hdmi24m = {
> + .name   = "sclk_hdmi24m",
> + .rate   = 2400,
> +};
> +
> +static struct clk exynos5_clk_sclk_hdmi27m = {
> + .name   = "sclk_hdmi27m",
> + .rate   = 2700,
> +};
> +
> +static struct clk exynos5_clk_sclk_hdmiphy = {
> + .name   = "sclk_hdmiphy",
> +};
> +
> +static struct clk exynos5_clk_sclk_usbphy = {
> + .name   = "sclk_usbphy",
> + .rate   = 4800,
> +};
> +
> +static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
> +}
> +
> +static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
> +}
> +
> +static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
> +}
> +
> +static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
> +}
> +
> +static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
> +}
> +
> +static int exynos5_clk_gate_block(struct clk *clk, int enable)
exynos5_clk_block_ctrl?
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
> +}
> +
> +/* Core list of CMU_CPU side */
> +
> +static struct clksrc_clk exynos5_clk_mout_apll = {
> + .clk= {
> + .name   = "mout_apll",
> + },
> + .sources = &clk_src_apll,
> + .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
> +};
> +
> +static struct clksrc_clk exynos5_clk_sclk_apll = {
> + .clk= {
> + .name   = "sclk_apll",
> + .parent = &exynos5_clk_mout_apll.clk,
> + },
> + .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 2

[PATCH 2/9] ARM: EXYNOS: add clock part for EXYNOS5250 SoC

2012-01-31 Thread Kukjin Kim 
Signed-off-by: Kukjin Kim 
---
 arch/arm/mach-exynos/clock-exynos5.c   | 1258 
 arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
 arch/arm/plat-s5p/clock.c  |   36 +
 arch/arm/plat-samsung/include/plat/s5p-clock.h |6 +
 4 files changed, 1362 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c 
b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 000..b0c4478
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1258 @@
+/* linux/arch/arm/mach-exynos/clock-exynos5.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS5 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+   /* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+   .name   = "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+   .name   = "sclk_hdmi24m",
+   .rate   = 2400,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+   .name   = "sclk_hdmi27m",
+   .rate   = 2700,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+   .name   = "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+   .name   = "sclk_usbphy",
+   .rate   = 4800,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_gate_block(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+   return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+   .clk= {
+   .name   = "mout_apll",
+   },
+   .sources = &clk_src_apll,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+   .clk= {
+   .name   = "sclk_apll",
+   .parent = &exynos5_clk_mout_apll.clk,
+   },
+   .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+   .clk= {
+   .name   = "mout_bpll",
+   },
+   .sources = &clk_src_bpll,
+   .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+   [0] = &clk_fin_mpll,
+   [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_use