Re: [PATCH 4/8] ARM: dts: Exynos5420: add CPU OPP and regulator supply property
Hi Bartlomiej,
> From: Thomas Abraham
>
> For Exynos5420 platforms, add CPU operating points and CPU
> regulator supply properties for migrating from Exynos specific
> cpufreq driver to using generic cpufreq driver.
>
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
>
> Cc: Kukjin Kim
> Cc: Doug Anderson
> Cc: Javier Martinez Canillas
> Cc: Andreas Faerber
> Cc: Sachin Kamat
> Signed-off-by: Thomas Abraham
> Signed-off-by: Bartlomiej Zolnierkiewicz
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 38
> + 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi
> b/arch/arm/boot/dts/exynos5420.dtsi index f67b23f..85b9cfc 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -59,8 +59,26 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x0>;
> + clocks = <&clock CLK_ARM_CLK>;
> + clock-names = "cpu-cluster.0";
> clock-frequency = <18>;
> cci-control-port = <&cci_control1>;
> + clock-latency = <14>;
> +
> + operating-points = <
> + 180 125
> + 170 1212500
> + 160 1175000
> + 150 1137500
> + 140 1112500
> + 130 1062500
> + 120 1037500
> + 110 1012500
> + 100 987500
> + 90 962500
> + 80 937500
> + 70 912500
> + >;
> };
>
> cpu1: cpu@1 {
> @@ -69,6 +87,7 @@
> reg = <0x1>;
> clock-frequency = <18>;
> cci-control-port = <&cci_control1>;
> + clock-latency = <14>;
> };
>
> cpu2: cpu@2 {
> @@ -77,6 +96,7 @@
> reg = <0x2>;
> clock-frequency = <18>;
> cci-control-port = <&cci_control1>;
> + clock-latency = <14>;
> };
>
> cpu3: cpu@3 {
> @@ -85,14 +105,29 @@
> reg = <0x3>;
> clock-frequency = <18>;
> cci-control-port = <&cci_control1>;
> + clock-latency = <14>;
> };
>
> cpu4: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x100>;
> + clocks = <&clock CLK_KFC_CLK>;
> + clock-names = "cpu-cluster.1";
> clock-frequency = <10>;
> cci-control-port = <&cci_control0>;
> + clock-latency = <14>;
> +
> + operating-points = <
> + 130 1275000
> + 120 1212500
> + 110 1162500
> + 100 1112500
> + 90 1062500
> + 80 1025000
> + 70 975000
> + 60 937500
> + >;
> };
>
> cpu5: cpu@101 {
> @@ -101,6 +136,7 @@
> reg = <0x101>;
> clock-frequency = <10>;
> cci-control-port = <&cci_control0>;
> + clock-latency = <14>;
> };
>
> cpu6: cpu@102 {
> @@ -109,6 +145,7 @@
> reg = <0x102>;
> clock-frequency = <10>;
> cci-control-port = <&cci_control0>;
> + clock-latency = <14>;
> };
>
> cpu7: cpu@103 {
> @@ -117,6 +154,7 @@
> reg = <0x103>;
> clock-frequency = <10>;
> cci-control-port = <&cci_control0>;
> + clock-latency = <14>;
> };
> };
>
Reviewed-by: Lukasz Majewski
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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[PATCH 4/8] ARM: dts: Exynos5420: add CPU OPP and regulator supply property
From: Thomas Abraham
For Exynos5420 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
Cc: Kukjin Kim
Cc: Doug Anderson
Cc: Javier Martinez Canillas
Cc: Andreas Faerber
Cc: Sachin Kamat
Signed-off-by: Thomas Abraham
Signed-off-by: Bartlomiej Zolnierkiewicz
---
arch/arm/boot/dts/exynos5420.dtsi | 38 +
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index f67b23f..85b9cfc 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
+ clock-names = "cpu-cluster.0";
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ clock-latency = <14>;
+
+ operating-points = <
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+ 100 987500
+90 962500
+80 937500
+70 912500
+ >;
};
cpu1: cpu@1 {
@@ -69,6 +87,7 @@
reg = <0x1>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ clock-latency = <14>;
};
cpu2: cpu@2 {
@@ -77,6 +96,7 @@
reg = <0x2>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ clock-latency = <14>;
};
cpu3: cpu@3 {
@@ -85,14 +105,29 @@
reg = <0x3>;
clock-frequency = <18>;
cci-control-port = <&cci_control1>;
+ clock-latency = <14>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
+ clock-names = "cpu-cluster.1";
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ clock-latency = <14>;
+
+ operating-points = <
+ 130 1275000
+ 120 1212500
+ 110 1162500
+ 100 1112500
+90 1062500
+80 1025000
+70 975000
+60 937500
+ >;
};
cpu5: cpu@101 {
@@ -101,6 +136,7 @@
reg = <0x101>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ clock-latency = <14>;
};
cpu6: cpu@102 {
@@ -109,6 +145,7 @@
reg = <0x102>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ clock-latency = <14>;
};
cpu7: cpu@103 {
@@ -117,6 +154,7 @@
reg = <0x103>;
clock-frequency = <10>;
cci-control-port = <&cci_control0>;
+ clock-latency = <14>;
};
};
--
1.7.9.5
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