Re: [PATCH V4 3/5] dt: exynos5420: Enable support for DWC3 controller
On 08.04.2014 16:36, Vivek Gautam wrote:
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index a6efb52..20c2d0b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -653,6 +653,23 @@
clock-names = tmu_apbif, tmu_triminfo_apbif;
};
+ usb@1200 {
+ compatible = samsung,exynos5250-dwusb3;
+ clocks = clock 366;
+ clock-names = usbdrd30;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ dwc3 {
+ compatible = synopsys,dwc3;
+ reg = 0x1200 0x1;
+ interrupts = 0 72 0;
+ phys = usbdrd_phy0 0, usbdrd_phy0 1;
+ phy-names = usb2-phy, usb3-phy;
+ };
+ };
+
usbdrd_phy0: phy@1210 {
compatible = samsung,exynos5420-usbdrd-phy;
reg = 0x1210 0x100;
@@ -663,6 +680,23 @@
#phy-cells = 1;
};
+ usb@1240 {
+ compatible = samsung,exynos5250-dwusb3;
+ clocks = clock 367;
+ clock-names = usbdrd30;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ dwc3 {
+ compatible = synopsys,dwc3;
+ reg = 0x1240 0x1;
+ interrupts = 0 73 0;
+ phys = usbdrd_phy1 0, usbdrd_phy1 1;
+ phy-names = usb2-phy, usb3-phy;
+ };
+ };
+
usbdrd_phy1: phy@1250 {
compatible = samsung,exynos5420-usbdrd-phy;
reg = 0x1250 0x100;
Reviewed-by: Tomasz Figa t.f...@samsung.com
--
Best regards,
Tomasz
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[PATCH V4 3/5] dt: exynos5420: Enable support for DWC3 controller
Add device tree nodes for DWC3 controller present on
Exynos 5420 SoC, to enable support for USB 3.0.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index a6efb52..20c2d0b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -653,6 +653,23 @@
clock-names = tmu_apbif, tmu_triminfo_apbif;
};
+ usb@1200 {
+ compatible = samsung,exynos5250-dwusb3;
+ clocks = clock 366;
+ clock-names = usbdrd30;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ dwc3 {
+ compatible = synopsys,dwc3;
+ reg = 0x1200 0x1;
+ interrupts = 0 72 0;
+ phys = usbdrd_phy0 0, usbdrd_phy0 1;
+ phy-names = usb2-phy, usb3-phy;
+ };
+ };
+
usbdrd_phy0: phy@1210 {
compatible = samsung,exynos5420-usbdrd-phy;
reg = 0x1210 0x100;
@@ -663,6 +680,23 @@
#phy-cells = 1;
};
+ usb@1240 {
+ compatible = samsung,exynos5250-dwusb3;
+ clocks = clock 367;
+ clock-names = usbdrd30;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ dwc3 {
+ compatible = synopsys,dwc3;
+ reg = 0x1240 0x1;
+ interrupts = 0 73 0;
+ phys = usbdrd_phy1 0, usbdrd_phy1 1;
+ phy-names = usb2-phy, usb3-phy;
+ };
+ };
+
usbdrd_phy1: phy@1250 {
compatible = samsung,exynos5420-usbdrd-phy;
reg = 0x1250 0x100;
--
1.7.10.4
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