Re: [PATCH v11 12/27] ARM: dts: Add description of System MMU of Exynos SoCs
On Sun, 20 Apr 2014 15:25:59 +0530, Shaik Ameer Basha wrote: > Hi KyongHo Cho, > > Please find the comments inline. > > On Fri, Mar 14, 2014 at 10:36 AM, Cho KyongHo wrote: > > This patch adds dts entries for the System MMU devices found on > > Exynos4 and Exynos5 SoC series and the System MMU binding > > documentation. > > > > CC: Rob Herring > > CC: Sylwester Nawrocki > > Signed-off-by: Cho KyongHo > > --- > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 86 +++ > > arch/arm/boot/dts/exynos4.dtsi | 107 > > arch/arm/boot/dts/exynos4210.dtsi | 23 +- > > arch/arm/boot/dts/exynos4x12.dtsi | 77 +- > > arch/arm/boot/dts/exynos5250.dtsi | 266 > > +++- > > arch/arm/boot/dts/exynos5420.dtsi | 205 ++- > > 6 files changed, 758 insertions(+), 6 deletions(-) > > create mode 100644 > > Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > > > diff --git > > a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > new file mode 100644 > > index 000..e4417bb > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > @@ -0,0 +1,86 @@ > > +Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) > > + > > +Samsung's Exynos architecture contains System MMUs that enables scattered > > +physical memory chunks visible as a contiguous region to DMA-capable > > peripheral > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. > > + > > [snip] > > > > diff --git a/arch/arm/boot/dts/exynos5250.dtsi > > b/arch/arm/boot/dts/exynos5250.dtsi > > index 8f6300f..df336ea 100644 > > --- a/arch/arm/boot/dts/exynos5250.dtsi > > +++ b/arch/arm/boot/dts/exynos5250.dtsi > > @@ -80,6 +80,16 @@ > > reg = <0x10044040 0x20>; > > }; > > > > + pd_isp: isp-power-domain@0x10044020 { > > + compatible = "samsung,exynos4210-pd"; > > + reg = <0x10044020 0x20>; > > + }; > > + > > + pd_disp1: disp1-power-domain@0x100440A0 { > > + compatible = "samsung,exynos4210-pd"; > > + reg = <0x100440A0 0x20>; > > + }; > > + > > clock: clock-controller@1001 { > > compatible = "samsung,exynos5250-clock"; > > reg = <0x1001 0x3>; > > @@ -679,7 +689,7 @@ > > "sclk_hdmiphy", "mout_hdmi"; > > }; > > > > - mixer { > > + mixer: mixer { > > compatible = "samsung,exynos5250-mixer"; > > reg = <0x1445 0x1>; > > interrupts = <0 94 0>; > > @@ -700,7 +710,7 @@ > > phy-names = "dp"; > > }; > > > > - fimd@1440 { > > + fimd: fimd@1440 { > > clocks = <&clock 133>, <&clock 339>; > > clock-names = "sclk_fimd", "fimd"; > > }; > > @@ -715,4 +725,256 @@ > > io-channel-ranges; > > status = "disabled"; > > }; > > + > > + sysmmu_g2d: sysmmu@10A6 { > > + compatible = "samsung,sysmmu-v1"; > > + reg = <0x10A6 0x1000>; > > + interrupt-parent = <&combiner>; > > + interrupts = <24 5>; > > + clock-names = "sysmmu"; > > + clocks = <&clock 361>; > > + }; > > + > > + sysmmu_mfc_r: sysmmu@1120 { > > + compatible = "samsung,sysmmu-v2"; > > + reg = <0x1120 0x1000>; > > + interrupt-parent = <&combiner>; > > + interrupts = <6 2>; > > + clock-names = "sysmmu", "master"; > > + clocks = <&clock 268>, <&clock 266>; > > Add mmu-masters... > mmu-masters = <&mfc>; > Ok. > > + samsung,power-domain = <&pd_mfc>; > > + }; > > + > > + sysmmu_mfc_l: sysmmu@1121 { > > + compatible = "samsung,sysmmu-v2"; > > + reg = <0x1121 0x1000>; > > + interrupt-parent = <&combiner>; > > + interrupts = <8 5>; > > + clock-names = "sysmmu", "master"; > > + clocks = <&clock 267>, <&clock 266>; > > Add mmu-masters... > mmu-masters = <&mfc>; > OK. > > > + samsung,power-domain = <&pd_mfc>; > > + }; > > + > > + sysmmu_rotator: sysmmu@11D4 { > > + compatible = "samsung,sysmmu-v1"; > > + reg = <0x11D4 0x1000>; > > + interrupt-parent = <&combiner>; > > + interrupts = <4 0>; > > + clock-names = "sysmmu"; > > + clocks = <&clock 272>; > > + }; > > + > > [snip] > > > }; > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi > > b/arch/arm
Re: [PATCH v11 12/27] ARM: dts: Add description of System MMU of Exynos SoCs
Hi KyongHo Cho, Please find the comments inline. On Fri, Mar 14, 2014 at 10:36 AM, Cho KyongHo wrote: > This patch adds dts entries for the System MMU devices found on > Exynos4 and Exynos5 SoC series and the System MMU binding > documentation. > > CC: Rob Herring > CC: Sylwester Nawrocki > Signed-off-by: Cho KyongHo > --- > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 86 +++ > arch/arm/boot/dts/exynos4.dtsi | 107 > arch/arm/boot/dts/exynos4210.dtsi | 23 +- > arch/arm/boot/dts/exynos4x12.dtsi | 77 +- > arch/arm/boot/dts/exynos5250.dtsi | 266 > +++- > arch/arm/boot/dts/exynos5420.dtsi | 205 ++- > 6 files changed, 758 insertions(+), 6 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > diff --git > a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > new file mode 100644 > index 000..e4417bb > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > @@ -0,0 +1,86 @@ > +Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) > + > +Samsung's Exynos architecture contains System MMUs that enables scattered > +physical memory chunks visible as a contiguous region to DMA-capable > peripheral > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. > + [snip] > diff --git a/arch/arm/boot/dts/exynos5250.dtsi > b/arch/arm/boot/dts/exynos5250.dtsi > index 8f6300f..df336ea 100644 > --- a/arch/arm/boot/dts/exynos5250.dtsi > +++ b/arch/arm/boot/dts/exynos5250.dtsi > @@ -80,6 +80,16 @@ > reg = <0x10044040 0x20>; > }; > > + pd_isp: isp-power-domain@0x10044020 { > + compatible = "samsung,exynos4210-pd"; > + reg = <0x10044020 0x20>; > + }; > + > + pd_disp1: disp1-power-domain@0x100440A0 { > + compatible = "samsung,exynos4210-pd"; > + reg = <0x100440A0 0x20>; > + }; > + > clock: clock-controller@1001 { > compatible = "samsung,exynos5250-clock"; > reg = <0x1001 0x3>; > @@ -679,7 +689,7 @@ > "sclk_hdmiphy", "mout_hdmi"; > }; > > - mixer { > + mixer: mixer { > compatible = "samsung,exynos5250-mixer"; > reg = <0x1445 0x1>; > interrupts = <0 94 0>; > @@ -700,7 +710,7 @@ > phy-names = "dp"; > }; > > - fimd@1440 { > + fimd: fimd@1440 { > clocks = <&clock 133>, <&clock 339>; > clock-names = "sclk_fimd", "fimd"; > }; > @@ -715,4 +725,256 @@ > io-channel-ranges; > status = "disabled"; > }; > + > + sysmmu_g2d: sysmmu@10A6 { > + compatible = "samsung,sysmmu-v1"; > + reg = <0x10A6 0x1000>; > + interrupt-parent = <&combiner>; > + interrupts = <24 5>; > + clock-names = "sysmmu"; > + clocks = <&clock 361>; > + }; > + > + sysmmu_mfc_r: sysmmu@1120 { > + compatible = "samsung,sysmmu-v2"; > + reg = <0x1120 0x1000>; > + interrupt-parent = <&combiner>; > + interrupts = <6 2>; > + clock-names = "sysmmu", "master"; > + clocks = <&clock 268>, <&clock 266>; Add mmu-masters... mmu-masters = <&mfc>; > + samsung,power-domain = <&pd_mfc>; > + }; > + > + sysmmu_mfc_l: sysmmu@1121 { > + compatible = "samsung,sysmmu-v2"; > + reg = <0x1121 0x1000>; > + interrupt-parent = <&combiner>; > + interrupts = <8 5>; > + clock-names = "sysmmu", "master"; > + clocks = <&clock 267>, <&clock 266>; Add mmu-masters... mmu-masters = <&mfc>; > + samsung,power-domain = <&pd_mfc>; > + }; > + > + sysmmu_rotator: sysmmu@11D4 { > + compatible = "samsung,sysmmu-v1"; > + reg = <0x11D4 0x1000>; > + interrupt-parent = <&combiner>; > + interrupts = <4 0>; > + clock-names = "sysmmu"; > + clocks = <&clock 272>; > + }; > + [snip] > }; > diff --git a/arch/arm/boot/dts/exynos5420.dtsi > b/arch/arm/boot/dts/exynos5420.dtsi > index 45e2e65..a736f09 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -470,7 +470,7 @@ > phy-names = "dp"; > }; > > - fimd@1440 { > + fimd: fimd@1440 { > samsung,power-domain = <&disp_pd>; > clocks = <&
Re: [PATCH v11 12/27] ARM: dts: Add description of System MMU of Exynos SoCs
On Fri, 14 Mar 2014 13:20:23 +0100, Tomasz Figa wrote: > Hi KyongHo, > > On 14.03.2014 06:06, Cho KyongHo wrote: > > This patch adds dts entries for the System MMU devices found on > > Exynos4 and Exynos5 SoC series and the System MMU binding > > documentation. > > > > CC: Rob Herring > > CC: Sylwester Nawrocki > > Signed-off-by: Cho KyongHo > > --- > > .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 86 +++ > > arch/arm/boot/dts/exynos4.dtsi | 107 > > arch/arm/boot/dts/exynos4210.dtsi | 23 +- > > arch/arm/boot/dts/exynos4x12.dtsi | 77 +- > > arch/arm/boot/dts/exynos5250.dtsi | 266 > > +++- > > arch/arm/boot/dts/exynos5420.dtsi | 205 ++- > > 6 files changed, 758 insertions(+), 6 deletions(-) > > create mode 100644 > > Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > > > diff --git > > a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > new file mode 100644 > > index 000..e4417bb > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt > > @@ -0,0 +1,86 @@ > > +Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) > > + > > +Samsung's Exynos architecture contains System MMUs that enables scattered > > +physical memory chunks visible as a contiguous region to DMA-capable > > peripheral > > +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. > > + > > +System MMU is an IOMMU and supports identical translation table format to > > +ARMv7 translation tables with minimum set of page properties including > > access > > +permissions, shareability and security protection. In addition, System MMU > > has > > +another capabilities like L2 TLB or block-fetch buffers to minimize > > translation > > +latency. > > + > > +System MMUs are in many to one relation with peripheral devices, i.e. > > single > > +peripheral device might have multiple System MMUs (usually one for each bus > > +master), but one System MMU can handle transactions from only one > > peripheral > > +device. The relation between a System MMU and the peripheral device needs > > to be > > +defined in device node of the peripheral device. > > + > > +MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 > > System > > +MMUs. > > +* MFC has one System MMU on its left and right bus. > > +* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other > > system MMU > > + for window 1, 2 and 3. > > +* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel > > and > > + the other System MMU on the write channel. > > +The drivers must consider how to handle those System MMUs. One of the idea > > is > > +to implement child devices or sub-devices which are the client devices of > > the > > +System MMU. > > + > > +Required properties: > > +- compatible: Should be one of: > > + "samsung,sysmmu-v1" > > + "samsung,sysmmu-v2" > > + "samsung,sysmmu-v3.1" > > + "samsung,sysmmu-v3.2" > > + "samsung,sysmmu-v3.3" > > + > > +- reg: A tuple of base address and size of System MMU registers. > > +- interrupt-parent: The phandle of the interrupt controller of System MMU > > +- interrupts: An interrupt specifier for interrupt signal of System MMU, > > + according to the format defined by a particular interrupt > > + controller. > > +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its > > clock. > > + Please refer to the following documents: > > + Documentation/devicetree/bindings/clock/clock-bindings.txt > > + Documentation/devicetree/bindings/clock/exynos4-clock.txt > > + Documentation/devicetree/bindings/clock/exynos5250-clock.txt > > + Documentation/devicetree/bindings/clock/exynos5420-clock.txt > > + Optional "master" if the clock to the System MMU is gated by > > + another gate clock other than "sysmmu". The System MMU driver > > + sets "master" the parent of "sysmmu". > > + Exynos4 SoCs, there needs no "master" clockj. > > + Exynos5 SoCs, some System MMUs must have "master" clocks. > > +- clocks: Required if the System MMU is needed to gate its clock. > > + Please refer to the documents listed above. > > +- samsung,power-domain: Required if the System MMU is needed to gate its > > power. > > + Please refer to the following document: > > + Documentation/devicetree/bindings/arm/exynos/power_domain.txt > > +- mmu-masters: A phandle to device nodes representing the master for which > > + the System MMU can provide a translation. Any additional > > values > > + after the phandle will be ignored because a System MMU never > > + have two or
Re: [PATCH v11 12/27] ARM: dts: Add description of System MMU of Exynos SoCs
Hi KyongHo, On 14.03.2014 06:06, Cho KyongHo wrote: This patch adds dts entries for the System MMU devices found on Exynos4 and Exynos5 SoC series and the System MMU binding documentation. CC: Rob Herring CC: Sylwester Nawrocki Signed-off-by: Cho KyongHo --- .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 86 +++ arch/arm/boot/dts/exynos4.dtsi | 107 arch/arm/boot/dts/exynos4210.dtsi | 23 +- arch/arm/boot/dts/exynos4x12.dtsi | 77 +- arch/arm/boot/dts/exynos5250.dtsi | 266 +++- arch/arm/boot/dts/exynos5420.dtsi | 205 ++- 6 files changed, 758 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt new file mode 100644 index 000..e4417bb --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt @@ -0,0 +1,86 @@ +Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) + +Samsung's Exynos architecture contains System MMUs that enables scattered +physical memory chunks visible as a contiguous region to DMA-capable peripheral +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. + +System MMU is an IOMMU and supports identical translation table format to +ARMv7 translation tables with minimum set of page properties including access +permissions, shareability and security protection. In addition, System MMU has +another capabilities like L2 TLB or block-fetch buffers to minimize translation +latency. + +System MMUs are in many to one relation with peripheral devices, i.e. single +peripheral device might have multiple System MMUs (usually one for each bus +master), but one System MMU can handle transactions from only one peripheral +device. The relation between a System MMU and the peripheral device needs to be +defined in device node of the peripheral device. + +MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System +MMUs. +* MFC has one System MMU on its left and right bus. +* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU + for window 1, 2 and 3. +* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and + the other System MMU on the write channel. +The drivers must consider how to handle those System MMUs. One of the idea is +to implement child devices or sub-devices which are the client devices of the +System MMU. + +Required properties: +- compatible: Should be one of: + "samsung,sysmmu-v1" + "samsung,sysmmu-v2" + "samsung,sysmmu-v3.1" + "samsung,sysmmu-v3.2" + "samsung,sysmmu-v3.3" + +- reg: A tuple of base address and size of System MMU registers. +- interrupt-parent: The phandle of the interrupt controller of System MMU +- interrupts: An interrupt specifier for interrupt signal of System MMU, + according to the format defined by a particular interrupt + controller. +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock. + Please refer to the following documents: + Documentation/devicetree/bindings/clock/clock-bindings.txt + Documentation/devicetree/bindings/clock/exynos4-clock.txt + Documentation/devicetree/bindings/clock/exynos5250-clock.txt + Documentation/devicetree/bindings/clock/exynos5420-clock.txt + Optional "master" if the clock to the System MMU is gated by + another gate clock other than "sysmmu". The System MMU driver + sets "master" the parent of "sysmmu". + Exynos4 SoCs, there needs no "master" clockj. + Exynos5 SoCs, some System MMUs must have "master" clocks. +- clocks: Required if the System MMU is needed to gate its clock. + Please refer to the documents listed above. +- samsung,power-domain: Required if the System MMU is needed to gate its power. + Please refer to the following document: + Documentation/devicetree/bindings/arm/exynos/power_domain.txt +- mmu-masters: A phandle to device nodes representing the master for which + the System MMU can provide a translation. Any additional values + after the phandle will be ignored because a System MMU never + have two or more masters. "#stream-id-cells" specified in the + master's node will be also ignored. + If more than one phandle is specified, only the first phandle + will be treated. + +Examples: + gsc_0: gsc@13e0 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e0 0x1000>; + interrupts = <0 85 0>; +
[PATCH v11 12/27] ARM: dts: Add description of System MMU of Exynos SoCs
This patch adds dts entries for the System MMU devices found on Exynos4 and Exynos5 SoC series and the System MMU binding documentation. CC: Rob Herring CC: Sylwester Nawrocki Signed-off-by: Cho KyongHo --- .../bindings/iommu/samsung,exynos4210-sysmmu.txt | 86 +++ arch/arm/boot/dts/exynos4.dtsi | 107 arch/arm/boot/dts/exynos4210.dtsi | 23 +- arch/arm/boot/dts/exynos4x12.dtsi | 77 +- arch/arm/boot/dts/exynos5250.dtsi | 266 +++- arch/arm/boot/dts/exynos5420.dtsi | 205 ++- 6 files changed, 758 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt diff --git a/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt new file mode 100644 index 000..e4417bb --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,exynos4210-sysmmu.txt @@ -0,0 +1,86 @@ +Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) + +Samsung's Exynos architecture contains System MMUs that enables scattered +physical memory chunks visible as a contiguous region to DMA-capable peripheral +devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. + +System MMU is an IOMMU and supports identical translation table format to +ARMv7 translation tables with minimum set of page properties including access +permissions, shareability and security protection. In addition, System MMU has +another capabilities like L2 TLB or block-fetch buffers to minimize translation +latency. + +System MMUs are in many to one relation with peripheral devices, i.e. single +peripheral device might have multiple System MMUs (usually one for each bus +master), but one System MMU can handle transactions from only one peripheral +device. The relation between a System MMU and the peripheral device needs to be +defined in device node of the peripheral device. + +MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System +MMUs. +* MFC has one System MMU on its left and right bus. +* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU + for window 1, 2 and 3. +* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and + the other System MMU on the write channel. +The drivers must consider how to handle those System MMUs. One of the idea is +to implement child devices or sub-devices which are the client devices of the +System MMU. + +Required properties: +- compatible: Should be one of: + "samsung,sysmmu-v1" + "samsung,sysmmu-v2" + "samsung,sysmmu-v3.1" + "samsung,sysmmu-v3.2" + "samsung,sysmmu-v3.3" + +- reg: A tuple of base address and size of System MMU registers. +- interrupt-parent: The phandle of the interrupt controller of System MMU +- interrupts: An interrupt specifier for interrupt signal of System MMU, + according to the format defined by a particular interrupt + controller. +- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock. + Please refer to the following documents: + Documentation/devicetree/bindings/clock/clock-bindings.txt + Documentation/devicetree/bindings/clock/exynos4-clock.txt + Documentation/devicetree/bindings/clock/exynos5250-clock.txt + Documentation/devicetree/bindings/clock/exynos5420-clock.txt + Optional "master" if the clock to the System MMU is gated by + another gate clock other than "sysmmu". The System MMU driver + sets "master" the parent of "sysmmu". + Exynos4 SoCs, there needs no "master" clockj. + Exynos5 SoCs, some System MMUs must have "master" clocks. +- clocks: Required if the System MMU is needed to gate its clock. + Please refer to the documents listed above. +- samsung,power-domain: Required if the System MMU is needed to gate its power. + Please refer to the following document: + Documentation/devicetree/bindings/arm/exynos/power_domain.txt +- mmu-masters: A phandle to device nodes representing the master for which + the System MMU can provide a translation. Any additional values + after the phandle will be ignored because a System MMU never + have two or more masters. "#stream-id-cells" specified in the + master's node will be also ignored. + If more than one phandle is specified, only the first phandle + will be treated. + +Examples: + gsc_0: gsc@13e0 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e0 0x1000>; + interrupts = <0 85 0>; + samsung,power-domain = <&pd_gsc>; + clocks = <&cl