Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 457 +
arch/arm/boot/dts/exynos4210.dtsi | 37 +++
2 files changed, 494 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1140 {
+ uart0_data: uart0-data {
+ samsung,pins = gpa0-0, gpa0-1;
+ samsung,pin-function = 0x2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = gpa0-2, gpa0-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = gpa0-4, gpa0-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = gpb-0, gpb-2, gpb-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = gpb-2, gpb-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = gpb-4, gpb-6, gpb-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ i2c5_bus: i2c5-bus {
+
